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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
ARM: imx: add clock driver for imx6sx
Add clock driver for i.MX6 SoloX SoC.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
authored by
Anson Huang
and committed by
Shawn Guo
d5513568
74368e81
+793
+13
Documentation/devicetree/bindings/clock/imx6sx-clock.txt
+13
Documentation/devicetree/bindings/clock/imx6sx-clock.txt
···
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* Clock bindings for Freescale i.MX6 SoloX
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Required properties:
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- compatible: Should be "fsl,imx6sx-ccm"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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- clocks: list of clock specifiers, must contain an entry for each required
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entry in clock-names
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- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
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for the full list of i.MX6 SoloX clock IDs.
+524
arch/arm/mach-imx/clk-imx6sx.c
+524
arch/arm/mach-imx/clk-imx6sx.c
···
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/clock/imx6sx-clock.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/types.h>
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#include "clk.h"
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#include "common.h"
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#define CCDR 0x4
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#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
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static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
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static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
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static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
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static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
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static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
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static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *ocram_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
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static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
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static const char *gpu_axi_sels[] = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
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static const char *gpu_core_sels[] = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
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static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
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static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
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static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
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static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
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static const char *pcie_axi_sels[] = { "axi", "ahb", };
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static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
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static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
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static const char *perclk_sels[] = { "ipg", "osc", };
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static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *vid_sels[] = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
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static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
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static const char *uart_sels[] = { "pll3_80m", "osc", };
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static const char *qspi2_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
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static const char *enet_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
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static const char *enet_sels[] = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *m4_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
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static const char *m4_sels[] = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *eim_slow_sels[] = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *ecspi_sels[] = { "pll3_60m", "osc", };
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static const char *lcdif1_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
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static const char *lcdif1_sels[] = { "lcdif1_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *lcdif2_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
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static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
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static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
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static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
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static const char *cko1_sels[] = {
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"pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
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"dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
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"epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
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};
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static const char *cko2_sels[] = {
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"dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
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"ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
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"lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
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"usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
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"dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",
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"spdif", "asrc", "dummy",
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};
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static const char *cko_sels[] = { "cko1", "cko2", };
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static const char *lvds_sels[] = {
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"arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
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"dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
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};
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static struct clk *clks[IMX6SX_CLK_CLK_END];
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static struct clk_onecell_data clk_data;
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static int const clks_init_on[] __initconst = {
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IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,
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IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
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IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
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IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
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IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4,
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IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
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IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
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IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
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IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
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IMX6SX_CLK_EPIT2,
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};
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static struct clk_div_table clk_enet_ref_table[] = {
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{ .val = 0, .div = 20, },
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{ .val = 1, .div = 10, },
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{ .val = 2, .div = 5, },
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{ .val = 3, .div = 4, },
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{ }
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};
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static struct clk_div_table post_div_table[] = {
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{ .val = 2, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 0, .div = 4, },
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{ }
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};
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static struct clk_div_table video_div_table[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 2, .div = 1, },
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{ .val = 3, .div = 4, },
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{ }
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};
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static u32 share_count_asrc;
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static u32 share_count_audio;
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static u32 share_count_esai;
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static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
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clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
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/* ipp_di clock is external input */
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clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
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clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
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base = of_iomap(np, 0);
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WARN_ON(!base);
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/* type name parent_name base div_mask */
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clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
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clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
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clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
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clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
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clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
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clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
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clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
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/*
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* Bit 20 is the reserved and read-only bit, we do this only for:
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* - Do nothing for usbphy clk_enable/disable
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* - Keep refcount when do usbphy clk_enable/disable, in that case,
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* the clk framework may need to enable/disable usbphy's parent
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*/
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clks[IMX6SX_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
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clks[IMX6SX_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
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/*
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* usbphy*_gate needs to be on after system boots up, and software
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* never needs to control it anymore.
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*/
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clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
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clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
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/* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */
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clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
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clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
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clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
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clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
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base + 0xe0, 0, 2, 0, clk_enet_ref_table,
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&imx_ccm_lock);
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clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
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base + 0xe0, 2, 2, 0, clk_enet_ref_table,
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&imx_ccm_lock);
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clks[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
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clks[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
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clks[IMX6SX_CLK_ENET_PTP] = imx_clk_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21);
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/* name parent_name reg idx */
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clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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clks[IMX6SX_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
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clks[IMX6SX_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
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clks[IMX6SX_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
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clks[IMX6SX_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
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clks[IMX6SX_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
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clks[IMX6SX_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
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clks[IMX6SX_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
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+
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/* name parent_name mult div */
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clks[IMX6SX_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
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clks[IMX6SX_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
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clks[IMX6SX_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
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clks[IMX6SX_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
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clks[IMX6SX_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
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clks[IMX6SX_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
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+
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clks[IMX6SX_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
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CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
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CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
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CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
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CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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+
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/* name reg shift width parent_names num_parents */
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clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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+
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np = ccm_node;
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base = of_iomap(np, 0);
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WARN_ON(!base);
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+
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imx6q_pm_set_ccm_base(base);
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+
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/* name reg shift width parent_names num_parents */
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clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
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clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
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clks[IMX6SX_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels));
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+
clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
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+
clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
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+
clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
232
+
clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
233
+
clks[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
234
+
clks[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
235
+
clks[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels));
236
+
clks[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
237
+
clks[IMX6SX_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
238
+
clks[IMX6SX_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
239
+
clks[IMX6SX_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
240
+
clks[IMX6SX_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
241
+
clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
242
+
clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
243
+
clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
244
+
clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux_flags("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT);
245
+
clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
246
+
clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
247
+
clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
248
+
clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
249
+
clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
250
+
clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
251
+
clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
252
+
clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
253
+
clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
254
+
clks[IMX6SX_CLK_ENET_SEL] = imx_clk_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels));
255
+
clks[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels));
256
+
clks[IMX6SX_CLK_M4_SEL] = imx_clk_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels));
257
+
clks[IMX6SX_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
258
+
clks[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels));
259
+
clks[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels));
260
+
clks[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels));
261
+
clks[IMX6SX_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
262
+
clks[IMX6SX_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
263
+
clks[IMX6SX_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
264
+
clks[IMX6SX_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
265
+
266
+
clks[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
267
+
clks[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
268
+
clks[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT);
269
+
clks[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT);
270
+
clks[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
271
+
clks[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT);
272
+
273
+
/* name parent_name reg shift width */
274
+
clks[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
275
+
clks[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
276
+
clks[IMX6SX_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
277
+
clks[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3);
278
+
clks[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3);
279
+
clks[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3);
280
+
clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
281
+
clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
282
+
clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3);
283
+
clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
284
+
clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2);
285
+
clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6);
286
+
clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
287
+
clks[IMX6SX_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
288
+
clks[IMX6SX_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
289
+
clks[IMX6SX_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
290
+
clks[IMX6SX_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
291
+
clks[IMX6SX_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
292
+
clks[IMX6SX_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
293
+
clks[IMX6SX_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
294
+
clks[IMX6SX_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
295
+
clks[IMX6SX_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
296
+
clks[IMX6SX_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
297
+
clks[IMX6SX_CLK_QSPI2_PRED] = imx_clk_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3);
298
+
clks[IMX6SX_CLK_QSPI2_PODF] = imx_clk_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6);
299
+
clks[IMX6SX_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
300
+
clks[IMX6SX_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
301
+
clks[IMX6SX_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
302
+
clks[IMX6SX_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
303
+
clks[IMX6SX_CLK_AUDIO_PRED] = imx_clk_divider("audio_pred", "audio_sel", base + 0x30, 12, 3);
304
+
clks[IMX6SX_CLK_AUDIO_PODF] = imx_clk_divider("audio_podf", "audio_pred", base + 0x30, 9, 3);
305
+
clks[IMX6SX_CLK_ENET_PODF] = imx_clk_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3);
306
+
clks[IMX6SX_CLK_M4_PODF] = imx_clk_divider("m4_podf", "m4_sel", base + 0x34, 3, 3);
307
+
clks[IMX6SX_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
308
+
clks[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3);
309
+
clks[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3);
310
+
clks[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_divider("display_podf", "display_sel", base + 0x3c, 16, 3);
311
+
clks[IMX6SX_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
312
+
clks[IMX6SX_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
313
+
clks[IMX6SX_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
314
+
315
+
clks[IMX6SX_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
316
+
clks[IMX6SX_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
317
+
clks[IMX6SX_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
318
+
clks[IMX6SX_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
319
+
320
+
/* name reg shift width busy: reg, shift parent_names num_parents */
321
+
clks[IMX6SX_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
322
+
clks[IMX6SX_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
323
+
/* name parent_name reg shift width busy: reg, shift */
324
+
clks[IMX6SX_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
325
+
clks[IMX6SX_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
326
+
clks[IMX6SX_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
327
+
clks[IMX6SX_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
328
+
329
+
/* name parent_name reg shift */
330
+
/* CCGR0 */
331
+
clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
332
+
clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
333
+
clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
334
+
clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
335
+
clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
336
+
clks[IMX6SX_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
337
+
clks[IMX6SX_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
338
+
clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
339
+
clks[IMX6SX_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
340
+
clks[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
341
+
clks[IMX6SX_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
342
+
clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
343
+
clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24);
344
+
clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26);
345
+
clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
346
+
347
+
/* CCGR1 */
348
+
clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
349
+
clks[IMX6SX_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
350
+
clks[IMX6SX_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
351
+
clks[IMX6SX_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
352
+
clks[IMX6SX_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8);
353
+
clks[IMX6SX_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
354
+
clks[IMX6SX_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
355
+
clks[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
356
+
clks[IMX6SX_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
357
+
clks[IMX6SX_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
358
+
clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18);
359
+
clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20);
360
+
clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
361
+
clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
362
+
clks[IMX6SX_CLK_CANFD] = imx_clk_gate2("canfd", "can_podf", base + 0x6c, 30);
363
+
364
+
/* CCGR2 */
365
+
clks[IMX6SX_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2);
366
+
clks[IMX6SX_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
367
+
clks[IMX6SX_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
368
+
clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
369
+
clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
370
+
clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14);
371
+
clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16);
372
+
clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18);
373
+
clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20);
374
+
clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22);
375
+
clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28);
376
+
clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30);
377
+
378
+
/* CCGR3 */
379
+
clks[IMX6SX_CLK_M4] = imx_clk_gate2("m4", "m4_podf", base + 0x74, 2);
380
+
clks[IMX6SX_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4);
381
+
clks[IMX6SX_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "enet_sel", base + 0x74, 4);
382
+
clks[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_gate2("display_axi", "display_podf", base + 0x74, 6);
383
+
clks[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8);
384
+
clks[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10);
385
+
clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
386
+
clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
387
+
clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18);
388
+
clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
389
+
clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
390
+
clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
391
+
392
+
/* CCGR4 */
393
+
clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0);
394
+
clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10);
395
+
clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
396
+
clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
397
+
clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
398
+
clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
399
+
clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
400
+
clks[IMX6SX_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
401
+
clks[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
402
+
clks[IMX6SX_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
403
+
clks[IMX6SX_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28);
404
+
clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
405
+
406
+
/* CCGR5 */
407
+
clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
408
+
clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
409
+
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
410
+
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
411
+
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
412
+
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
413
+
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
414
+
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
415
+
clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
416
+
clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
417
+
clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
418
+
clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
419
+
clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
420
+
clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28);
421
+
clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2("sai2_ipg", "ipg", base + 0x7c, 30);
422
+
clks[IMX6SX_CLK_SAI1] = imx_clk_gate2("sai1", "ssi1_podf", base + 0x7c, 28);
423
+
clks[IMX6SX_CLK_SAI2] = imx_clk_gate2("sai2", "ssi2_podf", base + 0x7c, 30);
424
+
425
+
/* CCGR6 */
426
+
clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
427
+
clks[IMX6SX_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
428
+
clks[IMX6SX_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
429
+
clks[IMX6SX_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
430
+
clks[IMX6SX_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
431
+
clks[IMX6SX_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
432
+
clks[IMX6SX_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16);
433
+
clks[IMX6SX_CLK_VADC] = imx_clk_gate2("vadc", "vid_podf", base + 0x80, 20);
434
+
clks[IMX6SX_CLK_GIS] = imx_clk_gate2("gis", "display_podf", base + 0x80, 22);
435
+
clks[IMX6SX_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24);
436
+
clks[IMX6SX_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26);
437
+
clks[IMX6SX_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
438
+
clks[IMX6SX_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30);
439
+
440
+
clks[IMX6SX_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
441
+
clks[IMX6SX_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
442
+
443
+
/* mask handshake of mmdc */
444
+
writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
445
+
446
+
for (i = 0; i < ARRAY_SIZE(clks); i++)
447
+
if (IS_ERR(clks[i]))
448
+
pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
449
+
450
+
clk_data.clks = clks;
451
+
clk_data.clk_num = ARRAY_SIZE(clks);
452
+
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
453
+
454
+
clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
455
+
clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
456
+
457
+
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
458
+
clk_prepare_enable(clks[clks_init_on[i]]);
459
+
460
+
if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
461
+
clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
462
+
clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
463
+
}
464
+
465
+
/* Set the default 132MHz for EIM module */
466
+
clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
467
+
clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
468
+
469
+
/* set parent clock for LCDIF1 pixel clock */
470
+
clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
471
+
clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
472
+
473
+
/* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
474
+
if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]))
475
+
pr_err("Failed to set pcie bus parent clk.\n");
476
+
if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]))
477
+
pr_err("Failed to set pcie parent clk.\n");
478
+
479
+
/*
480
+
* Init enet system AHB clock, set to 200Mhz
481
+
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
482
+
*/
483
+
clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
484
+
clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
485
+
clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
486
+
clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
487
+
clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
488
+
489
+
/* Audio clocks */
490
+
clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
491
+
492
+
clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
493
+
clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
494
+
495
+
clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
496
+
clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
497
+
498
+
clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
499
+
clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
500
+
clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
501
+
clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
502
+
clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
503
+
clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
504
+
505
+
clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
506
+
clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
507
+
508
+
/* Set parent clock for vadc */
509
+
clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
510
+
511
+
/* default parent of can_sel clock is invalid, manually set it here */
512
+
clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
513
+
514
+
/* Update gpu clock from default 528M to 720M */
515
+
clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
516
+
clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
517
+
518
+
/* Set initial power mode */
519
+
imx6q_set_lpm(WAIT_CLOCKED);
520
+
521
+
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
522
+
mxc_timer_init_dt(np);
523
+
}
524
+
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
+256
include/dt-bindings/clock/imx6sx-clock.h
+256
include/dt-bindings/clock/imx6sx-clock.h
···
1
+
/*
2
+
* Copyright (C) 2014 Freescale Semiconductor, Inc.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify
5
+
* it under the terms of the GNU General Public License version 2 as
6
+
* published by the Free Software Foundation.
7
+
*
8
+
*/
9
+
10
+
#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
11
+
#define __DT_BINDINGS_CLOCK_IMX6SX_H
12
+
13
+
#define IMX6SX_CLK_DUMMY 0
14
+
#define IMX6SX_CLK_CKIL 1
15
+
#define IMX6SX_CLK_CKIH 2
16
+
#define IMX6SX_CLK_OSC 3
17
+
#define IMX6SX_CLK_PLL1_SYS 4
18
+
#define IMX6SX_CLK_PLL2_BUS 5
19
+
#define IMX6SX_CLK_PLL3_USB_OTG 6
20
+
#define IMX6SX_CLK_PLL4_AUDIO 7
21
+
#define IMX6SX_CLK_PLL5_VIDEO 8
22
+
#define IMX6SX_CLK_PLL6_ENET 9
23
+
#define IMX6SX_CLK_PLL7_USB_HOST 10
24
+
#define IMX6SX_CLK_USBPHY1 11
25
+
#define IMX6SX_CLK_USBPHY2 12
26
+
#define IMX6SX_CLK_USBPHY1_GATE 13
27
+
#define IMX6SX_CLK_USBPHY2_GATE 14
28
+
#define IMX6SX_CLK_PCIE_REF 15
29
+
#define IMX6SX_CLK_PCIE_REF_125M 16
30
+
#define IMX6SX_CLK_ENET_REF 17
31
+
#define IMX6SX_CLK_PLL2_PFD0 18
32
+
#define IMX6SX_CLK_PLL2_PFD1 19
33
+
#define IMX6SX_CLK_PLL2_PFD2 20
34
+
#define IMX6SX_CLK_PLL2_PFD3 21
35
+
#define IMX6SX_CLK_PLL3_PFD0 22
36
+
#define IMX6SX_CLK_PLL3_PFD1 23
37
+
#define IMX6SX_CLK_PLL3_PFD2 24
38
+
#define IMX6SX_CLK_PLL3_PFD3 25
39
+
#define IMX6SX_CLK_PLL2_198M 26
40
+
#define IMX6SX_CLK_PLL3_120M 27
41
+
#define IMX6SX_CLK_PLL3_80M 28
42
+
#define IMX6SX_CLK_PLL3_60M 29
43
+
#define IMX6SX_CLK_TWD 30
44
+
#define IMX6SX_CLK_PLL4_POST_DIV 31
45
+
#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
46
+
#define IMX6SX_CLK_PLL5_POST_DIV 33
47
+
#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
48
+
#define IMX6SX_CLK_STEP 35
49
+
#define IMX6SX_CLK_PLL1_SW 36
50
+
#define IMX6SX_CLK_OCRAM_SEL 37
51
+
#define IMX6SX_CLK_PERIPH_PRE 38
52
+
#define IMX6SX_CLK_PERIPH2_PRE 39
53
+
#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
54
+
#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
55
+
#define IMX6SX_CLK_PCIE_AXI_SEL 42
56
+
#define IMX6SX_CLK_GPU_AXI_SEL 43
57
+
#define IMX6SX_CLK_GPU_CORE_SEL 44
58
+
#define IMX6SX_CLK_EIM_SLOW_SEL 45
59
+
#define IMX6SX_CLK_USDHC1_SEL 46
60
+
#define IMX6SX_CLK_USDHC2_SEL 47
61
+
#define IMX6SX_CLK_USDHC3_SEL 48
62
+
#define IMX6SX_CLK_USDHC4_SEL 49
63
+
#define IMX6SX_CLK_SSI1_SEL 50
64
+
#define IMX6SX_CLK_SSI2_SEL 51
65
+
#define IMX6SX_CLK_SSI3_SEL 52
66
+
#define IMX6SX_CLK_QSPI1_SEL 53
67
+
#define IMX6SX_CLK_PERCLK_SEL 54
68
+
#define IMX6SX_CLK_VID_SEL 55
69
+
#define IMX6SX_CLK_ESAI_SEL 56
70
+
#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
71
+
#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
72
+
#define IMX6SX_CLK_CAN_SEL 59
73
+
#define IMX6SX_CLK_UART_SEL 60
74
+
#define IMX6SX_CLK_QSPI2_SEL 61
75
+
#define IMX6SX_CLK_LDB_DI1_SEL 62
76
+
#define IMX6SX_CLK_LDB_DI0_SEL 63
77
+
#define IMX6SX_CLK_SPDIF_SEL 64
78
+
#define IMX6SX_CLK_AUDIO_SEL 65
79
+
#define IMX6SX_CLK_ENET_PRE_SEL 66
80
+
#define IMX6SX_CLK_ENET_SEL 67
81
+
#define IMX6SX_CLK_M4_PRE_SEL 68
82
+
#define IMX6SX_CLK_M4_SEL 69
83
+
#define IMX6SX_CLK_ECSPI_SEL 70
84
+
#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
85
+
#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
86
+
#define IMX6SX_CLK_LCDIF1_SEL 73
87
+
#define IMX6SX_CLK_LCDIF2_SEL 74
88
+
#define IMX6SX_CLK_DISPLAY_SEL 75
89
+
#define IMX6SX_CLK_CSI_SEL 76
90
+
#define IMX6SX_CLK_CKO1_SEL 77
91
+
#define IMX6SX_CLK_CKO2_SEL 78
92
+
#define IMX6SX_CLK_CKO 79
93
+
#define IMX6SX_CLK_PERIPH_CLK2 80
94
+
#define IMX6SX_CLK_PERIPH2_CLK2 81
95
+
#define IMX6SX_CLK_IPG 82
96
+
#define IMX6SX_CLK_GPU_CORE_PODF 83
97
+
#define IMX6SX_CLK_GPU_AXI_PODF 84
98
+
#define IMX6SX_CLK_LCDIF1_PODF 85
99
+
#define IMX6SX_CLK_QSPI1_PODF 86
100
+
#define IMX6SX_CLK_EIM_SLOW_PODF 87
101
+
#define IMX6SX_CLK_LCDIF2_PODF 88
102
+
#define IMX6SX_CLK_PERCLK 89
103
+
#define IMX6SX_CLK_VID_PODF 90
104
+
#define IMX6SX_CLK_CAN_PODF 91
105
+
#define IMX6SX_CLK_USDHC1_PODF 92
106
+
#define IMX6SX_CLK_USDHC2_PODF 93
107
+
#define IMX6SX_CLK_USDHC3_PODF 94
108
+
#define IMX6SX_CLK_USDHC4_PODF 95
109
+
#define IMX6SX_CLK_UART_PODF 96
110
+
#define IMX6SX_CLK_ESAI_PRED 97
111
+
#define IMX6SX_CLK_ESAI_PODF 98
112
+
#define IMX6SX_CLK_SSI3_PRED 99
113
+
#define IMX6SX_CLK_SSI3_PODF 100
114
+
#define IMX6SX_CLK_SSI1_PRED 101
115
+
#define IMX6SX_CLK_SSI1_PODF 102
116
+
#define IMX6SX_CLK_QSPI2_PRED 103
117
+
#define IMX6SX_CLK_QSPI2_PODF 104
118
+
#define IMX6SX_CLK_SSI2_PRED 105
119
+
#define IMX6SX_CLK_SSI2_PODF 106
120
+
#define IMX6SX_CLK_SPDIF_PRED 107
121
+
#define IMX6SX_CLK_SPDIF_PODF 108
122
+
#define IMX6SX_CLK_AUDIO_PRED 109
123
+
#define IMX6SX_CLK_AUDIO_PODF 110
124
+
#define IMX6SX_CLK_ENET_PODF 111
125
+
#define IMX6SX_CLK_M4_PODF 112
126
+
#define IMX6SX_CLK_ECSPI_PODF 113
127
+
#define IMX6SX_CLK_LCDIF1_PRED 114
128
+
#define IMX6SX_CLK_LCDIF2_PRED 115
129
+
#define IMX6SX_CLK_DISPLAY_PODF 116
130
+
#define IMX6SX_CLK_CSI_PODF 117
131
+
#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
132
+
#define IMX6SX_CLK_LDB_DI0_DIV_7 119
133
+
#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
134
+
#define IMX6SX_CLK_LDB_DI1_DIV_7 121
135
+
#define IMX6SX_CLK_CKO1_PODF 122
136
+
#define IMX6SX_CLK_CKO2_PODF 123
137
+
#define IMX6SX_CLK_PERIPH 124
138
+
#define IMX6SX_CLK_PERIPH2 125
139
+
#define IMX6SX_CLK_OCRAM 126
140
+
#define IMX6SX_CLK_AHB 127
141
+
#define IMX6SX_CLK_MMDC_PODF 128
142
+
#define IMX6SX_CLK_ARM 129
143
+
#define IMX6SX_CLK_AIPS_TZ1 130
144
+
#define IMX6SX_CLK_AIPS_TZ2 131
145
+
#define IMX6SX_CLK_APBH_DMA 132
146
+
#define IMX6SX_CLK_ASRC_GATE 133
147
+
#define IMX6SX_CLK_CAAM_MEM 134
148
+
#define IMX6SX_CLK_CAAM_ACLK 135
149
+
#define IMX6SX_CLK_CAAM_IPG 136
150
+
#define IMX6SX_CLK_CAN1_IPG 137
151
+
#define IMX6SX_CLK_CAN1_SERIAL 138
152
+
#define IMX6SX_CLK_CAN2_IPG 139
153
+
#define IMX6SX_CLK_CAN2_SERIAL 140
154
+
#define IMX6SX_CLK_CPU_DEBUG 141
155
+
#define IMX6SX_CLK_DCIC1 142
156
+
#define IMX6SX_CLK_DCIC2 143
157
+
#define IMX6SX_CLK_AIPS_TZ3 144
158
+
#define IMX6SX_CLK_ECSPI1 145
159
+
#define IMX6SX_CLK_ECSPI2 146
160
+
#define IMX6SX_CLK_ECSPI3 147
161
+
#define IMX6SX_CLK_ECSPI4 148
162
+
#define IMX6SX_CLK_ECSPI5 149
163
+
#define IMX6SX_CLK_EPIT1 150
164
+
#define IMX6SX_CLK_EPIT2 151
165
+
#define IMX6SX_CLK_ESAI_EXTAL 152
166
+
#define IMX6SX_CLK_WAKEUP 153
167
+
#define IMX6SX_CLK_GPT_BUS 154
168
+
#define IMX6SX_CLK_GPT_SERIAL 155
169
+
#define IMX6SX_CLK_GPU 156
170
+
#define IMX6SX_CLK_OCRAM_S 157
171
+
#define IMX6SX_CLK_CANFD 158
172
+
#define IMX6SX_CLK_CSI 159
173
+
#define IMX6SX_CLK_I2C1 160
174
+
#define IMX6SX_CLK_I2C2 161
175
+
#define IMX6SX_CLK_I2C3 162
176
+
#define IMX6SX_CLK_OCOTP 163
177
+
#define IMX6SX_CLK_IOMUXC 164
178
+
#define IMX6SX_CLK_IPMUX1 165
179
+
#define IMX6SX_CLK_IPMUX2 166
180
+
#define IMX6SX_CLK_IPMUX3 167
181
+
#define IMX6SX_CLK_TZASC1 168
182
+
#define IMX6SX_CLK_LCDIF_APB 169
183
+
#define IMX6SX_CLK_PXP_AXI 170
184
+
#define IMX6SX_CLK_M4 171
185
+
#define IMX6SX_CLK_ENET 172
186
+
#define IMX6SX_CLK_DISPLAY_AXI 173
187
+
#define IMX6SX_CLK_LCDIF2_PIX 174
188
+
#define IMX6SX_CLK_LCDIF1_PIX 175
189
+
#define IMX6SX_CLK_LDB_DI0 176
190
+
#define IMX6SX_CLK_QSPI1 177
191
+
#define IMX6SX_CLK_MLB 178
192
+
#define IMX6SX_CLK_MMDC_P0_FAST 179
193
+
#define IMX6SX_CLK_MMDC_P0_IPG 180
194
+
#define IMX6SX_CLK_AXI 181
195
+
#define IMX6SX_CLK_PCIE_AXI 182
196
+
#define IMX6SX_CLK_QSPI2 183
197
+
#define IMX6SX_CLK_PER1_BCH 184
198
+
#define IMX6SX_CLK_PER2_MAIN 185
199
+
#define IMX6SX_CLK_PWM1 186
200
+
#define IMX6SX_CLK_PWM2 187
201
+
#define IMX6SX_CLK_PWM3 188
202
+
#define IMX6SX_CLK_PWM4 189
203
+
#define IMX6SX_CLK_GPMI_BCH_APB 190
204
+
#define IMX6SX_CLK_GPMI_BCH 191
205
+
#define IMX6SX_CLK_GPMI_IO 192
206
+
#define IMX6SX_CLK_GPMI_APB 193
207
+
#define IMX6SX_CLK_ROM 194
208
+
#define IMX6SX_CLK_SDMA 195
209
+
#define IMX6SX_CLK_SPBA 196
210
+
#define IMX6SX_CLK_SPDIF 197
211
+
#define IMX6SX_CLK_SSI1_IPG 198
212
+
#define IMX6SX_CLK_SSI2_IPG 199
213
+
#define IMX6SX_CLK_SSI3_IPG 200
214
+
#define IMX6SX_CLK_SSI1 201
215
+
#define IMX6SX_CLK_SSI2 202
216
+
#define IMX6SX_CLK_SSI3 203
217
+
#define IMX6SX_CLK_UART_IPG 204
218
+
#define IMX6SX_CLK_UART_SERIAL 205
219
+
#define IMX6SX_CLK_SAI1 206
220
+
#define IMX6SX_CLK_SAI2 207
221
+
#define IMX6SX_CLK_USBOH3 208
222
+
#define IMX6SX_CLK_USDHC1 209
223
+
#define IMX6SX_CLK_USDHC2 210
224
+
#define IMX6SX_CLK_USDHC3 211
225
+
#define IMX6SX_CLK_USDHC4 212
226
+
#define IMX6SX_CLK_EIM_SLOW 213
227
+
#define IMX6SX_CLK_PWM8 214
228
+
#define IMX6SX_CLK_VADC 215
229
+
#define IMX6SX_CLK_GIS 216
230
+
#define IMX6SX_CLK_I2C4 217
231
+
#define IMX6SX_CLK_PWM5 218
232
+
#define IMX6SX_CLK_PWM6 219
233
+
#define IMX6SX_CLK_PWM7 220
234
+
#define IMX6SX_CLK_CKO1 221
235
+
#define IMX6SX_CLK_CKO2 222
236
+
#define IMX6SX_CLK_IPP_DI0 223
237
+
#define IMX6SX_CLK_IPP_DI1 224
238
+
#define IMX6SX_CLK_ENET_AHB 225
239
+
#define IMX6SX_CLK_OCRAM_PODF 226
240
+
#define IMX6SX_CLK_GPT_3M 227
241
+
#define IMX6SX_CLK_ENET_PTP 228
242
+
#define IMX6SX_CLK_ENET_PTP_REF 229
243
+
#define IMX6SX_CLK_ENET2_REF 230
244
+
#define IMX6SX_CLK_ENET2_REF_125M 231
245
+
#define IMX6SX_CLK_AUDIO 232
246
+
#define IMX6SX_CLK_LVDS1_SEL 233
247
+
#define IMX6SX_CLK_LVDS1_OUT 234
248
+
#define IMX6SX_CLK_ASRC_IPG 235
249
+
#define IMX6SX_CLK_ASRC_MEM 236
250
+
#define IMX6SX_CLK_SAI1_IPG 237
251
+
#define IMX6SX_CLK_SAI2_IPG 238
252
+
#define IMX6SX_CLK_ESAI_IPG 239
253
+
#define IMX6SX_CLK_ESAI_MEM 240
254
+
#define IMX6SX_CLK_CLK_END 241
255
+
256
+
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */