drm/i915: Move display device info capabilities to its own struct

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

This helps separate what capabilities are display capabilities.

v3: Moving display struct right after flags (Lucas)

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181130232048.14216-2-jose.souza@intel.com

José Roberto de Souza 7 years ago d53db442 e1bf094b

+103 -78

6 changed files

expand all

drivers

gpu

drm

i915

i915_drv.h

i915_pci.c

intel_device_info.c

intel_device_info.h

intel_display.c

intel_fbc.c

+11 -11

drivers/gpu/drm/i915/i915_drv.h

··· 2449 2449 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ 2450 2450 }) 2451 2451 2452 - #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) 2452 + #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay) 2453 2453 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ 2454 - ((dev_priv)->info.overlay_needs_physical) 2454 + ((dev_priv)->info.display.overlay_needs_physical) 2455 2455 2456 2456 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2457 2457 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) ··· 2472 2472 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ 2473 2473 !(IS_I915G(dev_priv) || \ 2474 2474 IS_I915GM(dev_priv))) 2475 - #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) 2476 - #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) 2475 + #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv) 2476 + #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug) 2477 2477 2478 2478 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) 2479 - #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) 2479 + #define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc) 2480 2480 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) 2481 2481 2482 2482 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) 2483 2483 2484 - #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) 2484 + #define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst) 2485 2485 2486 - #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) 2486 + #define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi) 2487 2487 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) 2488 - #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) 2488 + #define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr) 2489 2489 2490 2490 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) 2491 2491 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) 2492 2492 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ 2493 2493 2494 - #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) 2494 + #define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr) 2495 2495 2496 2496 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) 2497 2497 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) 2498 2498 2499 - #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) 2499 + #define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc) 2500 2500 2501 2501 /* 2502 2502 * For now, anything with a GuC requires uCode loading, and then supports ··· 2557 2557 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) 2558 2558 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) 2559 2559 2560 - #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) 2560 + #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display) 2561 2561 2562 2562 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) 2563 2563

+64 -53

drivers/gpu/drm/i915/i915_pci.c

··· 79 79 #define GEN2_FEATURES \ 80 80 GEN(2), \ 81 81 .num_pipes = 1, \ 82 - .has_overlay = 1, .overlay_needs_physical = 1, \ 83 - .has_gmch_display = 1, \ 82 + .display.has_overlay = 1, \ 83 + .display.overlay_needs_physical = 1, \ 84 + .display.has_gmch_display = 1, \ 84 85 .hws_needs_physical = 1, \ 85 86 .unfenced_needs_alignment = 1, \ 86 87 .ring_mask = RENDER_RING, \ ··· 94 93 static const struct intel_device_info intel_i830_info = { 95 94 GEN2_FEATURES, 96 95 PLATFORM(INTEL_I830), 97 - .is_mobile = 1, .cursor_needs_physical = 1, 96 + .is_mobile = 1, 97 + .display.cursor_needs_physical = 1, 98 98 .num_pipes = 2, /* legal, last one wins */ 99 99 }; 100 100 ··· 109 107 PLATFORM(INTEL_I85X), 110 108 .is_mobile = 1, 111 109 .num_pipes = 2, /* legal, last one wins */ 112 - .cursor_needs_physical = 1, 113 - .has_fbc = 1, 110 + .display.cursor_needs_physical = 1, 111 + .display.has_fbc = 1, 114 112 }; 115 113 116 114 static const struct intel_device_info intel_i865g_info = { ··· 121 119 #define GEN3_FEATURES \ 122 120 GEN(3), \ 123 121 .num_pipes = 2, \ 124 - .has_gmch_display = 1, \ 122 + .display.has_gmch_display = 1, \ 125 123 .ring_mask = RENDER_RING, \ 126 124 .has_snoop = true, \ 127 125 .has_coherent_ggtt = true, \ ··· 133 131 GEN3_FEATURES, 134 132 PLATFORM(INTEL_I915G), 135 133 .has_coherent_ggtt = false, 136 - .cursor_needs_physical = 1, 137 - .has_overlay = 1, .overlay_needs_physical = 1, 134 + .display.cursor_needs_physical = 1, 135 + .display.has_overlay = 1, 136 + .display.overlay_needs_physical = 1, 138 137 .hws_needs_physical = 1, 139 138 .unfenced_needs_alignment = 1, 140 139 }; ··· 144 141 GEN3_FEATURES, 145 142 PLATFORM(INTEL_I915GM), 146 143 .is_mobile = 1, 147 - .cursor_needs_physical = 1, 148 - .has_overlay = 1, .overlay_needs_physical = 1, 149 - .supports_tv = 1, 150 - .has_fbc = 1, 144 + .display.cursor_needs_physical = 1, 145 + .display.has_overlay = 1, 146 + .display.overlay_needs_physical = 1, 147 + .display.supports_tv = 1, 148 + .display.has_fbc = 1, 151 149 .hws_needs_physical = 1, 152 150 .unfenced_needs_alignment = 1, 153 151 }; ··· 156 152 static const struct intel_device_info intel_i945g_info = { 157 153 GEN3_FEATURES, 158 154 PLATFORM(INTEL_I945G), 159 - .has_hotplug = 1, .cursor_needs_physical = 1, 160 - .has_overlay = 1, .overlay_needs_physical = 1, 155 + .display.has_hotplug = 1, 156 + .display.cursor_needs_physical = 1, 157 + .display.has_overlay = 1, 158 + .display.overlay_needs_physical = 1, 161 159 .hws_needs_physical = 1, 162 160 .unfenced_needs_alignment = 1, 163 161 }; ··· 168 162 GEN3_FEATURES, 169 163 PLATFORM(INTEL_I945GM), 170 164 .is_mobile = 1, 171 - .has_hotplug = 1, .cursor_needs_physical = 1, 172 - .has_overlay = 1, .overlay_needs_physical = 1, 173 - .supports_tv = 1, 174 - .has_fbc = 1, 165 + .display.has_hotplug = 1, 166 + .display.cursor_needs_physical = 1, 167 + .display.has_overlay = 1, 168 + .display.overlay_needs_physical = 1, 169 + .display.supports_tv = 1, 170 + .display.has_fbc = 1, 175 171 .hws_needs_physical = 1, 176 172 .unfenced_needs_alignment = 1, 177 173 }; ··· 181 173 static const struct intel_device_info intel_g33_info = { 182 174 GEN3_FEATURES, 183 175 PLATFORM(INTEL_G33), 184 - .has_hotplug = 1, 185 - .has_overlay = 1, 176 + .display.has_hotplug = 1, 177 + .display.has_overlay = 1, 186 178 }; 187 179 188 180 static const struct intel_device_info intel_pineview_info = { 189 181 GEN3_FEATURES, 190 182 PLATFORM(INTEL_PINEVIEW), 191 183 .is_mobile = 1, 192 - .has_hotplug = 1, 193 - .has_overlay = 1, 184 + .display.has_hotplug = 1, 185 + .display.has_overlay = 1, 194 186 }; 195 187 196 188 #define GEN4_FEATURES \ 197 189 GEN(4), \ 198 190 .num_pipes = 2, \ 199 - .has_hotplug = 1, \ 200 - .has_gmch_display = 1, \ 191 + .display.has_hotplug = 1, \ 192 + .display.has_gmch_display = 1, \ 201 193 .ring_mask = RENDER_RING, \ 202 194 .has_snoop = true, \ 203 195 .has_coherent_ggtt = true, \ ··· 208 200 static const struct intel_device_info intel_i965g_info = { 209 201 GEN4_FEATURES, 210 202 PLATFORM(INTEL_I965G), 211 - .has_overlay = 1, 203 + .display.has_overlay = 1, 212 204 .hws_needs_physical = 1, 213 205 .has_snoop = false, 214 206 }; ··· 216 208 static const struct intel_device_info intel_i965gm_info = { 217 209 GEN4_FEATURES, 218 210 PLATFORM(INTEL_I965GM), 219 - .is_mobile = 1, .has_fbc = 1, 220 - .has_overlay = 1, 221 - .supports_tv = 1, 211 + .is_mobile = 1, 212 + .display.has_fbc = 1, 213 + .display.has_overlay = 1, 214 + .display.supports_tv = 1, 222 215 .hws_needs_physical = 1, 223 216 .has_snoop = false, 224 217 }; ··· 233 224 static const struct intel_device_info intel_gm45_info = { 234 225 GEN4_FEATURES, 235 226 PLATFORM(INTEL_GM45), 236 - .is_mobile = 1, .has_fbc = 1, 237 - .supports_tv = 1, 227 + .is_mobile = 1, 228 + .display.has_fbc = 1, 229 + .display.supports_tv = 1, 238 230 .ring_mask = RENDER_RING | BSD_RING, 239 231 }; 240 232 241 233 #define GEN5_FEATURES \ 242 234 GEN(5), \ 243 235 .num_pipes = 2, \ 244 - .has_hotplug = 1, \ 236 + .display.has_hotplug = 1, \ 245 237 .ring_mask = RENDER_RING | BSD_RING, \ 246 238 .has_snoop = true, \ 247 239 .has_coherent_ggtt = true, \ ··· 260 250 static const struct intel_device_info intel_ironlake_m_info = { 261 251 GEN5_FEATURES, 262 252 PLATFORM(INTEL_IRONLAKE), 263 - .is_mobile = 1, .has_fbc = 1, 253 + .is_mobile = 1, 254 + .display.has_fbc = 1, 264 255 }; 265 256 266 257 #define GEN6_FEATURES \ 267 258 GEN(6), \ 268 259 .num_pipes = 2, \ 269 - .has_hotplug = 1, \ 270 - .has_fbc = 1, \ 260 + .display.has_hotplug = 1, \ 261 + .display.has_fbc = 1, \ 271 262 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 272 263 .has_coherent_ggtt = true, \ 273 264 .has_llc = 1, \ ··· 312 301 #define GEN7_FEATURES \ 313 302 GEN(7), \ 314 303 .num_pipes = 3, \ 315 - .has_hotplug = 1, \ 316 - .has_fbc = 1, \ 304 + .display.has_hotplug = 1, \ 305 + .display.has_fbc = 1, \ 317 306 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 318 307 .has_coherent_ggtt = true, \ 319 308 .has_llc = 1, \ ··· 370 359 .num_pipes = 2, 371 360 .has_runtime_pm = 1, 372 361 .has_rc6 = 1, 373 - .has_gmch_display = 1, 374 - .has_hotplug = 1, 362 + .display.has_gmch_display = 1, 363 + .display.has_hotplug = 1, 375 364 .ppgtt = INTEL_PPGTT_FULL, 376 365 .has_snoop = true, 377 366 .has_coherent_ggtt = false, ··· 385 374 #define G75_FEATURES \ 386 375 GEN7_FEATURES, \ 387 376 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 388 - .has_ddi = 1, \ 377 + .display.has_ddi = 1, \ 389 378 .has_fpga_dbg = 1, \ 390 - .has_psr = 1, \ 391 - .has_dp_mst = 1, \ 379 + .display.has_psr = 1, \ 380 + .display.has_dp_mst = 1, \ 392 381 .has_rc6p = 0 /* RC6p removed-by HSW */, \ 393 382 .has_runtime_pm = 1 394 383 ··· 455 444 PLATFORM(INTEL_CHERRYVIEW), 456 445 GEN(8), 457 446 .num_pipes = 3, 458 - .has_hotplug = 1, 447 + .display.has_hotplug = 1, 459 448 .is_lp = 1, 460 449 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 461 450 .has_64bit_reloc = 1, 462 451 .has_runtime_pm = 1, 463 452 .has_rc6 = 1, 464 453 .has_logical_ring_contexts = 1, 465 - .has_gmch_display = 1, 454 + .display.has_gmch_display = 1, 466 455 .ppgtt = INTEL_PPGTT_FULL, 467 456 .has_reset_engine = 1, 468 457 .has_snoop = true, ··· 484 473 GEN(9), \ 485 474 GEN9_DEFAULT_PAGE_SIZES, \ 486 475 .has_logical_ring_preemption = 1, \ 487 - .has_csr = 1, \ 476 + .display.has_csr = 1, \ 488 477 .has_guc = 1, \ 489 - .has_ipc = 1, \ 478 + .display.has_ipc = 1, \ 490 479 .ddb_size = 896 491 480 492 481 #define SKL_PLATFORM \ 493 482 GEN9_FEATURES, \ 494 483 /* Display WA #0477 WaDisableIPC: skl */ \ 495 - .has_ipc = 0, \ 484 + .display.has_ipc = 0, \ 496 485 PLATFORM(INTEL_SKYLAKE) 497 486 498 487 static const struct intel_device_info intel_skylake_gt1_info = { ··· 523 512 #define GEN9_LP_FEATURES \ 524 513 GEN(9), \ 525 514 .is_lp = 1, \ 526 - .has_hotplug = 1, \ 515 + .display.has_hotplug = 1, \ 527 516 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 528 517 .num_pipes = 3, \ 529 518 .has_64bit_reloc = 1, \ 530 - .has_ddi = 1, \ 519 + .display.has_ddi = 1, \ 531 520 .has_fpga_dbg = 1, \ 532 - .has_fbc = 1, \ 533 - .has_psr = 1, \ 521 + .display.has_fbc = 1, \ 522 + .display.has_psr = 1, \ 534 523 .has_runtime_pm = 1, \ 535 524 .has_pooled_eu = 0, \ 536 - .has_csr = 1, \ 525 + .display.has_csr = 1, \ 537 526 .has_rc6 = 1, \ 538 - .has_dp_mst = 1, \ 527 + .display.has_dp_mst = 1, \ 539 528 .has_logical_ring_contexts = 1, \ 540 529 .has_logical_ring_preemption = 1, \ 541 530 .has_guc = 1, \ ··· 543 532 .has_reset_engine = 1, \ 544 533 .has_snoop = true, \ 545 534 .has_coherent_ggtt = false, \ 546 - .has_ipc = 1, \ 535 + .display.has_ipc = 1, \ 547 536 GEN9_DEFAULT_PAGE_SIZES, \ 548 537 GEN_DEFAULT_PIPEOFFSETS, \ 549 538 IVB_CURSOR_OFFSETS, \

drivers/gpu/drm/i915/intel_device_info.c

··· 77 77 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name)); 78 78 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 79 79 #undef PRINT_FLAG 80 + 81 + #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name)); 82 + DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 83 + #undef PRINT_FLAG 80 84 } 81 85 82 86 static void sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p)

+21 -11

drivers/gpu/drm/i915/intel_device_info.h

··· 89 89 func(is_alpha_support); \ 90 90 /* Keep has_* in alphabetical order */ \ 91 91 func(has_64bit_reloc); \ 92 - func(has_csr); \ 93 - func(has_ddi); \ 94 - func(has_dp_mst); \ 95 92 func(has_reset_engine); \ 96 - func(has_fbc); \ 97 93 func(has_fpga_dbg); \ 98 - func(has_gmch_display); \ 99 94 func(has_guc); \ 100 95 func(has_guc_ct); \ 101 - func(has_hotplug); \ 102 96 func(has_l3_dpf); \ 103 97 func(has_llc); \ 104 98 func(has_logical_ring_contexts); \ 105 99 func(has_logical_ring_elsq); \ 106 100 func(has_logical_ring_preemption); \ 107 - func(has_overlay); \ 108 101 func(has_pooled_eu); \ 109 - func(has_psr); \ 110 102 func(has_rc6); \ 111 103 func(has_rc6p); \ 112 104 func(has_runtime_pm); \ 113 105 func(has_snoop); \ 114 106 func(has_coherent_ggtt); \ 115 107 func(unfenced_needs_alignment); \ 108 + func(hws_needs_physical); 109 + 110 + #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 111 + /* Keep in alphabetical order */ \ 116 112 func(cursor_needs_physical); \ 117 - func(hws_needs_physical); \ 113 + func(has_csr); \ 114 + func(has_ddi); \ 115 + func(has_dp_mst); \ 116 + func(has_fbc); \ 117 + func(has_gmch_display); \ 118 + func(has_hotplug); \ 119 + func(has_ipc); \ 120 + func(has_overlay); \ 121 + func(has_psr); \ 118 122 func(overlay_needs_physical); \ 119 - func(supports_tv); \ 120 - func(has_ipc); 123 + func(supports_tv); 121 124 122 125 #define GEN_MAX_SLICES (6) /* CNL upper bound */ 123 126 #define GEN_MAX_SUBSLICES (8) /* ICL upper bound */ ··· 175 172 #define DEFINE_FLAG(name) u8 name:1 176 173 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 177 174 #undef DEFINE_FLAG 175 + 176 + struct { 177 + #define DEFINE_FLAG(name) u8 name:1 178 + DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 179 + #undef DEFINE_FLAG 180 + } display; 181 + 178 182 u16 ddb_size; /* in blocks */ 179 183 180 184 /* Register offsets for the various display pipes and transcoders */

+2 -2

drivers/gpu/drm/i915/intel_display.c

··· 9717 9717 const struct drm_i915_gem_object *obj = intel_fb_obj(fb); 9718 9718 u32 base; 9719 9719 9720 - if (INTEL_INFO(dev_priv)->cursor_needs_physical) 9720 + if (INTEL_INFO(dev_priv)->display.cursor_needs_physical) 9721 9721 base = obj->phys_handle->busaddr; 9722 9722 else 9723 9723 base = intel_plane_ggtt_offset(plane_state); ··· 13303 13303 struct i915_vma *vma; 13304 13304 13305 13305 if (plane->id == PLANE_CURSOR && 13306 - INTEL_INFO(dev_priv)->cursor_needs_physical) { 13306 + INTEL_INFO(dev_priv)->display.cursor_needs_physical) { 13307 13307 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 13308 13308 const int align = intel_cursor_alignment(dev_priv); 13309 13309 int err;

+1 -1

drivers/gpu/drm/i915/intel_fbc.c

··· 1309 1309 fbc->active = false; 1310 1310 1311 1311 if (need_fbc_vtd_wa(dev_priv)) 1312 - mkwrite_device_info(dev_priv)->has_fbc = false; 1312 + mkwrite_device_info(dev_priv)->display.has_fbc = false; 1313 1313 1314 1314 i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv); 1315 1315 DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",