tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ASoC: wm2200: Add WM2200 CODEC driver
The WM2200 is a low power mobile CODEC with enhanced Wolfson myZone
Ambient Noise Cancellation (ANC) intended for mobile telephony
applications.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+6006
+41
include/sound/wm2200.h
+41
include/sound/wm2200.h
···
1
+
/*
2
+
* linux/sound/wm2200.h -- Platform data for WM2200
3
+
*
4
+
* Copyright 2012 Wolfson Microelectronics. PLC.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License version 2 as
8
+
* published by the Free Software Foundation.
9
+
*/
10
+
11
+
#ifndef __LINUX_SND_WM2200_H
12
+
#define __LINUX_SND_WM2200_H
13
+
14
+
#define WM2200_GPIO_SET 0x10000
15
+
16
+
enum wm2200_in_mode {
17
+
WM2200_IN_SE = 0,
18
+
WM2200_IN_DIFF = 1,
19
+
WM2200_IN_DMIC = 2,
20
+
};
21
+
22
+
enum wm2200_dmic_sup {
23
+
WM2200_DMIC_SUP_MICVDD = 0,
24
+
WM2200_DMIC_SUP_MICBIAS1 = 1,
25
+
WM2200_DMIC_SUP_MICBIAS2 = 2,
26
+
};
27
+
28
+
struct wm2200_pdata {
29
+
int reset; /** GPIO controlling /RESET, if any */
30
+
int ldo_ena; /** GPIO controlling LODENA, if any */
31
+
int irq_flags;
32
+
33
+
int gpio_defaults[4];
34
+
35
+
enum wm2200_in_mode in_mode[3];
36
+
enum wm2200_dmic_sup dmic_sup[3];
37
+
38
+
int micbias_cfg[2]; /** Register value to configure MICBIAS */
39
+
};
40
+
41
+
#endif
+4
sound/soc/codecs/Kconfig
+4
sound/soc/codecs/Kconfig
···
62
62
select SND_SOC_WL1273 if MFD_WL1273_CORE
63
63
select SND_SOC_WM1250_EV1 if I2C
64
64
select SND_SOC_WM2000 if I2C
65
+
select SND_SOC_WM2200 if I2C
65
66
select SND_SOC_WM5100 if I2C
66
67
select SND_SOC_WM8350 if MFD_WM8350
67
68
select SND_SOC_WM8400 if MFD_WM8400
···
291
290
tristate
292
291
293
292
config SND_SOC_WM2000
293
+
tristate
294
+
295
+
config SND_SOC_WM2200
294
296
tristate
295
297
296
298
config SND_SOC_WM5100
+2
sound/soc/codecs/Makefile
+2
sound/soc/codecs/Makefile
···
51
51
snd-soc-wl1273-objs := wl1273.o
52
52
snd-soc-wm1250-ev1-objs := wm1250-ev1.o
53
53
snd-soc-wm2000-objs := wm2000.o
54
+
snd-soc-wm2200-objs := wm2200.o
54
55
snd-soc-wm5100-objs := wm5100.o wm5100-tables.o
55
56
snd-soc-wm8350-objs := wm8350.o
56
57
snd-soc-wm8400-objs := wm8400.o
···
154
153
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
155
154
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
156
155
obj-$(CONFIG_SND_SOC_WM2000) += snd-soc-wm2000.o
156
+
obj-$(CONFIG_SND_SOC_WM2200) += snd-soc-wm2200.o
157
157
obj-$(CONFIG_SND_SOC_WM5100) += snd-soc-wm5100.o
158
158
obj-$(CONFIG_SND_SOC_WM8350) += snd-soc-wm8350.o
159
159
obj-$(CONFIG_SND_SOC_WM8400) += snd-soc-wm8400.o
+2285
sound/soc/codecs/wm2200.c
+2285
sound/soc/codecs/wm2200.c
···
1
+
/*
2
+
* wm2200.c -- WM2200 ALSA SoC Audio driver
3
+
*
4
+
* Copyright 2012 Wolfson Microelectronics plc
5
+
*
6
+
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7
+
*
8
+
* This program is free software; you can redistribute it and/or modify
9
+
* it under the terms of the GNU General Public License version 2 as
10
+
* published by the Free Software Foundation.
11
+
*/
12
+
13
+
#include <linux/module.h>
14
+
#include <linux/moduleparam.h>
15
+
#include <linux/init.h>
16
+
#include <linux/delay.h>
17
+
#include <linux/pm.h>
18
+
#include <linux/gcd.h>
19
+
#include <linux/gpio.h>
20
+
#include <linux/i2c.h>
21
+
#include <linux/pm_runtime.h>
22
+
#include <linux/regulator/consumer.h>
23
+
#include <linux/regulator/fixed.h>
24
+
#include <linux/slab.h>
25
+
#include <sound/core.h>
26
+
#include <sound/pcm.h>
27
+
#include <sound/pcm_params.h>
28
+
#include <sound/soc.h>
29
+
#include <sound/jack.h>
30
+
#include <sound/initval.h>
31
+
#include <sound/tlv.h>
32
+
#include <sound/wm2200.h>
33
+
34
+
#include "wm2200.h"
35
+
36
+
/* The code assumes DCVDD is generated internally */
37
+
#define WM2200_NUM_CORE_SUPPLIES 2
38
+
static const char *wm2200_core_supply_names[WM2200_NUM_CORE_SUPPLIES] = {
39
+
"DBVDD",
40
+
"LDOVDD",
41
+
};
42
+
43
+
struct wm2200_fll {
44
+
int fref;
45
+
int fout;
46
+
int src;
47
+
struct completion lock;
48
+
};
49
+
50
+
/* codec private data */
51
+
struct wm2200_priv {
52
+
struct regmap *regmap;
53
+
struct device *dev;
54
+
struct snd_soc_codec *codec;
55
+
struct wm2200_pdata pdata;
56
+
struct regulator_bulk_data core_supplies[WM2200_NUM_CORE_SUPPLIES];
57
+
58
+
struct completion fll_lock;
59
+
int fll_fout;
60
+
int fll_fref;
61
+
int fll_src;
62
+
63
+
int rev;
64
+
int sysclk;
65
+
};
66
+
67
+
static struct reg_default wm2200_reg_defaults[] = {
68
+
{ 0x000B, 0x0000 }, /* R11 - Tone Generator 1 */
69
+
{ 0x0102, 0x0000 }, /* R258 - Clocking 3 */
70
+
{ 0x0103, 0x0011 }, /* R259 - Clocking 4 */
71
+
{ 0x0111, 0x0000 }, /* R273 - FLL Control 1 */
72
+
{ 0x0112, 0x0000 }, /* R274 - FLL Control 2 */
73
+
{ 0x0113, 0x0000 }, /* R275 - FLL Control 3 */
74
+
{ 0x0114, 0x0000 }, /* R276 - FLL Control 4 */
75
+
{ 0x0116, 0x0177 }, /* R278 - FLL Control 6 */
76
+
{ 0x0117, 0x0004 }, /* R279 - FLL Control 7 */
77
+
{ 0x0119, 0x0000 }, /* R281 - FLL EFS 1 */
78
+
{ 0x011A, 0x0002 }, /* R282 - FLL EFS 2 */
79
+
{ 0x0200, 0x0000 }, /* R512 - Mic Charge Pump 1 */
80
+
{ 0x0201, 0x03FF }, /* R513 - Mic Charge Pump 2 */
81
+
{ 0x0202, 0x9BDE }, /* R514 - DM Charge Pump 1 */
82
+
{ 0x020C, 0x0000 }, /* R524 - Mic Bias Ctrl 1 */
83
+
{ 0x020D, 0x0000 }, /* R525 - Mic Bias Ctrl 2 */
84
+
{ 0x020F, 0x0000 }, /* R527 - Ear Piece Ctrl 1 */
85
+
{ 0x0210, 0x0000 }, /* R528 - Ear Piece Ctrl 2 */
86
+
{ 0x0301, 0x0000 }, /* R769 - Input Enables */
87
+
{ 0x0302, 0x2240 }, /* R770 - IN1L Control */
88
+
{ 0x0303, 0x0040 }, /* R771 - IN1R Control */
89
+
{ 0x0304, 0x2240 }, /* R772 - IN2L Control */
90
+
{ 0x0305, 0x0040 }, /* R773 - IN2R Control */
91
+
{ 0x0306, 0x2240 }, /* R774 - IN3L Control */
92
+
{ 0x0307, 0x0040 }, /* R775 - IN3R Control */
93
+
{ 0x030A, 0x0000 }, /* R778 - RXANC_SRC */
94
+
{ 0x030B, 0x0022 }, /* R779 - Input Volume Ramp */
95
+
{ 0x030C, 0x0180 }, /* R780 - ADC Digital Volume 1L */
96
+
{ 0x030D, 0x0180 }, /* R781 - ADC Digital Volume 1R */
97
+
{ 0x030E, 0x0180 }, /* R782 - ADC Digital Volume 2L */
98
+
{ 0x030F, 0x0180 }, /* R783 - ADC Digital Volume 2R */
99
+
{ 0x0310, 0x0180 }, /* R784 - ADC Digital Volume 3L */
100
+
{ 0x0311, 0x0180 }, /* R785 - ADC Digital Volume 3R */
101
+
{ 0x0400, 0x0000 }, /* R1024 - Output Enables */
102
+
{ 0x0401, 0x0000 }, /* R1025 - DAC Volume Limit 1L */
103
+
{ 0x0402, 0x0000 }, /* R1026 - DAC Volume Limit 1R */
104
+
{ 0x0403, 0x0000 }, /* R1027 - DAC Volume Limit 2L */
105
+
{ 0x0404, 0x0000 }, /* R1028 - DAC Volume Limit 2R */
106
+
{ 0x0409, 0x0000 }, /* R1033 - DAC AEC Control 1 */
107
+
{ 0x040A, 0x0022 }, /* R1034 - Output Volume Ramp */
108
+
{ 0x040B, 0x0180 }, /* R1035 - DAC Digital Volume 1L */
109
+
{ 0x040C, 0x0180 }, /* R1036 - DAC Digital Volume 1R */
110
+
{ 0x040D, 0x0180 }, /* R1037 - DAC Digital Volume 2L */
111
+
{ 0x040E, 0x0180 }, /* R1038 - DAC Digital Volume 2R */
112
+
{ 0x0417, 0x0069 }, /* R1047 - PDM 1 */
113
+
{ 0x0418, 0x0000 }, /* R1048 - PDM 2 */
114
+
{ 0x0500, 0x0000 }, /* R1280 - Audio IF 1_1 */
115
+
{ 0x0501, 0x0008 }, /* R1281 - Audio IF 1_2 */
116
+
{ 0x0502, 0x0000 }, /* R1282 - Audio IF 1_3 */
117
+
{ 0x0503, 0x0000 }, /* R1283 - Audio IF 1_4 */
118
+
{ 0x0504, 0x0000 }, /* R1284 - Audio IF 1_5 */
119
+
{ 0x0505, 0x0001 }, /* R1285 - Audio IF 1_6 */
120
+
{ 0x0506, 0x0001 }, /* R1286 - Audio IF 1_7 */
121
+
{ 0x0507, 0x0000 }, /* R1287 - Audio IF 1_8 */
122
+
{ 0x0508, 0x0000 }, /* R1288 - Audio IF 1_9 */
123
+
{ 0x0509, 0x0000 }, /* R1289 - Audio IF 1_10 */
124
+
{ 0x050A, 0x0000 }, /* R1290 - Audio IF 1_11 */
125
+
{ 0x050B, 0x0000 }, /* R1291 - Audio IF 1_12 */
126
+
{ 0x050C, 0x0000 }, /* R1292 - Audio IF 1_13 */
127
+
{ 0x050D, 0x0000 }, /* R1293 - Audio IF 1_14 */
128
+
{ 0x050E, 0x0000 }, /* R1294 - Audio IF 1_15 */
129
+
{ 0x050F, 0x0000 }, /* R1295 - Audio IF 1_16 */
130
+
{ 0x0510, 0x0000 }, /* R1296 - Audio IF 1_17 */
131
+
{ 0x0511, 0x0000 }, /* R1297 - Audio IF 1_18 */
132
+
{ 0x0512, 0x0000 }, /* R1298 - Audio IF 1_19 */
133
+
{ 0x0513, 0x0000 }, /* R1299 - Audio IF 1_20 */
134
+
{ 0x0514, 0x0000 }, /* R1300 - Audio IF 1_21 */
135
+
{ 0x0515, 0x0001 }, /* R1301 - Audio IF 1_22 */
136
+
{ 0x0600, 0x0000 }, /* R1536 - OUT1LMIX Input 1 Source */
137
+
{ 0x0601, 0x0080 }, /* R1537 - OUT1LMIX Input 1 Volume */
138
+
{ 0x0602, 0x0000 }, /* R1538 - OUT1LMIX Input 2 Source */
139
+
{ 0x0603, 0x0080 }, /* R1539 - OUT1LMIX Input 2 Volume */
140
+
{ 0x0604, 0x0000 }, /* R1540 - OUT1LMIX Input 3 Source */
141
+
{ 0x0605, 0x0080 }, /* R1541 - OUT1LMIX Input 3 Volume */
142
+
{ 0x0606, 0x0000 }, /* R1542 - OUT1LMIX Input 4 Source */
143
+
{ 0x0607, 0x0080 }, /* R1543 - OUT1LMIX Input 4 Volume */
144
+
{ 0x0608, 0x0000 }, /* R1544 - OUT1RMIX Input 1 Source */
145
+
{ 0x0609, 0x0080 }, /* R1545 - OUT1RMIX Input 1 Volume */
146
+
{ 0x060A, 0x0000 }, /* R1546 - OUT1RMIX Input 2 Source */
147
+
{ 0x060B, 0x0080 }, /* R1547 - OUT1RMIX Input 2 Volume */
148
+
{ 0x060C, 0x0000 }, /* R1548 - OUT1RMIX Input 3 Source */
149
+
{ 0x060D, 0x0080 }, /* R1549 - OUT1RMIX Input 3 Volume */
150
+
{ 0x060E, 0x0000 }, /* R1550 - OUT1RMIX Input 4 Source */
151
+
{ 0x060F, 0x0080 }, /* R1551 - OUT1RMIX Input 4 Volume */
152
+
{ 0x0610, 0x0000 }, /* R1552 - OUT2LMIX Input 1 Source */
153
+
{ 0x0611, 0x0080 }, /* R1553 - OUT2LMIX Input 1 Volume */
154
+
{ 0x0612, 0x0000 }, /* R1554 - OUT2LMIX Input 2 Source */
155
+
{ 0x0613, 0x0080 }, /* R1555 - OUT2LMIX Input 2 Volume */
156
+
{ 0x0614, 0x0000 }, /* R1556 - OUT2LMIX Input 3 Source */
157
+
{ 0x0615, 0x0080 }, /* R1557 - OUT2LMIX Input 3 Volume */
158
+
{ 0x0616, 0x0000 }, /* R1558 - OUT2LMIX Input 4 Source */
159
+
{ 0x0617, 0x0080 }, /* R1559 - OUT2LMIX Input 4 Volume */
160
+
{ 0x0618, 0x0000 }, /* R1560 - OUT2RMIX Input 1 Source */
161
+
{ 0x0619, 0x0080 }, /* R1561 - OUT2RMIX Input 1 Volume */
162
+
{ 0x061A, 0x0000 }, /* R1562 - OUT2RMIX Input 2 Source */
163
+
{ 0x061B, 0x0080 }, /* R1563 - OUT2RMIX Input 2 Volume */
164
+
{ 0x061C, 0x0000 }, /* R1564 - OUT2RMIX Input 3 Source */
165
+
{ 0x061D, 0x0080 }, /* R1565 - OUT2RMIX Input 3 Volume */
166
+
{ 0x061E, 0x0000 }, /* R1566 - OUT2RMIX Input 4 Source */
167
+
{ 0x061F, 0x0080 }, /* R1567 - OUT2RMIX Input 4 Volume */
168
+
{ 0x0620, 0x0000 }, /* R1568 - AIF1TX1MIX Input 1 Source */
169
+
{ 0x0621, 0x0080 }, /* R1569 - AIF1TX1MIX Input 1 Volume */
170
+
{ 0x0622, 0x0000 }, /* R1570 - AIF1TX1MIX Input 2 Source */
171
+
{ 0x0623, 0x0080 }, /* R1571 - AIF1TX1MIX Input 2 Volume */
172
+
{ 0x0624, 0x0000 }, /* R1572 - AIF1TX1MIX Input 3 Source */
173
+
{ 0x0625, 0x0080 }, /* R1573 - AIF1TX1MIX Input 3 Volume */
174
+
{ 0x0626, 0x0000 }, /* R1574 - AIF1TX1MIX Input 4 Source */
175
+
{ 0x0627, 0x0080 }, /* R1575 - AIF1TX1MIX Input 4 Volume */
176
+
{ 0x0628, 0x0000 }, /* R1576 - AIF1TX2MIX Input 1 Source */
177
+
{ 0x0629, 0x0080 }, /* R1577 - AIF1TX2MIX Input 1 Volume */
178
+
{ 0x062A, 0x0000 }, /* R1578 - AIF1TX2MIX Input 2 Source */
179
+
{ 0x062B, 0x0080 }, /* R1579 - AIF1TX2MIX Input 2 Volume */
180
+
{ 0x062C, 0x0000 }, /* R1580 - AIF1TX2MIX Input 3 Source */
181
+
{ 0x062D, 0x0080 }, /* R1581 - AIF1TX2MIX Input 3 Volume */
182
+
{ 0x062E, 0x0000 }, /* R1582 - AIF1TX2MIX Input 4 Source */
183
+
{ 0x062F, 0x0080 }, /* R1583 - AIF1TX2MIX Input 4 Volume */
184
+
{ 0x0630, 0x0000 }, /* R1584 - AIF1TX3MIX Input 1 Source */
185
+
{ 0x0631, 0x0080 }, /* R1585 - AIF1TX3MIX Input 1 Volume */
186
+
{ 0x0632, 0x0000 }, /* R1586 - AIF1TX3MIX Input 2 Source */
187
+
{ 0x0633, 0x0080 }, /* R1587 - AIF1TX3MIX Input 2 Volume */
188
+
{ 0x0634, 0x0000 }, /* R1588 - AIF1TX3MIX Input 3 Source */
189
+
{ 0x0635, 0x0080 }, /* R1589 - AIF1TX3MIX Input 3 Volume */
190
+
{ 0x0636, 0x0000 }, /* R1590 - AIF1TX3MIX Input 4 Source */
191
+
{ 0x0637, 0x0080 }, /* R1591 - AIF1TX3MIX Input 4 Volume */
192
+
{ 0x0638, 0x0000 }, /* R1592 - AIF1TX4MIX Input 1 Source */
193
+
{ 0x0639, 0x0080 }, /* R1593 - AIF1TX4MIX Input 1 Volume */
194
+
{ 0x063A, 0x0000 }, /* R1594 - AIF1TX4MIX Input 2 Source */
195
+
{ 0x063B, 0x0080 }, /* R1595 - AIF1TX4MIX Input 2 Volume */
196
+
{ 0x063C, 0x0000 }, /* R1596 - AIF1TX4MIX Input 3 Source */
197
+
{ 0x063D, 0x0080 }, /* R1597 - AIF1TX4MIX Input 3 Volume */
198
+
{ 0x063E, 0x0000 }, /* R1598 - AIF1TX4MIX Input 4 Source */
199
+
{ 0x063F, 0x0080 }, /* R1599 - AIF1TX4MIX Input 4 Volume */
200
+
{ 0x0640, 0x0000 }, /* R1600 - AIF1TX5MIX Input 1 Source */
201
+
{ 0x0641, 0x0080 }, /* R1601 - AIF1TX5MIX Input 1 Volume */
202
+
{ 0x0642, 0x0000 }, /* R1602 - AIF1TX5MIX Input 2 Source */
203
+
{ 0x0643, 0x0080 }, /* R1603 - AIF1TX5MIX Input 2 Volume */
204
+
{ 0x0644, 0x0000 }, /* R1604 - AIF1TX5MIX Input 3 Source */
205
+
{ 0x0645, 0x0080 }, /* R1605 - AIF1TX5MIX Input 3 Volume */
206
+
{ 0x0646, 0x0000 }, /* R1606 - AIF1TX5MIX Input 4 Source */
207
+
{ 0x0647, 0x0080 }, /* R1607 - AIF1TX5MIX Input 4 Volume */
208
+
{ 0x0648, 0x0000 }, /* R1608 - AIF1TX6MIX Input 1 Source */
209
+
{ 0x0649, 0x0080 }, /* R1609 - AIF1TX6MIX Input 1 Volume */
210
+
{ 0x064A, 0x0000 }, /* R1610 - AIF1TX6MIX Input 2 Source */
211
+
{ 0x064B, 0x0080 }, /* R1611 - AIF1TX6MIX Input 2 Volume */
212
+
{ 0x064C, 0x0000 }, /* R1612 - AIF1TX6MIX Input 3 Source */
213
+
{ 0x064D, 0x0080 }, /* R1613 - AIF1TX6MIX Input 3 Volume */
214
+
{ 0x064E, 0x0000 }, /* R1614 - AIF1TX6MIX Input 4 Source */
215
+
{ 0x064F, 0x0080 }, /* R1615 - AIF1TX6MIX Input 4 Volume */
216
+
{ 0x0650, 0x0000 }, /* R1616 - EQLMIX Input 1 Source */
217
+
{ 0x0651, 0x0080 }, /* R1617 - EQLMIX Input 1 Volume */
218
+
{ 0x0652, 0x0000 }, /* R1618 - EQLMIX Input 2 Source */
219
+
{ 0x0653, 0x0080 }, /* R1619 - EQLMIX Input 2 Volume */
220
+
{ 0x0654, 0x0000 }, /* R1620 - EQLMIX Input 3 Source */
221
+
{ 0x0655, 0x0080 }, /* R1621 - EQLMIX Input 3 Volume */
222
+
{ 0x0656, 0x0000 }, /* R1622 - EQLMIX Input 4 Source */
223
+
{ 0x0657, 0x0080 }, /* R1623 - EQLMIX Input 4 Volume */
224
+
{ 0x0658, 0x0000 }, /* R1624 - EQRMIX Input 1 Source */
225
+
{ 0x0659, 0x0080 }, /* R1625 - EQRMIX Input 1 Volume */
226
+
{ 0x065A, 0x0000 }, /* R1626 - EQRMIX Input 2 Source */
227
+
{ 0x065B, 0x0080 }, /* R1627 - EQRMIX Input 2 Volume */
228
+
{ 0x065C, 0x0000 }, /* R1628 - EQRMIX Input 3 Source */
229
+
{ 0x065D, 0x0080 }, /* R1629 - EQRMIX Input 3 Volume */
230
+
{ 0x065E, 0x0000 }, /* R1630 - EQRMIX Input 4 Source */
231
+
{ 0x065F, 0x0080 }, /* R1631 - EQRMIX Input 4 Volume */
232
+
{ 0x0660, 0x0000 }, /* R1632 - LHPF1MIX Input 1 Source */
233
+
{ 0x0661, 0x0080 }, /* R1633 - LHPF1MIX Input 1 Volume */
234
+
{ 0x0662, 0x0000 }, /* R1634 - LHPF1MIX Input 2 Source */
235
+
{ 0x0663, 0x0080 }, /* R1635 - LHPF1MIX Input 2 Volume */
236
+
{ 0x0664, 0x0000 }, /* R1636 - LHPF1MIX Input 3 Source */
237
+
{ 0x0665, 0x0080 }, /* R1637 - LHPF1MIX Input 3 Volume */
238
+
{ 0x0666, 0x0000 }, /* R1638 - LHPF1MIX Input 4 Source */
239
+
{ 0x0667, 0x0080 }, /* R1639 - LHPF1MIX Input 4 Volume */
240
+
{ 0x0668, 0x0000 }, /* R1640 - LHPF2MIX Input 1 Source */
241
+
{ 0x0669, 0x0080 }, /* R1641 - LHPF2MIX Input 1 Volume */
242
+
{ 0x066A, 0x0000 }, /* R1642 - LHPF2MIX Input 2 Source */
243
+
{ 0x066B, 0x0080 }, /* R1643 - LHPF2MIX Input 2 Volume */
244
+
{ 0x066C, 0x0000 }, /* R1644 - LHPF2MIX Input 3 Source */
245
+
{ 0x066D, 0x0080 }, /* R1645 - LHPF2MIX Input 3 Volume */
246
+
{ 0x066E, 0x0000 }, /* R1646 - LHPF2MIX Input 4 Source */
247
+
{ 0x066F, 0x0080 }, /* R1647 - LHPF2MIX Input 4 Volume */
248
+
{ 0x0670, 0x0000 }, /* R1648 - DSP1LMIX Input 1 Source */
249
+
{ 0x0671, 0x0080 }, /* R1649 - DSP1LMIX Input 1 Volume */
250
+
{ 0x0672, 0x0000 }, /* R1650 - DSP1LMIX Input 2 Source */
251
+
{ 0x0673, 0x0080 }, /* R1651 - DSP1LMIX Input 2 Volume */
252
+
{ 0x0674, 0x0000 }, /* R1652 - DSP1LMIX Input 3 Source */
253
+
{ 0x0675, 0x0080 }, /* R1653 - DSP1LMIX Input 3 Volume */
254
+
{ 0x0676, 0x0000 }, /* R1654 - DSP1LMIX Input 4 Source */
255
+
{ 0x0677, 0x0080 }, /* R1655 - DSP1LMIX Input 4 Volume */
256
+
{ 0x0678, 0x0000 }, /* R1656 - DSP1RMIX Input 1 Source */
257
+
{ 0x0679, 0x0080 }, /* R1657 - DSP1RMIX Input 1 Volume */
258
+
{ 0x067A, 0x0000 }, /* R1658 - DSP1RMIX Input 2 Source */
259
+
{ 0x067B, 0x0080 }, /* R1659 - DSP1RMIX Input 2 Volume */
260
+
{ 0x067C, 0x0000 }, /* R1660 - DSP1RMIX Input 3 Source */
261
+
{ 0x067D, 0x0080 }, /* R1661 - DSP1RMIX Input 3 Volume */
262
+
{ 0x067E, 0x0000 }, /* R1662 - DSP1RMIX Input 4 Source */
263
+
{ 0x067F, 0x0080 }, /* R1663 - DSP1RMIX Input 4 Volume */
264
+
{ 0x0680, 0x0000 }, /* R1664 - DSP1AUX1MIX Input 1 Source */
265
+
{ 0x0681, 0x0000 }, /* R1665 - DSP1AUX2MIX Input 1 Source */
266
+
{ 0x0682, 0x0000 }, /* R1666 - DSP1AUX3MIX Input 1 Source */
267
+
{ 0x0683, 0x0000 }, /* R1667 - DSP1AUX4MIX Input 1 Source */
268
+
{ 0x0684, 0x0000 }, /* R1668 - DSP1AUX5MIX Input 1 Source */
269
+
{ 0x0685, 0x0000 }, /* R1669 - DSP1AUX6MIX Input 1 Source */
270
+
{ 0x0686, 0x0000 }, /* R1670 - DSP2LMIX Input 1 Source */
271
+
{ 0x0687, 0x0080 }, /* R1671 - DSP2LMIX Input 1 Volume */
272
+
{ 0x0688, 0x0000 }, /* R1672 - DSP2LMIX Input 2 Source */
273
+
{ 0x0689, 0x0080 }, /* R1673 - DSP2LMIX Input 2 Volume */
274
+
{ 0x068A, 0x0000 }, /* R1674 - DSP2LMIX Input 3 Source */
275
+
{ 0x068B, 0x0080 }, /* R1675 - DSP2LMIX Input 3 Volume */
276
+
{ 0x068C, 0x0000 }, /* R1676 - DSP2LMIX Input 4 Source */
277
+
{ 0x068D, 0x0080 }, /* R1677 - DSP2LMIX Input 4 Volume */
278
+
{ 0x068E, 0x0000 }, /* R1678 - DSP2RMIX Input 1 Source */
279
+
{ 0x068F, 0x0080 }, /* R1679 - DSP2RMIX Input 1 Volume */
280
+
{ 0x0690, 0x0000 }, /* R1680 - DSP2RMIX Input 2 Source */
281
+
{ 0x0691, 0x0080 }, /* R1681 - DSP2RMIX Input 2 Volume */
282
+
{ 0x0692, 0x0000 }, /* R1682 - DSP2RMIX Input 3 Source */
283
+
{ 0x0693, 0x0080 }, /* R1683 - DSP2RMIX Input 3 Volume */
284
+
{ 0x0694, 0x0000 }, /* R1684 - DSP2RMIX Input 4 Source */
285
+
{ 0x0695, 0x0080 }, /* R1685 - DSP2RMIX Input 4 Volume */
286
+
{ 0x0696, 0x0000 }, /* R1686 - DSP2AUX1MIX Input 1 Source */
287
+
{ 0x0697, 0x0000 }, /* R1687 - DSP2AUX2MIX Input 1 Source */
288
+
{ 0x0698, 0x0000 }, /* R1688 - DSP2AUX3MIX Input 1 Source */
289
+
{ 0x0699, 0x0000 }, /* R1689 - DSP2AUX4MIX Input 1 Source */
290
+
{ 0x069A, 0x0000 }, /* R1690 - DSP2AUX5MIX Input 1 Source */
291
+
{ 0x069B, 0x0000 }, /* R1691 - DSP2AUX6MIX Input 1 Source */
292
+
{ 0x0700, 0xA101 }, /* R1792 - GPIO CTRL 1 */
293
+
{ 0x0701, 0xA101 }, /* R1793 - GPIO CTRL 2 */
294
+
{ 0x0702, 0xA101 }, /* R1794 - GPIO CTRL 3 */
295
+
{ 0x0703, 0xA101 }, /* R1795 - GPIO CTRL 4 */
296
+
{ 0x0709, 0x0000 }, /* R1801 - Misc Pad Ctrl 1 */
297
+
{ 0x0801, 0x00FF }, /* R2049 - Interrupt Status 1 Mask */
298
+
{ 0x0804, 0xFFFF }, /* R2052 - Interrupt Status 2 Mask */
299
+
{ 0x0808, 0x0000 }, /* R2056 - Interrupt Control */
300
+
{ 0x0900, 0x0000 }, /* R2304 - EQL_1 */
301
+
{ 0x0901, 0x0000 }, /* R2305 - EQL_2 */
302
+
{ 0x0902, 0x0000 }, /* R2306 - EQL_3 */
303
+
{ 0x0903, 0x0000 }, /* R2307 - EQL_4 */
304
+
{ 0x0904, 0x0000 }, /* R2308 - EQL_5 */
305
+
{ 0x0905, 0x0000 }, /* R2309 - EQL_6 */
306
+
{ 0x0906, 0x0000 }, /* R2310 - EQL_7 */
307
+
{ 0x0907, 0x0000 }, /* R2311 - EQL_8 */
308
+
{ 0x0908, 0x0000 }, /* R2312 - EQL_9 */
309
+
{ 0x0909, 0x0000 }, /* R2313 - EQL_10 */
310
+
{ 0x090A, 0x0000 }, /* R2314 - EQL_11 */
311
+
{ 0x090B, 0x0000 }, /* R2315 - EQL_12 */
312
+
{ 0x090C, 0x0000 }, /* R2316 - EQL_13 */
313
+
{ 0x090D, 0x0000 }, /* R2317 - EQL_14 */
314
+
{ 0x090E, 0x0000 }, /* R2318 - EQL_15 */
315
+
{ 0x090F, 0x0000 }, /* R2319 - EQL_16 */
316
+
{ 0x0910, 0x0000 }, /* R2320 - EQL_17 */
317
+
{ 0x0911, 0x0000 }, /* R2321 - EQL_18 */
318
+
{ 0x0912, 0x0000 }, /* R2322 - EQL_19 */
319
+
{ 0x0913, 0x0000 }, /* R2323 - EQL_20 */
320
+
{ 0x0916, 0x0000 }, /* R2326 - EQR_1 */
321
+
{ 0x0917, 0x0000 }, /* R2327 - EQR_2 */
322
+
{ 0x0918, 0x0000 }, /* R2328 - EQR_3 */
323
+
{ 0x0919, 0x0000 }, /* R2329 - EQR_4 */
324
+
{ 0x091A, 0x0000 }, /* R2330 - EQR_5 */
325
+
{ 0x091B, 0x0000 }, /* R2331 - EQR_6 */
326
+
{ 0x091C, 0x0000 }, /* R2332 - EQR_7 */
327
+
{ 0x091D, 0x0000 }, /* R2333 - EQR_8 */
328
+
{ 0x091E, 0x0000 }, /* R2334 - EQR_9 */
329
+
{ 0x091F, 0x0000 }, /* R2335 - EQR_10 */
330
+
{ 0x0920, 0x0000 }, /* R2336 - EQR_11 */
331
+
{ 0x0921, 0x0000 }, /* R2337 - EQR_12 */
332
+
{ 0x0922, 0x0000 }, /* R2338 - EQR_13 */
333
+
{ 0x0923, 0x0000 }, /* R2339 - EQR_14 */
334
+
{ 0x0924, 0x0000 }, /* R2340 - EQR_15 */
335
+
{ 0x0925, 0x0000 }, /* R2341 - EQR_16 */
336
+
{ 0x0926, 0x0000 }, /* R2342 - EQR_17 */
337
+
{ 0x0927, 0x0000 }, /* R2343 - EQR_18 */
338
+
{ 0x0928, 0x0000 }, /* R2344 - EQR_19 */
339
+
{ 0x0929, 0x0000 }, /* R2345 - EQR_20 */
340
+
{ 0x093E, 0x0000 }, /* R2366 - HPLPF1_1 */
341
+
{ 0x093F, 0x0000 }, /* R2367 - HPLPF1_2 */
342
+
{ 0x0942, 0x0000 }, /* R2370 - HPLPF2_1 */
343
+
{ 0x0943, 0x0000 }, /* R2371 - HPLPF2_2 */
344
+
{ 0x0A00, 0x0000 }, /* R2560 - DSP1 Control 1 */
345
+
{ 0x0A02, 0x0000 }, /* R2562 - DSP1 Control 2 */
346
+
{ 0x0A03, 0x0000 }, /* R2563 - DSP1 Control 3 */
347
+
{ 0x0A04, 0x0000 }, /* R2564 - DSP1 Control 4 */
348
+
{ 0x0A06, 0x0000 }, /* R2566 - DSP1 Control 5 */
349
+
{ 0x0A07, 0x0000 }, /* R2567 - DSP1 Control 6 */
350
+
{ 0x0A08, 0x0000 }, /* R2568 - DSP1 Control 7 */
351
+
{ 0x0A09, 0x0000 }, /* R2569 - DSP1 Control 8 */
352
+
{ 0x0A0A, 0x0000 }, /* R2570 - DSP1 Control 9 */
353
+
{ 0x0A0B, 0x0000 }, /* R2571 - DSP1 Control 10 */
354
+
{ 0x0A0C, 0x0000 }, /* R2572 - DSP1 Control 11 */
355
+
{ 0x0A0D, 0x0000 }, /* R2573 - DSP1 Control 12 */
356
+
{ 0x0A0F, 0x0000 }, /* R2575 - DSP1 Control 13 */
357
+
{ 0x0A10, 0x0000 }, /* R2576 - DSP1 Control 14 */
358
+
{ 0x0A11, 0x0000 }, /* R2577 - DSP1 Control 15 */
359
+
{ 0x0A12, 0x0000 }, /* R2578 - DSP1 Control 16 */
360
+
{ 0x0A13, 0x0000 }, /* R2579 - DSP1 Control 17 */
361
+
{ 0x0A14, 0x0000 }, /* R2580 - DSP1 Control 18 */
362
+
{ 0x0A16, 0x0000 }, /* R2582 - DSP1 Control 19 */
363
+
{ 0x0A17, 0x0000 }, /* R2583 - DSP1 Control 20 */
364
+
{ 0x0A18, 0x0000 }, /* R2584 - DSP1 Control 21 */
365
+
{ 0x0A1A, 0x1800 }, /* R2586 - DSP1 Control 22 */
366
+
{ 0x0A1B, 0x1000 }, /* R2587 - DSP1 Control 23 */
367
+
{ 0x0A1C, 0x0400 }, /* R2588 - DSP1 Control 24 */
368
+
{ 0x0A1E, 0x0000 }, /* R2590 - DSP1 Control 25 */
369
+
{ 0x0A20, 0x0000 }, /* R2592 - DSP1 Control 26 */
370
+
{ 0x0A21, 0x0000 }, /* R2593 - DSP1 Control 27 */
371
+
{ 0x0A22, 0x0000 }, /* R2594 - DSP1 Control 28 */
372
+
{ 0x0A23, 0x0000 }, /* R2595 - DSP1 Control 29 */
373
+
{ 0x0A24, 0x0000 }, /* R2596 - DSP1 Control 30 */
374
+
{ 0x0A26, 0x0000 }, /* R2598 - DSP1 Control 31 */
375
+
{ 0x0B00, 0x0000 }, /* R2816 - DSP2 Control 1 */
376
+
{ 0x0B02, 0x0000 }, /* R2818 - DSP2 Control 2 */
377
+
{ 0x0B03, 0x0000 }, /* R2819 - DSP2 Control 3 */
378
+
{ 0x0B04, 0x0000 }, /* R2820 - DSP2 Control 4 */
379
+
{ 0x0B06, 0x0000 }, /* R2822 - DSP2 Control 5 */
380
+
{ 0x0B07, 0x0000 }, /* R2823 - DSP2 Control 6 */
381
+
{ 0x0B08, 0x0000 }, /* R2824 - DSP2 Control 7 */
382
+
{ 0x0B09, 0x0000 }, /* R2825 - DSP2 Control 8 */
383
+
{ 0x0B0A, 0x0000 }, /* R2826 - DSP2 Control 9 */
384
+
{ 0x0B0B, 0x0000 }, /* R2827 - DSP2 Control 10 */
385
+
{ 0x0B0C, 0x0000 }, /* R2828 - DSP2 Control 11 */
386
+
{ 0x0B0D, 0x0000 }, /* R2829 - DSP2 Control 12 */
387
+
{ 0x0B0F, 0x0000 }, /* R2831 - DSP2 Control 13 */
388
+
{ 0x0B10, 0x0000 }, /* R2832 - DSP2 Control 14 */
389
+
{ 0x0B11, 0x0000 }, /* R2833 - DSP2 Control 15 */
390
+
{ 0x0B12, 0x0000 }, /* R2834 - DSP2 Control 16 */
391
+
{ 0x0B13, 0x0000 }, /* R2835 - DSP2 Control 17 */
392
+
{ 0x0B14, 0x0000 }, /* R2836 - DSP2 Control 18 */
393
+
{ 0x0B16, 0x0000 }, /* R2838 - DSP2 Control 19 */
394
+
{ 0x0B17, 0x0000 }, /* R2839 - DSP2 Control 20 */
395
+
{ 0x0B18, 0x0000 }, /* R2840 - DSP2 Control 21 */
396
+
{ 0x0B1A, 0x0800 }, /* R2842 - DSP2 Control 22 */
397
+
{ 0x0B1B, 0x1000 }, /* R2843 - DSP2 Control 23 */
398
+
{ 0x0B1C, 0x0400 }, /* R2844 - DSP2 Control 24 */
399
+
{ 0x0B1E, 0x0000 }, /* R2846 - DSP2 Control 25 */
400
+
{ 0x0B20, 0x0000 }, /* R2848 - DSP2 Control 26 */
401
+
{ 0x0B21, 0x0000 }, /* R2849 - DSP2 Control 27 */
402
+
{ 0x0B22, 0x0000 }, /* R2850 - DSP2 Control 28 */
403
+
{ 0x0B23, 0x0000 }, /* R2851 - DSP2 Control 29 */
404
+
{ 0x0B24, 0x0000 }, /* R2852 - DSP2 Control 30 */
405
+
{ 0x0B26, 0x0000 }, /* R2854 - DSP2 Control 31 */
406
+
};
407
+
408
+
static bool wm2200_volatile_register(struct device *dev, unsigned int reg)
409
+
{
410
+
switch (reg) {
411
+
case WM2200_SOFTWARE_RESET:
412
+
case WM2200_DEVICE_REVISION:
413
+
case WM2200_ADPS1_IRQ0:
414
+
case WM2200_ADPS1_IRQ1:
415
+
case WM2200_INTERRUPT_STATUS_1:
416
+
case WM2200_INTERRUPT_STATUS_2:
417
+
case WM2200_INTERRUPT_RAW_STATUS_2:
418
+
return true;
419
+
default:
420
+
return false;
421
+
}
422
+
}
423
+
424
+
static bool wm2200_readable_register(struct device *dev, unsigned int reg)
425
+
{
426
+
switch (reg) {
427
+
case WM2200_SOFTWARE_RESET:
428
+
case WM2200_DEVICE_REVISION:
429
+
case WM2200_TONE_GENERATOR_1:
430
+
case WM2200_CLOCKING_3:
431
+
case WM2200_CLOCKING_4:
432
+
case WM2200_FLL_CONTROL_1:
433
+
case WM2200_FLL_CONTROL_2:
434
+
case WM2200_FLL_CONTROL_3:
435
+
case WM2200_FLL_CONTROL_4:
436
+
case WM2200_FLL_CONTROL_6:
437
+
case WM2200_FLL_CONTROL_7:
438
+
case WM2200_FLL_EFS_1:
439
+
case WM2200_FLL_EFS_2:
440
+
case WM2200_MIC_CHARGE_PUMP_1:
441
+
case WM2200_MIC_CHARGE_PUMP_2:
442
+
case WM2200_DM_CHARGE_PUMP_1:
443
+
case WM2200_MIC_BIAS_CTRL_1:
444
+
case WM2200_MIC_BIAS_CTRL_2:
445
+
case WM2200_EAR_PIECE_CTRL_1:
446
+
case WM2200_EAR_PIECE_CTRL_2:
447
+
case WM2200_INPUT_ENABLES:
448
+
case WM2200_IN1L_CONTROL:
449
+
case WM2200_IN1R_CONTROL:
450
+
case WM2200_IN2L_CONTROL:
451
+
case WM2200_IN2R_CONTROL:
452
+
case WM2200_IN3L_CONTROL:
453
+
case WM2200_IN3R_CONTROL:
454
+
case WM2200_RXANC_SRC:
455
+
case WM2200_INPUT_VOLUME_RAMP:
456
+
case WM2200_ADC_DIGITAL_VOLUME_1L:
457
+
case WM2200_ADC_DIGITAL_VOLUME_1R:
458
+
case WM2200_ADC_DIGITAL_VOLUME_2L:
459
+
case WM2200_ADC_DIGITAL_VOLUME_2R:
460
+
case WM2200_ADC_DIGITAL_VOLUME_3L:
461
+
case WM2200_ADC_DIGITAL_VOLUME_3R:
462
+
case WM2200_OUTPUT_ENABLES:
463
+
case WM2200_DAC_VOLUME_LIMIT_1L:
464
+
case WM2200_DAC_VOLUME_LIMIT_1R:
465
+
case WM2200_DAC_VOLUME_LIMIT_2L:
466
+
case WM2200_DAC_VOLUME_LIMIT_2R:
467
+
case WM2200_DAC_AEC_CONTROL_1:
468
+
case WM2200_OUTPUT_VOLUME_RAMP:
469
+
case WM2200_DAC_DIGITAL_VOLUME_1L:
470
+
case WM2200_DAC_DIGITAL_VOLUME_1R:
471
+
case WM2200_DAC_DIGITAL_VOLUME_2L:
472
+
case WM2200_DAC_DIGITAL_VOLUME_2R:
473
+
case WM2200_PDM_1:
474
+
case WM2200_PDM_2:
475
+
case WM2200_AUDIO_IF_1_1:
476
+
case WM2200_AUDIO_IF_1_2:
477
+
case WM2200_AUDIO_IF_1_3:
478
+
case WM2200_AUDIO_IF_1_4:
479
+
case WM2200_AUDIO_IF_1_5:
480
+
case WM2200_AUDIO_IF_1_6:
481
+
case WM2200_AUDIO_IF_1_7:
482
+
case WM2200_AUDIO_IF_1_8:
483
+
case WM2200_AUDIO_IF_1_9:
484
+
case WM2200_AUDIO_IF_1_10:
485
+
case WM2200_AUDIO_IF_1_11:
486
+
case WM2200_AUDIO_IF_1_12:
487
+
case WM2200_AUDIO_IF_1_13:
488
+
case WM2200_AUDIO_IF_1_14:
489
+
case WM2200_AUDIO_IF_1_15:
490
+
case WM2200_AUDIO_IF_1_16:
491
+
case WM2200_AUDIO_IF_1_17:
492
+
case WM2200_AUDIO_IF_1_18:
493
+
case WM2200_AUDIO_IF_1_19:
494
+
case WM2200_AUDIO_IF_1_20:
495
+
case WM2200_AUDIO_IF_1_21:
496
+
case WM2200_AUDIO_IF_1_22:
497
+
case WM2200_OUT1LMIX_INPUT_1_SOURCE:
498
+
case WM2200_OUT1LMIX_INPUT_1_VOLUME:
499
+
case WM2200_OUT1LMIX_INPUT_2_SOURCE:
500
+
case WM2200_OUT1LMIX_INPUT_2_VOLUME:
501
+
case WM2200_OUT1LMIX_INPUT_3_SOURCE:
502
+
case WM2200_OUT1LMIX_INPUT_3_VOLUME:
503
+
case WM2200_OUT1LMIX_INPUT_4_SOURCE:
504
+
case WM2200_OUT1LMIX_INPUT_4_VOLUME:
505
+
case WM2200_OUT1RMIX_INPUT_1_SOURCE:
506
+
case WM2200_OUT1RMIX_INPUT_1_VOLUME:
507
+
case WM2200_OUT1RMIX_INPUT_2_SOURCE:
508
+
case WM2200_OUT1RMIX_INPUT_2_VOLUME:
509
+
case WM2200_OUT1RMIX_INPUT_3_SOURCE:
510
+
case WM2200_OUT1RMIX_INPUT_3_VOLUME:
511
+
case WM2200_OUT1RMIX_INPUT_4_SOURCE:
512
+
case WM2200_OUT1RMIX_INPUT_4_VOLUME:
513
+
case WM2200_OUT2LMIX_INPUT_1_SOURCE:
514
+
case WM2200_OUT2LMIX_INPUT_1_VOLUME:
515
+
case WM2200_OUT2LMIX_INPUT_2_SOURCE:
516
+
case WM2200_OUT2LMIX_INPUT_2_VOLUME:
517
+
case WM2200_OUT2LMIX_INPUT_3_SOURCE:
518
+
case WM2200_OUT2LMIX_INPUT_3_VOLUME:
519
+
case WM2200_OUT2LMIX_INPUT_4_SOURCE:
520
+
case WM2200_OUT2LMIX_INPUT_4_VOLUME:
521
+
case WM2200_OUT2RMIX_INPUT_1_SOURCE:
522
+
case WM2200_OUT2RMIX_INPUT_1_VOLUME:
523
+
case WM2200_OUT2RMIX_INPUT_2_SOURCE:
524
+
case WM2200_OUT2RMIX_INPUT_2_VOLUME:
525
+
case WM2200_OUT2RMIX_INPUT_3_SOURCE:
526
+
case WM2200_OUT2RMIX_INPUT_3_VOLUME:
527
+
case WM2200_OUT2RMIX_INPUT_4_SOURCE:
528
+
case WM2200_OUT2RMIX_INPUT_4_VOLUME:
529
+
case WM2200_AIF1TX1MIX_INPUT_1_SOURCE:
530
+
case WM2200_AIF1TX1MIX_INPUT_1_VOLUME:
531
+
case WM2200_AIF1TX1MIX_INPUT_2_SOURCE:
532
+
case WM2200_AIF1TX1MIX_INPUT_2_VOLUME:
533
+
case WM2200_AIF1TX1MIX_INPUT_3_SOURCE:
534
+
case WM2200_AIF1TX1MIX_INPUT_3_VOLUME:
535
+
case WM2200_AIF1TX1MIX_INPUT_4_SOURCE:
536
+
case WM2200_AIF1TX1MIX_INPUT_4_VOLUME:
537
+
case WM2200_AIF1TX2MIX_INPUT_1_SOURCE:
538
+
case WM2200_AIF1TX2MIX_INPUT_1_VOLUME:
539
+
case WM2200_AIF1TX2MIX_INPUT_2_SOURCE:
540
+
case WM2200_AIF1TX2MIX_INPUT_2_VOLUME:
541
+
case WM2200_AIF1TX2MIX_INPUT_3_SOURCE:
542
+
case WM2200_AIF1TX2MIX_INPUT_3_VOLUME:
543
+
case WM2200_AIF1TX2MIX_INPUT_4_SOURCE:
544
+
case WM2200_AIF1TX2MIX_INPUT_4_VOLUME:
545
+
case WM2200_AIF1TX3MIX_INPUT_1_SOURCE:
546
+
case WM2200_AIF1TX3MIX_INPUT_1_VOLUME:
547
+
case WM2200_AIF1TX3MIX_INPUT_2_SOURCE:
548
+
case WM2200_AIF1TX3MIX_INPUT_2_VOLUME:
549
+
case WM2200_AIF1TX3MIX_INPUT_3_SOURCE:
550
+
case WM2200_AIF1TX3MIX_INPUT_3_VOLUME:
551
+
case WM2200_AIF1TX3MIX_INPUT_4_SOURCE:
552
+
case WM2200_AIF1TX3MIX_INPUT_4_VOLUME:
553
+
case WM2200_AIF1TX4MIX_INPUT_1_SOURCE:
554
+
case WM2200_AIF1TX4MIX_INPUT_1_VOLUME:
555
+
case WM2200_AIF1TX4MIX_INPUT_2_SOURCE:
556
+
case WM2200_AIF1TX4MIX_INPUT_2_VOLUME:
557
+
case WM2200_AIF1TX4MIX_INPUT_3_SOURCE:
558
+
case WM2200_AIF1TX4MIX_INPUT_3_VOLUME:
559
+
case WM2200_AIF1TX4MIX_INPUT_4_SOURCE:
560
+
case WM2200_AIF1TX4MIX_INPUT_4_VOLUME:
561
+
case WM2200_AIF1TX5MIX_INPUT_1_SOURCE:
562
+
case WM2200_AIF1TX5MIX_INPUT_1_VOLUME:
563
+
case WM2200_AIF1TX5MIX_INPUT_2_SOURCE:
564
+
case WM2200_AIF1TX5MIX_INPUT_2_VOLUME:
565
+
case WM2200_AIF1TX5MIX_INPUT_3_SOURCE:
566
+
case WM2200_AIF1TX5MIX_INPUT_3_VOLUME:
567
+
case WM2200_AIF1TX5MIX_INPUT_4_SOURCE:
568
+
case WM2200_AIF1TX5MIX_INPUT_4_VOLUME:
569
+
case WM2200_AIF1TX6MIX_INPUT_1_SOURCE:
570
+
case WM2200_AIF1TX6MIX_INPUT_1_VOLUME:
571
+
case WM2200_AIF1TX6MIX_INPUT_2_SOURCE:
572
+
case WM2200_AIF1TX6MIX_INPUT_2_VOLUME:
573
+
case WM2200_AIF1TX6MIX_INPUT_3_SOURCE:
574
+
case WM2200_AIF1TX6MIX_INPUT_3_VOLUME:
575
+
case WM2200_AIF1TX6MIX_INPUT_4_SOURCE:
576
+
case WM2200_AIF1TX6MIX_INPUT_4_VOLUME:
577
+
case WM2200_EQLMIX_INPUT_1_SOURCE:
578
+
case WM2200_EQLMIX_INPUT_1_VOLUME:
579
+
case WM2200_EQLMIX_INPUT_2_SOURCE:
580
+
case WM2200_EQLMIX_INPUT_2_VOLUME:
581
+
case WM2200_EQLMIX_INPUT_3_SOURCE:
582
+
case WM2200_EQLMIX_INPUT_3_VOLUME:
583
+
case WM2200_EQLMIX_INPUT_4_SOURCE:
584
+
case WM2200_EQLMIX_INPUT_4_VOLUME:
585
+
case WM2200_EQRMIX_INPUT_1_SOURCE:
586
+
case WM2200_EQRMIX_INPUT_1_VOLUME:
587
+
case WM2200_EQRMIX_INPUT_2_SOURCE:
588
+
case WM2200_EQRMIX_INPUT_2_VOLUME:
589
+
case WM2200_EQRMIX_INPUT_3_SOURCE:
590
+
case WM2200_EQRMIX_INPUT_3_VOLUME:
591
+
case WM2200_EQRMIX_INPUT_4_SOURCE:
592
+
case WM2200_EQRMIX_INPUT_4_VOLUME:
593
+
case WM2200_LHPF1MIX_INPUT_1_SOURCE:
594
+
case WM2200_LHPF1MIX_INPUT_1_VOLUME:
595
+
case WM2200_LHPF1MIX_INPUT_2_SOURCE:
596
+
case WM2200_LHPF1MIX_INPUT_2_VOLUME:
597
+
case WM2200_LHPF1MIX_INPUT_3_SOURCE:
598
+
case WM2200_LHPF1MIX_INPUT_3_VOLUME:
599
+
case WM2200_LHPF1MIX_INPUT_4_SOURCE:
600
+
case WM2200_LHPF1MIX_INPUT_4_VOLUME:
601
+
case WM2200_LHPF2MIX_INPUT_1_SOURCE:
602
+
case WM2200_LHPF2MIX_INPUT_1_VOLUME:
603
+
case WM2200_LHPF2MIX_INPUT_2_SOURCE:
604
+
case WM2200_LHPF2MIX_INPUT_2_VOLUME:
605
+
case WM2200_LHPF2MIX_INPUT_3_SOURCE:
606
+
case WM2200_LHPF2MIX_INPUT_3_VOLUME:
607
+
case WM2200_LHPF2MIX_INPUT_4_SOURCE:
608
+
case WM2200_LHPF2MIX_INPUT_4_VOLUME:
609
+
case WM2200_DSP1LMIX_INPUT_1_SOURCE:
610
+
case WM2200_DSP1LMIX_INPUT_1_VOLUME:
611
+
case WM2200_DSP1LMIX_INPUT_2_SOURCE:
612
+
case WM2200_DSP1LMIX_INPUT_2_VOLUME:
613
+
case WM2200_DSP1LMIX_INPUT_3_SOURCE:
614
+
case WM2200_DSP1LMIX_INPUT_3_VOLUME:
615
+
case WM2200_DSP1LMIX_INPUT_4_SOURCE:
616
+
case WM2200_DSP1LMIX_INPUT_4_VOLUME:
617
+
case WM2200_DSP1RMIX_INPUT_1_SOURCE:
618
+
case WM2200_DSP1RMIX_INPUT_1_VOLUME:
619
+
case WM2200_DSP1RMIX_INPUT_2_SOURCE:
620
+
case WM2200_DSP1RMIX_INPUT_2_VOLUME:
621
+
case WM2200_DSP1RMIX_INPUT_3_SOURCE:
622
+
case WM2200_DSP1RMIX_INPUT_3_VOLUME:
623
+
case WM2200_DSP1RMIX_INPUT_4_SOURCE:
624
+
case WM2200_DSP1RMIX_INPUT_4_VOLUME:
625
+
case WM2200_DSP1AUX1MIX_INPUT_1_SOURCE:
626
+
case WM2200_DSP1AUX2MIX_INPUT_1_SOURCE:
627
+
case WM2200_DSP1AUX3MIX_INPUT_1_SOURCE:
628
+
case WM2200_DSP1AUX4MIX_INPUT_1_SOURCE:
629
+
case WM2200_DSP1AUX5MIX_INPUT_1_SOURCE:
630
+
case WM2200_DSP1AUX6MIX_INPUT_1_SOURCE:
631
+
case WM2200_DSP2LMIX_INPUT_1_SOURCE:
632
+
case WM2200_DSP2LMIX_INPUT_1_VOLUME:
633
+
case WM2200_DSP2LMIX_INPUT_2_SOURCE:
634
+
case WM2200_DSP2LMIX_INPUT_2_VOLUME:
635
+
case WM2200_DSP2LMIX_INPUT_3_SOURCE:
636
+
case WM2200_DSP2LMIX_INPUT_3_VOLUME:
637
+
case WM2200_DSP2LMIX_INPUT_4_SOURCE:
638
+
case WM2200_DSP2LMIX_INPUT_4_VOLUME:
639
+
case WM2200_DSP2RMIX_INPUT_1_SOURCE:
640
+
case WM2200_DSP2RMIX_INPUT_1_VOLUME:
641
+
case WM2200_DSP2RMIX_INPUT_2_SOURCE:
642
+
case WM2200_DSP2RMIX_INPUT_2_VOLUME:
643
+
case WM2200_DSP2RMIX_INPUT_3_SOURCE:
644
+
case WM2200_DSP2RMIX_INPUT_3_VOLUME:
645
+
case WM2200_DSP2RMIX_INPUT_4_SOURCE:
646
+
case WM2200_DSP2RMIX_INPUT_4_VOLUME:
647
+
case WM2200_DSP2AUX1MIX_INPUT_1_SOURCE:
648
+
case WM2200_DSP2AUX2MIX_INPUT_1_SOURCE:
649
+
case WM2200_DSP2AUX3MIX_INPUT_1_SOURCE:
650
+
case WM2200_DSP2AUX4MIX_INPUT_1_SOURCE:
651
+
case WM2200_DSP2AUX5MIX_INPUT_1_SOURCE:
652
+
case WM2200_DSP2AUX6MIX_INPUT_1_SOURCE:
653
+
case WM2200_GPIO_CTRL_1:
654
+
case WM2200_GPIO_CTRL_2:
655
+
case WM2200_GPIO_CTRL_3:
656
+
case WM2200_GPIO_CTRL_4:
657
+
case WM2200_ADPS1_IRQ0:
658
+
case WM2200_ADPS1_IRQ1:
659
+
case WM2200_MISC_PAD_CTRL_1:
660
+
case WM2200_INTERRUPT_STATUS_1:
661
+
case WM2200_INTERRUPT_STATUS_1_MASK:
662
+
case WM2200_INTERRUPT_STATUS_2:
663
+
case WM2200_INTERRUPT_RAW_STATUS_2:
664
+
case WM2200_INTERRUPT_STATUS_2_MASK:
665
+
case WM2200_INTERRUPT_CONTROL:
666
+
case WM2200_EQL_1:
667
+
case WM2200_EQL_2:
668
+
case WM2200_EQL_3:
669
+
case WM2200_EQL_4:
670
+
case WM2200_EQL_5:
671
+
case WM2200_EQL_6:
672
+
case WM2200_EQL_7:
673
+
case WM2200_EQL_8:
674
+
case WM2200_EQL_9:
675
+
case WM2200_EQL_10:
676
+
case WM2200_EQL_11:
677
+
case WM2200_EQL_12:
678
+
case WM2200_EQL_13:
679
+
case WM2200_EQL_14:
680
+
case WM2200_EQL_15:
681
+
case WM2200_EQL_16:
682
+
case WM2200_EQL_17:
683
+
case WM2200_EQL_18:
684
+
case WM2200_EQL_19:
685
+
case WM2200_EQL_20:
686
+
case WM2200_EQR_1:
687
+
case WM2200_EQR_2:
688
+
case WM2200_EQR_3:
689
+
case WM2200_EQR_4:
690
+
case WM2200_EQR_5:
691
+
case WM2200_EQR_6:
692
+
case WM2200_EQR_7:
693
+
case WM2200_EQR_8:
694
+
case WM2200_EQR_9:
695
+
case WM2200_EQR_10:
696
+
case WM2200_EQR_11:
697
+
case WM2200_EQR_12:
698
+
case WM2200_EQR_13:
699
+
case WM2200_EQR_14:
700
+
case WM2200_EQR_15:
701
+
case WM2200_EQR_16:
702
+
case WM2200_EQR_17:
703
+
case WM2200_EQR_18:
704
+
case WM2200_EQR_19:
705
+
case WM2200_EQR_20:
706
+
case WM2200_HPLPF1_1:
707
+
case WM2200_HPLPF1_2:
708
+
case WM2200_HPLPF2_1:
709
+
case WM2200_HPLPF2_2:
710
+
case WM2200_DSP1_CONTROL_1:
711
+
case WM2200_DSP1_CONTROL_2:
712
+
case WM2200_DSP1_CONTROL_3:
713
+
case WM2200_DSP1_CONTROL_4:
714
+
case WM2200_DSP1_CONTROL_5:
715
+
case WM2200_DSP1_CONTROL_6:
716
+
case WM2200_DSP1_CONTROL_7:
717
+
case WM2200_DSP1_CONTROL_8:
718
+
case WM2200_DSP1_CONTROL_9:
719
+
case WM2200_DSP1_CONTROL_10:
720
+
case WM2200_DSP1_CONTROL_11:
721
+
case WM2200_DSP1_CONTROL_12:
722
+
case WM2200_DSP1_CONTROL_13:
723
+
case WM2200_DSP1_CONTROL_14:
724
+
case WM2200_DSP1_CONTROL_15:
725
+
case WM2200_DSP1_CONTROL_16:
726
+
case WM2200_DSP1_CONTROL_17:
727
+
case WM2200_DSP1_CONTROL_18:
728
+
case WM2200_DSP1_CONTROL_19:
729
+
case WM2200_DSP1_CONTROL_20:
730
+
case WM2200_DSP1_CONTROL_21:
731
+
case WM2200_DSP1_CONTROL_22:
732
+
case WM2200_DSP1_CONTROL_23:
733
+
case WM2200_DSP1_CONTROL_24:
734
+
case WM2200_DSP1_CONTROL_25:
735
+
case WM2200_DSP1_CONTROL_26:
736
+
case WM2200_DSP1_CONTROL_27:
737
+
case WM2200_DSP1_CONTROL_28:
738
+
case WM2200_DSP1_CONTROL_29:
739
+
case WM2200_DSP1_CONTROL_30:
740
+
case WM2200_DSP1_CONTROL_31:
741
+
case WM2200_DSP2_CONTROL_1:
742
+
case WM2200_DSP2_CONTROL_2:
743
+
case WM2200_DSP2_CONTROL_3:
744
+
case WM2200_DSP2_CONTROL_4:
745
+
case WM2200_DSP2_CONTROL_5:
746
+
case WM2200_DSP2_CONTROL_6:
747
+
case WM2200_DSP2_CONTROL_7:
748
+
case WM2200_DSP2_CONTROL_8:
749
+
case WM2200_DSP2_CONTROL_9:
750
+
case WM2200_DSP2_CONTROL_10:
751
+
case WM2200_DSP2_CONTROL_11:
752
+
case WM2200_DSP2_CONTROL_12:
753
+
case WM2200_DSP2_CONTROL_13:
754
+
case WM2200_DSP2_CONTROL_14:
755
+
case WM2200_DSP2_CONTROL_15:
756
+
case WM2200_DSP2_CONTROL_16:
757
+
case WM2200_DSP2_CONTROL_17:
758
+
case WM2200_DSP2_CONTROL_18:
759
+
case WM2200_DSP2_CONTROL_19:
760
+
case WM2200_DSP2_CONTROL_20:
761
+
case WM2200_DSP2_CONTROL_21:
762
+
case WM2200_DSP2_CONTROL_22:
763
+
case WM2200_DSP2_CONTROL_23:
764
+
case WM2200_DSP2_CONTROL_24:
765
+
case WM2200_DSP2_CONTROL_25:
766
+
case WM2200_DSP2_CONTROL_26:
767
+
case WM2200_DSP2_CONTROL_27:
768
+
case WM2200_DSP2_CONTROL_28:
769
+
case WM2200_DSP2_CONTROL_29:
770
+
case WM2200_DSP2_CONTROL_30:
771
+
case WM2200_DSP2_CONTROL_31:
772
+
return true;
773
+
default:
774
+
return false;
775
+
}
776
+
}
777
+
778
+
static const struct reg_default wm2200_reva_patch[] = {
779
+
{ 0x07, 0x0003 },
780
+
{ 0x102, 0x0200 },
781
+
{ 0x203, 0x0084 },
782
+
{ 0x201, 0x83FF },
783
+
{ 0x20C, 0x0062 },
784
+
{ 0x20D, 0x0062 },
785
+
{ 0x207, 0x2002 },
786
+
{ 0x208, 0x20C0 },
787
+
{ 0x21D, 0x01C0 },
788
+
{ 0x50A, 0x0001 },
789
+
{ 0x50B, 0x0002 },
790
+
{ 0x50C, 0x0003 },
791
+
{ 0x50D, 0x0004 },
792
+
{ 0x50E, 0x0005 },
793
+
{ 0x510, 0x0001 },
794
+
{ 0x511, 0x0002 },
795
+
{ 0x512, 0x0003 },
796
+
{ 0x513, 0x0004 },
797
+
{ 0x514, 0x0005 },
798
+
{ 0x515, 0x0000 },
799
+
{ 0x201, 0x8084 },
800
+
{ 0x202, 0xBBDE },
801
+
{ 0x203, 0x00EC },
802
+
{ 0x500, 0x8000 },
803
+
{ 0x507, 0x1820 },
804
+
{ 0x508, 0x1820 },
805
+
{ 0x505, 0x0300 },
806
+
{ 0x506, 0x0300 },
807
+
{ 0x302, 0x2280 },
808
+
{ 0x303, 0x0080 },
809
+
{ 0x304, 0x2280 },
810
+
{ 0x305, 0x0080 },
811
+
{ 0x306, 0x2280 },
812
+
{ 0x307, 0x0080 },
813
+
{ 0x401, 0x0080 },
814
+
{ 0x402, 0x0080 },
815
+
{ 0x417, 0x3069 },
816
+
{ 0x900, 0x6318 },
817
+
{ 0x901, 0x6300 },
818
+
{ 0x902, 0x0FC8 },
819
+
{ 0x903, 0x03FE },
820
+
{ 0x904, 0x00E0 },
821
+
{ 0x905, 0x1EC4 },
822
+
{ 0x906, 0xF136 },
823
+
{ 0x907, 0x0409 },
824
+
{ 0x908, 0x04CC },
825
+
{ 0x909, 0x1C9B },
826
+
{ 0x90A, 0xF337 },
827
+
{ 0x90B, 0x040B },
828
+
{ 0x90C, 0x0CBB },
829
+
{ 0x90D, 0x16F8 },
830
+
{ 0x90E, 0xF7D9 },
831
+
{ 0x90F, 0x040A },
832
+
{ 0x910, 0x1F14 },
833
+
{ 0x911, 0x058C },
834
+
{ 0x912, 0x0563 },
835
+
{ 0x913, 0x4000 },
836
+
{ 0x916, 0x6318 },
837
+
{ 0x917, 0x6300 },
838
+
{ 0x918, 0x0FC8 },
839
+
{ 0x919, 0x03FE },
840
+
{ 0x91A, 0x00E0 },
841
+
{ 0x91B, 0x1EC4 },
842
+
{ 0x91C, 0xF136 },
843
+
{ 0x91D, 0x0409 },
844
+
{ 0x91E, 0x04CC },
845
+
{ 0x91F, 0x1C9B },
846
+
{ 0x920, 0xF337 },
847
+
{ 0x921, 0x040B },
848
+
{ 0x922, 0x0CBB },
849
+
{ 0x923, 0x16F8 },
850
+
{ 0x924, 0xF7D9 },
851
+
{ 0x925, 0x040A },
852
+
{ 0x926, 0x1F14 },
853
+
{ 0x927, 0x058C },
854
+
{ 0x928, 0x0563 },
855
+
{ 0x929, 0x4000 },
856
+
{ 0x709, 0x2000 },
857
+
{ 0x207, 0x200E },
858
+
{ 0x208, 0x20D4 },
859
+
{ 0x20A, 0x0080 },
860
+
{ 0x07, 0x0000 },
861
+
};
862
+
863
+
static int wm2200_reset(struct wm2200_priv *wm2200)
864
+
{
865
+
if (wm2200->pdata.reset) {
866
+
gpio_set_value_cansleep(wm2200->pdata.reset, 0);
867
+
gpio_set_value_cansleep(wm2200->pdata.reset, 1);
868
+
869
+
return 0;
870
+
} else {
871
+
return regmap_write(wm2200->regmap, WM2200_SOFTWARE_RESET,
872
+
0x2200);
873
+
}
874
+
}
875
+
876
+
static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
877
+
static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
878
+
static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
879
+
880
+
static const char *wm2200_mixer_texts[] = {
881
+
"None",
882
+
"Tone Generator",
883
+
"AEC loopback",
884
+
"IN1L",
885
+
"IN1R",
886
+
"IN2L",
887
+
"IN2R",
888
+
"IN3L",
889
+
"IN3R",
890
+
"AIF1RX1",
891
+
"AIF1RX2",
892
+
"AIF1RX3",
893
+
"AIF1RX4",
894
+
"AIF1RX5",
895
+
"AIF1RX6",
896
+
"EQL",
897
+
"EQR",
898
+
"LHPF1",
899
+
"LHPF2",
900
+
"LHPF3",
901
+
"LHPF4",
902
+
"DSP1.1",
903
+
"DSP1.2",
904
+
"DSP1.3",
905
+
"DSP1.4",
906
+
"DSP1.5",
907
+
"DSP1.6",
908
+
"DSP2.1",
909
+
"DSP2.2",
910
+
"DSP2.3",
911
+
"DSP2.4",
912
+
"DSP2.5",
913
+
"DSP2.6",
914
+
};
915
+
916
+
static int wm2200_mixer_values[] = {
917
+
0x00,
918
+
0x04, /* Tone */
919
+
0x08, /* AEC */
920
+
0x10, /* Input */
921
+
0x11,
922
+
0x12,
923
+
0x13,
924
+
0x14,
925
+
0x15,
926
+
0x20, /* AIF */
927
+
0x21,
928
+
0x22,
929
+
0x23,
930
+
0x24,
931
+
0x25,
932
+
0x50, /* EQ */
933
+
0x51,
934
+
0x52,
935
+
0x60, /* LHPF1 */
936
+
0x61, /* LHPF2 */
937
+
0x68, /* DSP1 */
938
+
0x69,
939
+
0x6a,
940
+
0x6b,
941
+
0x6c,
942
+
0x6d,
943
+
0x70, /* DSP2 */
944
+
0x71,
945
+
0x72,
946
+
0x73,
947
+
0x74,
948
+
0x75,
949
+
};
950
+
951
+
#define WM2200_MIXER_CONTROLS(name, base) \
952
+
SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
953
+
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
954
+
SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
955
+
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
956
+
SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
957
+
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
958
+
SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
959
+
WM2200_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
960
+
961
+
#define WM2200_MUX_ENUM_DECL(name, reg) \
962
+
SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
963
+
wm2200_mixer_texts, wm2200_mixer_values)
964
+
965
+
#define WM2200_MUX_CTL_DECL(name) \
966
+
const struct snd_kcontrol_new name##_mux = \
967
+
SOC_DAPM_VALUE_ENUM("Route", name##_enum)
968
+
969
+
#define WM2200_MIXER_ENUMS(name, base_reg) \
970
+
static WM2200_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
971
+
static WM2200_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
972
+
static WM2200_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
973
+
static WM2200_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
974
+
static WM2200_MUX_CTL_DECL(name##_in1); \
975
+
static WM2200_MUX_CTL_DECL(name##_in2); \
976
+
static WM2200_MUX_CTL_DECL(name##_in3); \
977
+
static WM2200_MUX_CTL_DECL(name##_in4)
978
+
979
+
static const struct snd_kcontrol_new wm2200_snd_controls[] = {
980
+
SOC_SINGLE("IN1 High Performance Switch", WM2200_IN1L_CONTROL,
981
+
WM2200_IN1_OSR_SHIFT, 1, 0),
982
+
SOC_SINGLE("IN2 High Performance Switch", WM2200_IN2L_CONTROL,
983
+
WM2200_IN2_OSR_SHIFT, 1, 0),
984
+
SOC_SINGLE("IN3 High Performance Switch", WM2200_IN3L_CONTROL,
985
+
WM2200_IN3_OSR_SHIFT, 1, 0),
986
+
987
+
SOC_DOUBLE_R_TLV("IN1 Volume", WM2200_IN1L_CONTROL, WM2200_IN1R_CONTROL,
988
+
WM2200_IN1L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
989
+
SOC_DOUBLE_R_TLV("IN2 Volume", WM2200_IN2L_CONTROL, WM2200_IN2R_CONTROL,
990
+
WM2200_IN2L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
991
+
SOC_DOUBLE_R_TLV("IN3 Volume", WM2200_IN3L_CONTROL, WM2200_IN3R_CONTROL,
992
+
WM2200_IN3L_PGA_VOL_SHIFT, 0x5f, 0, in_tlv),
993
+
994
+
SOC_DOUBLE_R("IN1 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L,
995
+
WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_MUTE_SHIFT, 1, 1),
996
+
SOC_DOUBLE_R("IN2 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L,
997
+
WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_MUTE_SHIFT, 1, 1),
998
+
SOC_DOUBLE_R("IN3 Digital Switch", WM2200_ADC_DIGITAL_VOLUME_1L,
999
+
WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_MUTE_SHIFT, 1, 1),
1000
+
1001
+
SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_1L,
1002
+
WM2200_ADC_DIGITAL_VOLUME_1R, WM2200_IN1L_DIG_VOL_SHIFT,
1003
+
0xbf, 0, digital_tlv),
1004
+
SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_2L,
1005
+
WM2200_ADC_DIGITAL_VOLUME_2R, WM2200_IN2L_DIG_VOL_SHIFT,
1006
+
0xbf, 0, digital_tlv),
1007
+
SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM2200_ADC_DIGITAL_VOLUME_3L,
1008
+
WM2200_ADC_DIGITAL_VOLUME_3R, WM2200_IN3L_DIG_VOL_SHIFT,
1009
+
0xbf, 0, digital_tlv),
1010
+
1011
+
SOC_SINGLE("OUT1 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
1012
+
WM2200_OUT1_OSR_SHIFT, 1, 0),
1013
+
SOC_SINGLE("OUT2 High Performance Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
1014
+
WM2200_OUT2_OSR_SHIFT, 1, 0),
1015
+
1016
+
SOC_DOUBLE_R("OUT1 Digital Switch", WM2200_DAC_DIGITAL_VOLUME_1L,
1017
+
WM2200_DAC_DIGITAL_VOLUME_1R, WM2200_OUT1L_MUTE_SHIFT, 1, 1),
1018
+
SOC_DOUBLE_R_TLV("OUT1 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_1L,
1019
+
WM2200_DAC_DIGITAL_VOLUME_1R, WM2200_OUT1L_VOL_SHIFT, 0x9f, 0,
1020
+
digital_tlv),
1021
+
SOC_DOUBLE_R_TLV("OUT1 Volume", WM2200_DAC_VOLUME_LIMIT_1L,
1022
+
WM2200_DAC_VOLUME_LIMIT_1R, WM2200_OUT1L_PGA_VOL_SHIFT,
1023
+
0x46, 0, out_tlv),
1024
+
1025
+
SOC_DOUBLE_R("OUT2 Digital Switch", WM2200_DAC_DIGITAL_VOLUME_2L,
1026
+
WM2200_DAC_DIGITAL_VOLUME_2R, WM2200_OUT2L_MUTE_SHIFT, 1, 1),
1027
+
SOC_DOUBLE_R_TLV("OUT2 Digital Volume", WM2200_DAC_DIGITAL_VOLUME_2L,
1028
+
WM2200_DAC_DIGITAL_VOLUME_2R, WM2200_OUT2L_VOL_SHIFT, 0x9f, 0,
1029
+
digital_tlv),
1030
+
SOC_DOUBLE("OUT2 Switch", WM2200_PDM_1, WM2200_SPK1L_MUTE_SHIFT,
1031
+
WM2200_SPK1R_MUTE_SHIFT, 1, 0),
1032
+
};
1033
+
1034
+
WM2200_MIXER_ENUMS(OUT1L, WM2200_OUT1LMIX_INPUT_1_SOURCE);
1035
+
WM2200_MIXER_ENUMS(OUT1R, WM2200_OUT1RMIX_INPUT_1_SOURCE);
1036
+
WM2200_MIXER_ENUMS(OUT2L, WM2200_OUT2LMIX_INPUT_1_SOURCE);
1037
+
WM2200_MIXER_ENUMS(OUT2R, WM2200_OUT2RMIX_INPUT_1_SOURCE);
1038
+
1039
+
WM2200_MIXER_ENUMS(AIF1TX1, WM2200_AIF1TX1MIX_INPUT_1_SOURCE);
1040
+
WM2200_MIXER_ENUMS(AIF1TX2, WM2200_AIF1TX2MIX_INPUT_1_SOURCE);
1041
+
WM2200_MIXER_ENUMS(AIF1TX3, WM2200_AIF1TX3MIX_INPUT_1_SOURCE);
1042
+
WM2200_MIXER_ENUMS(AIF1TX4, WM2200_AIF1TX4MIX_INPUT_1_SOURCE);
1043
+
WM2200_MIXER_ENUMS(AIF1TX5, WM2200_AIF1TX5MIX_INPUT_1_SOURCE);
1044
+
WM2200_MIXER_ENUMS(AIF1TX6, WM2200_AIF1TX6MIX_INPUT_1_SOURCE);
1045
+
1046
+
WM2200_MIXER_ENUMS(EQL, WM2200_EQLMIX_INPUT_1_SOURCE);
1047
+
WM2200_MIXER_ENUMS(EQR, WM2200_EQRMIX_INPUT_1_SOURCE);
1048
+
1049
+
WM2200_MIXER_ENUMS(DSP1L, WM2200_DSP1LMIX_INPUT_1_SOURCE);
1050
+
WM2200_MIXER_ENUMS(DSP1R, WM2200_DSP1RMIX_INPUT_1_SOURCE);
1051
+
WM2200_MIXER_ENUMS(DSP2L, WM2200_DSP2LMIX_INPUT_1_SOURCE);
1052
+
WM2200_MIXER_ENUMS(DSP2R, WM2200_DSP2RMIX_INPUT_1_SOURCE);
1053
+
1054
+
WM2200_MIXER_ENUMS(LHPF1, WM2200_LHPF1MIX_INPUT_1_SOURCE);
1055
+
WM2200_MIXER_ENUMS(LHPF2, WM2200_LHPF2MIX_INPUT_1_SOURCE);
1056
+
1057
+
#define WM2200_MUX(name, ctrl) \
1058
+
SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
1059
+
1060
+
#define WM2200_MIXER_WIDGETS(name, name_str) \
1061
+
WM2200_MUX(name_str " Input 1", &name##_in1_mux), \
1062
+
WM2200_MUX(name_str " Input 2", &name##_in2_mux), \
1063
+
WM2200_MUX(name_str " Input 3", &name##_in3_mux), \
1064
+
WM2200_MUX(name_str " Input 4", &name##_in4_mux), \
1065
+
SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
1066
+
1067
+
#define WM2200_MIXER_INPUT_ROUTES(name) \
1068
+
{ name, "Tone Generator", "Tone Generator" }, \
1069
+
{ name, "IN1L", "IN1L PGA" }, \
1070
+
{ name, "IN1R", "IN1R PGA" }, \
1071
+
{ name, "IN2L", "IN2L PGA" }, \
1072
+
{ name, "IN2R", "IN2R PGA" }, \
1073
+
{ name, "IN3L", "IN3L PGA" }, \
1074
+
{ name, "IN3R", "IN3R PGA" }, \
1075
+
{ name, "DSP1.1", "DSP1" }, \
1076
+
{ name, "DSP1.2", "DSP1" }, \
1077
+
{ name, "DSP1.3", "DSP1" }, \
1078
+
{ name, "DSP1.4", "DSP1" }, \
1079
+
{ name, "DSP1.5", "DSP1" }, \
1080
+
{ name, "DSP1.6", "DSP1" }, \
1081
+
{ name, "DSP2.1", "DSP2" }, \
1082
+
{ name, "DSP2.2", "DSP2" }, \
1083
+
{ name, "DSP2.3", "DSP2" }, \
1084
+
{ name, "DSP2.4", "DSP2" }, \
1085
+
{ name, "DSP2.5", "DSP2" }, \
1086
+
{ name, "DSP2.6", "DSP2" }, \
1087
+
{ name, "AIF1RX1", "AIF1RX1" }, \
1088
+
{ name, "AIF1RX2", "AIF1RX2" }, \
1089
+
{ name, "AIF1RX3", "AIF1RX3" }, \
1090
+
{ name, "AIF1RX4", "AIF1RX4" }, \
1091
+
{ name, "AIF1RX5", "AIF1RX5" }, \
1092
+
{ name, "AIF1RX6", "AIF1RX6" }, \
1093
+
{ name, "EQL", "EQL" }, \
1094
+
{ name, "EQR", "EQR" }, \
1095
+
{ name, "LHPF1", "LHPF1" }, \
1096
+
{ name, "LHPF2", "LHPF2" }
1097
+
1098
+
#define WM2200_MIXER_ROUTES(widget, name) \
1099
+
{ widget, NULL, name " Mixer" }, \
1100
+
{ name " Mixer", NULL, name " Input 1" }, \
1101
+
{ name " Mixer", NULL, name " Input 2" }, \
1102
+
{ name " Mixer", NULL, name " Input 3" }, \
1103
+
{ name " Mixer", NULL, name " Input 4" }, \
1104
+
WM2200_MIXER_INPUT_ROUTES(name " Input 1"), \
1105
+
WM2200_MIXER_INPUT_ROUTES(name " Input 2"), \
1106
+
WM2200_MIXER_INPUT_ROUTES(name " Input 3"), \
1107
+
WM2200_MIXER_INPUT_ROUTES(name " Input 4")
1108
+
1109
+
static const struct snd_soc_dapm_widget wm2200_dapm_widgets[] = {
1110
+
SND_SOC_DAPM_SUPPLY("SYSCLK", WM2200_CLOCKING_3, WM2200_SYSCLK_ENA_SHIFT, 0,
1111
+
NULL, 0),
1112
+
SND_SOC_DAPM_SUPPLY("CP1", WM2200_DM_CHARGE_PUMP_1, WM2200_CPDM_ENA_SHIFT, 0,
1113
+
NULL, 0),
1114
+
SND_SOC_DAPM_SUPPLY("CP2", WM2200_MIC_CHARGE_PUMP_1, WM2200_CPMIC_ENA_SHIFT, 0,
1115
+
NULL, 0),
1116
+
SND_SOC_DAPM_SUPPLY("MICBIAS1", WM2200_MIC_BIAS_CTRL_1, WM2200_MICB1_ENA_SHIFT,
1117
+
0, NULL, 0),
1118
+
SND_SOC_DAPM_SUPPLY("MICBIAS2", WM2200_MIC_BIAS_CTRL_2, WM2200_MICB2_ENA_SHIFT,
1119
+
0, NULL, 0),
1120
+
SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20),
1121
+
SND_SOC_DAPM_REGULATOR_SUPPLY("AVDD", 20),
1122
+
1123
+
SND_SOC_DAPM_INPUT("IN1L"),
1124
+
SND_SOC_DAPM_INPUT("IN1R"),
1125
+
SND_SOC_DAPM_INPUT("IN2L"),
1126
+
SND_SOC_DAPM_INPUT("IN2R"),
1127
+
SND_SOC_DAPM_INPUT("IN3L"),
1128
+
SND_SOC_DAPM_INPUT("IN3R"),
1129
+
1130
+
SND_SOC_DAPM_SIGGEN("TONE"),
1131
+
SND_SOC_DAPM_PGA("Tone Generator", WM2200_TONE_GENERATOR_1,
1132
+
WM2200_TONE_ENA_SHIFT, 0, NULL, 0),
1133
+
1134
+
SND_SOC_DAPM_PGA("IN1L PGA", WM2200_INPUT_ENABLES, WM2200_IN1L_ENA_SHIFT, 0,
1135
+
NULL, 0),
1136
+
SND_SOC_DAPM_PGA("IN1R PGA", WM2200_INPUT_ENABLES, WM2200_IN1R_ENA_SHIFT, 0,
1137
+
NULL, 0),
1138
+
SND_SOC_DAPM_PGA("IN2L PGA", WM2200_INPUT_ENABLES, WM2200_IN2L_ENA_SHIFT, 0,
1139
+
NULL, 0),
1140
+
SND_SOC_DAPM_PGA("IN2R PGA", WM2200_INPUT_ENABLES, WM2200_IN2R_ENA_SHIFT, 0,
1141
+
NULL, 0),
1142
+
SND_SOC_DAPM_PGA("IN3L PGA", WM2200_INPUT_ENABLES, WM2200_IN3L_ENA_SHIFT, 0,
1143
+
NULL, 0),
1144
+
SND_SOC_DAPM_PGA("IN3R PGA", WM2200_INPUT_ENABLES, WM2200_IN3R_ENA_SHIFT, 0,
1145
+
NULL, 0),
1146
+
1147
+
SND_SOC_DAPM_AIF_IN("AIF1RX1", "Playback", 0,
1148
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX1_ENA_SHIFT, 0),
1149
+
SND_SOC_DAPM_AIF_IN("AIF1RX2", "Playback", 1,
1150
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX2_ENA_SHIFT, 0),
1151
+
SND_SOC_DAPM_AIF_IN("AIF1RX3", "Playback", 2,
1152
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX3_ENA_SHIFT, 0),
1153
+
SND_SOC_DAPM_AIF_IN("AIF1RX4", "Playback", 3,
1154
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX4_ENA_SHIFT, 0),
1155
+
SND_SOC_DAPM_AIF_IN("AIF1RX5", "Playback", 4,
1156
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX5_ENA_SHIFT, 0),
1157
+
SND_SOC_DAPM_AIF_IN("AIF1RX6", "Playback", 5,
1158
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1RX6_ENA_SHIFT, 0),
1159
+
1160
+
SND_SOC_DAPM_PGA("EQL", WM2200_EQL_1, WM2200_EQL_ENA_SHIFT, 0, NULL, 0),
1161
+
SND_SOC_DAPM_PGA("EQR", WM2200_EQR_1, WM2200_EQR_ENA_SHIFT, 0, NULL, 0),
1162
+
1163
+
SND_SOC_DAPM_PGA("LHPF1", WM2200_HPLPF1_1, WM2200_LHPF1_ENA_SHIFT, 0,
1164
+
NULL, 0),
1165
+
SND_SOC_DAPM_PGA("LHPF2", WM2200_HPLPF2_1, WM2200_LHPF2_ENA_SHIFT, 0,
1166
+
NULL, 0),
1167
+
1168
+
SND_SOC_DAPM_PGA_E("DSP1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
1169
+
SND_SOC_DAPM_PGA_E("DSP2", SND_SOC_NOPM, 1, 0, NULL, 0, NULL, 0),
1170
+
1171
+
SND_SOC_DAPM_AIF_OUT("AIF1TX1", "Capture", 0,
1172
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX1_ENA_SHIFT, 0),
1173
+
SND_SOC_DAPM_AIF_OUT("AIF1TX2", "Capture", 1,
1174
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX2_ENA_SHIFT, 0),
1175
+
SND_SOC_DAPM_AIF_OUT("AIF1TX3", "Capture", 2,
1176
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX3_ENA_SHIFT, 0),
1177
+
SND_SOC_DAPM_AIF_OUT("AIF1TX4", "Capture", 3,
1178
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX4_ENA_SHIFT, 0),
1179
+
SND_SOC_DAPM_AIF_OUT("AIF1TX5", "Capture", 4,
1180
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX5_ENA_SHIFT, 0),
1181
+
SND_SOC_DAPM_AIF_OUT("AIF1TX6", "Capture", 5,
1182
+
WM2200_AUDIO_IF_1_22, WM2200_AIF1TX6_ENA_SHIFT, 0),
1183
+
1184
+
SND_SOC_DAPM_PGA_S("OUT1L", 0, WM2200_OUTPUT_ENABLES,
1185
+
WM2200_OUT1L_ENA_SHIFT, 0, NULL, 0),
1186
+
SND_SOC_DAPM_PGA_S("OUT1R", 0, WM2200_OUTPUT_ENABLES,
1187
+
WM2200_OUT1R_ENA_SHIFT, 0, NULL, 0),
1188
+
1189
+
SND_SOC_DAPM_PGA_S("EPD_LP", 1, WM2200_EAR_PIECE_CTRL_1,
1190
+
WM2200_EPD_LP_ENA_SHIFT, 0, NULL, 0),
1191
+
SND_SOC_DAPM_PGA_S("EPD_OUTP_LP", 1, WM2200_EAR_PIECE_CTRL_1,
1192
+
WM2200_EPD_OUTP_LP_ENA_SHIFT, 0, NULL, 0),
1193
+
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_LP", 1, WM2200_EAR_PIECE_CTRL_1,
1194
+
WM2200_EPD_RMV_SHRT_LP_SHIFT, 0, NULL, 0),
1195
+
1196
+
SND_SOC_DAPM_PGA_S("EPD_LN", 1, WM2200_EAR_PIECE_CTRL_1,
1197
+
WM2200_EPD_LN_ENA_SHIFT, 0, NULL, 0),
1198
+
SND_SOC_DAPM_PGA_S("EPD_OUTP_LN", 1, WM2200_EAR_PIECE_CTRL_1,
1199
+
WM2200_EPD_OUTP_LN_ENA_SHIFT, 0, NULL, 0),
1200
+
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_LN", 1, WM2200_EAR_PIECE_CTRL_1,
1201
+
WM2200_EPD_RMV_SHRT_LN_SHIFT, 0, NULL, 0),
1202
+
1203
+
SND_SOC_DAPM_PGA_S("EPD_RP", 1, WM2200_EAR_PIECE_CTRL_2,
1204
+
WM2200_EPD_RP_ENA_SHIFT, 0, NULL, 0),
1205
+
SND_SOC_DAPM_PGA_S("EPD_OUTP_RP", 1, WM2200_EAR_PIECE_CTRL_2,
1206
+
WM2200_EPD_OUTP_RP_ENA_SHIFT, 0, NULL, 0),
1207
+
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_RP", 1, WM2200_EAR_PIECE_CTRL_2,
1208
+
WM2200_EPD_RMV_SHRT_RP_SHIFT, 0, NULL, 0),
1209
+
1210
+
SND_SOC_DAPM_PGA_S("EPD_RN", 1, WM2200_EAR_PIECE_CTRL_2,
1211
+
WM2200_EPD_RN_ENA_SHIFT, 0, NULL, 0),
1212
+
SND_SOC_DAPM_PGA_S("EPD_OUTP_RN", 1, WM2200_EAR_PIECE_CTRL_2,
1213
+
WM2200_EPD_OUTP_RN_ENA_SHIFT, 0, NULL, 0),
1214
+
SND_SOC_DAPM_PGA_S("EPD_RMV_SHRT_RN", 1, WM2200_EAR_PIECE_CTRL_2,
1215
+
WM2200_EPD_RMV_SHRT_RN_SHIFT, 0, NULL, 0),
1216
+
1217
+
SND_SOC_DAPM_PGA("OUT2L", WM2200_OUTPUT_ENABLES, WM2200_OUT2L_ENA_SHIFT,
1218
+
0, NULL, 0),
1219
+
SND_SOC_DAPM_PGA("OUT2R", WM2200_OUTPUT_ENABLES, WM2200_OUT2R_ENA_SHIFT,
1220
+
0, NULL, 0),
1221
+
1222
+
SND_SOC_DAPM_OUTPUT("EPOUTLN"),
1223
+
SND_SOC_DAPM_OUTPUT("EPOUTLP"),
1224
+
SND_SOC_DAPM_OUTPUT("EPOUTRN"),
1225
+
SND_SOC_DAPM_OUTPUT("EPOUTRP"),
1226
+
SND_SOC_DAPM_OUTPUT("SPK"),
1227
+
1228
+
WM2200_MIXER_WIDGETS(EQL, "EQL"),
1229
+
WM2200_MIXER_WIDGETS(EQR, "EQR"),
1230
+
1231
+
WM2200_MIXER_WIDGETS(LHPF1, "LHPF1"),
1232
+
WM2200_MIXER_WIDGETS(LHPF2, "LHPF2"),
1233
+
1234
+
WM2200_MIXER_WIDGETS(DSP1L, "DSP1L"),
1235
+
WM2200_MIXER_WIDGETS(DSP1R, "DSP1R"),
1236
+
WM2200_MIXER_WIDGETS(DSP2L, "DSP2L"),
1237
+
WM2200_MIXER_WIDGETS(DSP2R, "DSP2R"),
1238
+
1239
+
WM2200_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1240
+
WM2200_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1241
+
WM2200_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1242
+
WM2200_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1243
+
WM2200_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1244
+
WM2200_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1245
+
1246
+
WM2200_MIXER_WIDGETS(OUT1L, "OUT1L"),
1247
+
WM2200_MIXER_WIDGETS(OUT1R, "OUT1R"),
1248
+
WM2200_MIXER_WIDGETS(OUT2L, "OUT2L"),
1249
+
WM2200_MIXER_WIDGETS(OUT2R, "OUT2R"),
1250
+
};
1251
+
1252
+
static const struct snd_soc_dapm_route wm2200_dapm_routes[] = {
1253
+
/* Everything needs SYSCLK but only hook up things on the edge
1254
+
* of the chip */
1255
+
{ "IN1L", NULL, "SYSCLK" },
1256
+
{ "IN1R", NULL, "SYSCLK" },
1257
+
{ "IN2L", NULL, "SYSCLK" },
1258
+
{ "IN2R", NULL, "SYSCLK" },
1259
+
{ "IN3L", NULL, "SYSCLK" },
1260
+
{ "IN3R", NULL, "SYSCLK" },
1261
+
{ "OUT1L", NULL, "SYSCLK" },
1262
+
{ "OUT1R", NULL, "SYSCLK" },
1263
+
{ "OUT2L", NULL, "SYSCLK" },
1264
+
{ "OUT2R", NULL, "SYSCLK" },
1265
+
{ "AIF1RX1", NULL, "SYSCLK" },
1266
+
{ "AIF1RX2", NULL, "SYSCLK" },
1267
+
{ "AIF1RX3", NULL, "SYSCLK" },
1268
+
{ "AIF1RX4", NULL, "SYSCLK" },
1269
+
{ "AIF1RX5", NULL, "SYSCLK" },
1270
+
{ "AIF1RX6", NULL, "SYSCLK" },
1271
+
{ "AIF1TX1", NULL, "SYSCLK" },
1272
+
{ "AIF1TX2", NULL, "SYSCLK" },
1273
+
{ "AIF1TX3", NULL, "SYSCLK" },
1274
+
{ "AIF1TX4", NULL, "SYSCLK" },
1275
+
{ "AIF1TX5", NULL, "SYSCLK" },
1276
+
{ "AIF1TX6", NULL, "SYSCLK" },
1277
+
1278
+
{ "IN1L", NULL, "AVDD" },
1279
+
{ "IN1R", NULL, "AVDD" },
1280
+
{ "IN2L", NULL, "AVDD" },
1281
+
{ "IN2R", NULL, "AVDD" },
1282
+
{ "IN3L", NULL, "AVDD" },
1283
+
{ "IN3R", NULL, "AVDD" },
1284
+
{ "OUT1L", NULL, "AVDD" },
1285
+
{ "OUT1R", NULL, "AVDD" },
1286
+
1287
+
{ "IN1L PGA", NULL, "IN1L" },
1288
+
{ "IN1R PGA", NULL, "IN1R" },
1289
+
{ "IN2L PGA", NULL, "IN2L" },
1290
+
{ "IN2R PGA", NULL, "IN2R" },
1291
+
{ "IN3L PGA", NULL, "IN3L" },
1292
+
{ "IN3R PGA", NULL, "IN3R" },
1293
+
1294
+
{ "Tone Generator", NULL, "TONE" },
1295
+
1296
+
{ "CP2", NULL, "CPVDD" },
1297
+
{ "MICBIAS1", NULL, "CP2" },
1298
+
{ "MICBIAS2", NULL, "CP2" },
1299
+
1300
+
{ "CP1", NULL, "CPVDD" },
1301
+
{ "EPD_LN", NULL, "CP1" },
1302
+
{ "EPD_LP", NULL, "CP1" },
1303
+
{ "EPD_RN", NULL, "CP1" },
1304
+
{ "EPD_RP", NULL, "CP1" },
1305
+
1306
+
{ "EPD_LP", NULL, "OUT1L" },
1307
+
{ "EPD_OUTP_LP", NULL, "EPD_LP" },
1308
+
{ "EPD_RMV_SHRT_LP", NULL, "EPD_OUTP_LP" },
1309
+
{ "EPOUTLP", NULL, "EPD_RMV_SHRT_LP" },
1310
+
1311
+
{ "EPD_LN", NULL, "OUT1L" },
1312
+
{ "EPD_OUTP_LN", NULL, "EPD_LN" },
1313
+
{ "EPD_RMV_SHRT_LN", NULL, "EPD_OUTP_LN" },
1314
+
{ "EPOUTLN", NULL, "EPD_RMV_SHRT_LN" },
1315
+
1316
+
{ "EPD_RP", NULL, "OUT1R" },
1317
+
{ "EPD_OUTP_RP", NULL, "EPD_RP" },
1318
+
{ "EPD_RMV_SHRT_RP", NULL, "EPD_OUTP_RP" },
1319
+
{ "EPOUTRP", NULL, "EPD_RMV_SHRT_RP" },
1320
+
1321
+
{ "EPD_RN", NULL, "OUT1R" },
1322
+
{ "EPD_OUTP_RN", NULL, "EPD_RN" },
1323
+
{ "EPD_RMV_SHRT_RN", NULL, "EPD_OUTP_RN" },
1324
+
{ "EPOUTRN", NULL, "EPD_RMV_SHRT_RN" },
1325
+
1326
+
{ "SPK", NULL, "OUT2L" },
1327
+
{ "SPK", NULL, "OUT2R" },
1328
+
1329
+
WM2200_MIXER_ROUTES("DSP1", "DSP1L"),
1330
+
WM2200_MIXER_ROUTES("DSP1", "DSP1R"),
1331
+
WM2200_MIXER_ROUTES("DSP2", "DSP2L"),
1332
+
WM2200_MIXER_ROUTES("DSP2", "DSP2R"),
1333
+
1334
+
WM2200_MIXER_ROUTES("OUT1L", "OUT1L"),
1335
+
WM2200_MIXER_ROUTES("OUT1R", "OUT1R"),
1336
+
WM2200_MIXER_ROUTES("OUT2L", "OUT2L"),
1337
+
WM2200_MIXER_ROUTES("OUT2R", "OUT2R"),
1338
+
1339
+
WM2200_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1340
+
WM2200_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1341
+
WM2200_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1342
+
WM2200_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1343
+
WM2200_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1344
+
WM2200_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1345
+
1346
+
WM2200_MIXER_ROUTES("EQL", "EQL"),
1347
+
WM2200_MIXER_ROUTES("EQR", "EQR"),
1348
+
1349
+
WM2200_MIXER_ROUTES("LHPF1", "LHPF1"),
1350
+
WM2200_MIXER_ROUTES("LHPF2", "LHPF2"),
1351
+
};
1352
+
1353
+
static int wm2200_probe(struct snd_soc_codec *codec)
1354
+
{
1355
+
struct wm2200_priv *wm2200 = dev_get_drvdata(codec->dev);
1356
+
int ret;
1357
+
1358
+
wm2200->codec = codec;
1359
+
codec->control_data = wm2200->regmap;
1360
+
codec->dapm.bias_level = SND_SOC_BIAS_OFF;
1361
+
1362
+
ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
1363
+
if (ret != 0) {
1364
+
dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1365
+
return ret;
1366
+
}
1367
+
1368
+
return ret;
1369
+
}
1370
+
1371
+
static int wm2200_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1372
+
{
1373
+
struct snd_soc_codec *codec = dai->codec;
1374
+
int lrclk, bclk, fmt_val;
1375
+
1376
+
lrclk = 0;
1377
+
bclk = 0;
1378
+
1379
+
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1380
+
case SND_SOC_DAIFMT_DSP_A:
1381
+
fmt_val = 0;
1382
+
break;
1383
+
case SND_SOC_DAIFMT_DSP_B:
1384
+
fmt_val = 1;
1385
+
break;
1386
+
case SND_SOC_DAIFMT_I2S:
1387
+
fmt_val = 2;
1388
+
break;
1389
+
case SND_SOC_DAIFMT_LEFT_J:
1390
+
fmt_val = 3;
1391
+
break;
1392
+
default:
1393
+
dev_err(codec->dev, "Unsupported DAI format %d\n",
1394
+
fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1395
+
return -EINVAL;
1396
+
}
1397
+
1398
+
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1399
+
case SND_SOC_DAIFMT_CBS_CFS:
1400
+
break;
1401
+
case SND_SOC_DAIFMT_CBS_CFM:
1402
+
lrclk |= WM2200_AIF1TX_LRCLK_MSTR;
1403
+
break;
1404
+
case SND_SOC_DAIFMT_CBM_CFS:
1405
+
bclk |= WM2200_AIF1_BCLK_MSTR;
1406
+
break;
1407
+
case SND_SOC_DAIFMT_CBM_CFM:
1408
+
lrclk |= WM2200_AIF1TX_LRCLK_MSTR;
1409
+
bclk |= WM2200_AIF1_BCLK_MSTR;
1410
+
break;
1411
+
default:
1412
+
dev_err(codec->dev, "Unsupported master mode %d\n",
1413
+
fmt & SND_SOC_DAIFMT_MASTER_MASK);
1414
+
return -EINVAL;
1415
+
}
1416
+
1417
+
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1418
+
case SND_SOC_DAIFMT_NB_NF:
1419
+
break;
1420
+
case SND_SOC_DAIFMT_IB_IF:
1421
+
bclk |= WM2200_AIF1_BCLK_INV;
1422
+
lrclk |= WM2200_AIF1TX_LRCLK_INV;
1423
+
break;
1424
+
case SND_SOC_DAIFMT_IB_NF:
1425
+
bclk |= WM2200_AIF1_BCLK_INV;
1426
+
break;
1427
+
case SND_SOC_DAIFMT_NB_IF:
1428
+
lrclk |= WM2200_AIF1TX_LRCLK_INV;
1429
+
break;
1430
+
default:
1431
+
return -EINVAL;
1432
+
}
1433
+
1434
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_1, WM2200_AIF1_BCLK_MSTR |
1435
+
WM2200_AIF1_BCLK_INV, bclk);
1436
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_2,
1437
+
WM2200_AIF1TX_LRCLK_MSTR | WM2200_AIF1TX_LRCLK_INV,
1438
+
lrclk);
1439
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_3,
1440
+
WM2200_AIF1TX_LRCLK_MSTR | WM2200_AIF1TX_LRCLK_INV,
1441
+
lrclk);
1442
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_5,
1443
+
WM2200_AIF1_FMT_MASK << 1, fmt_val << 1);
1444
+
1445
+
return 0;
1446
+
}
1447
+
1448
+
static int wm2200_sr_code[] = {
1449
+
0,
1450
+
12000,
1451
+
24000,
1452
+
48000,
1453
+
96000,
1454
+
192000,
1455
+
384000,
1456
+
768000,
1457
+
0,
1458
+
11025,
1459
+
22050,
1460
+
44100,
1461
+
88200,
1462
+
176400,
1463
+
352800,
1464
+
705600,
1465
+
4000,
1466
+
8000,
1467
+
16000,
1468
+
32000,
1469
+
64000,
1470
+
128000,
1471
+
256000,
1472
+
512000,
1473
+
};
1474
+
1475
+
#define WM2200_NUM_BCLK_RATES 12
1476
+
1477
+
static int wm2200_bclk_rates_dat[WM2200_NUM_BCLK_RATES] = {
1478
+
6144000,
1479
+
3072000,
1480
+
2048000,
1481
+
1536000,
1482
+
768000,
1483
+
512000,
1484
+
384000,
1485
+
256000,
1486
+
192000,
1487
+
128000,
1488
+
96000,
1489
+
64000,
1490
+
};
1491
+
1492
+
static int wm2200_bclk_rates_cd[WM2200_NUM_BCLK_RATES] = {
1493
+
5644800,
1494
+
2882400,
1495
+
1881600,
1496
+
1411200,
1497
+
705600,
1498
+
470400,
1499
+
352800,
1500
+
176400,
1501
+
117600,
1502
+
88200,
1503
+
58800,
1504
+
};
1505
+
1506
+
static int wm2200_hw_params(struct snd_pcm_substream *substream,
1507
+
struct snd_pcm_hw_params *params,
1508
+
struct snd_soc_dai *dai)
1509
+
{
1510
+
struct snd_soc_codec *codec = dai->codec;
1511
+
struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
1512
+
int i, bclk, lrclk, wl, fl, sr_code;
1513
+
int *bclk_rates;
1514
+
1515
+
/* Data sizes if not using TDM */
1516
+
wl = snd_pcm_format_width(params_format(params));
1517
+
if (wl < 0)
1518
+
return wl;
1519
+
fl = snd_soc_params_to_frame_size(params);
1520
+
if (fl < 0)
1521
+
return fl;
1522
+
1523
+
dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1524
+
wl, fl);
1525
+
1526
+
/* Target BCLK rate */
1527
+
bclk = snd_soc_params_to_bclk(params);
1528
+
if (bclk < 0)
1529
+
return bclk;
1530
+
1531
+
if (!wm2200->sysclk) {
1532
+
dev_err(codec->dev, "SYSCLK has no rate set\n");
1533
+
return -EINVAL;
1534
+
}
1535
+
1536
+
for (i = 0; i < ARRAY_SIZE(wm2200_sr_code); i++)
1537
+
if (wm2200_sr_code[i] == params_rate(params))
1538
+
break;
1539
+
if (i == ARRAY_SIZE(wm2200_sr_code)) {
1540
+
dev_err(codec->dev, "Unsupported sample rate: %dHz\n",
1541
+
params_rate(params));
1542
+
return -EINVAL;
1543
+
}
1544
+
sr_code = i;
1545
+
1546
+
dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n",
1547
+
bclk, wm2200->sysclk);
1548
+
1549
+
if (wm2200->sysclk % 4000)
1550
+
bclk_rates = wm2200_bclk_rates_cd;
1551
+
else
1552
+
bclk_rates = wm2200_bclk_rates_dat;
1553
+
1554
+
for (i = 0; i < WM2200_NUM_BCLK_RATES; i++)
1555
+
if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1556
+
break;
1557
+
if (i == WM2200_NUM_BCLK_RATES) {
1558
+
dev_err(codec->dev,
1559
+
"No valid BCLK for %dHz found from %dHz SYSCLK\n",
1560
+
bclk, wm2200->sysclk);
1561
+
return -EINVAL;
1562
+
}
1563
+
1564
+
bclk = i;
1565
+
dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1566
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_1,
1567
+
WM2200_AIF1_BCLK_DIV_MASK, bclk);
1568
+
1569
+
lrclk = bclk_rates[bclk] / params_rate(params);
1570
+
dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1571
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1572
+
dai->symmetric_rates)
1573
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_7,
1574
+
WM2200_AIF1RX_BCPF_MASK, lrclk);
1575
+
else
1576
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_6,
1577
+
WM2200_AIF1TX_BCPF_MASK, lrclk);
1578
+
1579
+
i = (wl << WM2200_AIF1TX_WL_SHIFT) | wl;
1580
+
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1581
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_9,
1582
+
WM2200_AIF1RX_WL_MASK |
1583
+
WM2200_AIF1RX_SLOT_LEN_MASK, i);
1584
+
else
1585
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_8,
1586
+
WM2200_AIF1TX_WL_MASK |
1587
+
WM2200_AIF1TX_SLOT_LEN_MASK, i);
1588
+
1589
+
snd_soc_update_bits(codec, WM2200_CLOCKING_4,
1590
+
WM2200_SAMPLE_RATE_1_MASK, sr_code);
1591
+
1592
+
return 0;
1593
+
}
1594
+
1595
+
static const struct snd_soc_dai_ops wm2200_dai_ops = {
1596
+
.set_fmt = wm2200_set_fmt,
1597
+
.hw_params = wm2200_hw_params,
1598
+
};
1599
+
1600
+
static int wm2200_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1601
+
int source, unsigned int freq, int dir)
1602
+
{
1603
+
struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
1604
+
int fval;
1605
+
1606
+
switch (clk_id) {
1607
+
case WM2200_CLK_SYSCLK:
1608
+
break;
1609
+
1610
+
default:
1611
+
dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1612
+
return -EINVAL;
1613
+
}
1614
+
1615
+
switch (source) {
1616
+
case WM2200_CLKSRC_MCLK1:
1617
+
case WM2200_CLKSRC_MCLK2:
1618
+
case WM2200_CLKSRC_FLL:
1619
+
case WM2200_CLKSRC_BCLK1:
1620
+
break;
1621
+
default:
1622
+
dev_err(codec->dev, "Invalid source %d\n", source);
1623
+
return -EINVAL;
1624
+
}
1625
+
1626
+
switch (freq) {
1627
+
case 22579200:
1628
+
case 24576000:
1629
+
fval = 2;
1630
+
break;
1631
+
default:
1632
+
dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1633
+
return -EINVAL;
1634
+
}
1635
+
1636
+
/* TODO: Check if MCLKs are in use and enable/disable pulls to
1637
+
* match.
1638
+
*/
1639
+
1640
+
snd_soc_update_bits(codec, WM2200_CLOCKING_3, WM2200_SYSCLK_FREQ_MASK |
1641
+
WM2200_SYSCLK_SRC_MASK,
1642
+
fval << WM2200_SYSCLK_FREQ_SHIFT | source);
1643
+
1644
+
wm2200->sysclk = freq;
1645
+
1646
+
return 0;
1647
+
}
1648
+
1649
+
struct _fll_div {
1650
+
u16 fll_fratio;
1651
+
u16 fll_outdiv;
1652
+
u16 fll_refclk_div;
1653
+
u16 n;
1654
+
u16 theta;
1655
+
u16 lambda;
1656
+
};
1657
+
1658
+
static struct {
1659
+
unsigned int min;
1660
+
unsigned int max;
1661
+
u16 fll_fratio;
1662
+
int ratio;
1663
+
} fll_fratios[] = {
1664
+
{ 0, 64000, 4, 16 },
1665
+
{ 64000, 128000, 3, 8 },
1666
+
{ 128000, 256000, 2, 4 },
1667
+
{ 256000, 1000000, 1, 2 },
1668
+
{ 1000000, 13500000, 0, 1 },
1669
+
};
1670
+
1671
+
static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1672
+
unsigned int Fout)
1673
+
{
1674
+
unsigned int target;
1675
+
unsigned int div;
1676
+
unsigned int fratio, gcd_fll;
1677
+
int i;
1678
+
1679
+
/* Fref must be <=13.5MHz */
1680
+
div = 1;
1681
+
fll_div->fll_refclk_div = 0;
1682
+
while ((Fref / div) > 13500000) {
1683
+
div *= 2;
1684
+
fll_div->fll_refclk_div++;
1685
+
1686
+
if (div > 8) {
1687
+
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1688
+
Fref);
1689
+
return -EINVAL;
1690
+
}
1691
+
}
1692
+
1693
+
pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1694
+
1695
+
/* Apply the division for our remaining calculations */
1696
+
Fref /= div;
1697
+
1698
+
/* Fvco should be 90-100MHz; don't check the upper bound */
1699
+
div = 2;
1700
+
while (Fout * div < 90000000) {
1701
+
div++;
1702
+
if (div > 64) {
1703
+
pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1704
+
Fout);
1705
+
return -EINVAL;
1706
+
}
1707
+
}
1708
+
target = Fout * div;
1709
+
fll_div->fll_outdiv = div - 1;
1710
+
1711
+
pr_debug("FLL Fvco=%dHz\n", target);
1712
+
1713
+
/* Find an appropraite FLL_FRATIO and factor it out of the target */
1714
+
for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1715
+
if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1716
+
fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1717
+
fratio = fll_fratios[i].ratio;
1718
+
break;
1719
+
}
1720
+
}
1721
+
if (i == ARRAY_SIZE(fll_fratios)) {
1722
+
pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1723
+
return -EINVAL;
1724
+
}
1725
+
1726
+
fll_div->n = target / (fratio * Fref);
1727
+
1728
+
if (target % Fref == 0) {
1729
+
fll_div->theta = 0;
1730
+
fll_div->lambda = 0;
1731
+
} else {
1732
+
gcd_fll = gcd(target, fratio * Fref);
1733
+
1734
+
fll_div->theta = (target - (fll_div->n * fratio * Fref))
1735
+
/ gcd_fll;
1736
+
fll_div->lambda = (fratio * Fref) / gcd_fll;
1737
+
}
1738
+
1739
+
pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1740
+
fll_div->n, fll_div->theta, fll_div->lambda);
1741
+
pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1742
+
fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1743
+
fll_div->fll_refclk_div);
1744
+
1745
+
return 0;
1746
+
}
1747
+
1748
+
static int wm2200_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1749
+
unsigned int Fref, unsigned int Fout)
1750
+
{
1751
+
struct i2c_client *i2c = to_i2c_client(codec->dev);
1752
+
struct wm2200_priv *wm2200 = snd_soc_codec_get_drvdata(codec);
1753
+
struct _fll_div factors;
1754
+
int ret, i, timeout;
1755
+
1756
+
if (!Fout) {
1757
+
dev_dbg(codec->dev, "FLL disabled");
1758
+
1759
+
if (wm2200->fll_fout)
1760
+
pm_runtime_put(codec->dev);
1761
+
1762
+
wm2200->fll_fout = 0;
1763
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_1,
1764
+
WM2200_FLL_ENA, 0);
1765
+
return 0;
1766
+
}
1767
+
1768
+
switch (source) {
1769
+
case WM2200_FLL_SRC_MCLK1:
1770
+
case WM2200_FLL_SRC_MCLK2:
1771
+
case WM2200_FLL_SRC_BCLK:
1772
+
break;
1773
+
default:
1774
+
dev_err(codec->dev, "Invalid FLL source %d\n", source);
1775
+
return -EINVAL;
1776
+
}
1777
+
1778
+
ret = fll_factors(&factors, Fref, Fout);
1779
+
if (ret < 0)
1780
+
return ret;
1781
+
1782
+
/* Disable the FLL while we reconfigure */
1783
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_1, WM2200_FLL_ENA, 0);
1784
+
1785
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_2,
1786
+
WM2200_FLL_OUTDIV_MASK | WM2200_FLL_FRATIO_MASK,
1787
+
(factors.fll_outdiv << WM2200_FLL_OUTDIV_SHIFT) |
1788
+
factors.fll_fratio);
1789
+
if (factors.theta) {
1790
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_3,
1791
+
WM2200_FLL_FRACN_ENA,
1792
+
WM2200_FLL_FRACN_ENA);
1793
+
snd_soc_update_bits(codec, WM2200_FLL_EFS_2,
1794
+
WM2200_FLL_EFS_ENA,
1795
+
WM2200_FLL_EFS_ENA);
1796
+
} else {
1797
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_3,
1798
+
WM2200_FLL_FRACN_ENA, 0);
1799
+
snd_soc_update_bits(codec, WM2200_FLL_EFS_2,
1800
+
WM2200_FLL_EFS_ENA, 0);
1801
+
}
1802
+
1803
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_4, WM2200_FLL_THETA_MASK,
1804
+
factors.theta);
1805
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_6, WM2200_FLL_N_MASK,
1806
+
factors.n);
1807
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_7,
1808
+
WM2200_FLL_CLK_REF_DIV_MASK |
1809
+
WM2200_FLL_CLK_REF_SRC_MASK,
1810
+
(factors.fll_refclk_div
1811
+
<< WM2200_FLL_CLK_REF_DIV_SHIFT) | source);
1812
+
snd_soc_update_bits(codec, WM2200_FLL_EFS_1,
1813
+
WM2200_FLL_LAMBDA_MASK, factors.lambda);
1814
+
1815
+
/* Clear any pending completions */
1816
+
try_wait_for_completion(&wm2200->fll_lock);
1817
+
1818
+
pm_runtime_get_sync(codec->dev);
1819
+
1820
+
snd_soc_update_bits(codec, WM2200_FLL_CONTROL_1,
1821
+
WM2200_FLL_ENA, WM2200_FLL_ENA);
1822
+
1823
+
if (i2c->irq)
1824
+
timeout = 2;
1825
+
else
1826
+
timeout = 50;
1827
+
1828
+
snd_soc_update_bits(codec, WM2200_CLOCKING_3, WM2200_SYSCLK_ENA,
1829
+
WM2200_SYSCLK_ENA);
1830
+
1831
+
/* Poll for the lock; will use the interrupt to exit quickly */
1832
+
for (i = 0; i < timeout; i++) {
1833
+
if (i2c->irq) {
1834
+
ret = wait_for_completion_timeout(&wm2200->fll_lock,
1835
+
msecs_to_jiffies(25));
1836
+
if (ret > 0)
1837
+
break;
1838
+
} else {
1839
+
msleep(1);
1840
+
}
1841
+
1842
+
ret = snd_soc_read(codec,
1843
+
WM2200_INTERRUPT_RAW_STATUS_2);
1844
+
if (ret < 0) {
1845
+
dev_err(codec->dev,
1846
+
"Failed to read FLL status: %d\n",
1847
+
ret);
1848
+
continue;
1849
+
}
1850
+
if (ret & WM2200_FLL_LOCK_STS)
1851
+
break;
1852
+
}
1853
+
if (i == timeout) {
1854
+
dev_err(codec->dev, "FLL lock timed out\n");
1855
+
pm_runtime_put(codec->dev);
1856
+
return -ETIMEDOUT;
1857
+
}
1858
+
1859
+
wm2200->fll_src = source;
1860
+
wm2200->fll_fref = Fref;
1861
+
wm2200->fll_fout = Fout;
1862
+
1863
+
dev_dbg(codec->dev, "FLL running %dHz->%dHz\n", Fref, Fout);
1864
+
1865
+
return 0;
1866
+
}
1867
+
1868
+
static int wm2200_dai_probe(struct snd_soc_dai *dai)
1869
+
{
1870
+
struct snd_soc_codec *codec = dai->codec;
1871
+
unsigned int val = 0;
1872
+
int ret;
1873
+
1874
+
ret = snd_soc_read(codec, WM2200_GPIO_CTRL_1);
1875
+
if (ret >= 0) {
1876
+
if ((ret & WM2200_GP1_FN_MASK) != 0) {
1877
+
dai->symmetric_rates = true;
1878
+
val = WM2200_AIF1TX_LRCLK_SRC;
1879
+
}
1880
+
} else {
1881
+
dev_err(codec->dev, "Failed to read GPIO 1 config: %d\n", ret);
1882
+
}
1883
+
1884
+
snd_soc_update_bits(codec, WM2200_AUDIO_IF_1_2,
1885
+
WM2200_AIF1TX_LRCLK_SRC, val);
1886
+
1887
+
return 0;
1888
+
}
1889
+
1890
+
#define WM2200_RATES SNDRV_PCM_RATE_8000_48000
1891
+
1892
+
#define WM2200_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1893
+
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1894
+
1895
+
static struct snd_soc_dai_driver wm2200_dai = {
1896
+
.name = "wm2200",
1897
+
.probe = wm2200_dai_probe,
1898
+
.playback = {
1899
+
.stream_name = "Playback",
1900
+
.channels_min = 2,
1901
+
.channels_max = 2,
1902
+
.rates = WM2200_RATES,
1903
+
.formats = WM2200_FORMATS,
1904
+
},
1905
+
.capture = {
1906
+
.stream_name = "Capture",
1907
+
.channels_min = 2,
1908
+
.channels_max = 2,
1909
+
.rates = WM2200_RATES,
1910
+
.formats = WM2200_FORMATS,
1911
+
},
1912
+
.ops = &wm2200_dai_ops,
1913
+
};
1914
+
1915
+
static struct snd_soc_codec_driver soc_codec_wm2200 = {
1916
+
.probe = wm2200_probe,
1917
+
1918
+
.idle_bias_off = true,
1919
+
.set_sysclk = wm2200_set_sysclk,
1920
+
.set_pll = wm2200_set_fll,
1921
+
1922
+
.controls = wm2200_snd_controls,
1923
+
.num_controls = ARRAY_SIZE(wm2200_snd_controls),
1924
+
.dapm_widgets = wm2200_dapm_widgets,
1925
+
.num_dapm_widgets = ARRAY_SIZE(wm2200_dapm_widgets),
1926
+
.dapm_routes = wm2200_dapm_routes,
1927
+
.num_dapm_routes = ARRAY_SIZE(wm2200_dapm_routes),
1928
+
};
1929
+
1930
+
static irqreturn_t wm2200_irq(int irq, void *data)
1931
+
{
1932
+
struct wm2200_priv *wm2200 = data;
1933
+
unsigned int val, mask;
1934
+
int ret;
1935
+
1936
+
ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, &val);
1937
+
if (ret != 0) {
1938
+
dev_err(wm2200->dev, "Failed to read IRQ status: %d\n", ret);
1939
+
return IRQ_NONE;
1940
+
}
1941
+
1942
+
ret = regmap_read(wm2200->regmap, WM2200_INTERRUPT_STATUS_2_MASK,
1943
+
&mask);
1944
+
if (ret != 0) {
1945
+
dev_warn(wm2200->dev, "Failed to read IRQ mask: %d\n", ret);
1946
+
mask = 0;
1947
+
}
1948
+
1949
+
val &= ~mask;
1950
+
1951
+
if (val & WM2200_FLL_LOCK_EINT) {
1952
+
dev_dbg(wm2200->dev, "FLL locked\n");
1953
+
complete(&wm2200->fll_lock);
1954
+
}
1955
+
1956
+
if (val) {
1957
+
regmap_write(wm2200->regmap, WM2200_INTERRUPT_STATUS_2, val);
1958
+
1959
+
return IRQ_HANDLED;
1960
+
} else {
1961
+
return IRQ_NONE;
1962
+
}
1963
+
}
1964
+
1965
+
static const struct regmap_config wm2200_regmap = {
1966
+
.reg_bits = 16,
1967
+
.val_bits = 16,
1968
+
1969
+
.max_register = WM2200_MAX_REGISTER,
1970
+
.reg_defaults = wm2200_reg_defaults,
1971
+
.num_reg_defaults = ARRAY_SIZE(wm2200_reg_defaults),
1972
+
.volatile_reg = wm2200_volatile_register,
1973
+
.readable_reg = wm2200_readable_register,
1974
+
.cache_type = REGCACHE_RBTREE,
1975
+
};
1976
+
1977
+
static const unsigned int wm2200_dig_vu[] = {
1978
+
WM2200_DAC_DIGITAL_VOLUME_1L,
1979
+
WM2200_DAC_DIGITAL_VOLUME_1R,
1980
+
WM2200_DAC_DIGITAL_VOLUME_2L,
1981
+
WM2200_DAC_DIGITAL_VOLUME_2R,
1982
+
WM2200_ADC_DIGITAL_VOLUME_1L,
1983
+
WM2200_ADC_DIGITAL_VOLUME_1R,
1984
+
WM2200_ADC_DIGITAL_VOLUME_2L,
1985
+
WM2200_ADC_DIGITAL_VOLUME_2R,
1986
+
WM2200_ADC_DIGITAL_VOLUME_3L,
1987
+
WM2200_ADC_DIGITAL_VOLUME_3R,
1988
+
};
1989
+
1990
+
static const unsigned int wm2200_mic_ctrl_reg[] = {
1991
+
WM2200_IN1L_CONTROL,
1992
+
WM2200_IN2L_CONTROL,
1993
+
WM2200_IN3L_CONTROL,
1994
+
};
1995
+
1996
+
static __devinit int wm2200_i2c_probe(struct i2c_client *i2c,
1997
+
const struct i2c_device_id *id)
1998
+
{
1999
+
struct wm2200_pdata *pdata = dev_get_platdata(&i2c->dev);
2000
+
struct wm2200_priv *wm2200;
2001
+
unsigned int reg;
2002
+
int ret, i;
2003
+
2004
+
wm2200 = devm_kzalloc(&i2c->dev, sizeof(struct wm2200_priv),
2005
+
GFP_KERNEL);
2006
+
if (wm2200 == NULL)
2007
+
return -ENOMEM;
2008
+
2009
+
wm2200->dev = &i2c->dev;
2010
+
init_completion(&wm2200->fll_lock);
2011
+
2012
+
wm2200->regmap = regmap_init_i2c(i2c, &wm2200_regmap);
2013
+
if (IS_ERR(wm2200->regmap)) {
2014
+
ret = PTR_ERR(wm2200->regmap);
2015
+
dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2016
+
ret);
2017
+
goto err;
2018
+
}
2019
+
2020
+
if (pdata)
2021
+
wm2200->pdata = *pdata;
2022
+
2023
+
i2c_set_clientdata(i2c, wm2200);
2024
+
2025
+
for (i = 0; i < ARRAY_SIZE(wm2200->core_supplies); i++)
2026
+
wm2200->core_supplies[i].supply = wm2200_core_supply_names[i];
2027
+
2028
+
ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm2200->core_supplies),
2029
+
wm2200->core_supplies);
2030
+
if (ret != 0) {
2031
+
dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2032
+
ret);
2033
+
goto err_regmap;
2034
+
}
2035
+
2036
+
ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies),
2037
+
wm2200->core_supplies);
2038
+
if (ret != 0) {
2039
+
dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2040
+
ret);
2041
+
goto err_core;
2042
+
}
2043
+
2044
+
if (wm2200->pdata.ldo_ena) {
2045
+
ret = gpio_request_one(wm2200->pdata.ldo_ena,
2046
+
GPIOF_OUT_INIT_HIGH, "WM2200 LDOENA");
2047
+
if (ret < 0) {
2048
+
dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2049
+
wm2200->pdata.ldo_ena, ret);
2050
+
goto err_enable;
2051
+
}
2052
+
msleep(2);
2053
+
}
2054
+
2055
+
if (wm2200->pdata.reset) {
2056
+
ret = gpio_request_one(wm2200->pdata.reset,
2057
+
GPIOF_OUT_INIT_HIGH, "WM2200 /RESET");
2058
+
if (ret < 0) {
2059
+
dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2060
+
wm2200->pdata.reset, ret);
2061
+
goto err_ldo;
2062
+
}
2063
+
}
2064
+
2065
+
ret = regmap_read(wm2200->regmap, WM2200_SOFTWARE_RESET, ®);
2066
+
if (ret < 0) {
2067
+
dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2068
+
goto err_reset;
2069
+
}
2070
+
switch (reg) {
2071
+
case 0x2200:
2072
+
break;
2073
+
2074
+
default:
2075
+
dev_err(&i2c->dev, "Device is not a WM2200, ID is %x\n", reg);
2076
+
ret = -EINVAL;
2077
+
goto err_reset;
2078
+
}
2079
+
2080
+
ret = regmap_read(wm2200->regmap, WM2200_DEVICE_REVISION, ®);
2081
+
if (ret < 0) {
2082
+
dev_err(&i2c->dev, "Failed to read revision register\n");
2083
+
goto err_reset;
2084
+
}
2085
+
2086
+
wm2200->rev = ret & WM2200_DEVICE_REVISION_MASK;
2087
+
2088
+
dev_info(&i2c->dev, "revision %c\n", wm2200->rev + 'A');
2089
+
2090
+
switch (wm2200->rev) {
2091
+
case 0:
2092
+
ret = regmap_register_patch(wm2200->regmap, wm2200_reva_patch,
2093
+
ARRAY_SIZE(wm2200_reva_patch));
2094
+
if (ret != 0) {
2095
+
dev_err(&i2c->dev, "Failed to register patch: %d\n",
2096
+
ret);
2097
+
}
2098
+
break;
2099
+
default:
2100
+
break;
2101
+
}
2102
+
2103
+
ret = wm2200_reset(wm2200);
2104
+
if (ret < 0) {
2105
+
dev_err(&i2c->dev, "Failed to issue reset\n");
2106
+
goto err_reset;
2107
+
}
2108
+
2109
+
for (i = 0; i < ARRAY_SIZE(wm2200->pdata.gpio_defaults); i++) {
2110
+
if (!wm2200->pdata.gpio_defaults[i])
2111
+
continue;
2112
+
2113
+
regmap_write(wm2200->regmap, WM2200_GPIO_CTRL_1 + i,
2114
+
wm2200->pdata.gpio_defaults[i]);
2115
+
}
2116
+
2117
+
for (i = 0; i < ARRAY_SIZE(wm2200_dig_vu); i++)
2118
+
regmap_update_bits(wm2200->regmap, wm2200_dig_vu[i],
2119
+
WM2200_OUT_VU, WM2200_OUT_VU);
2120
+
2121
+
/* Assign slots 1-6 to channels 1-6 for both TX and RX */
2122
+
for (i = 0; i < 6; i++) {
2123
+
regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_10 + i, i);
2124
+
regmap_write(wm2200->regmap, WM2200_AUDIO_IF_1_16 + i, i);
2125
+
}
2126
+
2127
+
for (i = 0; i < ARRAY_SIZE(wm2200->pdata.in_mode); i++) {
2128
+
regmap_update_bits(wm2200->regmap, wm2200_mic_ctrl_reg[i],
2129
+
WM2200_IN1_MODE_MASK |
2130
+
WM2200_IN1_DMIC_SUP_MASK,
2131
+
(wm2200->pdata.in_mode[i] <<
2132
+
WM2200_IN1_MODE_SHIFT) |
2133
+
(wm2200->pdata.dmic_sup[i] <<
2134
+
WM2200_IN1_DMIC_SUP_SHIFT));
2135
+
}
2136
+
2137
+
if (i2c->irq) {
2138
+
ret = request_threaded_irq(i2c->irq, NULL, wm2200_irq,
2139
+
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2140
+
"wm2200", wm2200);
2141
+
if (ret == 0)
2142
+
regmap_update_bits(wm2200->regmap,
2143
+
WM2200_INTERRUPT_STATUS_2_MASK,
2144
+
WM2200_FLL_LOCK_EINT, 0);
2145
+
else
2146
+
dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2147
+
i2c->irq, ret);
2148
+
}
2149
+
2150
+
pm_runtime_set_active(&i2c->dev);
2151
+
pm_runtime_enable(&i2c->dev);
2152
+
pm_request_idle(&i2c->dev);
2153
+
2154
+
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_wm2200,
2155
+
&wm2200_dai, 1);
2156
+
if (ret != 0) {
2157
+
dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
2158
+
goto err_pm_runtime;
2159
+
}
2160
+
2161
+
return 0;
2162
+
2163
+
err_pm_runtime:
2164
+
pm_runtime_disable(&i2c->dev);
2165
+
err_reset:
2166
+
if (wm2200->pdata.reset) {
2167
+
gpio_set_value_cansleep(wm2200->pdata.reset, 0);
2168
+
gpio_free(wm2200->pdata.reset);
2169
+
}
2170
+
err_ldo:
2171
+
if (wm2200->pdata.ldo_ena) {
2172
+
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
2173
+
gpio_free(wm2200->pdata.ldo_ena);
2174
+
}
2175
+
err_enable:
2176
+
regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
2177
+
wm2200->core_supplies);
2178
+
err_core:
2179
+
regulator_bulk_free(ARRAY_SIZE(wm2200->core_supplies),
2180
+
wm2200->core_supplies);
2181
+
err_regmap:
2182
+
regmap_exit(wm2200->regmap);
2183
+
err:
2184
+
return ret;
2185
+
}
2186
+
2187
+
static __devexit int wm2200_i2c_remove(struct i2c_client *i2c)
2188
+
{
2189
+
struct wm2200_priv *wm2200 = i2c_get_clientdata(i2c);
2190
+
2191
+
snd_soc_unregister_codec(&i2c->dev);
2192
+
if (i2c->irq)
2193
+
free_irq(i2c->irq, wm2200);
2194
+
if (wm2200->pdata.reset) {
2195
+
gpio_set_value_cansleep(wm2200->pdata.reset, 0);
2196
+
gpio_free(wm2200->pdata.reset);
2197
+
}
2198
+
if (wm2200->pdata.ldo_ena) {
2199
+
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
2200
+
gpio_free(wm2200->pdata.ldo_ena);
2201
+
}
2202
+
regulator_bulk_free(ARRAY_SIZE(wm2200->core_supplies),
2203
+
wm2200->core_supplies);
2204
+
regmap_exit(wm2200->regmap);
2205
+
2206
+
return 0;
2207
+
}
2208
+
2209
+
#ifdef CONFIG_PM_RUNTIME
2210
+
static int wm2200_runtime_suspend(struct device *dev)
2211
+
{
2212
+
struct wm2200_priv *wm2200 = dev_get_drvdata(dev);
2213
+
2214
+
regcache_cache_only(wm2200->regmap, true);
2215
+
regcache_mark_dirty(wm2200->regmap);
2216
+
if (wm2200->pdata.ldo_ena)
2217
+
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 0);
2218
+
regulator_bulk_disable(ARRAY_SIZE(wm2200->core_supplies),
2219
+
wm2200->core_supplies);
2220
+
2221
+
return 0;
2222
+
}
2223
+
2224
+
static int wm2200_runtime_resume(struct device *dev)
2225
+
{
2226
+
struct wm2200_priv *wm2200 = dev_get_drvdata(dev);
2227
+
int ret;
2228
+
2229
+
ret = regulator_bulk_enable(ARRAY_SIZE(wm2200->core_supplies),
2230
+
wm2200->core_supplies);
2231
+
if (ret != 0) {
2232
+
dev_err(dev, "Failed to enable supplies: %d\n",
2233
+
ret);
2234
+
return ret;
2235
+
}
2236
+
2237
+
if (wm2200->pdata.ldo_ena) {
2238
+
gpio_set_value_cansleep(wm2200->pdata.ldo_ena, 1);
2239
+
msleep(2);
2240
+
}
2241
+
2242
+
regcache_cache_only(wm2200->regmap, false);
2243
+
regcache_sync(wm2200->regmap);
2244
+
2245
+
return 0;
2246
+
}
2247
+
#endif
2248
+
2249
+
static struct dev_pm_ops wm2200_pm = {
2250
+
SET_RUNTIME_PM_OPS(wm2200_runtime_suspend, wm2200_runtime_resume,
2251
+
NULL)
2252
+
};
2253
+
2254
+
static const struct i2c_device_id wm2200_i2c_id[] = {
2255
+
{ "wm2200", 0 },
2256
+
{ }
2257
+
};
2258
+
MODULE_DEVICE_TABLE(i2c, wm2200_i2c_id);
2259
+
2260
+
static struct i2c_driver wm2200_i2c_driver = {
2261
+
.driver = {
2262
+
.name = "wm2200",
2263
+
.owner = THIS_MODULE,
2264
+
.pm = &wm2200_pm,
2265
+
},
2266
+
.probe = wm2200_i2c_probe,
2267
+
.remove = __devexit_p(wm2200_i2c_remove),
2268
+
.id_table = wm2200_i2c_id,
2269
+
};
2270
+
2271
+
static int __init wm2200_modinit(void)
2272
+
{
2273
+
return i2c_add_driver(&wm2200_i2c_driver);
2274
+
}
2275
+
module_init(wm2200_modinit);
2276
+
2277
+
static void __exit wm2200_exit(void)
2278
+
{
2279
+
i2c_del_driver(&wm2200_i2c_driver);
2280
+
}
2281
+
module_exit(wm2200_exit);
2282
+
2283
+
MODULE_DESCRIPTION("ASoC WM2200 driver");
2284
+
MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2285
+
MODULE_LICENSE("GPL");
+3674
sound/soc/codecs/wm2200.h
+3674
sound/soc/codecs/wm2200.h
···
1
+
/*
2
+
* wm2200.h - WM2200 audio codec interface
3
+
*
4
+
* Copyright 2012 Wolfson Microelectronics PLC.
5
+
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6
+
*
7
+
* This program is free software; you can redistribute it and/or modify it
8
+
* under the terms of the GNU General Public License as published by the
9
+
* Free Software Foundation; either version 2 of the License, or (at your
10
+
* option) any later version.
11
+
*/
12
+
13
+
#ifndef _WM2200_H
14
+
#define _WM2200_H
15
+
16
+
#define WM2200_CLK_SYSCLK 1
17
+
18
+
#define WM2200_CLKSRC_MCLK1 0
19
+
#define WM2200_CLKSRC_MCLK2 1
20
+
#define WM2200_CLKSRC_FLL 4
21
+
#define WM2200_CLKSRC_BCLK1 8
22
+
23
+
#define WM2200_FLL_SRC_MCLK1 0
24
+
#define WM2200_FLL_SRC_MCLK2 1
25
+
#define WM2200_FLL_SRC_BCLK 2
26
+
27
+
/*
28
+
* Register values.
29
+
*/
30
+
#define WM2200_SOFTWARE_RESET 0x00
31
+
#define WM2200_DEVICE_REVISION 0x01
32
+
#define WM2200_TONE_GENERATOR_1 0x0B
33
+
#define WM2200_CLOCKING_3 0x102
34
+
#define WM2200_CLOCKING_4 0x103
35
+
#define WM2200_FLL_CONTROL_1 0x111
36
+
#define WM2200_FLL_CONTROL_2 0x112
37
+
#define WM2200_FLL_CONTROL_3 0x113
38
+
#define WM2200_FLL_CONTROL_4 0x114
39
+
#define WM2200_FLL_CONTROL_6 0x116
40
+
#define WM2200_FLL_CONTROL_7 0x117
41
+
#define WM2200_FLL_EFS_1 0x119
42
+
#define WM2200_FLL_EFS_2 0x11A
43
+
#define WM2200_MIC_CHARGE_PUMP_1 0x200
44
+
#define WM2200_MIC_CHARGE_PUMP_2 0x201
45
+
#define WM2200_DM_CHARGE_PUMP_1 0x202
46
+
#define WM2200_MIC_BIAS_CTRL_1 0x20C
47
+
#define WM2200_MIC_BIAS_CTRL_2 0x20D
48
+
#define WM2200_EAR_PIECE_CTRL_1 0x20F
49
+
#define WM2200_EAR_PIECE_CTRL_2 0x210
50
+
#define WM2200_INPUT_ENABLES 0x301
51
+
#define WM2200_IN1L_CONTROL 0x302
52
+
#define WM2200_IN1R_CONTROL 0x303
53
+
#define WM2200_IN2L_CONTROL 0x304
54
+
#define WM2200_IN2R_CONTROL 0x305
55
+
#define WM2200_IN3L_CONTROL 0x306
56
+
#define WM2200_IN3R_CONTROL 0x307
57
+
#define WM2200_RXANC_SRC 0x30A
58
+
#define WM2200_INPUT_VOLUME_RAMP 0x30B
59
+
#define WM2200_ADC_DIGITAL_VOLUME_1L 0x30C
60
+
#define WM2200_ADC_DIGITAL_VOLUME_1R 0x30D
61
+
#define WM2200_ADC_DIGITAL_VOLUME_2L 0x30E
62
+
#define WM2200_ADC_DIGITAL_VOLUME_2R 0x30F
63
+
#define WM2200_ADC_DIGITAL_VOLUME_3L 0x310
64
+
#define WM2200_ADC_DIGITAL_VOLUME_3R 0x311
65
+
#define WM2200_OUTPUT_ENABLES 0x400
66
+
#define WM2200_DAC_VOLUME_LIMIT_1L 0x401
67
+
#define WM2200_DAC_VOLUME_LIMIT_1R 0x402
68
+
#define WM2200_DAC_VOLUME_LIMIT_2L 0x403
69
+
#define WM2200_DAC_VOLUME_LIMIT_2R 0x404
70
+
#define WM2200_DAC_AEC_CONTROL_1 0x409
71
+
#define WM2200_OUTPUT_VOLUME_RAMP 0x40A
72
+
#define WM2200_DAC_DIGITAL_VOLUME_1L 0x40B
73
+
#define WM2200_DAC_DIGITAL_VOLUME_1R 0x40C
74
+
#define WM2200_DAC_DIGITAL_VOLUME_2L 0x40D
75
+
#define WM2200_DAC_DIGITAL_VOLUME_2R 0x40E
76
+
#define WM2200_PDM_1 0x417
77
+
#define WM2200_PDM_2 0x418
78
+
#define WM2200_AUDIO_IF_1_1 0x500
79
+
#define WM2200_AUDIO_IF_1_2 0x501
80
+
#define WM2200_AUDIO_IF_1_3 0x502
81
+
#define WM2200_AUDIO_IF_1_4 0x503
82
+
#define WM2200_AUDIO_IF_1_5 0x504
83
+
#define WM2200_AUDIO_IF_1_6 0x505
84
+
#define WM2200_AUDIO_IF_1_7 0x506
85
+
#define WM2200_AUDIO_IF_1_8 0x507
86
+
#define WM2200_AUDIO_IF_1_9 0x508
87
+
#define WM2200_AUDIO_IF_1_10 0x509
88
+
#define WM2200_AUDIO_IF_1_11 0x50A
89
+
#define WM2200_AUDIO_IF_1_12 0x50B
90
+
#define WM2200_AUDIO_IF_1_13 0x50C
91
+
#define WM2200_AUDIO_IF_1_14 0x50D
92
+
#define WM2200_AUDIO_IF_1_15 0x50E
93
+
#define WM2200_AUDIO_IF_1_16 0x50F
94
+
#define WM2200_AUDIO_IF_1_17 0x510
95
+
#define WM2200_AUDIO_IF_1_18 0x511
96
+
#define WM2200_AUDIO_IF_1_19 0x512
97
+
#define WM2200_AUDIO_IF_1_20 0x513
98
+
#define WM2200_AUDIO_IF_1_21 0x514
99
+
#define WM2200_AUDIO_IF_1_22 0x515
100
+
#define WM2200_OUT1LMIX_INPUT_1_SOURCE 0x600
101
+
#define WM2200_OUT1LMIX_INPUT_1_VOLUME 0x601
102
+
#define WM2200_OUT1LMIX_INPUT_2_SOURCE 0x602
103
+
#define WM2200_OUT1LMIX_INPUT_2_VOLUME 0x603
104
+
#define WM2200_OUT1LMIX_INPUT_3_SOURCE 0x604
105
+
#define WM2200_OUT1LMIX_INPUT_3_VOLUME 0x605
106
+
#define WM2200_OUT1LMIX_INPUT_4_SOURCE 0x606
107
+
#define WM2200_OUT1LMIX_INPUT_4_VOLUME 0x607
108
+
#define WM2200_OUT1RMIX_INPUT_1_SOURCE 0x608
109
+
#define WM2200_OUT1RMIX_INPUT_1_VOLUME 0x609
110
+
#define WM2200_OUT1RMIX_INPUT_2_SOURCE 0x60A
111
+
#define WM2200_OUT1RMIX_INPUT_2_VOLUME 0x60B
112
+
#define WM2200_OUT1RMIX_INPUT_3_SOURCE 0x60C
113
+
#define WM2200_OUT1RMIX_INPUT_3_VOLUME 0x60D
114
+
#define WM2200_OUT1RMIX_INPUT_4_SOURCE 0x60E
115
+
#define WM2200_OUT1RMIX_INPUT_4_VOLUME 0x60F
116
+
#define WM2200_OUT2LMIX_INPUT_1_SOURCE 0x610
117
+
#define WM2200_OUT2LMIX_INPUT_1_VOLUME 0x611
118
+
#define WM2200_OUT2LMIX_INPUT_2_SOURCE 0x612
119
+
#define WM2200_OUT2LMIX_INPUT_2_VOLUME 0x613
120
+
#define WM2200_OUT2LMIX_INPUT_3_SOURCE 0x614
121
+
#define WM2200_OUT2LMIX_INPUT_3_VOLUME 0x615
122
+
#define WM2200_OUT2LMIX_INPUT_4_SOURCE 0x616
123
+
#define WM2200_OUT2LMIX_INPUT_4_VOLUME 0x617
124
+
#define WM2200_OUT2RMIX_INPUT_1_SOURCE 0x618
125
+
#define WM2200_OUT2RMIX_INPUT_1_VOLUME 0x619
126
+
#define WM2200_OUT2RMIX_INPUT_2_SOURCE 0x61A
127
+
#define WM2200_OUT2RMIX_INPUT_2_VOLUME 0x61B
128
+
#define WM2200_OUT2RMIX_INPUT_3_SOURCE 0x61C
129
+
#define WM2200_OUT2RMIX_INPUT_3_VOLUME 0x61D
130
+
#define WM2200_OUT2RMIX_INPUT_4_SOURCE 0x61E
131
+
#define WM2200_OUT2RMIX_INPUT_4_VOLUME 0x61F
132
+
#define WM2200_AIF1TX1MIX_INPUT_1_SOURCE 0x620
133
+
#define WM2200_AIF1TX1MIX_INPUT_1_VOLUME 0x621
134
+
#define WM2200_AIF1TX1MIX_INPUT_2_SOURCE 0x622
135
+
#define WM2200_AIF1TX1MIX_INPUT_2_VOLUME 0x623
136
+
#define WM2200_AIF1TX1MIX_INPUT_3_SOURCE 0x624
137
+
#define WM2200_AIF1TX1MIX_INPUT_3_VOLUME 0x625
138
+
#define WM2200_AIF1TX1MIX_INPUT_4_SOURCE 0x626
139
+
#define WM2200_AIF1TX1MIX_INPUT_4_VOLUME 0x627
140
+
#define WM2200_AIF1TX2MIX_INPUT_1_SOURCE 0x628
141
+
#define WM2200_AIF1TX2MIX_INPUT_1_VOLUME 0x629
142
+
#define WM2200_AIF1TX2MIX_INPUT_2_SOURCE 0x62A
143
+
#define WM2200_AIF1TX2MIX_INPUT_2_VOLUME 0x62B
144
+
#define WM2200_AIF1TX2MIX_INPUT_3_SOURCE 0x62C
145
+
#define WM2200_AIF1TX2MIX_INPUT_3_VOLUME 0x62D
146
+
#define WM2200_AIF1TX2MIX_INPUT_4_SOURCE 0x62E
147
+
#define WM2200_AIF1TX2MIX_INPUT_4_VOLUME 0x62F
148
+
#define WM2200_AIF1TX3MIX_INPUT_1_SOURCE 0x630
149
+
#define WM2200_AIF1TX3MIX_INPUT_1_VOLUME 0x631
150
+
#define WM2200_AIF1TX3MIX_INPUT_2_SOURCE 0x632
151
+
#define WM2200_AIF1TX3MIX_INPUT_2_VOLUME 0x633
152
+
#define WM2200_AIF1TX3MIX_INPUT_3_SOURCE 0x634
153
+
#define WM2200_AIF1TX3MIX_INPUT_3_VOLUME 0x635
154
+
#define WM2200_AIF1TX3MIX_INPUT_4_SOURCE 0x636
155
+
#define WM2200_AIF1TX3MIX_INPUT_4_VOLUME 0x637
156
+
#define WM2200_AIF1TX4MIX_INPUT_1_SOURCE 0x638
157
+
#define WM2200_AIF1TX4MIX_INPUT_1_VOLUME 0x639
158
+
#define WM2200_AIF1TX4MIX_INPUT_2_SOURCE 0x63A
159
+
#define WM2200_AIF1TX4MIX_INPUT_2_VOLUME 0x63B
160
+
#define WM2200_AIF1TX4MIX_INPUT_3_SOURCE 0x63C
161
+
#define WM2200_AIF1TX4MIX_INPUT_3_VOLUME 0x63D
162
+
#define WM2200_AIF1TX4MIX_INPUT_4_SOURCE 0x63E
163
+
#define WM2200_AIF1TX4MIX_INPUT_4_VOLUME 0x63F
164
+
#define WM2200_AIF1TX5MIX_INPUT_1_SOURCE 0x640
165
+
#define WM2200_AIF1TX5MIX_INPUT_1_VOLUME 0x641
166
+
#define WM2200_AIF1TX5MIX_INPUT_2_SOURCE 0x642
167
+
#define WM2200_AIF1TX5MIX_INPUT_2_VOLUME 0x643
168
+
#define WM2200_AIF1TX5MIX_INPUT_3_SOURCE 0x644
169
+
#define WM2200_AIF1TX5MIX_INPUT_3_VOLUME 0x645
170
+
#define WM2200_AIF1TX5MIX_INPUT_4_SOURCE 0x646
171
+
#define WM2200_AIF1TX5MIX_INPUT_4_VOLUME 0x647
172
+
#define WM2200_AIF1TX6MIX_INPUT_1_SOURCE 0x648
173
+
#define WM2200_AIF1TX6MIX_INPUT_1_VOLUME 0x649
174
+
#define WM2200_AIF1TX6MIX_INPUT_2_SOURCE 0x64A
175
+
#define WM2200_AIF1TX6MIX_INPUT_2_VOLUME 0x64B
176
+
#define WM2200_AIF1TX6MIX_INPUT_3_SOURCE 0x64C
177
+
#define WM2200_AIF1TX6MIX_INPUT_3_VOLUME 0x64D
178
+
#define WM2200_AIF1TX6MIX_INPUT_4_SOURCE 0x64E
179
+
#define WM2200_AIF1TX6MIX_INPUT_4_VOLUME 0x64F
180
+
#define WM2200_EQLMIX_INPUT_1_SOURCE 0x650
181
+
#define WM2200_EQLMIX_INPUT_1_VOLUME 0x651
182
+
#define WM2200_EQLMIX_INPUT_2_SOURCE 0x652
183
+
#define WM2200_EQLMIX_INPUT_2_VOLUME 0x653
184
+
#define WM2200_EQLMIX_INPUT_3_SOURCE 0x654
185
+
#define WM2200_EQLMIX_INPUT_3_VOLUME 0x655
186
+
#define WM2200_EQLMIX_INPUT_4_SOURCE 0x656
187
+
#define WM2200_EQLMIX_INPUT_4_VOLUME 0x657
188
+
#define WM2200_EQRMIX_INPUT_1_SOURCE 0x658
189
+
#define WM2200_EQRMIX_INPUT_1_VOLUME 0x659
190
+
#define WM2200_EQRMIX_INPUT_2_SOURCE 0x65A
191
+
#define WM2200_EQRMIX_INPUT_2_VOLUME 0x65B
192
+
#define WM2200_EQRMIX_INPUT_3_SOURCE 0x65C
193
+
#define WM2200_EQRMIX_INPUT_3_VOLUME 0x65D
194
+
#define WM2200_EQRMIX_INPUT_4_SOURCE 0x65E
195
+
#define WM2200_EQRMIX_INPUT_4_VOLUME 0x65F
196
+
#define WM2200_LHPF1MIX_INPUT_1_SOURCE 0x660
197
+
#define WM2200_LHPF1MIX_INPUT_1_VOLUME 0x661
198
+
#define WM2200_LHPF1MIX_INPUT_2_SOURCE 0x662
199
+
#define WM2200_LHPF1MIX_INPUT_2_VOLUME 0x663
200
+
#define WM2200_LHPF1MIX_INPUT_3_SOURCE 0x664
201
+
#define WM2200_LHPF1MIX_INPUT_3_VOLUME 0x665
202
+
#define WM2200_LHPF1MIX_INPUT_4_SOURCE 0x666
203
+
#define WM2200_LHPF1MIX_INPUT_4_VOLUME 0x667
204
+
#define WM2200_LHPF2MIX_INPUT_1_SOURCE 0x668
205
+
#define WM2200_LHPF2MIX_INPUT_1_VOLUME 0x669
206
+
#define WM2200_LHPF2MIX_INPUT_2_SOURCE 0x66A
207
+
#define WM2200_LHPF2MIX_INPUT_2_VOLUME 0x66B
208
+
#define WM2200_LHPF2MIX_INPUT_3_SOURCE 0x66C
209
+
#define WM2200_LHPF2MIX_INPUT_3_VOLUME 0x66D
210
+
#define WM2200_LHPF2MIX_INPUT_4_SOURCE 0x66E
211
+
#define WM2200_LHPF2MIX_INPUT_4_VOLUME 0x66F
212
+
#define WM2200_DSP1LMIX_INPUT_1_SOURCE 0x670
213
+
#define WM2200_DSP1LMIX_INPUT_1_VOLUME 0x671
214
+
#define WM2200_DSP1LMIX_INPUT_2_SOURCE 0x672
215
+
#define WM2200_DSP1LMIX_INPUT_2_VOLUME 0x673
216
+
#define WM2200_DSP1LMIX_INPUT_3_SOURCE 0x674
217
+
#define WM2200_DSP1LMIX_INPUT_3_VOLUME 0x675
218
+
#define WM2200_DSP1LMIX_INPUT_4_SOURCE 0x676
219
+
#define WM2200_DSP1LMIX_INPUT_4_VOLUME 0x677
220
+
#define WM2200_DSP1RMIX_INPUT_1_SOURCE 0x678
221
+
#define WM2200_DSP1RMIX_INPUT_1_VOLUME 0x679
222
+
#define WM2200_DSP1RMIX_INPUT_2_SOURCE 0x67A
223
+
#define WM2200_DSP1RMIX_INPUT_2_VOLUME 0x67B
224
+
#define WM2200_DSP1RMIX_INPUT_3_SOURCE 0x67C
225
+
#define WM2200_DSP1RMIX_INPUT_3_VOLUME 0x67D
226
+
#define WM2200_DSP1RMIX_INPUT_4_SOURCE 0x67E
227
+
#define WM2200_DSP1RMIX_INPUT_4_VOLUME 0x67F
228
+
#define WM2200_DSP1AUX1MIX_INPUT_1_SOURCE 0x680
229
+
#define WM2200_DSP1AUX2MIX_INPUT_1_SOURCE 0x681
230
+
#define WM2200_DSP1AUX3MIX_INPUT_1_SOURCE 0x682
231
+
#define WM2200_DSP1AUX4MIX_INPUT_1_SOURCE 0x683
232
+
#define WM2200_DSP1AUX5MIX_INPUT_1_SOURCE 0x684
233
+
#define WM2200_DSP1AUX6MIX_INPUT_1_SOURCE 0x685
234
+
#define WM2200_DSP2LMIX_INPUT_1_SOURCE 0x686
235
+
#define WM2200_DSP2LMIX_INPUT_1_VOLUME 0x687
236
+
#define WM2200_DSP2LMIX_INPUT_2_SOURCE 0x688
237
+
#define WM2200_DSP2LMIX_INPUT_2_VOLUME 0x689
238
+
#define WM2200_DSP2LMIX_INPUT_3_SOURCE 0x68A
239
+
#define WM2200_DSP2LMIX_INPUT_3_VOLUME 0x68B
240
+
#define WM2200_DSP2LMIX_INPUT_4_SOURCE 0x68C
241
+
#define WM2200_DSP2LMIX_INPUT_4_VOLUME 0x68D
242
+
#define WM2200_DSP2RMIX_INPUT_1_SOURCE 0x68E
243
+
#define WM2200_DSP2RMIX_INPUT_1_VOLUME 0x68F
244
+
#define WM2200_DSP2RMIX_INPUT_2_SOURCE 0x690
245
+
#define WM2200_DSP2RMIX_INPUT_2_VOLUME 0x691
246
+
#define WM2200_DSP2RMIX_INPUT_3_SOURCE 0x692
247
+
#define WM2200_DSP2RMIX_INPUT_3_VOLUME 0x693
248
+
#define WM2200_DSP2RMIX_INPUT_4_SOURCE 0x694
249
+
#define WM2200_DSP2RMIX_INPUT_4_VOLUME 0x695
250
+
#define WM2200_DSP2AUX1MIX_INPUT_1_SOURCE 0x696
251
+
#define WM2200_DSP2AUX2MIX_INPUT_1_SOURCE 0x697
252
+
#define WM2200_DSP2AUX3MIX_INPUT_1_SOURCE 0x698
253
+
#define WM2200_DSP2AUX4MIX_INPUT_1_SOURCE 0x699
254
+
#define WM2200_DSP2AUX5MIX_INPUT_1_SOURCE 0x69A
255
+
#define WM2200_DSP2AUX6MIX_INPUT_1_SOURCE 0x69B
256
+
#define WM2200_GPIO_CTRL_1 0x700
257
+
#define WM2200_GPIO_CTRL_2 0x701
258
+
#define WM2200_GPIO_CTRL_3 0x702
259
+
#define WM2200_GPIO_CTRL_4 0x703
260
+
#define WM2200_ADPS1_IRQ0 0x707
261
+
#define WM2200_ADPS1_IRQ1 0x708
262
+
#define WM2200_MISC_PAD_CTRL_1 0x709
263
+
#define WM2200_INTERRUPT_STATUS_1 0x800
264
+
#define WM2200_INTERRUPT_STATUS_1_MASK 0x801
265
+
#define WM2200_INTERRUPT_STATUS_2 0x802
266
+
#define WM2200_INTERRUPT_RAW_STATUS_2 0x803
267
+
#define WM2200_INTERRUPT_STATUS_2_MASK 0x804
268
+
#define WM2200_INTERRUPT_CONTROL 0x808
269
+
#define WM2200_EQL_1 0x900
270
+
#define WM2200_EQL_2 0x901
271
+
#define WM2200_EQL_3 0x902
272
+
#define WM2200_EQL_4 0x903
273
+
#define WM2200_EQL_5 0x904
274
+
#define WM2200_EQL_6 0x905
275
+
#define WM2200_EQL_7 0x906
276
+
#define WM2200_EQL_8 0x907
277
+
#define WM2200_EQL_9 0x908
278
+
#define WM2200_EQL_10 0x909
279
+
#define WM2200_EQL_11 0x90A
280
+
#define WM2200_EQL_12 0x90B
281
+
#define WM2200_EQL_13 0x90C
282
+
#define WM2200_EQL_14 0x90D
283
+
#define WM2200_EQL_15 0x90E
284
+
#define WM2200_EQL_16 0x90F
285
+
#define WM2200_EQL_17 0x910
286
+
#define WM2200_EQL_18 0x911
287
+
#define WM2200_EQL_19 0x912
288
+
#define WM2200_EQL_20 0x913
289
+
#define WM2200_EQR_1 0x916
290
+
#define WM2200_EQR_2 0x917
291
+
#define WM2200_EQR_3 0x918
292
+
#define WM2200_EQR_4 0x919
293
+
#define WM2200_EQR_5 0x91A
294
+
#define WM2200_EQR_6 0x91B
295
+
#define WM2200_EQR_7 0x91C
296
+
#define WM2200_EQR_8 0x91D
297
+
#define WM2200_EQR_9 0x91E
298
+
#define WM2200_EQR_10 0x91F
299
+
#define WM2200_EQR_11 0x920
300
+
#define WM2200_EQR_12 0x921
301
+
#define WM2200_EQR_13 0x922
302
+
#define WM2200_EQR_14 0x923
303
+
#define WM2200_EQR_15 0x924
304
+
#define WM2200_EQR_16 0x925
305
+
#define WM2200_EQR_17 0x926
306
+
#define WM2200_EQR_18 0x927
307
+
#define WM2200_EQR_19 0x928
308
+
#define WM2200_EQR_20 0x929
309
+
#define WM2200_HPLPF1_1 0x93E
310
+
#define WM2200_HPLPF1_2 0x93F
311
+
#define WM2200_HPLPF2_1 0x942
312
+
#define WM2200_HPLPF2_2 0x943
313
+
#define WM2200_DSP1_CONTROL_1 0xA00
314
+
#define WM2200_DSP1_CONTROL_2 0xA02
315
+
#define WM2200_DSP1_CONTROL_3 0xA03
316
+
#define WM2200_DSP1_CONTROL_4 0xA04
317
+
#define WM2200_DSP1_CONTROL_5 0xA06
318
+
#define WM2200_DSP1_CONTROL_6 0xA07
319
+
#define WM2200_DSP1_CONTROL_7 0xA08
320
+
#define WM2200_DSP1_CONTROL_8 0xA09
321
+
#define WM2200_DSP1_CONTROL_9 0xA0A
322
+
#define WM2200_DSP1_CONTROL_10 0xA0B
323
+
#define WM2200_DSP1_CONTROL_11 0xA0C
324
+
#define WM2200_DSP1_CONTROL_12 0xA0D
325
+
#define WM2200_DSP1_CONTROL_13 0xA0F
326
+
#define WM2200_DSP1_CONTROL_14 0xA10
327
+
#define WM2200_DSP1_CONTROL_15 0xA11
328
+
#define WM2200_DSP1_CONTROL_16 0xA12
329
+
#define WM2200_DSP1_CONTROL_17 0xA13
330
+
#define WM2200_DSP1_CONTROL_18 0xA14
331
+
#define WM2200_DSP1_CONTROL_19 0xA16
332
+
#define WM2200_DSP1_CONTROL_20 0xA17
333
+
#define WM2200_DSP1_CONTROL_21 0xA18
334
+
#define WM2200_DSP1_CONTROL_22 0xA1A
335
+
#define WM2200_DSP1_CONTROL_23 0xA1B
336
+
#define WM2200_DSP1_CONTROL_24 0xA1C
337
+
#define WM2200_DSP1_CONTROL_25 0xA1E
338
+
#define WM2200_DSP1_CONTROL_26 0xA20
339
+
#define WM2200_DSP1_CONTROL_27 0xA21
340
+
#define WM2200_DSP1_CONTROL_28 0xA22
341
+
#define WM2200_DSP1_CONTROL_29 0xA23
342
+
#define WM2200_DSP1_CONTROL_30 0xA24
343
+
#define WM2200_DSP1_CONTROL_31 0xA26
344
+
#define WM2200_DSP2_CONTROL_1 0xB00
345
+
#define WM2200_DSP2_CONTROL_2 0xB02
346
+
#define WM2200_DSP2_CONTROL_3 0xB03
347
+
#define WM2200_DSP2_CONTROL_4 0xB04
348
+
#define WM2200_DSP2_CONTROL_5 0xB06
349
+
#define WM2200_DSP2_CONTROL_6 0xB07
350
+
#define WM2200_DSP2_CONTROL_7 0xB08
351
+
#define WM2200_DSP2_CONTROL_8 0xB09
352
+
#define WM2200_DSP2_CONTROL_9 0xB0A
353
+
#define WM2200_DSP2_CONTROL_10 0xB0B
354
+
#define WM2200_DSP2_CONTROL_11 0xB0C
355
+
#define WM2200_DSP2_CONTROL_12 0xB0D
356
+
#define WM2200_DSP2_CONTROL_13 0xB0F
357
+
#define WM2200_DSP2_CONTROL_14 0xB10
358
+
#define WM2200_DSP2_CONTROL_15 0xB11
359
+
#define WM2200_DSP2_CONTROL_16 0xB12
360
+
#define WM2200_DSP2_CONTROL_17 0xB13
361
+
#define WM2200_DSP2_CONTROL_18 0xB14
362
+
#define WM2200_DSP2_CONTROL_19 0xB16
363
+
#define WM2200_DSP2_CONTROL_20 0xB17
364
+
#define WM2200_DSP2_CONTROL_21 0xB18
365
+
#define WM2200_DSP2_CONTROL_22 0xB1A
366
+
#define WM2200_DSP2_CONTROL_23 0xB1B
367
+
#define WM2200_DSP2_CONTROL_24 0xB1C
368
+
#define WM2200_DSP2_CONTROL_25 0xB1E
369
+
#define WM2200_DSP2_CONTROL_26 0xB20
370
+
#define WM2200_DSP2_CONTROL_27 0xB21
371
+
#define WM2200_DSP2_CONTROL_28 0xB22
372
+
#define WM2200_DSP2_CONTROL_29 0xB23
373
+
#define WM2200_DSP2_CONTROL_30 0xB24
374
+
#define WM2200_DSP2_CONTROL_31 0xB26
375
+
#define WM2200_ANC_CTRL1 0xD00
376
+
#define WM2200_ANC_CTRL2 0xD01
377
+
#define WM2200_ANC_CTRL3 0xD02
378
+
#define WM2200_ANC_CTRL7 0xD08
379
+
#define WM2200_ANC_CTRL8 0xD09
380
+
#define WM2200_ANC_CTRL9 0xD0A
381
+
#define WM2200_ANC_CTRL10 0xD0B
382
+
#define WM2200_ANC_CTRL11 0xD0C
383
+
#define WM2200_ANC_CTRL12 0xD0D
384
+
#define WM2200_ANC_CTRL13 0xD0E
385
+
#define WM2200_ANC_CTRL14 0xD0F
386
+
#define WM2200_ANC_CTRL15 0xD10
387
+
#define WM2200_ANC_CTRL16 0xD11
388
+
#define WM2200_ANC_CTRL17 0xD12
389
+
#define WM2200_ANC_CTRL18 0xD15
390
+
#define WM2200_ANC_CTRL19 0xD16
391
+
#define WM2200_ANC_CTRL20 0xD17
392
+
#define WM2200_ANC_CTRL21 0xD18
393
+
#define WM2200_ANC_CTRL22 0xD19
394
+
#define WM2200_ANC_CTRL23 0xD1A
395
+
#define WM2200_ANC_CTRL24 0xD1B
396
+
#define WM2200_ANC_CTRL25 0xD1C
397
+
#define WM2200_ANC_CTRL26 0xD1D
398
+
#define WM2200_ANC_CTRL27 0xD1E
399
+
#define WM2200_ANC_CTRL28 0xD1F
400
+
#define WM2200_ANC_CTRL29 0xD20
401
+
#define WM2200_ANC_CTRL30 0xD21
402
+
#define WM2200_ANC_CTRL31 0xD23
403
+
#define WM2200_ANC_CTRL32 0xD24
404
+
#define WM2200_ANC_CTRL33 0xD25
405
+
#define WM2200_ANC_CTRL34 0xD27
406
+
#define WM2200_ANC_CTRL35 0xD28
407
+
#define WM2200_ANC_CTRL36 0xD29
408
+
#define WM2200_ANC_CTRL37 0xD2A
409
+
#define WM2200_ANC_CTRL38 0xD2B
410
+
#define WM2200_ANC_CTRL39 0xD2C
411
+
#define WM2200_ANC_CTRL40 0xD2D
412
+
#define WM2200_ANC_CTRL41 0xD2E
413
+
#define WM2200_ANC_CTRL42 0xD2F
414
+
#define WM2200_ANC_CTRL43 0xD30
415
+
#define WM2200_ANC_CTRL44 0xD31
416
+
#define WM2200_ANC_CTRL45 0xD32
417
+
#define WM2200_ANC_CTRL46 0xD33
418
+
#define WM2200_ANC_CTRL47 0xD34
419
+
#define WM2200_ANC_CTRL48 0xD35
420
+
#define WM2200_ANC_CTRL49 0xD36
421
+
#define WM2200_ANC_CTRL50 0xD37
422
+
#define WM2200_ANC_CTRL51 0xD38
423
+
#define WM2200_ANC_CTRL52 0xD39
424
+
#define WM2200_ANC_CTRL53 0xD3A
425
+
#define WM2200_ANC_CTRL54 0xD3B
426
+
#define WM2200_ANC_CTRL55 0xD3C
427
+
#define WM2200_ANC_CTRL56 0xD3D
428
+
#define WM2200_ANC_CTRL57 0xD3E
429
+
#define WM2200_ANC_CTRL58 0xD3F
430
+
#define WM2200_ANC_CTRL59 0xD40
431
+
#define WM2200_ANC_CTRL60 0xD41
432
+
#define WM2200_ANC_CTRL61 0xD42
433
+
#define WM2200_ANC_CTRL62 0xD43
434
+
#define WM2200_ANC_CTRL63 0xD44
435
+
#define WM2200_ANC_CTRL64 0xD45
436
+
#define WM2200_ANC_CTRL65 0xD46
437
+
#define WM2200_ANC_CTRL66 0xD47
438
+
#define WM2200_ANC_CTRL67 0xD48
439
+
#define WM2200_ANC_CTRL68 0xD49
440
+
#define WM2200_ANC_CTRL69 0xD4A
441
+
#define WM2200_ANC_CTRL70 0xD4B
442
+
#define WM2200_ANC_CTRL71 0xD4C
443
+
#define WM2200_ANC_CTRL72 0xD4D
444
+
#define WM2200_ANC_CTRL73 0xD4E
445
+
#define WM2200_ANC_CTRL74 0xD4F
446
+
#define WM2200_ANC_CTRL75 0xD50
447
+
#define WM2200_ANC_CTRL76 0xD51
448
+
#define WM2200_ANC_CTRL77 0xD52
449
+
#define WM2200_ANC_CTRL78 0xD53
450
+
#define WM2200_ANC_CTRL79 0xD54
451
+
#define WM2200_ANC_CTRL80 0xD55
452
+
#define WM2200_ANC_CTRL81 0xD56
453
+
#define WM2200_ANC_CTRL82 0xD57
454
+
#define WM2200_ANC_CTRL83 0xD58
455
+
#define WM2200_ANC_CTRL84 0xD5B
456
+
#define WM2200_ANC_CTRL85 0xD5C
457
+
#define WM2200_ANC_CTRL86 0xD5F
458
+
#define WM2200_ANC_CTRL87 0xD60
459
+
#define WM2200_ANC_CTRL88 0xD61
460
+
#define WM2200_ANC_CTRL89 0xD62
461
+
#define WM2200_ANC_CTRL90 0xD63
462
+
#define WM2200_ANC_CTRL91 0xD64
463
+
#define WM2200_ANC_CTRL92 0xD65
464
+
#define WM2200_ANC_CTRL93 0xD66
465
+
#define WM2200_ANC_CTRL94 0xD67
466
+
#define WM2200_ANC_CTRL95 0xD68
467
+
#define WM2200_ANC_CTRL96 0xD69
468
+
#define WM2200_DSP1_DM_0 0x3000
469
+
#define WM2200_DSP1_DM_1 0x3001
470
+
#define WM2200_DSP1_DM_2 0x3002
471
+
#define WM2200_DSP1_DM_3 0x3003
472
+
#define WM2200_DSP1_DM_2044 0x37FC
473
+
#define WM2200_DSP1_DM_2045 0x37FD
474
+
#define WM2200_DSP1_DM_2046 0x37FE
475
+
#define WM2200_DSP1_DM_2047 0x37FF
476
+
#define WM2200_DSP1_PM_0 0x3800
477
+
#define WM2200_DSP1_PM_1 0x3801
478
+
#define WM2200_DSP1_PM_2 0x3802
479
+
#define WM2200_DSP1_PM_3 0x3803
480
+
#define WM2200_DSP1_PM_4 0x3804
481
+
#define WM2200_DSP1_PM_5 0x3805
482
+
#define WM2200_DSP1_PM_762 0x3AFA
483
+
#define WM2200_DSP1_PM_763 0x3AFB
484
+
#define WM2200_DSP1_PM_764 0x3AFC
485
+
#define WM2200_DSP1_PM_765 0x3AFD
486
+
#define WM2200_DSP1_PM_766 0x3AFE
487
+
#define WM2200_DSP1_PM_767 0x3AFF
488
+
#define WM2200_DSP1_ZM_0 0x3C00
489
+
#define WM2200_DSP1_ZM_1 0x3C01
490
+
#define WM2200_DSP1_ZM_2 0x3C02
491
+
#define WM2200_DSP1_ZM_3 0x3C03
492
+
#define WM2200_DSP1_ZM_1020 0x3FFC
493
+
#define WM2200_DSP1_ZM_1021 0x3FFD
494
+
#define WM2200_DSP1_ZM_1022 0x3FFE
495
+
#define WM2200_DSP1_ZM_1023 0x3FFF
496
+
#define WM2200_DSP2_DM_0 0x4000
497
+
#define WM2200_DSP2_DM_1 0x4001
498
+
#define WM2200_DSP2_DM_2 0x4002
499
+
#define WM2200_DSP2_DM_3 0x4003
500
+
#define WM2200_DSP2_DM_2044 0x47FC
501
+
#define WM2200_DSP2_DM_2045 0x47FD
502
+
#define WM2200_DSP2_DM_2046 0x47FE
503
+
#define WM2200_DSP2_DM_2047 0x47FF
504
+
#define WM2200_DSP2_PM_0 0x4800
505
+
#define WM2200_DSP2_PM_1 0x4801
506
+
#define WM2200_DSP2_PM_2 0x4802
507
+
#define WM2200_DSP2_PM_3 0x4803
508
+
#define WM2200_DSP2_PM_4 0x4804
509
+
#define WM2200_DSP2_PM_5 0x4805
510
+
#define WM2200_DSP2_PM_762 0x4AFA
511
+
#define WM2200_DSP2_PM_763 0x4AFB
512
+
#define WM2200_DSP2_PM_764 0x4AFC
513
+
#define WM2200_DSP2_PM_765 0x4AFD
514
+
#define WM2200_DSP2_PM_766 0x4AFE
515
+
#define WM2200_DSP2_PM_767 0x4AFF
516
+
#define WM2200_DSP2_ZM_0 0x4C00
517
+
#define WM2200_DSP2_ZM_1 0x4C01
518
+
#define WM2200_DSP2_ZM_2 0x4C02
519
+
#define WM2200_DSP2_ZM_3 0x4C03
520
+
#define WM2200_DSP2_ZM_1020 0x4FFC
521
+
#define WM2200_DSP2_ZM_1021 0x4FFD
522
+
#define WM2200_DSP2_ZM_1022 0x4FFE
523
+
#define WM2200_DSP2_ZM_1023 0x4FFF
524
+
525
+
#define WM2200_REGISTER_COUNT 494
526
+
#define WM2200_MAX_REGISTER 0x4FFF
527
+
528
+
/*
529
+
* Field Definitions.
530
+
*/
531
+
532
+
/*
533
+
* R0 (0x00) - software reset
534
+
*/
535
+
#define WM2200_SW_RESET_CHIP_ID1_MASK 0xFFFF /* SW_RESET_CHIP_ID1 - [15:0] */
536
+
#define WM2200_SW_RESET_CHIP_ID1_SHIFT 0 /* SW_RESET_CHIP_ID1 - [15:0] */
537
+
#define WM2200_SW_RESET_CHIP_ID1_WIDTH 16 /* SW_RESET_CHIP_ID1 - [15:0] */
538
+
539
+
/*
540
+
* R1 (0x01) - Device Revision
541
+
*/
542
+
#define WM2200_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */
543
+
#define WM2200_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */
544
+
#define WM2200_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */
545
+
546
+
/*
547
+
* R11 (0x0B) - Tone Generator 1
548
+
*/
549
+
#define WM2200_TONE_ENA 0x0001 /* TONE_ENA */
550
+
#define WM2200_TONE_ENA_MASK 0x0001 /* TONE_ENA */
551
+
#define WM2200_TONE_ENA_SHIFT 0 /* TONE_ENA */
552
+
#define WM2200_TONE_ENA_WIDTH 1 /* TONE_ENA */
553
+
554
+
/*
555
+
* R258 (0x102) - Clocking 3
556
+
*/
557
+
#define WM2200_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
558
+
#define WM2200_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
559
+
#define WM2200_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
560
+
#define WM2200_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
561
+
#define WM2200_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
562
+
#define WM2200_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
563
+
#define WM2200_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
564
+
#define WM2200_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
565
+
#define WM2200_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
566
+
#define WM2200_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
567
+
568
+
/*
569
+
* R259 (0x103) - Clocking 4
570
+
*/
571
+
#define WM2200_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
572
+
#define WM2200_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
573
+
#define WM2200_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
574
+
575
+
/*
576
+
* R273 (0x111) - FLL Control 1
577
+
*/
578
+
#define WM2200_FLL_ENA 0x0001 /* FLL_ENA */
579
+
#define WM2200_FLL_ENA_MASK 0x0001 /* FLL_ENA */
580
+
#define WM2200_FLL_ENA_SHIFT 0 /* FLL_ENA */
581
+
#define WM2200_FLL_ENA_WIDTH 1 /* FLL_ENA */
582
+
583
+
/*
584
+
* R274 (0x112) - FLL Control 2
585
+
*/
586
+
#define WM2200_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
587
+
#define WM2200_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
588
+
#define WM2200_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
589
+
#define WM2200_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
590
+
#define WM2200_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
591
+
#define WM2200_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
592
+
593
+
/*
594
+
* R275 (0x113) - FLL Control 3
595
+
*/
596
+
#define WM2200_FLL_FRACN_ENA 0x0001 /* FLL_FRACN_ENA */
597
+
#define WM2200_FLL_FRACN_ENA_MASK 0x0001 /* FLL_FRACN_ENA */
598
+
#define WM2200_FLL_FRACN_ENA_SHIFT 0 /* FLL_FRACN_ENA */
599
+
#define WM2200_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */
600
+
601
+
/*
602
+
* R276 (0x114) - FLL Control 4
603
+
*/
604
+
#define WM2200_FLL_THETA_MASK 0xFFFF /* FLL_THETA - [15:0] */
605
+
#define WM2200_FLL_THETA_SHIFT 0 /* FLL_THETA - [15:0] */
606
+
#define WM2200_FLL_THETA_WIDTH 16 /* FLL_THETA - [15:0] */
607
+
608
+
/*
609
+
* R278 (0x116) - FLL Control 6
610
+
*/
611
+
#define WM2200_FLL_N_MASK 0x03FF /* FLL_N - [9:0] */
612
+
#define WM2200_FLL_N_SHIFT 0 /* FLL_N - [9:0] */
613
+
#define WM2200_FLL_N_WIDTH 10 /* FLL_N - [9:0] */
614
+
615
+
/*
616
+
* R279 (0x117) - FLL Control 7
617
+
*/
618
+
#define WM2200_FLL_CLK_REF_DIV_MASK 0x0030 /* FLL_CLK_REF_DIV - [5:4] */
619
+
#define WM2200_FLL_CLK_REF_DIV_SHIFT 4 /* FLL_CLK_REF_DIV - [5:4] */
620
+
#define WM2200_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [5:4] */
621
+
#define WM2200_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */
622
+
#define WM2200_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */
623
+
#define WM2200_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
624
+
625
+
/*
626
+
* R281 (0x119) - FLL EFS 1
627
+
*/
628
+
#define WM2200_FLL_LAMBDA_MASK 0xFFFF /* FLL_LAMBDA - [15:0] */
629
+
#define WM2200_FLL_LAMBDA_SHIFT 0 /* FLL_LAMBDA - [15:0] */
630
+
#define WM2200_FLL_LAMBDA_WIDTH 16 /* FLL_LAMBDA - [15:0] */
631
+
632
+
/*
633
+
* R282 (0x11A) - FLL EFS 2
634
+
*/
635
+
#define WM2200_FLL_EFS_ENA 0x0001 /* FLL_EFS_ENA */
636
+
#define WM2200_FLL_EFS_ENA_MASK 0x0001 /* FLL_EFS_ENA */
637
+
#define WM2200_FLL_EFS_ENA_SHIFT 0 /* FLL_EFS_ENA */
638
+
#define WM2200_FLL_EFS_ENA_WIDTH 1 /* FLL_EFS_ENA */
639
+
640
+
/*
641
+
* R512 (0x200) - Mic Charge Pump 1
642
+
*/
643
+
#define WM2200_CPMIC_BYPASS_MODE 0x0020 /* CPMIC_BYPASS_MODE */
644
+
#define WM2200_CPMIC_BYPASS_MODE_MASK 0x0020 /* CPMIC_BYPASS_MODE */
645
+
#define WM2200_CPMIC_BYPASS_MODE_SHIFT 5 /* CPMIC_BYPASS_MODE */
646
+
#define WM2200_CPMIC_BYPASS_MODE_WIDTH 1 /* CPMIC_BYPASS_MODE */
647
+
#define WM2200_CPMIC_ENA 0x0001 /* CPMIC_ENA */
648
+
#define WM2200_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
649
+
#define WM2200_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
650
+
#define WM2200_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */
651
+
652
+
/*
653
+
* R513 (0x201) - Mic Charge Pump 2
654
+
*/
655
+
#define WM2200_CPMIC_LDO_VSEL_OVERRIDE_MASK 0xF800 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
656
+
#define WM2200_CPMIC_LDO_VSEL_OVERRIDE_SHIFT 11 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
657
+
#define WM2200_CPMIC_LDO_VSEL_OVERRIDE_WIDTH 5 /* CPMIC_LDO_VSEL_OVERRIDE - [15:11] */
658
+
659
+
/*
660
+
* R514 (0x202) - DM Charge Pump 1
661
+
*/
662
+
#define WM2200_CPDM_ENA 0x0001 /* CPDM_ENA */
663
+
#define WM2200_CPDM_ENA_MASK 0x0001 /* CPDM_ENA */
664
+
#define WM2200_CPDM_ENA_SHIFT 0 /* CPDM_ENA */
665
+
#define WM2200_CPDM_ENA_WIDTH 1 /* CPDM_ENA */
666
+
667
+
/*
668
+
* R524 (0x20C) - Mic Bias Ctrl 1
669
+
*/
670
+
#define WM2200_MICB1_DISCH 0x0040 /* MICB1_DISCH */
671
+
#define WM2200_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */
672
+
#define WM2200_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */
673
+
#define WM2200_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
674
+
#define WM2200_MICB1_RATE 0x0020 /* MICB1_RATE */
675
+
#define WM2200_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
676
+
#define WM2200_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
677
+
#define WM2200_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
678
+
#define WM2200_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */
679
+
#define WM2200_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */
680
+
#define WM2200_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */
681
+
#define WM2200_MICB1_MODE 0x0002 /* MICB1_MODE */
682
+
#define WM2200_MICB1_MODE_MASK 0x0002 /* MICB1_MODE */
683
+
#define WM2200_MICB1_MODE_SHIFT 1 /* MICB1_MODE */
684
+
#define WM2200_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
685
+
#define WM2200_MICB1_ENA 0x0001 /* MICB1_ENA */
686
+
#define WM2200_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
687
+
#define WM2200_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
688
+
#define WM2200_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
689
+
690
+
/*
691
+
* R525 (0x20D) - Mic Bias Ctrl 2
692
+
*/
693
+
#define WM2200_MICB2_DISCH 0x0040 /* MICB2_DISCH */
694
+
#define WM2200_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */
695
+
#define WM2200_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */
696
+
#define WM2200_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
697
+
#define WM2200_MICB2_RATE 0x0020 /* MICB2_RATE */
698
+
#define WM2200_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
699
+
#define WM2200_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
700
+
#define WM2200_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
701
+
#define WM2200_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */
702
+
#define WM2200_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */
703
+
#define WM2200_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */
704
+
#define WM2200_MICB2_MODE 0x0002 /* MICB2_MODE */
705
+
#define WM2200_MICB2_MODE_MASK 0x0002 /* MICB2_MODE */
706
+
#define WM2200_MICB2_MODE_SHIFT 1 /* MICB2_MODE */
707
+
#define WM2200_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
708
+
#define WM2200_MICB2_ENA 0x0001 /* MICB2_ENA */
709
+
#define WM2200_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
710
+
#define WM2200_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
711
+
#define WM2200_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
712
+
713
+
/*
714
+
* R527 (0x20F) - Ear Piece Ctrl 1
715
+
*/
716
+
#define WM2200_EPD_LP_ENA 0x4000 /* EPD_LP_ENA */
717
+
#define WM2200_EPD_LP_ENA_MASK 0x4000 /* EPD_LP_ENA */
718
+
#define WM2200_EPD_LP_ENA_SHIFT 14 /* EPD_LP_ENA */
719
+
#define WM2200_EPD_LP_ENA_WIDTH 1 /* EPD_LP_ENA */
720
+
#define WM2200_EPD_OUTP_LP_ENA 0x2000 /* EPD_OUTP_LP_ENA */
721
+
#define WM2200_EPD_OUTP_LP_ENA_MASK 0x2000 /* EPD_OUTP_LP_ENA */
722
+
#define WM2200_EPD_OUTP_LP_ENA_SHIFT 13 /* EPD_OUTP_LP_ENA */
723
+
#define WM2200_EPD_OUTP_LP_ENA_WIDTH 1 /* EPD_OUTP_LP_ENA */
724
+
#define WM2200_EPD_RMV_SHRT_LP 0x1000 /* EPD_RMV_SHRT_LP */
725
+
#define WM2200_EPD_RMV_SHRT_LP_MASK 0x1000 /* EPD_RMV_SHRT_LP */
726
+
#define WM2200_EPD_RMV_SHRT_LP_SHIFT 12 /* EPD_RMV_SHRT_LP */
727
+
#define WM2200_EPD_RMV_SHRT_LP_WIDTH 1 /* EPD_RMV_SHRT_LP */
728
+
#define WM2200_EPD_LN_ENA 0x0800 /* EPD_LN_ENA */
729
+
#define WM2200_EPD_LN_ENA_MASK 0x0800 /* EPD_LN_ENA */
730
+
#define WM2200_EPD_LN_ENA_SHIFT 11 /* EPD_LN_ENA */
731
+
#define WM2200_EPD_LN_ENA_WIDTH 1 /* EPD_LN_ENA */
732
+
#define WM2200_EPD_OUTP_LN_ENA 0x0400 /* EPD_OUTP_LN_ENA */
733
+
#define WM2200_EPD_OUTP_LN_ENA_MASK 0x0400 /* EPD_OUTP_LN_ENA */
734
+
#define WM2200_EPD_OUTP_LN_ENA_SHIFT 10 /* EPD_OUTP_LN_ENA */
735
+
#define WM2200_EPD_OUTP_LN_ENA_WIDTH 1 /* EPD_OUTP_LN_ENA */
736
+
#define WM2200_EPD_RMV_SHRT_LN 0x0200 /* EPD_RMV_SHRT_LN */
737
+
#define WM2200_EPD_RMV_SHRT_LN_MASK 0x0200 /* EPD_RMV_SHRT_LN */
738
+
#define WM2200_EPD_RMV_SHRT_LN_SHIFT 9 /* EPD_RMV_SHRT_LN */
739
+
#define WM2200_EPD_RMV_SHRT_LN_WIDTH 1 /* EPD_RMV_SHRT_LN */
740
+
741
+
/*
742
+
* R528 (0x210) - Ear Piece Ctrl 2
743
+
*/
744
+
#define WM2200_EPD_RP_ENA 0x4000 /* EPD_RP_ENA */
745
+
#define WM2200_EPD_RP_ENA_MASK 0x4000 /* EPD_RP_ENA */
746
+
#define WM2200_EPD_RP_ENA_SHIFT 14 /* EPD_RP_ENA */
747
+
#define WM2200_EPD_RP_ENA_WIDTH 1 /* EPD_RP_ENA */
748
+
#define WM2200_EPD_OUTP_RP_ENA 0x2000 /* EPD_OUTP_RP_ENA */
749
+
#define WM2200_EPD_OUTP_RP_ENA_MASK 0x2000 /* EPD_OUTP_RP_ENA */
750
+
#define WM2200_EPD_OUTP_RP_ENA_SHIFT 13 /* EPD_OUTP_RP_ENA */
751
+
#define WM2200_EPD_OUTP_RP_ENA_WIDTH 1 /* EPD_OUTP_RP_ENA */
752
+
#define WM2200_EPD_RMV_SHRT_RP 0x1000 /* EPD_RMV_SHRT_RP */
753
+
#define WM2200_EPD_RMV_SHRT_RP_MASK 0x1000 /* EPD_RMV_SHRT_RP */
754
+
#define WM2200_EPD_RMV_SHRT_RP_SHIFT 12 /* EPD_RMV_SHRT_RP */
755
+
#define WM2200_EPD_RMV_SHRT_RP_WIDTH 1 /* EPD_RMV_SHRT_RP */
756
+
#define WM2200_EPD_RN_ENA 0x0800 /* EPD_RN_ENA */
757
+
#define WM2200_EPD_RN_ENA_MASK 0x0800 /* EPD_RN_ENA */
758
+
#define WM2200_EPD_RN_ENA_SHIFT 11 /* EPD_RN_ENA */
759
+
#define WM2200_EPD_RN_ENA_WIDTH 1 /* EPD_RN_ENA */
760
+
#define WM2200_EPD_OUTP_RN_ENA 0x0400 /* EPD_OUTP_RN_ENA */
761
+
#define WM2200_EPD_OUTP_RN_ENA_MASK 0x0400 /* EPD_OUTP_RN_ENA */
762
+
#define WM2200_EPD_OUTP_RN_ENA_SHIFT 10 /* EPD_OUTP_RN_ENA */
763
+
#define WM2200_EPD_OUTP_RN_ENA_WIDTH 1 /* EPD_OUTP_RN_ENA */
764
+
#define WM2200_EPD_RMV_SHRT_RN 0x0200 /* EPD_RMV_SHRT_RN */
765
+
#define WM2200_EPD_RMV_SHRT_RN_MASK 0x0200 /* EPD_RMV_SHRT_RN */
766
+
#define WM2200_EPD_RMV_SHRT_RN_SHIFT 9 /* EPD_RMV_SHRT_RN */
767
+
#define WM2200_EPD_RMV_SHRT_RN_WIDTH 1 /* EPD_RMV_SHRT_RN */
768
+
769
+
/*
770
+
* R769 (0x301) - Input Enables
771
+
*/
772
+
#define WM2200_IN3L_ENA 0x0020 /* IN3L_ENA */
773
+
#define WM2200_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
774
+
#define WM2200_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
775
+
#define WM2200_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
776
+
#define WM2200_IN3R_ENA 0x0010 /* IN3R_ENA */
777
+
#define WM2200_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
778
+
#define WM2200_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
779
+
#define WM2200_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
780
+
#define WM2200_IN2L_ENA 0x0008 /* IN2L_ENA */
781
+
#define WM2200_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
782
+
#define WM2200_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
783
+
#define WM2200_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
784
+
#define WM2200_IN2R_ENA 0x0004 /* IN2R_ENA */
785
+
#define WM2200_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
786
+
#define WM2200_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
787
+
#define WM2200_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
788
+
#define WM2200_IN1L_ENA 0x0002 /* IN1L_ENA */
789
+
#define WM2200_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
790
+
#define WM2200_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
791
+
#define WM2200_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
792
+
#define WM2200_IN1R_ENA 0x0001 /* IN1R_ENA */
793
+
#define WM2200_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
794
+
#define WM2200_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
795
+
#define WM2200_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
796
+
797
+
/*
798
+
* R770 (0x302) - IN1L Control
799
+
*/
800
+
#define WM2200_IN1_OSR 0x2000 /* IN1_OSR */
801
+
#define WM2200_IN1_OSR_MASK 0x2000 /* IN1_OSR */
802
+
#define WM2200_IN1_OSR_SHIFT 13 /* IN1_OSR */
803
+
#define WM2200_IN1_OSR_WIDTH 1 /* IN1_OSR */
804
+
#define WM2200_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
805
+
#define WM2200_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
806
+
#define WM2200_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
807
+
#define WM2200_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
808
+
#define WM2200_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
809
+
#define WM2200_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
810
+
#define WM2200_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
811
+
#define WM2200_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
812
+
#define WM2200_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
813
+
814
+
/*
815
+
* R771 (0x303) - IN1R Control
816
+
*/
817
+
#define WM2200_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
818
+
#define WM2200_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
819
+
#define WM2200_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
820
+
821
+
/*
822
+
* R772 (0x304) - IN2L Control
823
+
*/
824
+
#define WM2200_IN2_OSR 0x2000 /* IN2_OSR */
825
+
#define WM2200_IN2_OSR_MASK 0x2000 /* IN2_OSR */
826
+
#define WM2200_IN2_OSR_SHIFT 13 /* IN2_OSR */
827
+
#define WM2200_IN2_OSR_WIDTH 1 /* IN2_OSR */
828
+
#define WM2200_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
829
+
#define WM2200_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
830
+
#define WM2200_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
831
+
#define WM2200_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
832
+
#define WM2200_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
833
+
#define WM2200_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
834
+
#define WM2200_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
835
+
#define WM2200_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
836
+
#define WM2200_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
837
+
838
+
/*
839
+
* R773 (0x305) - IN2R Control
840
+
*/
841
+
#define WM2200_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
842
+
#define WM2200_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
843
+
#define WM2200_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
844
+
845
+
/*
846
+
* R774 (0x306) - IN3L Control
847
+
*/
848
+
#define WM2200_IN3_OSR 0x2000 /* IN3_OSR */
849
+
#define WM2200_IN3_OSR_MASK 0x2000 /* IN3_OSR */
850
+
#define WM2200_IN3_OSR_SHIFT 13 /* IN3_OSR */
851
+
#define WM2200_IN3_OSR_WIDTH 1 /* IN3_OSR */
852
+
#define WM2200_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
853
+
#define WM2200_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
854
+
#define WM2200_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
855
+
#define WM2200_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
856
+
#define WM2200_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
857
+
#define WM2200_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
858
+
#define WM2200_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
859
+
#define WM2200_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
860
+
#define WM2200_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
861
+
862
+
/*
863
+
* R775 (0x307) - IN3R Control
864
+
*/
865
+
#define WM2200_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
866
+
#define WM2200_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
867
+
#define WM2200_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
868
+
869
+
/*
870
+
* R778 (0x30A) - RXANC_SRC
871
+
*/
872
+
#define WM2200_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */
873
+
#define WM2200_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */
874
+
#define WM2200_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */
875
+
876
+
/*
877
+
* R779 (0x30B) - Input Volume Ramp
878
+
*/
879
+
#define WM2200_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
880
+
#define WM2200_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
881
+
#define WM2200_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
882
+
#define WM2200_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
883
+
#define WM2200_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
884
+
#define WM2200_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
885
+
886
+
/*
887
+
* R780 (0x30C) - ADC Digital Volume 1L
888
+
*/
889
+
#define WM2200_IN_VU 0x0200 /* IN_VU */
890
+
#define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
891
+
#define WM2200_IN_VU_SHIFT 9 /* IN_VU */
892
+
#define WM2200_IN_VU_WIDTH 1 /* IN_VU */
893
+
#define WM2200_IN1L_MUTE 0x0100 /* IN1L_MUTE */
894
+
#define WM2200_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
895
+
#define WM2200_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
896
+
#define WM2200_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
897
+
#define WM2200_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
898
+
#define WM2200_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
899
+
#define WM2200_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
900
+
901
+
/*
902
+
* R781 (0x30D) - ADC Digital Volume 1R
903
+
*/
904
+
#define WM2200_IN_VU 0x0200 /* IN_VU */
905
+
#define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
906
+
#define WM2200_IN_VU_SHIFT 9 /* IN_VU */
907
+
#define WM2200_IN_VU_WIDTH 1 /* IN_VU */
908
+
#define WM2200_IN1R_MUTE 0x0100 /* IN1R_MUTE */
909
+
#define WM2200_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
910
+
#define WM2200_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
911
+
#define WM2200_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
912
+
#define WM2200_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
913
+
#define WM2200_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
914
+
#define WM2200_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
915
+
916
+
/*
917
+
* R782 (0x30E) - ADC Digital Volume 2L
918
+
*/
919
+
#define WM2200_IN_VU 0x0200 /* IN_VU */
920
+
#define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
921
+
#define WM2200_IN_VU_SHIFT 9 /* IN_VU */
922
+
#define WM2200_IN_VU_WIDTH 1 /* IN_VU */
923
+
#define WM2200_IN2L_MUTE 0x0100 /* IN2L_MUTE */
924
+
#define WM2200_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
925
+
#define WM2200_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
926
+
#define WM2200_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
927
+
#define WM2200_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
928
+
#define WM2200_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
929
+
#define WM2200_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
930
+
931
+
/*
932
+
* R783 (0x30F) - ADC Digital Volume 2R
933
+
*/
934
+
#define WM2200_IN_VU 0x0200 /* IN_VU */
935
+
#define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
936
+
#define WM2200_IN_VU_SHIFT 9 /* IN_VU */
937
+
#define WM2200_IN_VU_WIDTH 1 /* IN_VU */
938
+
#define WM2200_IN2R_MUTE 0x0100 /* IN2R_MUTE */
939
+
#define WM2200_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
940
+
#define WM2200_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
941
+
#define WM2200_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
942
+
#define WM2200_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
943
+
#define WM2200_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
944
+
#define WM2200_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
945
+
946
+
/*
947
+
* R784 (0x310) - ADC Digital Volume 3L
948
+
*/
949
+
#define WM2200_IN_VU 0x0200 /* IN_VU */
950
+
#define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
951
+
#define WM2200_IN_VU_SHIFT 9 /* IN_VU */
952
+
#define WM2200_IN_VU_WIDTH 1 /* IN_VU */
953
+
#define WM2200_IN3L_MUTE 0x0100 /* IN3L_MUTE */
954
+
#define WM2200_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
955
+
#define WM2200_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
956
+
#define WM2200_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
957
+
#define WM2200_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
958
+
#define WM2200_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
959
+
#define WM2200_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
960
+
961
+
/*
962
+
* R785 (0x311) - ADC Digital Volume 3R
963
+
*/
964
+
#define WM2200_IN_VU 0x0200 /* IN_VU */
965
+
#define WM2200_IN_VU_MASK 0x0200 /* IN_VU */
966
+
#define WM2200_IN_VU_SHIFT 9 /* IN_VU */
967
+
#define WM2200_IN_VU_WIDTH 1 /* IN_VU */
968
+
#define WM2200_IN3R_MUTE 0x0100 /* IN3R_MUTE */
969
+
#define WM2200_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
970
+
#define WM2200_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
971
+
#define WM2200_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
972
+
#define WM2200_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
973
+
#define WM2200_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
974
+
#define WM2200_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
975
+
976
+
/*
977
+
* R1024 (0x400) - Output Enables
978
+
*/
979
+
#define WM2200_OUT2L_ENA 0x0008 /* OUT2L_ENA */
980
+
#define WM2200_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
981
+
#define WM2200_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */
982
+
#define WM2200_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */
983
+
#define WM2200_OUT2R_ENA 0x0004 /* OUT2R_ENA */
984
+
#define WM2200_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
985
+
#define WM2200_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */
986
+
#define WM2200_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */
987
+
#define WM2200_OUT1L_ENA 0x0002 /* OUT1L_ENA */
988
+
#define WM2200_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
989
+
#define WM2200_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */
990
+
#define WM2200_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */
991
+
#define WM2200_OUT1R_ENA 0x0001 /* OUT1R_ENA */
992
+
#define WM2200_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
993
+
#define WM2200_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
994
+
#define WM2200_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */
995
+
996
+
/*
997
+
* R1025 (0x401) - DAC Volume Limit 1L
998
+
*/
999
+
#define WM2200_OUT1_OSR 0x2000 /* OUT1_OSR */
1000
+
#define WM2200_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
1001
+
#define WM2200_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
1002
+
#define WM2200_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
1003
+
#define WM2200_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */
1004
+
#define WM2200_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */
1005
+
#define WM2200_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */
1006
+
#define WM2200_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */
1007
+
#define WM2200_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
1008
+
#define WM2200_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
1009
+
#define WM2200_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
1010
+
1011
+
/*
1012
+
* R1026 (0x402) - DAC Volume Limit 1R
1013
+
*/
1014
+
#define WM2200_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */
1015
+
#define WM2200_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */
1016
+
#define WM2200_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */
1017
+
#define WM2200_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */
1018
+
#define WM2200_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
1019
+
#define WM2200_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
1020
+
#define WM2200_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
1021
+
1022
+
/*
1023
+
* R1027 (0x403) - DAC Volume Limit 2L
1024
+
*/
1025
+
#define WM2200_OUT2_OSR 0x2000 /* OUT2_OSR */
1026
+
#define WM2200_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
1027
+
#define WM2200_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
1028
+
#define WM2200_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
1029
+
#define WM2200_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */
1030
+
#define WM2200_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */
1031
+
#define WM2200_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */
1032
+
#define WM2200_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */
1033
+
1034
+
/*
1035
+
* R1028 (0x404) - DAC Volume Limit 2R
1036
+
*/
1037
+
#define WM2200_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */
1038
+
#define WM2200_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */
1039
+
#define WM2200_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */
1040
+
#define WM2200_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */
1041
+
1042
+
/*
1043
+
* R1033 (0x409) - DAC AEC Control 1
1044
+
*/
1045
+
#define WM2200_AEC_LOOPBACK_ENA 0x0004 /* AEC_LOOPBACK_ENA */
1046
+
#define WM2200_AEC_LOOPBACK_ENA_MASK 0x0004 /* AEC_LOOPBACK_ENA */
1047
+
#define WM2200_AEC_LOOPBACK_ENA_SHIFT 2 /* AEC_LOOPBACK_ENA */
1048
+
#define WM2200_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
1049
+
#define WM2200_AEC_LOOPBACK_SRC_MASK 0x0003 /* AEC_LOOPBACK_SRC - [1:0] */
1050
+
#define WM2200_AEC_LOOPBACK_SRC_SHIFT 0 /* AEC_LOOPBACK_SRC - [1:0] */
1051
+
#define WM2200_AEC_LOOPBACK_SRC_WIDTH 2 /* AEC_LOOPBACK_SRC - [1:0] */
1052
+
1053
+
/*
1054
+
* R1034 (0x40A) - Output Volume Ramp
1055
+
*/
1056
+
#define WM2200_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
1057
+
#define WM2200_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
1058
+
#define WM2200_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
1059
+
#define WM2200_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
1060
+
#define WM2200_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
1061
+
#define WM2200_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
1062
+
1063
+
/*
1064
+
* R1035 (0x40B) - DAC Digital Volume 1L
1065
+
*/
1066
+
#define WM2200_OUT_VU 0x0200 /* OUT_VU */
1067
+
#define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1068
+
#define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
1069
+
#define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
1070
+
#define WM2200_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
1071
+
#define WM2200_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
1072
+
#define WM2200_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
1073
+
#define WM2200_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
1074
+
#define WM2200_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
1075
+
#define WM2200_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
1076
+
#define WM2200_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
1077
+
1078
+
/*
1079
+
* R1036 (0x40C) - DAC Digital Volume 1R
1080
+
*/
1081
+
#define WM2200_OUT_VU 0x0200 /* OUT_VU */
1082
+
#define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1083
+
#define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
1084
+
#define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
1085
+
#define WM2200_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
1086
+
#define WM2200_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
1087
+
#define WM2200_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
1088
+
#define WM2200_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
1089
+
#define WM2200_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
1090
+
#define WM2200_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
1091
+
#define WM2200_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
1092
+
1093
+
/*
1094
+
* R1037 (0x40D) - DAC Digital Volume 2L
1095
+
*/
1096
+
#define WM2200_OUT_VU 0x0200 /* OUT_VU */
1097
+
#define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1098
+
#define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
1099
+
#define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
1100
+
#define WM2200_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
1101
+
#define WM2200_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
1102
+
#define WM2200_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
1103
+
#define WM2200_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
1104
+
#define WM2200_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
1105
+
#define WM2200_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
1106
+
#define WM2200_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
1107
+
1108
+
/*
1109
+
* R1038 (0x40E) - DAC Digital Volume 2R
1110
+
*/
1111
+
#define WM2200_OUT_VU 0x0200 /* OUT_VU */
1112
+
#define WM2200_OUT_VU_MASK 0x0200 /* OUT_VU */
1113
+
#define WM2200_OUT_VU_SHIFT 9 /* OUT_VU */
1114
+
#define WM2200_OUT_VU_WIDTH 1 /* OUT_VU */
1115
+
#define WM2200_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
1116
+
#define WM2200_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
1117
+
#define WM2200_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
1118
+
#define WM2200_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
1119
+
#define WM2200_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
1120
+
#define WM2200_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
1121
+
#define WM2200_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
1122
+
1123
+
/*
1124
+
* R1047 (0x417) - PDM 1
1125
+
*/
1126
+
#define WM2200_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
1127
+
#define WM2200_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
1128
+
#define WM2200_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
1129
+
#define WM2200_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
1130
+
#define WM2200_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
1131
+
#define WM2200_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
1132
+
#define WM2200_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
1133
+
#define WM2200_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
1134
+
#define WM2200_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
1135
+
#define WM2200_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
1136
+
#define WM2200_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
1137
+
#define WM2200_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
1138
+
#define WM2200_SPK1_MUTE_SEQL_MASK 0x00FF /* SPK1_MUTE_SEQL - [7:0] */
1139
+
#define WM2200_SPK1_MUTE_SEQL_SHIFT 0 /* SPK1_MUTE_SEQL - [7:0] */
1140
+
#define WM2200_SPK1_MUTE_SEQL_WIDTH 8 /* SPK1_MUTE_SEQL - [7:0] */
1141
+
1142
+
/*
1143
+
* R1048 (0x418) - PDM 2
1144
+
*/
1145
+
#define WM2200_SPK1_FMT 0x0001 /* SPK1_FMT */
1146
+
#define WM2200_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
1147
+
#define WM2200_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
1148
+
#define WM2200_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
1149
+
1150
+
/*
1151
+
* R1280 (0x500) - Audio IF 1_1
1152
+
*/
1153
+
#define WM2200_AIF1_BCLK_INV 0x0040 /* AIF1_BCLK_INV */
1154
+
#define WM2200_AIF1_BCLK_INV_MASK 0x0040 /* AIF1_BCLK_INV */
1155
+
#define WM2200_AIF1_BCLK_INV_SHIFT 6 /* AIF1_BCLK_INV */
1156
+
#define WM2200_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
1157
+
#define WM2200_AIF1_BCLK_FRC 0x0020 /* AIF1_BCLK_FRC */
1158
+
#define WM2200_AIF1_BCLK_FRC_MASK 0x0020 /* AIF1_BCLK_FRC */
1159
+
#define WM2200_AIF1_BCLK_FRC_SHIFT 5 /* AIF1_BCLK_FRC */
1160
+
#define WM2200_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
1161
+
#define WM2200_AIF1_BCLK_MSTR 0x0010 /* AIF1_BCLK_MSTR */
1162
+
#define WM2200_AIF1_BCLK_MSTR_MASK 0x0010 /* AIF1_BCLK_MSTR */
1163
+
#define WM2200_AIF1_BCLK_MSTR_SHIFT 4 /* AIF1_BCLK_MSTR */
1164
+
#define WM2200_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
1165
+
#define WM2200_AIF1_BCLK_DIV_MASK 0x000F /* AIF1_BCLK_DIV - [3:0] */
1166
+
#define WM2200_AIF1_BCLK_DIV_SHIFT 0 /* AIF1_BCLK_DIV - [3:0] */
1167
+
#define WM2200_AIF1_BCLK_DIV_WIDTH 4 /* AIF1_BCLK_DIV - [3:0] */
1168
+
1169
+
/*
1170
+
* R1281 (0x501) - Audio IF 1_2
1171
+
*/
1172
+
#define WM2200_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
1173
+
#define WM2200_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
1174
+
#define WM2200_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
1175
+
#define WM2200_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
1176
+
#define WM2200_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
1177
+
#define WM2200_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
1178
+
#define WM2200_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
1179
+
#define WM2200_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
1180
+
#define WM2200_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
1181
+
#define WM2200_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
1182
+
#define WM2200_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
1183
+
#define WM2200_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
1184
+
#define WM2200_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
1185
+
#define WM2200_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
1186
+
#define WM2200_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
1187
+
#define WM2200_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
1188
+
#define WM2200_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
1189
+
#define WM2200_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
1190
+
#define WM2200_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
1191
+
#define WM2200_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
1192
+
1193
+
/*
1194
+
* R1282 (0x502) - Audio IF 1_3
1195
+
*/
1196
+
#define WM2200_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
1197
+
#define WM2200_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
1198
+
#define WM2200_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
1199
+
#define WM2200_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
1200
+
#define WM2200_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
1201
+
#define WM2200_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
1202
+
#define WM2200_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
1203
+
#define WM2200_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
1204
+
#define WM2200_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
1205
+
#define WM2200_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
1206
+
#define WM2200_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
1207
+
#define WM2200_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
1208
+
1209
+
/*
1210
+
* R1283 (0x503) - Audio IF 1_4
1211
+
*/
1212
+
#define WM2200_AIF1_TRI 0x0040 /* AIF1_TRI */
1213
+
#define WM2200_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
1214
+
#define WM2200_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
1215
+
#define WM2200_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
1216
+
1217
+
/*
1218
+
* R1284 (0x504) - Audio IF 1_5
1219
+
*/
1220
+
#define WM2200_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
1221
+
#define WM2200_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
1222
+
#define WM2200_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
1223
+
1224
+
/*
1225
+
* R1285 (0x505) - Audio IF 1_6
1226
+
*/
1227
+
#define WM2200_AIF1TX_BCPF_MASK 0x07FF /* AIF1TX_BCPF - [10:0] */
1228
+
#define WM2200_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [10:0] */
1229
+
#define WM2200_AIF1TX_BCPF_WIDTH 11 /* AIF1TX_BCPF - [10:0] */
1230
+
1231
+
/*
1232
+
* R1286 (0x506) - Audio IF 1_7
1233
+
*/
1234
+
#define WM2200_AIF1RX_BCPF_MASK 0x07FF /* AIF1RX_BCPF - [10:0] */
1235
+
#define WM2200_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [10:0] */
1236
+
#define WM2200_AIF1RX_BCPF_WIDTH 11 /* AIF1RX_BCPF - [10:0] */
1237
+
1238
+
/*
1239
+
* R1287 (0x507) - Audio IF 1_8
1240
+
*/
1241
+
#define WM2200_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
1242
+
#define WM2200_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
1243
+
#define WM2200_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
1244
+
#define WM2200_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
1245
+
#define WM2200_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
1246
+
#define WM2200_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
1247
+
1248
+
/*
1249
+
* R1288 (0x508) - Audio IF 1_9
1250
+
*/
1251
+
#define WM2200_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
1252
+
#define WM2200_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
1253
+
#define WM2200_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
1254
+
#define WM2200_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
1255
+
#define WM2200_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
1256
+
#define WM2200_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
1257
+
1258
+
/*
1259
+
* R1289 (0x509) - Audio IF 1_10
1260
+
*/
1261
+
#define WM2200_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
1262
+
#define WM2200_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
1263
+
#define WM2200_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
1264
+
1265
+
/*
1266
+
* R1290 (0x50A) - Audio IF 1_11
1267
+
*/
1268
+
#define WM2200_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
1269
+
#define WM2200_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
1270
+
#define WM2200_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
1271
+
1272
+
/*
1273
+
* R1291 (0x50B) - Audio IF 1_12
1274
+
*/
1275
+
#define WM2200_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
1276
+
#define WM2200_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
1277
+
#define WM2200_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
1278
+
1279
+
/*
1280
+
* R1292 (0x50C) - Audio IF 1_13
1281
+
*/
1282
+
#define WM2200_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
1283
+
#define WM2200_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
1284
+
#define WM2200_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
1285
+
1286
+
/*
1287
+
* R1293 (0x50D) - Audio IF 1_14
1288
+
*/
1289
+
#define WM2200_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
1290
+
#define WM2200_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
1291
+
#define WM2200_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
1292
+
1293
+
/*
1294
+
* R1294 (0x50E) - Audio IF 1_15
1295
+
*/
1296
+
#define WM2200_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
1297
+
#define WM2200_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
1298
+
#define WM2200_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
1299
+
1300
+
/*
1301
+
* R1295 (0x50F) - Audio IF 1_16
1302
+
*/
1303
+
#define WM2200_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
1304
+
#define WM2200_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
1305
+
#define WM2200_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
1306
+
1307
+
/*
1308
+
* R1296 (0x510) - Audio IF 1_17
1309
+
*/
1310
+
#define WM2200_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
1311
+
#define WM2200_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
1312
+
#define WM2200_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
1313
+
1314
+
/*
1315
+
* R1297 (0x511) - Audio IF 1_18
1316
+
*/
1317
+
#define WM2200_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
1318
+
#define WM2200_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
1319
+
#define WM2200_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
1320
+
1321
+
/*
1322
+
* R1298 (0x512) - Audio IF 1_19
1323
+
*/
1324
+
#define WM2200_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
1325
+
#define WM2200_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
1326
+
#define WM2200_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
1327
+
1328
+
/*
1329
+
* R1299 (0x513) - Audio IF 1_20
1330
+
*/
1331
+
#define WM2200_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
1332
+
#define WM2200_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
1333
+
#define WM2200_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
1334
+
1335
+
/*
1336
+
* R1300 (0x514) - Audio IF 1_21
1337
+
*/
1338
+
#define WM2200_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
1339
+
#define WM2200_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
1340
+
#define WM2200_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
1341
+
1342
+
/*
1343
+
* R1301 (0x515) - Audio IF 1_22
1344
+
*/
1345
+
#define WM2200_AIF1RX6_ENA 0x0800 /* AIF1RX6_ENA */
1346
+
#define WM2200_AIF1RX6_ENA_MASK 0x0800 /* AIF1RX6_ENA */
1347
+
#define WM2200_AIF1RX6_ENA_SHIFT 11 /* AIF1RX6_ENA */
1348
+
#define WM2200_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
1349
+
#define WM2200_AIF1RX5_ENA 0x0400 /* AIF1RX5_ENA */
1350
+
#define WM2200_AIF1RX5_ENA_MASK 0x0400 /* AIF1RX5_ENA */
1351
+
#define WM2200_AIF1RX5_ENA_SHIFT 10 /* AIF1RX5_ENA */
1352
+
#define WM2200_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
1353
+
#define WM2200_AIF1RX4_ENA 0x0200 /* AIF1RX4_ENA */
1354
+
#define WM2200_AIF1RX4_ENA_MASK 0x0200 /* AIF1RX4_ENA */
1355
+
#define WM2200_AIF1RX4_ENA_SHIFT 9 /* AIF1RX4_ENA */
1356
+
#define WM2200_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
1357
+
#define WM2200_AIF1RX3_ENA 0x0100 /* AIF1RX3_ENA */
1358
+
#define WM2200_AIF1RX3_ENA_MASK 0x0100 /* AIF1RX3_ENA */
1359
+
#define WM2200_AIF1RX3_ENA_SHIFT 8 /* AIF1RX3_ENA */
1360
+
#define WM2200_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
1361
+
#define WM2200_AIF1RX2_ENA 0x0080 /* AIF1RX2_ENA */
1362
+
#define WM2200_AIF1RX2_ENA_MASK 0x0080 /* AIF1RX2_ENA */
1363
+
#define WM2200_AIF1RX2_ENA_SHIFT 7 /* AIF1RX2_ENA */
1364
+
#define WM2200_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
1365
+
#define WM2200_AIF1RX1_ENA 0x0040 /* AIF1RX1_ENA */
1366
+
#define WM2200_AIF1RX1_ENA_MASK 0x0040 /* AIF1RX1_ENA */
1367
+
#define WM2200_AIF1RX1_ENA_SHIFT 6 /* AIF1RX1_ENA */
1368
+
#define WM2200_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
1369
+
#define WM2200_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
1370
+
#define WM2200_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
1371
+
#define WM2200_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
1372
+
#define WM2200_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
1373
+
#define WM2200_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
1374
+
#define WM2200_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
1375
+
#define WM2200_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
1376
+
#define WM2200_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
1377
+
#define WM2200_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
1378
+
#define WM2200_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
1379
+
#define WM2200_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
1380
+
#define WM2200_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
1381
+
#define WM2200_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
1382
+
#define WM2200_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
1383
+
#define WM2200_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
1384
+
#define WM2200_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
1385
+
#define WM2200_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
1386
+
#define WM2200_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
1387
+
#define WM2200_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
1388
+
#define WM2200_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
1389
+
#define WM2200_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
1390
+
#define WM2200_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
1391
+
#define WM2200_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
1392
+
#define WM2200_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
1393
+
1394
+
/*
1395
+
* R1536 (0x600) - OUT1LMIX Input 1 Source
1396
+
*/
1397
+
#define WM2200_OUT1LMIX_SRC1_MASK 0x007F /* OUT1LMIX_SRC1 - [6:0] */
1398
+
#define WM2200_OUT1LMIX_SRC1_SHIFT 0 /* OUT1LMIX_SRC1 - [6:0] */
1399
+
#define WM2200_OUT1LMIX_SRC1_WIDTH 7 /* OUT1LMIX_SRC1 - [6:0] */
1400
+
1401
+
/*
1402
+
* R1537 (0x601) - OUT1LMIX Input 1 Volume
1403
+
*/
1404
+
#define WM2200_OUT1LMIX_VOL1_MASK 0x00FE /* OUT1LMIX_VOL1 - [7:1] */
1405
+
#define WM2200_OUT1LMIX_VOL1_SHIFT 1 /* OUT1LMIX_VOL1 - [7:1] */
1406
+
#define WM2200_OUT1LMIX_VOL1_WIDTH 7 /* OUT1LMIX_VOL1 - [7:1] */
1407
+
1408
+
/*
1409
+
* R1538 (0x602) - OUT1LMIX Input 2 Source
1410
+
*/
1411
+
#define WM2200_OUT1LMIX_SRC2_MASK 0x007F /* OUT1LMIX_SRC2 - [6:0] */
1412
+
#define WM2200_OUT1LMIX_SRC2_SHIFT 0 /* OUT1LMIX_SRC2 - [6:0] */
1413
+
#define WM2200_OUT1LMIX_SRC2_WIDTH 7 /* OUT1LMIX_SRC2 - [6:0] */
1414
+
1415
+
/*
1416
+
* R1539 (0x603) - OUT1LMIX Input 2 Volume
1417
+
*/
1418
+
#define WM2200_OUT1LMIX_VOL2_MASK 0x00FE /* OUT1LMIX_VOL2 - [7:1] */
1419
+
#define WM2200_OUT1LMIX_VOL2_SHIFT 1 /* OUT1LMIX_VOL2 - [7:1] */
1420
+
#define WM2200_OUT1LMIX_VOL2_WIDTH 7 /* OUT1LMIX_VOL2 - [7:1] */
1421
+
1422
+
/*
1423
+
* R1540 (0x604) - OUT1LMIX Input 3 Source
1424
+
*/
1425
+
#define WM2200_OUT1LMIX_SRC3_MASK 0x007F /* OUT1LMIX_SRC3 - [6:0] */
1426
+
#define WM2200_OUT1LMIX_SRC3_SHIFT 0 /* OUT1LMIX_SRC3 - [6:0] */
1427
+
#define WM2200_OUT1LMIX_SRC3_WIDTH 7 /* OUT1LMIX_SRC3 - [6:0] */
1428
+
1429
+
/*
1430
+
* R1541 (0x605) - OUT1LMIX Input 3 Volume
1431
+
*/
1432
+
#define WM2200_OUT1LMIX_VOL3_MASK 0x00FE /* OUT1LMIX_VOL3 - [7:1] */
1433
+
#define WM2200_OUT1LMIX_VOL3_SHIFT 1 /* OUT1LMIX_VOL3 - [7:1] */
1434
+
#define WM2200_OUT1LMIX_VOL3_WIDTH 7 /* OUT1LMIX_VOL3 - [7:1] */
1435
+
1436
+
/*
1437
+
* R1542 (0x606) - OUT1LMIX Input 4 Source
1438
+
*/
1439
+
#define WM2200_OUT1LMIX_SRC4_MASK 0x007F /* OUT1LMIX_SRC4 - [6:0] */
1440
+
#define WM2200_OUT1LMIX_SRC4_SHIFT 0 /* OUT1LMIX_SRC4 - [6:0] */
1441
+
#define WM2200_OUT1LMIX_SRC4_WIDTH 7 /* OUT1LMIX_SRC4 - [6:0] */
1442
+
1443
+
/*
1444
+
* R1543 (0x607) - OUT1LMIX Input 4 Volume
1445
+
*/
1446
+
#define WM2200_OUT1LMIX_VOL4_MASK 0x00FE /* OUT1LMIX_VOL4 - [7:1] */
1447
+
#define WM2200_OUT1LMIX_VOL4_SHIFT 1 /* OUT1LMIX_VOL4 - [7:1] */
1448
+
#define WM2200_OUT1LMIX_VOL4_WIDTH 7 /* OUT1LMIX_VOL4 - [7:1] */
1449
+
1450
+
/*
1451
+
* R1544 (0x608) - OUT1RMIX Input 1 Source
1452
+
*/
1453
+
#define WM2200_OUT1RMIX_SRC1_MASK 0x007F /* OUT1RMIX_SRC1 - [6:0] */
1454
+
#define WM2200_OUT1RMIX_SRC1_SHIFT 0 /* OUT1RMIX_SRC1 - [6:0] */
1455
+
#define WM2200_OUT1RMIX_SRC1_WIDTH 7 /* OUT1RMIX_SRC1 - [6:0] */
1456
+
1457
+
/*
1458
+
* R1545 (0x609) - OUT1RMIX Input 1 Volume
1459
+
*/
1460
+
#define WM2200_OUT1RMIX_VOL1_MASK 0x00FE /* OUT1RMIX_VOL1 - [7:1] */
1461
+
#define WM2200_OUT1RMIX_VOL1_SHIFT 1 /* OUT1RMIX_VOL1 - [7:1] */
1462
+
#define WM2200_OUT1RMIX_VOL1_WIDTH 7 /* OUT1RMIX_VOL1 - [7:1] */
1463
+
1464
+
/*
1465
+
* R1546 (0x60A) - OUT1RMIX Input 2 Source
1466
+
*/
1467
+
#define WM2200_OUT1RMIX_SRC2_MASK 0x007F /* OUT1RMIX_SRC2 - [6:0] */
1468
+
#define WM2200_OUT1RMIX_SRC2_SHIFT 0 /* OUT1RMIX_SRC2 - [6:0] */
1469
+
#define WM2200_OUT1RMIX_SRC2_WIDTH 7 /* OUT1RMIX_SRC2 - [6:0] */
1470
+
1471
+
/*
1472
+
* R1547 (0x60B) - OUT1RMIX Input 2 Volume
1473
+
*/
1474
+
#define WM2200_OUT1RMIX_VOL2_MASK 0x00FE /* OUT1RMIX_VOL2 - [7:1] */
1475
+
#define WM2200_OUT1RMIX_VOL2_SHIFT 1 /* OUT1RMIX_VOL2 - [7:1] */
1476
+
#define WM2200_OUT1RMIX_VOL2_WIDTH 7 /* OUT1RMIX_VOL2 - [7:1] */
1477
+
1478
+
/*
1479
+
* R1548 (0x60C) - OUT1RMIX Input 3 Source
1480
+
*/
1481
+
#define WM2200_OUT1RMIX_SRC3_MASK 0x007F /* OUT1RMIX_SRC3 - [6:0] */
1482
+
#define WM2200_OUT1RMIX_SRC3_SHIFT 0 /* OUT1RMIX_SRC3 - [6:0] */
1483
+
#define WM2200_OUT1RMIX_SRC3_WIDTH 7 /* OUT1RMIX_SRC3 - [6:0] */
1484
+
1485
+
/*
1486
+
* R1549 (0x60D) - OUT1RMIX Input 3 Volume
1487
+
*/
1488
+
#define WM2200_OUT1RMIX_VOL3_MASK 0x00FE /* OUT1RMIX_VOL3 - [7:1] */
1489
+
#define WM2200_OUT1RMIX_VOL3_SHIFT 1 /* OUT1RMIX_VOL3 - [7:1] */
1490
+
#define WM2200_OUT1RMIX_VOL3_WIDTH 7 /* OUT1RMIX_VOL3 - [7:1] */
1491
+
1492
+
/*
1493
+
* R1550 (0x60E) - OUT1RMIX Input 4 Source
1494
+
*/
1495
+
#define WM2200_OUT1RMIX_SRC4_MASK 0x007F /* OUT1RMIX_SRC4 - [6:0] */
1496
+
#define WM2200_OUT1RMIX_SRC4_SHIFT 0 /* OUT1RMIX_SRC4 - [6:0] */
1497
+
#define WM2200_OUT1RMIX_SRC4_WIDTH 7 /* OUT1RMIX_SRC4 - [6:0] */
1498
+
1499
+
/*
1500
+
* R1551 (0x60F) - OUT1RMIX Input 4 Volume
1501
+
*/
1502
+
#define WM2200_OUT1RMIX_VOL4_MASK 0x00FE /* OUT1RMIX_VOL4 - [7:1] */
1503
+
#define WM2200_OUT1RMIX_VOL4_SHIFT 1 /* OUT1RMIX_VOL4 - [7:1] */
1504
+
#define WM2200_OUT1RMIX_VOL4_WIDTH 7 /* OUT1RMIX_VOL4 - [7:1] */
1505
+
1506
+
/*
1507
+
* R1552 (0x610) - OUT2LMIX Input 1 Source
1508
+
*/
1509
+
#define WM2200_OUT2LMIX_SRC1_MASK 0x007F /* OUT2LMIX_SRC1 - [6:0] */
1510
+
#define WM2200_OUT2LMIX_SRC1_SHIFT 0 /* OUT2LMIX_SRC1 - [6:0] */
1511
+
#define WM2200_OUT2LMIX_SRC1_WIDTH 7 /* OUT2LMIX_SRC1 - [6:0] */
1512
+
1513
+
/*
1514
+
* R1553 (0x611) - OUT2LMIX Input 1 Volume
1515
+
*/
1516
+
#define WM2200_OUT2LMIX_VOL1_MASK 0x00FE /* OUT2LMIX_VOL1 - [7:1] */
1517
+
#define WM2200_OUT2LMIX_VOL1_SHIFT 1 /* OUT2LMIX_VOL1 - [7:1] */
1518
+
#define WM2200_OUT2LMIX_VOL1_WIDTH 7 /* OUT2LMIX_VOL1 - [7:1] */
1519
+
1520
+
/*
1521
+
* R1554 (0x612) - OUT2LMIX Input 2 Source
1522
+
*/
1523
+
#define WM2200_OUT2LMIX_SRC2_MASK 0x007F /* OUT2LMIX_SRC2 - [6:0] */
1524
+
#define WM2200_OUT2LMIX_SRC2_SHIFT 0 /* OUT2LMIX_SRC2 - [6:0] */
1525
+
#define WM2200_OUT2LMIX_SRC2_WIDTH 7 /* OUT2LMIX_SRC2 - [6:0] */
1526
+
1527
+
/*
1528
+
* R1555 (0x613) - OUT2LMIX Input 2 Volume
1529
+
*/
1530
+
#define WM2200_OUT2LMIX_VOL2_MASK 0x00FE /* OUT2LMIX_VOL2 - [7:1] */
1531
+
#define WM2200_OUT2LMIX_VOL2_SHIFT 1 /* OUT2LMIX_VOL2 - [7:1] */
1532
+
#define WM2200_OUT2LMIX_VOL2_WIDTH 7 /* OUT2LMIX_VOL2 - [7:1] */
1533
+
1534
+
/*
1535
+
* R1556 (0x614) - OUT2LMIX Input 3 Source
1536
+
*/
1537
+
#define WM2200_OUT2LMIX_SRC3_MASK 0x007F /* OUT2LMIX_SRC3 - [6:0] */
1538
+
#define WM2200_OUT2LMIX_SRC3_SHIFT 0 /* OUT2LMIX_SRC3 - [6:0] */
1539
+
#define WM2200_OUT2LMIX_SRC3_WIDTH 7 /* OUT2LMIX_SRC3 - [6:0] */
1540
+
1541
+
/*
1542
+
* R1557 (0x615) - OUT2LMIX Input 3 Volume
1543
+
*/
1544
+
#define WM2200_OUT2LMIX_VOL3_MASK 0x00FE /* OUT2LMIX_VOL3 - [7:1] */
1545
+
#define WM2200_OUT2LMIX_VOL3_SHIFT 1 /* OUT2LMIX_VOL3 - [7:1] */
1546
+
#define WM2200_OUT2LMIX_VOL3_WIDTH 7 /* OUT2LMIX_VOL3 - [7:1] */
1547
+
1548
+
/*
1549
+
* R1558 (0x616) - OUT2LMIX Input 4 Source
1550
+
*/
1551
+
#define WM2200_OUT2LMIX_SRC4_MASK 0x007F /* OUT2LMIX_SRC4 - [6:0] */
1552
+
#define WM2200_OUT2LMIX_SRC4_SHIFT 0 /* OUT2LMIX_SRC4 - [6:0] */
1553
+
#define WM2200_OUT2LMIX_SRC4_WIDTH 7 /* OUT2LMIX_SRC4 - [6:0] */
1554
+
1555
+
/*
1556
+
* R1559 (0x617) - OUT2LMIX Input 4 Volume
1557
+
*/
1558
+
#define WM2200_OUT2LMIX_VOL4_MASK 0x00FE /* OUT2LMIX_VOL4 - [7:1] */
1559
+
#define WM2200_OUT2LMIX_VOL4_SHIFT 1 /* OUT2LMIX_VOL4 - [7:1] */
1560
+
#define WM2200_OUT2LMIX_VOL4_WIDTH 7 /* OUT2LMIX_VOL4 - [7:1] */
1561
+
1562
+
/*
1563
+
* R1560 (0x618) - OUT2RMIX Input 1 Source
1564
+
*/
1565
+
#define WM2200_OUT2RMIX_SRC1_MASK 0x007F /* OUT2RMIX_SRC1 - [6:0] */
1566
+
#define WM2200_OUT2RMIX_SRC1_SHIFT 0 /* OUT2RMIX_SRC1 - [6:0] */
1567
+
#define WM2200_OUT2RMIX_SRC1_WIDTH 7 /* OUT2RMIX_SRC1 - [6:0] */
1568
+
1569
+
/*
1570
+
* R1561 (0x619) - OUT2RMIX Input 1 Volume
1571
+
*/
1572
+
#define WM2200_OUT2RMIX_VOL1_MASK 0x00FE /* OUT2RMIX_VOL1 - [7:1] */
1573
+
#define WM2200_OUT2RMIX_VOL1_SHIFT 1 /* OUT2RMIX_VOL1 - [7:1] */
1574
+
#define WM2200_OUT2RMIX_VOL1_WIDTH 7 /* OUT2RMIX_VOL1 - [7:1] */
1575
+
1576
+
/*
1577
+
* R1562 (0x61A) - OUT2RMIX Input 2 Source
1578
+
*/
1579
+
#define WM2200_OUT2RMIX_SRC2_MASK 0x007F /* OUT2RMIX_SRC2 - [6:0] */
1580
+
#define WM2200_OUT2RMIX_SRC2_SHIFT 0 /* OUT2RMIX_SRC2 - [6:0] */
1581
+
#define WM2200_OUT2RMIX_SRC2_WIDTH 7 /* OUT2RMIX_SRC2 - [6:0] */
1582
+
1583
+
/*
1584
+
* R1563 (0x61B) - OUT2RMIX Input 2 Volume
1585
+
*/
1586
+
#define WM2200_OUT2RMIX_VOL2_MASK 0x00FE /* OUT2RMIX_VOL2 - [7:1] */
1587
+
#define WM2200_OUT2RMIX_VOL2_SHIFT 1 /* OUT2RMIX_VOL2 - [7:1] */
1588
+
#define WM2200_OUT2RMIX_VOL2_WIDTH 7 /* OUT2RMIX_VOL2 - [7:1] */
1589
+
1590
+
/*
1591
+
* R1564 (0x61C) - OUT2RMIX Input 3 Source
1592
+
*/
1593
+
#define WM2200_OUT2RMIX_SRC3_MASK 0x007F /* OUT2RMIX_SRC3 - [6:0] */
1594
+
#define WM2200_OUT2RMIX_SRC3_SHIFT 0 /* OUT2RMIX_SRC3 - [6:0] */
1595
+
#define WM2200_OUT2RMIX_SRC3_WIDTH 7 /* OUT2RMIX_SRC3 - [6:0] */
1596
+
1597
+
/*
1598
+
* R1565 (0x61D) - OUT2RMIX Input 3 Volume
1599
+
*/
1600
+
#define WM2200_OUT2RMIX_VOL3_MASK 0x00FE /* OUT2RMIX_VOL3 - [7:1] */
1601
+
#define WM2200_OUT2RMIX_VOL3_SHIFT 1 /* OUT2RMIX_VOL3 - [7:1] */
1602
+
#define WM2200_OUT2RMIX_VOL3_WIDTH 7 /* OUT2RMIX_VOL3 - [7:1] */
1603
+
1604
+
/*
1605
+
* R1566 (0x61E) - OUT2RMIX Input 4 Source
1606
+
*/
1607
+
#define WM2200_OUT2RMIX_SRC4_MASK 0x007F /* OUT2RMIX_SRC4 - [6:0] */
1608
+
#define WM2200_OUT2RMIX_SRC4_SHIFT 0 /* OUT2RMIX_SRC4 - [6:0] */
1609
+
#define WM2200_OUT2RMIX_SRC4_WIDTH 7 /* OUT2RMIX_SRC4 - [6:0] */
1610
+
1611
+
/*
1612
+
* R1567 (0x61F) - OUT2RMIX Input 4 Volume
1613
+
*/
1614
+
#define WM2200_OUT2RMIX_VOL4_MASK 0x00FE /* OUT2RMIX_VOL4 - [7:1] */
1615
+
#define WM2200_OUT2RMIX_VOL4_SHIFT 1 /* OUT2RMIX_VOL4 - [7:1] */
1616
+
#define WM2200_OUT2RMIX_VOL4_WIDTH 7 /* OUT2RMIX_VOL4 - [7:1] */
1617
+
1618
+
/*
1619
+
* R1568 (0x620) - AIF1TX1MIX Input 1 Source
1620
+
*/
1621
+
#define WM2200_AIF1TX1MIX_SRC1_MASK 0x007F /* AIF1TX1MIX_SRC1 - [6:0] */
1622
+
#define WM2200_AIF1TX1MIX_SRC1_SHIFT 0 /* AIF1TX1MIX_SRC1 - [6:0] */
1623
+
#define WM2200_AIF1TX1MIX_SRC1_WIDTH 7 /* AIF1TX1MIX_SRC1 - [6:0] */
1624
+
1625
+
/*
1626
+
* R1569 (0x621) - AIF1TX1MIX Input 1 Volume
1627
+
*/
1628
+
#define WM2200_AIF1TX1MIX_VOL1_MASK 0x00FE /* AIF1TX1MIX_VOL1 - [7:1] */
1629
+
#define WM2200_AIF1TX1MIX_VOL1_SHIFT 1 /* AIF1TX1MIX_VOL1 - [7:1] */
1630
+
#define WM2200_AIF1TX1MIX_VOL1_WIDTH 7 /* AIF1TX1MIX_VOL1 - [7:1] */
1631
+
1632
+
/*
1633
+
* R1570 (0x622) - AIF1TX1MIX Input 2 Source
1634
+
*/
1635
+
#define WM2200_AIF1TX1MIX_SRC2_MASK 0x007F /* AIF1TX1MIX_SRC2 - [6:0] */
1636
+
#define WM2200_AIF1TX1MIX_SRC2_SHIFT 0 /* AIF1TX1MIX_SRC2 - [6:0] */
1637
+
#define WM2200_AIF1TX1MIX_SRC2_WIDTH 7 /* AIF1TX1MIX_SRC2 - [6:0] */
1638
+
1639
+
/*
1640
+
* R1571 (0x623) - AIF1TX1MIX Input 2 Volume
1641
+
*/
1642
+
#define WM2200_AIF1TX1MIX_VOL2_MASK 0x00FE /* AIF1TX1MIX_VOL2 - [7:1] */
1643
+
#define WM2200_AIF1TX1MIX_VOL2_SHIFT 1 /* AIF1TX1MIX_VOL2 - [7:1] */
1644
+
#define WM2200_AIF1TX1MIX_VOL2_WIDTH 7 /* AIF1TX1MIX_VOL2 - [7:1] */
1645
+
1646
+
/*
1647
+
* R1572 (0x624) - AIF1TX1MIX Input 3 Source
1648
+
*/
1649
+
#define WM2200_AIF1TX1MIX_SRC3_MASK 0x007F /* AIF1TX1MIX_SRC3 - [6:0] */
1650
+
#define WM2200_AIF1TX1MIX_SRC3_SHIFT 0 /* AIF1TX1MIX_SRC3 - [6:0] */
1651
+
#define WM2200_AIF1TX1MIX_SRC3_WIDTH 7 /* AIF1TX1MIX_SRC3 - [6:0] */
1652
+
1653
+
/*
1654
+
* R1573 (0x625) - AIF1TX1MIX Input 3 Volume
1655
+
*/
1656
+
#define WM2200_AIF1TX1MIX_VOL3_MASK 0x00FE /* AIF1TX1MIX_VOL3 - [7:1] */
1657
+
#define WM2200_AIF1TX1MIX_VOL3_SHIFT 1 /* AIF1TX1MIX_VOL3 - [7:1] */
1658
+
#define WM2200_AIF1TX1MIX_VOL3_WIDTH 7 /* AIF1TX1MIX_VOL3 - [7:1] */
1659
+
1660
+
/*
1661
+
* R1574 (0x626) - AIF1TX1MIX Input 4 Source
1662
+
*/
1663
+
#define WM2200_AIF1TX1MIX_SRC4_MASK 0x007F /* AIF1TX1MIX_SRC4 - [6:0] */
1664
+
#define WM2200_AIF1TX1MIX_SRC4_SHIFT 0 /* AIF1TX1MIX_SRC4 - [6:0] */
1665
+
#define WM2200_AIF1TX1MIX_SRC4_WIDTH 7 /* AIF1TX1MIX_SRC4 - [6:0] */
1666
+
1667
+
/*
1668
+
* R1575 (0x627) - AIF1TX1MIX Input 4 Volume
1669
+
*/
1670
+
#define WM2200_AIF1TX1MIX_VOL4_MASK 0x00FE /* AIF1TX1MIX_VOL4 - [7:1] */
1671
+
#define WM2200_AIF1TX1MIX_VOL4_SHIFT 1 /* AIF1TX1MIX_VOL4 - [7:1] */
1672
+
#define WM2200_AIF1TX1MIX_VOL4_WIDTH 7 /* AIF1TX1MIX_VOL4 - [7:1] */
1673
+
1674
+
/*
1675
+
* R1576 (0x628) - AIF1TX2MIX Input 1 Source
1676
+
*/
1677
+
#define WM2200_AIF1TX2MIX_SRC1_MASK 0x007F /* AIF1TX2MIX_SRC1 - [6:0] */
1678
+
#define WM2200_AIF1TX2MIX_SRC1_SHIFT 0 /* AIF1TX2MIX_SRC1 - [6:0] */
1679
+
#define WM2200_AIF1TX2MIX_SRC1_WIDTH 7 /* AIF1TX2MIX_SRC1 - [6:0] */
1680
+
1681
+
/*
1682
+
* R1577 (0x629) - AIF1TX2MIX Input 1 Volume
1683
+
*/
1684
+
#define WM2200_AIF1TX2MIX_VOL1_MASK 0x00FE /* AIF1TX2MIX_VOL1 - [7:1] */
1685
+
#define WM2200_AIF1TX2MIX_VOL1_SHIFT 1 /* AIF1TX2MIX_VOL1 - [7:1] */
1686
+
#define WM2200_AIF1TX2MIX_VOL1_WIDTH 7 /* AIF1TX2MIX_VOL1 - [7:1] */
1687
+
1688
+
/*
1689
+
* R1578 (0x62A) - AIF1TX2MIX Input 2 Source
1690
+
*/
1691
+
#define WM2200_AIF1TX2MIX_SRC2_MASK 0x007F /* AIF1TX2MIX_SRC2 - [6:0] */
1692
+
#define WM2200_AIF1TX2MIX_SRC2_SHIFT 0 /* AIF1TX2MIX_SRC2 - [6:0] */
1693
+
#define WM2200_AIF1TX2MIX_SRC2_WIDTH 7 /* AIF1TX2MIX_SRC2 - [6:0] */
1694
+
1695
+
/*
1696
+
* R1579 (0x62B) - AIF1TX2MIX Input 2 Volume
1697
+
*/
1698
+
#define WM2200_AIF1TX2MIX_VOL2_MASK 0x00FE /* AIF1TX2MIX_VOL2 - [7:1] */
1699
+
#define WM2200_AIF1TX2MIX_VOL2_SHIFT 1 /* AIF1TX2MIX_VOL2 - [7:1] */
1700
+
#define WM2200_AIF1TX2MIX_VOL2_WIDTH 7 /* AIF1TX2MIX_VOL2 - [7:1] */
1701
+
1702
+
/*
1703
+
* R1580 (0x62C) - AIF1TX2MIX Input 3 Source
1704
+
*/
1705
+
#define WM2200_AIF1TX2MIX_SRC3_MASK 0x007F /* AIF1TX2MIX_SRC3 - [6:0] */
1706
+
#define WM2200_AIF1TX2MIX_SRC3_SHIFT 0 /* AIF1TX2MIX_SRC3 - [6:0] */
1707
+
#define WM2200_AIF1TX2MIX_SRC3_WIDTH 7 /* AIF1TX2MIX_SRC3 - [6:0] */
1708
+
1709
+
/*
1710
+
* R1581 (0x62D) - AIF1TX2MIX Input 3 Volume
1711
+
*/
1712
+
#define WM2200_AIF1TX2MIX_VOL3_MASK 0x00FE /* AIF1TX2MIX_VOL3 - [7:1] */
1713
+
#define WM2200_AIF1TX2MIX_VOL3_SHIFT 1 /* AIF1TX2MIX_VOL3 - [7:1] */
1714
+
#define WM2200_AIF1TX2MIX_VOL3_WIDTH 7 /* AIF1TX2MIX_VOL3 - [7:1] */
1715
+
1716
+
/*
1717
+
* R1582 (0x62E) - AIF1TX2MIX Input 4 Source
1718
+
*/
1719
+
#define WM2200_AIF1TX2MIX_SRC4_MASK 0x007F /* AIF1TX2MIX_SRC4 - [6:0] */
1720
+
#define WM2200_AIF1TX2MIX_SRC4_SHIFT 0 /* AIF1TX2MIX_SRC4 - [6:0] */
1721
+
#define WM2200_AIF1TX2MIX_SRC4_WIDTH 7 /* AIF1TX2MIX_SRC4 - [6:0] */
1722
+
1723
+
/*
1724
+
* R1583 (0x62F) - AIF1TX2MIX Input 4 Volume
1725
+
*/
1726
+
#define WM2200_AIF1TX2MIX_VOL4_MASK 0x00FE /* AIF1TX2MIX_VOL4 - [7:1] */
1727
+
#define WM2200_AIF1TX2MIX_VOL4_SHIFT 1 /* AIF1TX2MIX_VOL4 - [7:1] */
1728
+
#define WM2200_AIF1TX2MIX_VOL4_WIDTH 7 /* AIF1TX2MIX_VOL4 - [7:1] */
1729
+
1730
+
/*
1731
+
* R1584 (0x630) - AIF1TX3MIX Input 1 Source
1732
+
*/
1733
+
#define WM2200_AIF1TX3MIX_SRC1_MASK 0x007F /* AIF1TX3MIX_SRC1 - [6:0] */
1734
+
#define WM2200_AIF1TX3MIX_SRC1_SHIFT 0 /* AIF1TX3MIX_SRC1 - [6:0] */
1735
+
#define WM2200_AIF1TX3MIX_SRC1_WIDTH 7 /* AIF1TX3MIX_SRC1 - [6:0] */
1736
+
1737
+
/*
1738
+
* R1585 (0x631) - AIF1TX3MIX Input 1 Volume
1739
+
*/
1740
+
#define WM2200_AIF1TX3MIX_VOL1_MASK 0x00FE /* AIF1TX3MIX_VOL1 - [7:1] */
1741
+
#define WM2200_AIF1TX3MIX_VOL1_SHIFT 1 /* AIF1TX3MIX_VOL1 - [7:1] */
1742
+
#define WM2200_AIF1TX3MIX_VOL1_WIDTH 7 /* AIF1TX3MIX_VOL1 - [7:1] */
1743
+
1744
+
/*
1745
+
* R1586 (0x632) - AIF1TX3MIX Input 2 Source
1746
+
*/
1747
+
#define WM2200_AIF1TX3MIX_SRC2_MASK 0x007F /* AIF1TX3MIX_SRC2 - [6:0] */
1748
+
#define WM2200_AIF1TX3MIX_SRC2_SHIFT 0 /* AIF1TX3MIX_SRC2 - [6:0] */
1749
+
#define WM2200_AIF1TX3MIX_SRC2_WIDTH 7 /* AIF1TX3MIX_SRC2 - [6:0] */
1750
+
1751
+
/*
1752
+
* R1587 (0x633) - AIF1TX3MIX Input 2 Volume
1753
+
*/
1754
+
#define WM2200_AIF1TX3MIX_VOL2_MASK 0x00FE /* AIF1TX3MIX_VOL2 - [7:1] */
1755
+
#define WM2200_AIF1TX3MIX_VOL2_SHIFT 1 /* AIF1TX3MIX_VOL2 - [7:1] */
1756
+
#define WM2200_AIF1TX3MIX_VOL2_WIDTH 7 /* AIF1TX3MIX_VOL2 - [7:1] */
1757
+
1758
+
/*
1759
+
* R1588 (0x634) - AIF1TX3MIX Input 3 Source
1760
+
*/
1761
+
#define WM2200_AIF1TX3MIX_SRC3_MASK 0x007F /* AIF1TX3MIX_SRC3 - [6:0] */
1762
+
#define WM2200_AIF1TX3MIX_SRC3_SHIFT 0 /* AIF1TX3MIX_SRC3 - [6:0] */
1763
+
#define WM2200_AIF1TX3MIX_SRC3_WIDTH 7 /* AIF1TX3MIX_SRC3 - [6:0] */
1764
+
1765
+
/*
1766
+
* R1589 (0x635) - AIF1TX3MIX Input 3 Volume
1767
+
*/
1768
+
#define WM2200_AIF1TX3MIX_VOL3_MASK 0x00FE /* AIF1TX3MIX_VOL3 - [7:1] */
1769
+
#define WM2200_AIF1TX3MIX_VOL3_SHIFT 1 /* AIF1TX3MIX_VOL3 - [7:1] */
1770
+
#define WM2200_AIF1TX3MIX_VOL3_WIDTH 7 /* AIF1TX3MIX_VOL3 - [7:1] */
1771
+
1772
+
/*
1773
+
* R1590 (0x636) - AIF1TX3MIX Input 4 Source
1774
+
*/
1775
+
#define WM2200_AIF1TX3MIX_SRC4_MASK 0x007F /* AIF1TX3MIX_SRC4 - [6:0] */
1776
+
#define WM2200_AIF1TX3MIX_SRC4_SHIFT 0 /* AIF1TX3MIX_SRC4 - [6:0] */
1777
+
#define WM2200_AIF1TX3MIX_SRC4_WIDTH 7 /* AIF1TX3MIX_SRC4 - [6:0] */
1778
+
1779
+
/*
1780
+
* R1591 (0x637) - AIF1TX3MIX Input 4 Volume
1781
+
*/
1782
+
#define WM2200_AIF1TX3MIX_VOL4_MASK 0x00FE /* AIF1TX3MIX_VOL4 - [7:1] */
1783
+
#define WM2200_AIF1TX3MIX_VOL4_SHIFT 1 /* AIF1TX3MIX_VOL4 - [7:1] */
1784
+
#define WM2200_AIF1TX3MIX_VOL4_WIDTH 7 /* AIF1TX3MIX_VOL4 - [7:1] */
1785
+
1786
+
/*
1787
+
* R1592 (0x638) - AIF1TX4MIX Input 1 Source
1788
+
*/
1789
+
#define WM2200_AIF1TX4MIX_SRC1_MASK 0x007F /* AIF1TX4MIX_SRC1 - [6:0] */
1790
+
#define WM2200_AIF1TX4MIX_SRC1_SHIFT 0 /* AIF1TX4MIX_SRC1 - [6:0] */
1791
+
#define WM2200_AIF1TX4MIX_SRC1_WIDTH 7 /* AIF1TX4MIX_SRC1 - [6:0] */
1792
+
1793
+
/*
1794
+
* R1593 (0x639) - AIF1TX4MIX Input 1 Volume
1795
+
*/
1796
+
#define WM2200_AIF1TX4MIX_VOL1_MASK 0x00FE /* AIF1TX4MIX_VOL1 - [7:1] */
1797
+
#define WM2200_AIF1TX4MIX_VOL1_SHIFT 1 /* AIF1TX4MIX_VOL1 - [7:1] */
1798
+
#define WM2200_AIF1TX4MIX_VOL1_WIDTH 7 /* AIF1TX4MIX_VOL1 - [7:1] */
1799
+
1800
+
/*
1801
+
* R1594 (0x63A) - AIF1TX4MIX Input 2 Source
1802
+
*/
1803
+
#define WM2200_AIF1TX4MIX_SRC2_MASK 0x007F /* AIF1TX4MIX_SRC2 - [6:0] */
1804
+
#define WM2200_AIF1TX4MIX_SRC2_SHIFT 0 /* AIF1TX4MIX_SRC2 - [6:0] */
1805
+
#define WM2200_AIF1TX4MIX_SRC2_WIDTH 7 /* AIF1TX4MIX_SRC2 - [6:0] */
1806
+
1807
+
/*
1808
+
* R1595 (0x63B) - AIF1TX4MIX Input 2 Volume
1809
+
*/
1810
+
#define WM2200_AIF1TX4MIX_VOL2_MASK 0x00FE /* AIF1TX4MIX_VOL2 - [7:1] */
1811
+
#define WM2200_AIF1TX4MIX_VOL2_SHIFT 1 /* AIF1TX4MIX_VOL2 - [7:1] */
1812
+
#define WM2200_AIF1TX4MIX_VOL2_WIDTH 7 /* AIF1TX4MIX_VOL2 - [7:1] */
1813
+
1814
+
/*
1815
+
* R1596 (0x63C) - AIF1TX4MIX Input 3 Source
1816
+
*/
1817
+
#define WM2200_AIF1TX4MIX_SRC3_MASK 0x007F /* AIF1TX4MIX_SRC3 - [6:0] */
1818
+
#define WM2200_AIF1TX4MIX_SRC3_SHIFT 0 /* AIF1TX4MIX_SRC3 - [6:0] */
1819
+
#define WM2200_AIF1TX4MIX_SRC3_WIDTH 7 /* AIF1TX4MIX_SRC3 - [6:0] */
1820
+
1821
+
/*
1822
+
* R1597 (0x63D) - AIF1TX4MIX Input 3 Volume
1823
+
*/
1824
+
#define WM2200_AIF1TX4MIX_VOL3_MASK 0x00FE /* AIF1TX4MIX_VOL3 - [7:1] */
1825
+
#define WM2200_AIF1TX4MIX_VOL3_SHIFT 1 /* AIF1TX4MIX_VOL3 - [7:1] */
1826
+
#define WM2200_AIF1TX4MIX_VOL3_WIDTH 7 /* AIF1TX4MIX_VOL3 - [7:1] */
1827
+
1828
+
/*
1829
+
* R1598 (0x63E) - AIF1TX4MIX Input 4 Source
1830
+
*/
1831
+
#define WM2200_AIF1TX4MIX_SRC4_MASK 0x007F /* AIF1TX4MIX_SRC4 - [6:0] */
1832
+
#define WM2200_AIF1TX4MIX_SRC4_SHIFT 0 /* AIF1TX4MIX_SRC4 - [6:0] */
1833
+
#define WM2200_AIF1TX4MIX_SRC4_WIDTH 7 /* AIF1TX4MIX_SRC4 - [6:0] */
1834
+
1835
+
/*
1836
+
* R1599 (0x63F) - AIF1TX4MIX Input 4 Volume
1837
+
*/
1838
+
#define WM2200_AIF1TX4MIX_VOL4_MASK 0x00FE /* AIF1TX4MIX_VOL4 - [7:1] */
1839
+
#define WM2200_AIF1TX4MIX_VOL4_SHIFT 1 /* AIF1TX4MIX_VOL4 - [7:1] */
1840
+
#define WM2200_AIF1TX4MIX_VOL4_WIDTH 7 /* AIF1TX4MIX_VOL4 - [7:1] */
1841
+
1842
+
/*
1843
+
* R1600 (0x640) - AIF1TX5MIX Input 1 Source
1844
+
*/
1845
+
#define WM2200_AIF1TX5MIX_SRC1_MASK 0x007F /* AIF1TX5MIX_SRC1 - [6:0] */
1846
+
#define WM2200_AIF1TX5MIX_SRC1_SHIFT 0 /* AIF1TX5MIX_SRC1 - [6:0] */
1847
+
#define WM2200_AIF1TX5MIX_SRC1_WIDTH 7 /* AIF1TX5MIX_SRC1 - [6:0] */
1848
+
1849
+
/*
1850
+
* R1601 (0x641) - AIF1TX5MIX Input 1 Volume
1851
+
*/
1852
+
#define WM2200_AIF1TX5MIX_VOL1_MASK 0x00FE /* AIF1TX5MIX_VOL1 - [7:1] */
1853
+
#define WM2200_AIF1TX5MIX_VOL1_SHIFT 1 /* AIF1TX5MIX_VOL1 - [7:1] */
1854
+
#define WM2200_AIF1TX5MIX_VOL1_WIDTH 7 /* AIF1TX5MIX_VOL1 - [7:1] */
1855
+
1856
+
/*
1857
+
* R1602 (0x642) - AIF1TX5MIX Input 2 Source
1858
+
*/
1859
+
#define WM2200_AIF1TX5MIX_SRC2_MASK 0x007F /* AIF1TX5MIX_SRC2 - [6:0] */
1860
+
#define WM2200_AIF1TX5MIX_SRC2_SHIFT 0 /* AIF1TX5MIX_SRC2 - [6:0] */
1861
+
#define WM2200_AIF1TX5MIX_SRC2_WIDTH 7 /* AIF1TX5MIX_SRC2 - [6:0] */
1862
+
1863
+
/*
1864
+
* R1603 (0x643) - AIF1TX5MIX Input 2 Volume
1865
+
*/
1866
+
#define WM2200_AIF1TX5MIX_VOL2_MASK 0x00FE /* AIF1TX5MIX_VOL2 - [7:1] */
1867
+
#define WM2200_AIF1TX5MIX_VOL2_SHIFT 1 /* AIF1TX5MIX_VOL2 - [7:1] */
1868
+
#define WM2200_AIF1TX5MIX_VOL2_WIDTH 7 /* AIF1TX5MIX_VOL2 - [7:1] */
1869
+
1870
+
/*
1871
+
* R1604 (0x644) - AIF1TX5MIX Input 3 Source
1872
+
*/
1873
+
#define WM2200_AIF1TX5MIX_SRC3_MASK 0x007F /* AIF1TX5MIX_SRC3 - [6:0] */
1874
+
#define WM2200_AIF1TX5MIX_SRC3_SHIFT 0 /* AIF1TX5MIX_SRC3 - [6:0] */
1875
+
#define WM2200_AIF1TX5MIX_SRC3_WIDTH 7 /* AIF1TX5MIX_SRC3 - [6:0] */
1876
+
1877
+
/*
1878
+
* R1605 (0x645) - AIF1TX5MIX Input 3 Volume
1879
+
*/
1880
+
#define WM2200_AIF1TX5MIX_VOL3_MASK 0x00FE /* AIF1TX5MIX_VOL3 - [7:1] */
1881
+
#define WM2200_AIF1TX5MIX_VOL3_SHIFT 1 /* AIF1TX5MIX_VOL3 - [7:1] */
1882
+
#define WM2200_AIF1TX5MIX_VOL3_WIDTH 7 /* AIF1TX5MIX_VOL3 - [7:1] */
1883
+
1884
+
/*
1885
+
* R1606 (0x646) - AIF1TX5MIX Input 4 Source
1886
+
*/
1887
+
#define WM2200_AIF1TX5MIX_SRC4_MASK 0x007F /* AIF1TX5MIX_SRC4 - [6:0] */
1888
+
#define WM2200_AIF1TX5MIX_SRC4_SHIFT 0 /* AIF1TX5MIX_SRC4 - [6:0] */
1889
+
#define WM2200_AIF1TX5MIX_SRC4_WIDTH 7 /* AIF1TX5MIX_SRC4 - [6:0] */
1890
+
1891
+
/*
1892
+
* R1607 (0x647) - AIF1TX5MIX Input 4 Volume
1893
+
*/
1894
+
#define WM2200_AIF1TX5MIX_VOL4_MASK 0x00FE /* AIF1TX5MIX_VOL4 - [7:1] */
1895
+
#define WM2200_AIF1TX5MIX_VOL4_SHIFT 1 /* AIF1TX5MIX_VOL4 - [7:1] */
1896
+
#define WM2200_AIF1TX5MIX_VOL4_WIDTH 7 /* AIF1TX5MIX_VOL4 - [7:1] */
1897
+
1898
+
/*
1899
+
* R1608 (0x648) - AIF1TX6MIX Input 1 Source
1900
+
*/
1901
+
#define WM2200_AIF1TX6MIX_SRC1_MASK 0x007F /* AIF1TX6MIX_SRC1 - [6:0] */
1902
+
#define WM2200_AIF1TX6MIX_SRC1_SHIFT 0 /* AIF1TX6MIX_SRC1 - [6:0] */
1903
+
#define WM2200_AIF1TX6MIX_SRC1_WIDTH 7 /* AIF1TX6MIX_SRC1 - [6:0] */
1904
+
1905
+
/*
1906
+
* R1609 (0x649) - AIF1TX6MIX Input 1 Volume
1907
+
*/
1908
+
#define WM2200_AIF1TX6MIX_VOL1_MASK 0x00FE /* AIF1TX6MIX_VOL1 - [7:1] */
1909
+
#define WM2200_AIF1TX6MIX_VOL1_SHIFT 1 /* AIF1TX6MIX_VOL1 - [7:1] */
1910
+
#define WM2200_AIF1TX6MIX_VOL1_WIDTH 7 /* AIF1TX6MIX_VOL1 - [7:1] */
1911
+
1912
+
/*
1913
+
* R1610 (0x64A) - AIF1TX6MIX Input 2 Source
1914
+
*/
1915
+
#define WM2200_AIF1TX6MIX_SRC2_MASK 0x007F /* AIF1TX6MIX_SRC2 - [6:0] */
1916
+
#define WM2200_AIF1TX6MIX_SRC2_SHIFT 0 /* AIF1TX6MIX_SRC2 - [6:0] */
1917
+
#define WM2200_AIF1TX6MIX_SRC2_WIDTH 7 /* AIF1TX6MIX_SRC2 - [6:0] */
1918
+
1919
+
/*
1920
+
* R1611 (0x64B) - AIF1TX6MIX Input 2 Volume
1921
+
*/
1922
+
#define WM2200_AIF1TX6MIX_VOL2_MASK 0x00FE /* AIF1TX6MIX_VOL2 - [7:1] */
1923
+
#define WM2200_AIF1TX6MIX_VOL2_SHIFT 1 /* AIF1TX6MIX_VOL2 - [7:1] */
1924
+
#define WM2200_AIF1TX6MIX_VOL2_WIDTH 7 /* AIF1TX6MIX_VOL2 - [7:1] */
1925
+
1926
+
/*
1927
+
* R1612 (0x64C) - AIF1TX6MIX Input 3 Source
1928
+
*/
1929
+
#define WM2200_AIF1TX6MIX_SRC3_MASK 0x007F /* AIF1TX6MIX_SRC3 - [6:0] */
1930
+
#define WM2200_AIF1TX6MIX_SRC3_SHIFT 0 /* AIF1TX6MIX_SRC3 - [6:0] */
1931
+
#define WM2200_AIF1TX6MIX_SRC3_WIDTH 7 /* AIF1TX6MIX_SRC3 - [6:0] */
1932
+
1933
+
/*
1934
+
* R1613 (0x64D) - AIF1TX6MIX Input 3 Volume
1935
+
*/
1936
+
#define WM2200_AIF1TX6MIX_VOL3_MASK 0x00FE /* AIF1TX6MIX_VOL3 - [7:1] */
1937
+
#define WM2200_AIF1TX6MIX_VOL3_SHIFT 1 /* AIF1TX6MIX_VOL3 - [7:1] */
1938
+
#define WM2200_AIF1TX6MIX_VOL3_WIDTH 7 /* AIF1TX6MIX_VOL3 - [7:1] */
1939
+
1940
+
/*
1941
+
* R1614 (0x64E) - AIF1TX6MIX Input 4 Source
1942
+
*/
1943
+
#define WM2200_AIF1TX6MIX_SRC4_MASK 0x007F /* AIF1TX6MIX_SRC4 - [6:0] */
1944
+
#define WM2200_AIF1TX6MIX_SRC4_SHIFT 0 /* AIF1TX6MIX_SRC4 - [6:0] */
1945
+
#define WM2200_AIF1TX6MIX_SRC4_WIDTH 7 /* AIF1TX6MIX_SRC4 - [6:0] */
1946
+
1947
+
/*
1948
+
* R1615 (0x64F) - AIF1TX6MIX Input 4 Volume
1949
+
*/
1950
+
#define WM2200_AIF1TX6MIX_VOL4_MASK 0x00FE /* AIF1TX6MIX_VOL4 - [7:1] */
1951
+
#define WM2200_AIF1TX6MIX_VOL4_SHIFT 1 /* AIF1TX6MIX_VOL4 - [7:1] */
1952
+
#define WM2200_AIF1TX6MIX_VOL4_WIDTH 7 /* AIF1TX6MIX_VOL4 - [7:1] */
1953
+
1954
+
/*
1955
+
* R1616 (0x650) - EQLMIX Input 1 Source
1956
+
*/
1957
+
#define WM2200_EQLMIX_SRC1_MASK 0x007F /* EQLMIX_SRC1 - [6:0] */
1958
+
#define WM2200_EQLMIX_SRC1_SHIFT 0 /* EQLMIX_SRC1 - [6:0] */
1959
+
#define WM2200_EQLMIX_SRC1_WIDTH 7 /* EQLMIX_SRC1 - [6:0] */
1960
+
1961
+
/*
1962
+
* R1617 (0x651) - EQLMIX Input 1 Volume
1963
+
*/
1964
+
#define WM2200_EQLMIX_VOL1_MASK 0x00FE /* EQLMIX_VOL1 - [7:1] */
1965
+
#define WM2200_EQLMIX_VOL1_SHIFT 1 /* EQLMIX_VOL1 - [7:1] */
1966
+
#define WM2200_EQLMIX_VOL1_WIDTH 7 /* EQLMIX_VOL1 - [7:1] */
1967
+
1968
+
/*
1969
+
* R1618 (0x652) - EQLMIX Input 2 Source
1970
+
*/
1971
+
#define WM2200_EQLMIX_SRC2_MASK 0x007F /* EQLMIX_SRC2 - [6:0] */
1972
+
#define WM2200_EQLMIX_SRC2_SHIFT 0 /* EQLMIX_SRC2 - [6:0] */
1973
+
#define WM2200_EQLMIX_SRC2_WIDTH 7 /* EQLMIX_SRC2 - [6:0] */
1974
+
1975
+
/*
1976
+
* R1619 (0x653) - EQLMIX Input 2 Volume
1977
+
*/
1978
+
#define WM2200_EQLMIX_VOL2_MASK 0x00FE /* EQLMIX_VOL2 - [7:1] */
1979
+
#define WM2200_EQLMIX_VOL2_SHIFT 1 /* EQLMIX_VOL2 - [7:1] */
1980
+
#define WM2200_EQLMIX_VOL2_WIDTH 7 /* EQLMIX_VOL2 - [7:1] */
1981
+
1982
+
/*
1983
+
* R1620 (0x654) - EQLMIX Input 3 Source
1984
+
*/
1985
+
#define WM2200_EQLMIX_SRC3_MASK 0x007F /* EQLMIX_SRC3 - [6:0] */
1986
+
#define WM2200_EQLMIX_SRC3_SHIFT 0 /* EQLMIX_SRC3 - [6:0] */
1987
+
#define WM2200_EQLMIX_SRC3_WIDTH 7 /* EQLMIX_SRC3 - [6:0] */
1988
+
1989
+
/*
1990
+
* R1621 (0x655) - EQLMIX Input 3 Volume
1991
+
*/
1992
+
#define WM2200_EQLMIX_VOL3_MASK 0x00FE /* EQLMIX_VOL3 - [7:1] */
1993
+
#define WM2200_EQLMIX_VOL3_SHIFT 1 /* EQLMIX_VOL3 - [7:1] */
1994
+
#define WM2200_EQLMIX_VOL3_WIDTH 7 /* EQLMIX_VOL3 - [7:1] */
1995
+
1996
+
/*
1997
+
* R1622 (0x656) - EQLMIX Input 4 Source
1998
+
*/
1999
+
#define WM2200_EQLMIX_SRC4_MASK 0x007F /* EQLMIX_SRC4 - [6:0] */
2000
+
#define WM2200_EQLMIX_SRC4_SHIFT 0 /* EQLMIX_SRC4 - [6:0] */
2001
+
#define WM2200_EQLMIX_SRC4_WIDTH 7 /* EQLMIX_SRC4 - [6:0] */
2002
+
2003
+
/*
2004
+
* R1623 (0x657) - EQLMIX Input 4 Volume
2005
+
*/
2006
+
#define WM2200_EQLMIX_VOL4_MASK 0x00FE /* EQLMIX_VOL4 - [7:1] */
2007
+
#define WM2200_EQLMIX_VOL4_SHIFT 1 /* EQLMIX_VOL4 - [7:1] */
2008
+
#define WM2200_EQLMIX_VOL4_WIDTH 7 /* EQLMIX_VOL4 - [7:1] */
2009
+
2010
+
/*
2011
+
* R1624 (0x658) - EQRMIX Input 1 Source
2012
+
*/
2013
+
#define WM2200_EQRMIX_SRC1_MASK 0x007F /* EQRMIX_SRC1 - [6:0] */
2014
+
#define WM2200_EQRMIX_SRC1_SHIFT 0 /* EQRMIX_SRC1 - [6:0] */
2015
+
#define WM2200_EQRMIX_SRC1_WIDTH 7 /* EQRMIX_SRC1 - [6:0] */
2016
+
2017
+
/*
2018
+
* R1625 (0x659) - EQRMIX Input 1 Volume
2019
+
*/
2020
+
#define WM2200_EQRMIX_VOL1_MASK 0x00FE /* EQRMIX_VOL1 - [7:1] */
2021
+
#define WM2200_EQRMIX_VOL1_SHIFT 1 /* EQRMIX_VOL1 - [7:1] */
2022
+
#define WM2200_EQRMIX_VOL1_WIDTH 7 /* EQRMIX_VOL1 - [7:1] */
2023
+
2024
+
/*
2025
+
* R1626 (0x65A) - EQRMIX Input 2 Source
2026
+
*/
2027
+
#define WM2200_EQRMIX_SRC2_MASK 0x007F /* EQRMIX_SRC2 - [6:0] */
2028
+
#define WM2200_EQRMIX_SRC2_SHIFT 0 /* EQRMIX_SRC2 - [6:0] */
2029
+
#define WM2200_EQRMIX_SRC2_WIDTH 7 /* EQRMIX_SRC2 - [6:0] */
2030
+
2031
+
/*
2032
+
* R1627 (0x65B) - EQRMIX Input 2 Volume
2033
+
*/
2034
+
#define WM2200_EQRMIX_VOL2_MASK 0x00FE /* EQRMIX_VOL2 - [7:1] */
2035
+
#define WM2200_EQRMIX_VOL2_SHIFT 1 /* EQRMIX_VOL2 - [7:1] */
2036
+
#define WM2200_EQRMIX_VOL2_WIDTH 7 /* EQRMIX_VOL2 - [7:1] */
2037
+
2038
+
/*
2039
+
* R1628 (0x65C) - EQRMIX Input 3 Source
2040
+
*/
2041
+
#define WM2200_EQRMIX_SRC3_MASK 0x007F /* EQRMIX_SRC3 - [6:0] */
2042
+
#define WM2200_EQRMIX_SRC3_SHIFT 0 /* EQRMIX_SRC3 - [6:0] */
2043
+
#define WM2200_EQRMIX_SRC3_WIDTH 7 /* EQRMIX_SRC3 - [6:0] */
2044
+
2045
+
/*
2046
+
* R1629 (0x65D) - EQRMIX Input 3 Volume
2047
+
*/
2048
+
#define WM2200_EQRMIX_VOL3_MASK 0x00FE /* EQRMIX_VOL3 - [7:1] */
2049
+
#define WM2200_EQRMIX_VOL3_SHIFT 1 /* EQRMIX_VOL3 - [7:1] */
2050
+
#define WM2200_EQRMIX_VOL3_WIDTH 7 /* EQRMIX_VOL3 - [7:1] */
2051
+
2052
+
/*
2053
+
* R1630 (0x65E) - EQRMIX Input 4 Source
2054
+
*/
2055
+
#define WM2200_EQRMIX_SRC4_MASK 0x007F /* EQRMIX_SRC4 - [6:0] */
2056
+
#define WM2200_EQRMIX_SRC4_SHIFT 0 /* EQRMIX_SRC4 - [6:0] */
2057
+
#define WM2200_EQRMIX_SRC4_WIDTH 7 /* EQRMIX_SRC4 - [6:0] */
2058
+
2059
+
/*
2060
+
* R1631 (0x65F) - EQRMIX Input 4 Volume
2061
+
*/
2062
+
#define WM2200_EQRMIX_VOL4_MASK 0x00FE /* EQRMIX_VOL4 - [7:1] */
2063
+
#define WM2200_EQRMIX_VOL4_SHIFT 1 /* EQRMIX_VOL4 - [7:1] */
2064
+
#define WM2200_EQRMIX_VOL4_WIDTH 7 /* EQRMIX_VOL4 - [7:1] */
2065
+
2066
+
/*
2067
+
* R1632 (0x660) - LHPF1MIX Input 1 Source
2068
+
*/
2069
+
#define WM2200_LHPF1MIX_SRC1_MASK 0x007F /* LHPF1MIX_SRC1 - [6:0] */
2070
+
#define WM2200_LHPF1MIX_SRC1_SHIFT 0 /* LHPF1MIX_SRC1 - [6:0] */
2071
+
#define WM2200_LHPF1MIX_SRC1_WIDTH 7 /* LHPF1MIX_SRC1 - [6:0] */
2072
+
2073
+
/*
2074
+
* R1633 (0x661) - LHPF1MIX Input 1 Volume
2075
+
*/
2076
+
#define WM2200_LHPF1MIX_VOL1_MASK 0x00FE /* LHPF1MIX_VOL1 - [7:1] */
2077
+
#define WM2200_LHPF1MIX_VOL1_SHIFT 1 /* LHPF1MIX_VOL1 - [7:1] */
2078
+
#define WM2200_LHPF1MIX_VOL1_WIDTH 7 /* LHPF1MIX_VOL1 - [7:1] */
2079
+
2080
+
/*
2081
+
* R1634 (0x662) - LHPF1MIX Input 2 Source
2082
+
*/
2083
+
#define WM2200_LHPF1MIX_SRC2_MASK 0x007F /* LHPF1MIX_SRC2 - [6:0] */
2084
+
#define WM2200_LHPF1MIX_SRC2_SHIFT 0 /* LHPF1MIX_SRC2 - [6:0] */
2085
+
#define WM2200_LHPF1MIX_SRC2_WIDTH 7 /* LHPF1MIX_SRC2 - [6:0] */
2086
+
2087
+
/*
2088
+
* R1635 (0x663) - LHPF1MIX Input 2 Volume
2089
+
*/
2090
+
#define WM2200_LHPF1MIX_VOL2_MASK 0x00FE /* LHPF1MIX_VOL2 - [7:1] */
2091
+
#define WM2200_LHPF1MIX_VOL2_SHIFT 1 /* LHPF1MIX_VOL2 - [7:1] */
2092
+
#define WM2200_LHPF1MIX_VOL2_WIDTH 7 /* LHPF1MIX_VOL2 - [7:1] */
2093
+
2094
+
/*
2095
+
* R1636 (0x664) - LHPF1MIX Input 3 Source
2096
+
*/
2097
+
#define WM2200_LHPF1MIX_SRC3_MASK 0x007F /* LHPF1MIX_SRC3 - [6:0] */
2098
+
#define WM2200_LHPF1MIX_SRC3_SHIFT 0 /* LHPF1MIX_SRC3 - [6:0] */
2099
+
#define WM2200_LHPF1MIX_SRC3_WIDTH 7 /* LHPF1MIX_SRC3 - [6:0] */
2100
+
2101
+
/*
2102
+
* R1637 (0x665) - LHPF1MIX Input 3 Volume
2103
+
*/
2104
+
#define WM2200_LHPF1MIX_VOL3_MASK 0x00FE /* LHPF1MIX_VOL3 - [7:1] */
2105
+
#define WM2200_LHPF1MIX_VOL3_SHIFT 1 /* LHPF1MIX_VOL3 - [7:1] */
2106
+
#define WM2200_LHPF1MIX_VOL3_WIDTH 7 /* LHPF1MIX_VOL3 - [7:1] */
2107
+
2108
+
/*
2109
+
* R1638 (0x666) - LHPF1MIX Input 4 Source
2110
+
*/
2111
+
#define WM2200_LHPF1MIX_SRC4_MASK 0x007F /* LHPF1MIX_SRC4 - [6:0] */
2112
+
#define WM2200_LHPF1MIX_SRC4_SHIFT 0 /* LHPF1MIX_SRC4 - [6:0] */
2113
+
#define WM2200_LHPF1MIX_SRC4_WIDTH 7 /* LHPF1MIX_SRC4 - [6:0] */
2114
+
2115
+
/*
2116
+
* R1639 (0x667) - LHPF1MIX Input 4 Volume
2117
+
*/
2118
+
#define WM2200_LHPF1MIX_VOL4_MASK 0x00FE /* LHPF1MIX_VOL4 - [7:1] */
2119
+
#define WM2200_LHPF1MIX_VOL4_SHIFT 1 /* LHPF1MIX_VOL4 - [7:1] */
2120
+
#define WM2200_LHPF1MIX_VOL4_WIDTH 7 /* LHPF1MIX_VOL4 - [7:1] */
2121
+
2122
+
/*
2123
+
* R1640 (0x668) - LHPF2MIX Input 1 Source
2124
+
*/
2125
+
#define WM2200_LHPF2MIX_SRC1_MASK 0x007F /* LHPF2MIX_SRC1 - [6:0] */
2126
+
#define WM2200_LHPF2MIX_SRC1_SHIFT 0 /* LHPF2MIX_SRC1 - [6:0] */
2127
+
#define WM2200_LHPF2MIX_SRC1_WIDTH 7 /* LHPF2MIX_SRC1 - [6:0] */
2128
+
2129
+
/*
2130
+
* R1641 (0x669) - LHPF2MIX Input 1 Volume
2131
+
*/
2132
+
#define WM2200_LHPF2MIX_VOL1_MASK 0x00FE /* LHPF2MIX_VOL1 - [7:1] */
2133
+
#define WM2200_LHPF2MIX_VOL1_SHIFT 1 /* LHPF2MIX_VOL1 - [7:1] */
2134
+
#define WM2200_LHPF2MIX_VOL1_WIDTH 7 /* LHPF2MIX_VOL1 - [7:1] */
2135
+
2136
+
/*
2137
+
* R1642 (0x66A) - LHPF2MIX Input 2 Source
2138
+
*/
2139
+
#define WM2200_LHPF2MIX_SRC2_MASK 0x007F /* LHPF2MIX_SRC2 - [6:0] */
2140
+
#define WM2200_LHPF2MIX_SRC2_SHIFT 0 /* LHPF2MIX_SRC2 - [6:0] */
2141
+
#define WM2200_LHPF2MIX_SRC2_WIDTH 7 /* LHPF2MIX_SRC2 - [6:0] */
2142
+
2143
+
/*
2144
+
* R1643 (0x66B) - LHPF2MIX Input 2 Volume
2145
+
*/
2146
+
#define WM2200_LHPF2MIX_VOL2_MASK 0x00FE /* LHPF2MIX_VOL2 - [7:1] */
2147
+
#define WM2200_LHPF2MIX_VOL2_SHIFT 1 /* LHPF2MIX_VOL2 - [7:1] */
2148
+
#define WM2200_LHPF2MIX_VOL2_WIDTH 7 /* LHPF2MIX_VOL2 - [7:1] */
2149
+
2150
+
/*
2151
+
* R1644 (0x66C) - LHPF2MIX Input 3 Source
2152
+
*/
2153
+
#define WM2200_LHPF2MIX_SRC3_MASK 0x007F /* LHPF2MIX_SRC3 - [6:0] */
2154
+
#define WM2200_LHPF2MIX_SRC3_SHIFT 0 /* LHPF2MIX_SRC3 - [6:0] */
2155
+
#define WM2200_LHPF2MIX_SRC3_WIDTH 7 /* LHPF2MIX_SRC3 - [6:0] */
2156
+
2157
+
/*
2158
+
* R1645 (0x66D) - LHPF2MIX Input 3 Volume
2159
+
*/
2160
+
#define WM2200_LHPF2MIX_VOL3_MASK 0x00FE /* LHPF2MIX_VOL3 - [7:1] */
2161
+
#define WM2200_LHPF2MIX_VOL3_SHIFT 1 /* LHPF2MIX_VOL3 - [7:1] */
2162
+
#define WM2200_LHPF2MIX_VOL3_WIDTH 7 /* LHPF2MIX_VOL3 - [7:1] */
2163
+
2164
+
/*
2165
+
* R1646 (0x66E) - LHPF2MIX Input 4 Source
2166
+
*/
2167
+
#define WM2200_LHPF2MIX_SRC4_MASK 0x007F /* LHPF2MIX_SRC4 - [6:0] */
2168
+
#define WM2200_LHPF2MIX_SRC4_SHIFT 0 /* LHPF2MIX_SRC4 - [6:0] */
2169
+
#define WM2200_LHPF2MIX_SRC4_WIDTH 7 /* LHPF2MIX_SRC4 - [6:0] */
2170
+
2171
+
/*
2172
+
* R1647 (0x66F) - LHPF2MIX Input 4 Volume
2173
+
*/
2174
+
#define WM2200_LHPF2MIX_VOL4_MASK 0x00FE /* LHPF2MIX_VOL4 - [7:1] */
2175
+
#define WM2200_LHPF2MIX_VOL4_SHIFT 1 /* LHPF2MIX_VOL4 - [7:1] */
2176
+
#define WM2200_LHPF2MIX_VOL4_WIDTH 7 /* LHPF2MIX_VOL4 - [7:1] */
2177
+
2178
+
/*
2179
+
* R1648 (0x670) - DSP1LMIX Input 1 Source
2180
+
*/
2181
+
#define WM2200_DSP1LMIX_SRC1_MASK 0x007F /* DSP1LMIX_SRC1 - [6:0] */
2182
+
#define WM2200_DSP1LMIX_SRC1_SHIFT 0 /* DSP1LMIX_SRC1 - [6:0] */
2183
+
#define WM2200_DSP1LMIX_SRC1_WIDTH 7 /* DSP1LMIX_SRC1 - [6:0] */
2184
+
2185
+
/*
2186
+
* R1649 (0x671) - DSP1LMIX Input 1 Volume
2187
+
*/
2188
+
#define WM2200_DSP1LMIX_VOL1_MASK 0x00FE /* DSP1LMIX_VOL1 - [7:1] */
2189
+
#define WM2200_DSP1LMIX_VOL1_SHIFT 1 /* DSP1LMIX_VOL1 - [7:1] */
2190
+
#define WM2200_DSP1LMIX_VOL1_WIDTH 7 /* DSP1LMIX_VOL1 - [7:1] */
2191
+
2192
+
/*
2193
+
* R1650 (0x672) - DSP1LMIX Input 2 Source
2194
+
*/
2195
+
#define WM2200_DSP1LMIX_SRC2_MASK 0x007F /* DSP1LMIX_SRC2 - [6:0] */
2196
+
#define WM2200_DSP1LMIX_SRC2_SHIFT 0 /* DSP1LMIX_SRC2 - [6:0] */
2197
+
#define WM2200_DSP1LMIX_SRC2_WIDTH 7 /* DSP1LMIX_SRC2 - [6:0] */
2198
+
2199
+
/*
2200
+
* R1651 (0x673) - DSP1LMIX Input 2 Volume
2201
+
*/
2202
+
#define WM2200_DSP1LMIX_VOL2_MASK 0x00FE /* DSP1LMIX_VOL2 - [7:1] */
2203
+
#define WM2200_DSP1LMIX_VOL2_SHIFT 1 /* DSP1LMIX_VOL2 - [7:1] */
2204
+
#define WM2200_DSP1LMIX_VOL2_WIDTH 7 /* DSP1LMIX_VOL2 - [7:1] */
2205
+
2206
+
/*
2207
+
* R1652 (0x674) - DSP1LMIX Input 3 Source
2208
+
*/
2209
+
#define WM2200_DSP1LMIX_SRC3_MASK 0x007F /* DSP1LMIX_SRC3 - [6:0] */
2210
+
#define WM2200_DSP1LMIX_SRC3_SHIFT 0 /* DSP1LMIX_SRC3 - [6:0] */
2211
+
#define WM2200_DSP1LMIX_SRC3_WIDTH 7 /* DSP1LMIX_SRC3 - [6:0] */
2212
+
2213
+
/*
2214
+
* R1653 (0x675) - DSP1LMIX Input 3 Volume
2215
+
*/
2216
+
#define WM2200_DSP1LMIX_VOL3_MASK 0x00FE /* DSP1LMIX_VOL3 - [7:1] */
2217
+
#define WM2200_DSP1LMIX_VOL3_SHIFT 1 /* DSP1LMIX_VOL3 - [7:1] */
2218
+
#define WM2200_DSP1LMIX_VOL3_WIDTH 7 /* DSP1LMIX_VOL3 - [7:1] */
2219
+
2220
+
/*
2221
+
* R1654 (0x676) - DSP1LMIX Input 4 Source
2222
+
*/
2223
+
#define WM2200_DSP1LMIX_SRC4_MASK 0x007F /* DSP1LMIX_SRC4 - [6:0] */
2224
+
#define WM2200_DSP1LMIX_SRC4_SHIFT 0 /* DSP1LMIX_SRC4 - [6:0] */
2225
+
#define WM2200_DSP1LMIX_SRC4_WIDTH 7 /* DSP1LMIX_SRC4 - [6:0] */
2226
+
2227
+
/*
2228
+
* R1655 (0x677) - DSP1LMIX Input 4 Volume
2229
+
*/
2230
+
#define WM2200_DSP1LMIX_VOL4_MASK 0x00FE /* DSP1LMIX_VOL4 - [7:1] */
2231
+
#define WM2200_DSP1LMIX_VOL4_SHIFT 1 /* DSP1LMIX_VOL4 - [7:1] */
2232
+
#define WM2200_DSP1LMIX_VOL4_WIDTH 7 /* DSP1LMIX_VOL4 - [7:1] */
2233
+
2234
+
/*
2235
+
* R1656 (0x678) - DSP1RMIX Input 1 Source
2236
+
*/
2237
+
#define WM2200_DSP1RMIX_SRC1_MASK 0x007F /* DSP1RMIX_SRC1 - [6:0] */
2238
+
#define WM2200_DSP1RMIX_SRC1_SHIFT 0 /* DSP1RMIX_SRC1 - [6:0] */
2239
+
#define WM2200_DSP1RMIX_SRC1_WIDTH 7 /* DSP1RMIX_SRC1 - [6:0] */
2240
+
2241
+
/*
2242
+
* R1657 (0x679) - DSP1RMIX Input 1 Volume
2243
+
*/
2244
+
#define WM2200_DSP1RMIX_VOL1_MASK 0x00FE /* DSP1RMIX_VOL1 - [7:1] */
2245
+
#define WM2200_DSP1RMIX_VOL1_SHIFT 1 /* DSP1RMIX_VOL1 - [7:1] */
2246
+
#define WM2200_DSP1RMIX_VOL1_WIDTH 7 /* DSP1RMIX_VOL1 - [7:1] */
2247
+
2248
+
/*
2249
+
* R1658 (0x67A) - DSP1RMIX Input 2 Source
2250
+
*/
2251
+
#define WM2200_DSP1RMIX_SRC2_MASK 0x007F /* DSP1RMIX_SRC2 - [6:0] */
2252
+
#define WM2200_DSP1RMIX_SRC2_SHIFT 0 /* DSP1RMIX_SRC2 - [6:0] */
2253
+
#define WM2200_DSP1RMIX_SRC2_WIDTH 7 /* DSP1RMIX_SRC2 - [6:0] */
2254
+
2255
+
/*
2256
+
* R1659 (0x67B) - DSP1RMIX Input 2 Volume
2257
+
*/
2258
+
#define WM2200_DSP1RMIX_VOL2_MASK 0x00FE /* DSP1RMIX_VOL2 - [7:1] */
2259
+
#define WM2200_DSP1RMIX_VOL2_SHIFT 1 /* DSP1RMIX_VOL2 - [7:1] */
2260
+
#define WM2200_DSP1RMIX_VOL2_WIDTH 7 /* DSP1RMIX_VOL2 - [7:1] */
2261
+
2262
+
/*
2263
+
* R1660 (0x67C) - DSP1RMIX Input 3 Source
2264
+
*/
2265
+
#define WM2200_DSP1RMIX_SRC3_MASK 0x007F /* DSP1RMIX_SRC3 - [6:0] */
2266
+
#define WM2200_DSP1RMIX_SRC3_SHIFT 0 /* DSP1RMIX_SRC3 - [6:0] */
2267
+
#define WM2200_DSP1RMIX_SRC3_WIDTH 7 /* DSP1RMIX_SRC3 - [6:0] */
2268
+
2269
+
/*
2270
+
* R1661 (0x67D) - DSP1RMIX Input 3 Volume
2271
+
*/
2272
+
#define WM2200_DSP1RMIX_VOL3_MASK 0x00FE /* DSP1RMIX_VOL3 - [7:1] */
2273
+
#define WM2200_DSP1RMIX_VOL3_SHIFT 1 /* DSP1RMIX_VOL3 - [7:1] */
2274
+
#define WM2200_DSP1RMIX_VOL3_WIDTH 7 /* DSP1RMIX_VOL3 - [7:1] */
2275
+
2276
+
/*
2277
+
* R1662 (0x67E) - DSP1RMIX Input 4 Source
2278
+
*/
2279
+
#define WM2200_DSP1RMIX_SRC4_MASK 0x007F /* DSP1RMIX_SRC4 - [6:0] */
2280
+
#define WM2200_DSP1RMIX_SRC4_SHIFT 0 /* DSP1RMIX_SRC4 - [6:0] */
2281
+
#define WM2200_DSP1RMIX_SRC4_WIDTH 7 /* DSP1RMIX_SRC4 - [6:0] */
2282
+
2283
+
/*
2284
+
* R1663 (0x67F) - DSP1RMIX Input 4 Volume
2285
+
*/
2286
+
#define WM2200_DSP1RMIX_VOL4_MASK 0x00FE /* DSP1RMIX_VOL4 - [7:1] */
2287
+
#define WM2200_DSP1RMIX_VOL4_SHIFT 1 /* DSP1RMIX_VOL4 - [7:1] */
2288
+
#define WM2200_DSP1RMIX_VOL4_WIDTH 7 /* DSP1RMIX_VOL4 - [7:1] */
2289
+
2290
+
/*
2291
+
* R1664 (0x680) - DSP1AUX1MIX Input 1 Source
2292
+
*/
2293
+
#define WM2200_DSP1AUX1MIX_SRC1_MASK 0x007F /* DSP1AUX1MIX_SRC1 - [6:0] */
2294
+
#define WM2200_DSP1AUX1MIX_SRC1_SHIFT 0 /* DSP1AUX1MIX_SRC1 - [6:0] */
2295
+
#define WM2200_DSP1AUX1MIX_SRC1_WIDTH 7 /* DSP1AUX1MIX_SRC1 - [6:0] */
2296
+
2297
+
/*
2298
+
* R1665 (0x681) - DSP1AUX2MIX Input 1 Source
2299
+
*/
2300
+
#define WM2200_DSP1AUX2MIX_SRC1_MASK 0x007F /* DSP1AUX2MIX_SRC1 - [6:0] */
2301
+
#define WM2200_DSP1AUX2MIX_SRC1_SHIFT 0 /* DSP1AUX2MIX_SRC1 - [6:0] */
2302
+
#define WM2200_DSP1AUX2MIX_SRC1_WIDTH 7 /* DSP1AUX2MIX_SRC1 - [6:0] */
2303
+
2304
+
/*
2305
+
* R1666 (0x682) - DSP1AUX3MIX Input 1 Source
2306
+
*/
2307
+
#define WM2200_DSP1AUX3MIX_SRC1_MASK 0x007F /* DSP1AUX3MIX_SRC1 - [6:0] */
2308
+
#define WM2200_DSP1AUX3MIX_SRC1_SHIFT 0 /* DSP1AUX3MIX_SRC1 - [6:0] */
2309
+
#define WM2200_DSP1AUX3MIX_SRC1_WIDTH 7 /* DSP1AUX3MIX_SRC1 - [6:0] */
2310
+
2311
+
/*
2312
+
* R1667 (0x683) - DSP1AUX4MIX Input 1 Source
2313
+
*/
2314
+
#define WM2200_DSP1AUX4MIX_SRC1_MASK 0x007F /* DSP1AUX4MIX_SRC1 - [6:0] */
2315
+
#define WM2200_DSP1AUX4MIX_SRC1_SHIFT 0 /* DSP1AUX4MIX_SRC1 - [6:0] */
2316
+
#define WM2200_DSP1AUX4MIX_SRC1_WIDTH 7 /* DSP1AUX4MIX_SRC1 - [6:0] */
2317
+
2318
+
/*
2319
+
* R1668 (0x684) - DSP1AUX5MIX Input 1 Source
2320
+
*/
2321
+
#define WM2200_DSP1AUX5MIX_SRC1_MASK 0x007F /* DSP1AUX5MIX_SRC1 - [6:0] */
2322
+
#define WM2200_DSP1AUX5MIX_SRC1_SHIFT 0 /* DSP1AUX5MIX_SRC1 - [6:0] */
2323
+
#define WM2200_DSP1AUX5MIX_SRC1_WIDTH 7 /* DSP1AUX5MIX_SRC1 - [6:0] */
2324
+
2325
+
/*
2326
+
* R1669 (0x685) - DSP1AUX6MIX Input 1 Source
2327
+
*/
2328
+
#define WM2200_DSP1AUX6MIX_SRC1_MASK 0x007F /* DSP1AUX6MIX_SRC1 - [6:0] */
2329
+
#define WM2200_DSP1AUX6MIX_SRC1_SHIFT 0 /* DSP1AUX6MIX_SRC1 - [6:0] */
2330
+
#define WM2200_DSP1AUX6MIX_SRC1_WIDTH 7 /* DSP1AUX6MIX_SRC1 - [6:0] */
2331
+
2332
+
/*
2333
+
* R1670 (0x686) - DSP2LMIX Input 1 Source
2334
+
*/
2335
+
#define WM2200_DSP2LMIX_SRC1_MASK 0x007F /* DSP2LMIX_SRC1 - [6:0] */
2336
+
#define WM2200_DSP2LMIX_SRC1_SHIFT 0 /* DSP2LMIX_SRC1 - [6:0] */
2337
+
#define WM2200_DSP2LMIX_SRC1_WIDTH 7 /* DSP2LMIX_SRC1 - [6:0] */
2338
+
2339
+
/*
2340
+
* R1671 (0x687) - DSP2LMIX Input 1 Volume
2341
+
*/
2342
+
#define WM2200_DSP2LMIX_VOL1_MASK 0x00FE /* DSP2LMIX_VOL1 - [7:1] */
2343
+
#define WM2200_DSP2LMIX_VOL1_SHIFT 1 /* DSP2LMIX_VOL1 - [7:1] */
2344
+
#define WM2200_DSP2LMIX_VOL1_WIDTH 7 /* DSP2LMIX_VOL1 - [7:1] */
2345
+
2346
+
/*
2347
+
* R1672 (0x688) - DSP2LMIX Input 2 Source
2348
+
*/
2349
+
#define WM2200_DSP2LMIX_SRC2_MASK 0x007F /* DSP2LMIX_SRC2 - [6:0] */
2350
+
#define WM2200_DSP2LMIX_SRC2_SHIFT 0 /* DSP2LMIX_SRC2 - [6:0] */
2351
+
#define WM2200_DSP2LMIX_SRC2_WIDTH 7 /* DSP2LMIX_SRC2 - [6:0] */
2352
+
2353
+
/*
2354
+
* R1673 (0x689) - DSP2LMIX Input 2 Volume
2355
+
*/
2356
+
#define WM2200_DSP2LMIX_VOL2_MASK 0x00FE /* DSP2LMIX_VOL2 - [7:1] */
2357
+
#define WM2200_DSP2LMIX_VOL2_SHIFT 1 /* DSP2LMIX_VOL2 - [7:1] */
2358
+
#define WM2200_DSP2LMIX_VOL2_WIDTH 7 /* DSP2LMIX_VOL2 - [7:1] */
2359
+
2360
+
/*
2361
+
* R1674 (0x68A) - DSP2LMIX Input 3 Source
2362
+
*/
2363
+
#define WM2200_DSP2LMIX_SRC3_MASK 0x007F /* DSP2LMIX_SRC3 - [6:0] */
2364
+
#define WM2200_DSP2LMIX_SRC3_SHIFT 0 /* DSP2LMIX_SRC3 - [6:0] */
2365
+
#define WM2200_DSP2LMIX_SRC3_WIDTH 7 /* DSP2LMIX_SRC3 - [6:0] */
2366
+
2367
+
/*
2368
+
* R1675 (0x68B) - DSP2LMIX Input 3 Volume
2369
+
*/
2370
+
#define WM2200_DSP2LMIX_VOL3_MASK 0x00FE /* DSP2LMIX_VOL3 - [7:1] */
2371
+
#define WM2200_DSP2LMIX_VOL3_SHIFT 1 /* DSP2LMIX_VOL3 - [7:1] */
2372
+
#define WM2200_DSP2LMIX_VOL3_WIDTH 7 /* DSP2LMIX_VOL3 - [7:1] */
2373
+
2374
+
/*
2375
+
* R1676 (0x68C) - DSP2LMIX Input 4 Source
2376
+
*/
2377
+
#define WM2200_DSP2LMIX_SRC4_MASK 0x007F /* DSP2LMIX_SRC4 - [6:0] */
2378
+
#define WM2200_DSP2LMIX_SRC4_SHIFT 0 /* DSP2LMIX_SRC4 - [6:0] */
2379
+
#define WM2200_DSP2LMIX_SRC4_WIDTH 7 /* DSP2LMIX_SRC4 - [6:0] */
2380
+
2381
+
/*
2382
+
* R1677 (0x68D) - DSP2LMIX Input 4 Volume
2383
+
*/
2384
+
#define WM2200_DSP2LMIX_VOL4_MASK 0x00FE /* DSP2LMIX_VOL4 - [7:1] */
2385
+
#define WM2200_DSP2LMIX_VOL4_SHIFT 1 /* DSP2LMIX_VOL4 - [7:1] */
2386
+
#define WM2200_DSP2LMIX_VOL4_WIDTH 7 /* DSP2LMIX_VOL4 - [7:1] */
2387
+
2388
+
/*
2389
+
* R1678 (0x68E) - DSP2RMIX Input 1 Source
2390
+
*/
2391
+
#define WM2200_DSP2RMIX_SRC1_MASK 0x007F /* DSP2RMIX_SRC1 - [6:0] */
2392
+
#define WM2200_DSP2RMIX_SRC1_SHIFT 0 /* DSP2RMIX_SRC1 - [6:0] */
2393
+
#define WM2200_DSP2RMIX_SRC1_WIDTH 7 /* DSP2RMIX_SRC1 - [6:0] */
2394
+
2395
+
/*
2396
+
* R1679 (0x68F) - DSP2RMIX Input 1 Volume
2397
+
*/
2398
+
#define WM2200_DSP2RMIX_VOL1_MASK 0x00FE /* DSP2RMIX_VOL1 - [7:1] */
2399
+
#define WM2200_DSP2RMIX_VOL1_SHIFT 1 /* DSP2RMIX_VOL1 - [7:1] */
2400
+
#define WM2200_DSP2RMIX_VOL1_WIDTH 7 /* DSP2RMIX_VOL1 - [7:1] */
2401
+
2402
+
/*
2403
+
* R1680 (0x690) - DSP2RMIX Input 2 Source
2404
+
*/
2405
+
#define WM2200_DSP2RMIX_SRC2_MASK 0x007F /* DSP2RMIX_SRC2 - [6:0] */
2406
+
#define WM2200_DSP2RMIX_SRC2_SHIFT 0 /* DSP2RMIX_SRC2 - [6:0] */
2407
+
#define WM2200_DSP2RMIX_SRC2_WIDTH 7 /* DSP2RMIX_SRC2 - [6:0] */
2408
+
2409
+
/*
2410
+
* R1681 (0x691) - DSP2RMIX Input 2 Volume
2411
+
*/
2412
+
#define WM2200_DSP2RMIX_VOL2_MASK 0x00FE /* DSP2RMIX_VOL2 - [7:1] */
2413
+
#define WM2200_DSP2RMIX_VOL2_SHIFT 1 /* DSP2RMIX_VOL2 - [7:1] */
2414
+
#define WM2200_DSP2RMIX_VOL2_WIDTH 7 /* DSP2RMIX_VOL2 - [7:1] */
2415
+
2416
+
/*
2417
+
* R1682 (0x692) - DSP2RMIX Input 3 Source
2418
+
*/
2419
+
#define WM2200_DSP2RMIX_SRC3_MASK 0x007F /* DSP2RMIX_SRC3 - [6:0] */
2420
+
#define WM2200_DSP2RMIX_SRC3_SHIFT 0 /* DSP2RMIX_SRC3 - [6:0] */
2421
+
#define WM2200_DSP2RMIX_SRC3_WIDTH 7 /* DSP2RMIX_SRC3 - [6:0] */
2422
+
2423
+
/*
2424
+
* R1683 (0x693) - DSP2RMIX Input 3 Volume
2425
+
*/
2426
+
#define WM2200_DSP2RMIX_VOL3_MASK 0x00FE /* DSP2RMIX_VOL3 - [7:1] */
2427
+
#define WM2200_DSP2RMIX_VOL3_SHIFT 1 /* DSP2RMIX_VOL3 - [7:1] */
2428
+
#define WM2200_DSP2RMIX_VOL3_WIDTH 7 /* DSP2RMIX_VOL3 - [7:1] */
2429
+
2430
+
/*
2431
+
* R1684 (0x694) - DSP2RMIX Input 4 Source
2432
+
*/
2433
+
#define WM2200_DSP2RMIX_SRC4_MASK 0x007F /* DSP2RMIX_SRC4 - [6:0] */
2434
+
#define WM2200_DSP2RMIX_SRC4_SHIFT 0 /* DSP2RMIX_SRC4 - [6:0] */
2435
+
#define WM2200_DSP2RMIX_SRC4_WIDTH 7 /* DSP2RMIX_SRC4 - [6:0] */
2436
+
2437
+
/*
2438
+
* R1685 (0x695) - DSP2RMIX Input 4 Volume
2439
+
*/
2440
+
#define WM2200_DSP2RMIX_VOL4_MASK 0x00FE /* DSP2RMIX_VOL4 - [7:1] */
2441
+
#define WM2200_DSP2RMIX_VOL4_SHIFT 1 /* DSP2RMIX_VOL4 - [7:1] */
2442
+
#define WM2200_DSP2RMIX_VOL4_WIDTH 7 /* DSP2RMIX_VOL4 - [7:1] */
2443
+
2444
+
/*
2445
+
* R1686 (0x696) - DSP2AUX1MIX Input 1 Source
2446
+
*/
2447
+
#define WM2200_DSP2AUX1MIX_SRC1_MASK 0x007F /* DSP2AUX1MIX_SRC1 - [6:0] */
2448
+
#define WM2200_DSP2AUX1MIX_SRC1_SHIFT 0 /* DSP2AUX1MIX_SRC1 - [6:0] */
2449
+
#define WM2200_DSP2AUX1MIX_SRC1_WIDTH 7 /* DSP2AUX1MIX_SRC1 - [6:0] */
2450
+
2451
+
/*
2452
+
* R1687 (0x697) - DSP2AUX2MIX Input 1 Source
2453
+
*/
2454
+
#define WM2200_DSP2AUX2MIX_SRC1_MASK 0x007F /* DSP2AUX2MIX_SRC1 - [6:0] */
2455
+
#define WM2200_DSP2AUX2MIX_SRC1_SHIFT 0 /* DSP2AUX2MIX_SRC1 - [6:0] */
2456
+
#define WM2200_DSP2AUX2MIX_SRC1_WIDTH 7 /* DSP2AUX2MIX_SRC1 - [6:0] */
2457
+
2458
+
/*
2459
+
* R1688 (0x698) - DSP2AUX3MIX Input 1 Source
2460
+
*/
2461
+
#define WM2200_DSP2AUX3MIX_SRC1_MASK 0x007F /* DSP2AUX3MIX_SRC1 - [6:0] */
2462
+
#define WM2200_DSP2AUX3MIX_SRC1_SHIFT 0 /* DSP2AUX3MIX_SRC1 - [6:0] */
2463
+
#define WM2200_DSP2AUX3MIX_SRC1_WIDTH 7 /* DSP2AUX3MIX_SRC1 - [6:0] */
2464
+
2465
+
/*
2466
+
* R1689 (0x699) - DSP2AUX4MIX Input 1 Source
2467
+
*/
2468
+
#define WM2200_DSP2AUX4MIX_SRC1_MASK 0x007F /* DSP2AUX4MIX_SRC1 - [6:0] */
2469
+
#define WM2200_DSP2AUX4MIX_SRC1_SHIFT 0 /* DSP2AUX4MIX_SRC1 - [6:0] */
2470
+
#define WM2200_DSP2AUX4MIX_SRC1_WIDTH 7 /* DSP2AUX4MIX_SRC1 - [6:0] */
2471
+
2472
+
/*
2473
+
* R1690 (0x69A) - DSP2AUX5MIX Input 1 Source
2474
+
*/
2475
+
#define WM2200_DSP2AUX5MIX_SRC1_MASK 0x007F /* DSP2AUX5MIX_SRC1 - [6:0] */
2476
+
#define WM2200_DSP2AUX5MIX_SRC1_SHIFT 0 /* DSP2AUX5MIX_SRC1 - [6:0] */
2477
+
#define WM2200_DSP2AUX5MIX_SRC1_WIDTH 7 /* DSP2AUX5MIX_SRC1 - [6:0] */
2478
+
2479
+
/*
2480
+
* R1691 (0x69B) - DSP2AUX6MIX Input 1 Source
2481
+
*/
2482
+
#define WM2200_DSP2AUX6MIX_SRC1_MASK 0x007F /* DSP2AUX6MIX_SRC1 - [6:0] */
2483
+
#define WM2200_DSP2AUX6MIX_SRC1_SHIFT 0 /* DSP2AUX6MIX_SRC1 - [6:0] */
2484
+
#define WM2200_DSP2AUX6MIX_SRC1_WIDTH 7 /* DSP2AUX6MIX_SRC1 - [6:0] */
2485
+
2486
+
/*
2487
+
* R1792 (0x700) - GPIO CTRL 1
2488
+
*/
2489
+
#define WM2200_GP1_DIR 0x8000 /* GP1_DIR */
2490
+
#define WM2200_GP1_DIR_MASK 0x8000 /* GP1_DIR */
2491
+
#define WM2200_GP1_DIR_SHIFT 15 /* GP1_DIR */
2492
+
#define WM2200_GP1_DIR_WIDTH 1 /* GP1_DIR */
2493
+
#define WM2200_GP1_PU 0x4000 /* GP1_PU */
2494
+
#define WM2200_GP1_PU_MASK 0x4000 /* GP1_PU */
2495
+
#define WM2200_GP1_PU_SHIFT 14 /* GP1_PU */
2496
+
#define WM2200_GP1_PU_WIDTH 1 /* GP1_PU */
2497
+
#define WM2200_GP1_PD 0x2000 /* GP1_PD */
2498
+
#define WM2200_GP1_PD_MASK 0x2000 /* GP1_PD */
2499
+
#define WM2200_GP1_PD_SHIFT 13 /* GP1_PD */
2500
+
#define WM2200_GP1_PD_WIDTH 1 /* GP1_PD */
2501
+
#define WM2200_GP1_POL 0x0400 /* GP1_POL */
2502
+
#define WM2200_GP1_POL_MASK 0x0400 /* GP1_POL */
2503
+
#define WM2200_GP1_POL_SHIFT 10 /* GP1_POL */
2504
+
#define WM2200_GP1_POL_WIDTH 1 /* GP1_POL */
2505
+
#define WM2200_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */
2506
+
#define WM2200_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */
2507
+
#define WM2200_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */
2508
+
#define WM2200_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
2509
+
#define WM2200_GP1_DB 0x0100 /* GP1_DB */
2510
+
#define WM2200_GP1_DB_MASK 0x0100 /* GP1_DB */
2511
+
#define WM2200_GP1_DB_SHIFT 8 /* GP1_DB */
2512
+
#define WM2200_GP1_DB_WIDTH 1 /* GP1_DB */
2513
+
#define WM2200_GP1_LVL 0x0040 /* GP1_LVL */
2514
+
#define WM2200_GP1_LVL_MASK 0x0040 /* GP1_LVL */
2515
+
#define WM2200_GP1_LVL_SHIFT 6 /* GP1_LVL */
2516
+
#define WM2200_GP1_LVL_WIDTH 1 /* GP1_LVL */
2517
+
#define WM2200_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */
2518
+
#define WM2200_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */
2519
+
#define WM2200_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */
2520
+
2521
+
/*
2522
+
* R1793 (0x701) - GPIO CTRL 2
2523
+
*/
2524
+
#define WM2200_GP2_DIR 0x8000 /* GP2_DIR */
2525
+
#define WM2200_GP2_DIR_MASK 0x8000 /* GP2_DIR */
2526
+
#define WM2200_GP2_DIR_SHIFT 15 /* GP2_DIR */
2527
+
#define WM2200_GP2_DIR_WIDTH 1 /* GP2_DIR */
2528
+
#define WM2200_GP2_PU 0x4000 /* GP2_PU */
2529
+
#define WM2200_GP2_PU_MASK 0x4000 /* GP2_PU */
2530
+
#define WM2200_GP2_PU_SHIFT 14 /* GP2_PU */
2531
+
#define WM2200_GP2_PU_WIDTH 1 /* GP2_PU */
2532
+
#define WM2200_GP2_PD 0x2000 /* GP2_PD */
2533
+
#define WM2200_GP2_PD_MASK 0x2000 /* GP2_PD */
2534
+
#define WM2200_GP2_PD_SHIFT 13 /* GP2_PD */
2535
+
#define WM2200_GP2_PD_WIDTH 1 /* GP2_PD */
2536
+
#define WM2200_GP2_POL 0x0400 /* GP2_POL */
2537
+
#define WM2200_GP2_POL_MASK 0x0400 /* GP2_POL */
2538
+
#define WM2200_GP2_POL_SHIFT 10 /* GP2_POL */
2539
+
#define WM2200_GP2_POL_WIDTH 1 /* GP2_POL */
2540
+
#define WM2200_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */
2541
+
#define WM2200_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */
2542
+
#define WM2200_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */
2543
+
#define WM2200_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
2544
+
#define WM2200_GP2_DB 0x0100 /* GP2_DB */
2545
+
#define WM2200_GP2_DB_MASK 0x0100 /* GP2_DB */
2546
+
#define WM2200_GP2_DB_SHIFT 8 /* GP2_DB */
2547
+
#define WM2200_GP2_DB_WIDTH 1 /* GP2_DB */
2548
+
#define WM2200_GP2_LVL 0x0040 /* GP2_LVL */
2549
+
#define WM2200_GP2_LVL_MASK 0x0040 /* GP2_LVL */
2550
+
#define WM2200_GP2_LVL_SHIFT 6 /* GP2_LVL */
2551
+
#define WM2200_GP2_LVL_WIDTH 1 /* GP2_LVL */
2552
+
#define WM2200_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */
2553
+
#define WM2200_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */
2554
+
#define WM2200_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */
2555
+
2556
+
/*
2557
+
* R1794 (0x702) - GPIO CTRL 3
2558
+
*/
2559
+
#define WM2200_GP3_DIR 0x8000 /* GP3_DIR */
2560
+
#define WM2200_GP3_DIR_MASK 0x8000 /* GP3_DIR */
2561
+
#define WM2200_GP3_DIR_SHIFT 15 /* GP3_DIR */
2562
+
#define WM2200_GP3_DIR_WIDTH 1 /* GP3_DIR */
2563
+
#define WM2200_GP3_PU 0x4000 /* GP3_PU */
2564
+
#define WM2200_GP3_PU_MASK 0x4000 /* GP3_PU */
2565
+
#define WM2200_GP3_PU_SHIFT 14 /* GP3_PU */
2566
+
#define WM2200_GP3_PU_WIDTH 1 /* GP3_PU */
2567
+
#define WM2200_GP3_PD 0x2000 /* GP3_PD */
2568
+
#define WM2200_GP3_PD_MASK 0x2000 /* GP3_PD */
2569
+
#define WM2200_GP3_PD_SHIFT 13 /* GP3_PD */
2570
+
#define WM2200_GP3_PD_WIDTH 1 /* GP3_PD */
2571
+
#define WM2200_GP3_POL 0x0400 /* GP3_POL */
2572
+
#define WM2200_GP3_POL_MASK 0x0400 /* GP3_POL */
2573
+
#define WM2200_GP3_POL_SHIFT 10 /* GP3_POL */
2574
+
#define WM2200_GP3_POL_WIDTH 1 /* GP3_POL */
2575
+
#define WM2200_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */
2576
+
#define WM2200_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */
2577
+
#define WM2200_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */
2578
+
#define WM2200_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
2579
+
#define WM2200_GP3_DB 0x0100 /* GP3_DB */
2580
+
#define WM2200_GP3_DB_MASK 0x0100 /* GP3_DB */
2581
+
#define WM2200_GP3_DB_SHIFT 8 /* GP3_DB */
2582
+
#define WM2200_GP3_DB_WIDTH 1 /* GP3_DB */
2583
+
#define WM2200_GP3_LVL 0x0040 /* GP3_LVL */
2584
+
#define WM2200_GP3_LVL_MASK 0x0040 /* GP3_LVL */
2585
+
#define WM2200_GP3_LVL_SHIFT 6 /* GP3_LVL */
2586
+
#define WM2200_GP3_LVL_WIDTH 1 /* GP3_LVL */
2587
+
#define WM2200_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */
2588
+
#define WM2200_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */
2589
+
#define WM2200_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */
2590
+
2591
+
/*
2592
+
* R1795 (0x703) - GPIO CTRL 4
2593
+
*/
2594
+
#define WM2200_GP4_DIR 0x8000 /* GP4_DIR */
2595
+
#define WM2200_GP4_DIR_MASK 0x8000 /* GP4_DIR */
2596
+
#define WM2200_GP4_DIR_SHIFT 15 /* GP4_DIR */
2597
+
#define WM2200_GP4_DIR_WIDTH 1 /* GP4_DIR */
2598
+
#define WM2200_GP4_PU 0x4000 /* GP4_PU */
2599
+
#define WM2200_GP4_PU_MASK 0x4000 /* GP4_PU */
2600
+
#define WM2200_GP4_PU_SHIFT 14 /* GP4_PU */
2601
+
#define WM2200_GP4_PU_WIDTH 1 /* GP4_PU */
2602
+
#define WM2200_GP4_PD 0x2000 /* GP4_PD */
2603
+
#define WM2200_GP4_PD_MASK 0x2000 /* GP4_PD */
2604
+
#define WM2200_GP4_PD_SHIFT 13 /* GP4_PD */
2605
+
#define WM2200_GP4_PD_WIDTH 1 /* GP4_PD */
2606
+
#define WM2200_GP4_POL 0x0400 /* GP4_POL */
2607
+
#define WM2200_GP4_POL_MASK 0x0400 /* GP4_POL */
2608
+
#define WM2200_GP4_POL_SHIFT 10 /* GP4_POL */
2609
+
#define WM2200_GP4_POL_WIDTH 1 /* GP4_POL */
2610
+
#define WM2200_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */
2611
+
#define WM2200_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */
2612
+
#define WM2200_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */
2613
+
#define WM2200_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
2614
+
#define WM2200_GP4_DB 0x0100 /* GP4_DB */
2615
+
#define WM2200_GP4_DB_MASK 0x0100 /* GP4_DB */
2616
+
#define WM2200_GP4_DB_SHIFT 8 /* GP4_DB */
2617
+
#define WM2200_GP4_DB_WIDTH 1 /* GP4_DB */
2618
+
#define WM2200_GP4_LVL 0x0040 /* GP4_LVL */
2619
+
#define WM2200_GP4_LVL_MASK 0x0040 /* GP4_LVL */
2620
+
#define WM2200_GP4_LVL_SHIFT 6 /* GP4_LVL */
2621
+
#define WM2200_GP4_LVL_WIDTH 1 /* GP4_LVL */
2622
+
#define WM2200_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */
2623
+
#define WM2200_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */
2624
+
#define WM2200_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */
2625
+
2626
+
/*
2627
+
* R1799 (0x707) - ADPS1 IRQ0
2628
+
*/
2629
+
#define WM2200_DSP_IRQ1 0x0002 /* DSP_IRQ1 */
2630
+
#define WM2200_DSP_IRQ1_MASK 0x0002 /* DSP_IRQ1 */
2631
+
#define WM2200_DSP_IRQ1_SHIFT 1 /* DSP_IRQ1 */
2632
+
#define WM2200_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */
2633
+
#define WM2200_DSP_IRQ0 0x0001 /* DSP_IRQ0 */
2634
+
#define WM2200_DSP_IRQ0_MASK 0x0001 /* DSP_IRQ0 */
2635
+
#define WM2200_DSP_IRQ0_SHIFT 0 /* DSP_IRQ0 */
2636
+
#define WM2200_DSP_IRQ0_WIDTH 1 /* DSP_IRQ0 */
2637
+
2638
+
/*
2639
+
* R1800 (0x708) - ADPS1 IRQ1
2640
+
*/
2641
+
#define WM2200_DSP_IRQ3 0x0002 /* DSP_IRQ3 */
2642
+
#define WM2200_DSP_IRQ3_MASK 0x0002 /* DSP_IRQ3 */
2643
+
#define WM2200_DSP_IRQ3_SHIFT 1 /* DSP_IRQ3 */
2644
+
#define WM2200_DSP_IRQ3_WIDTH 1 /* DSP_IRQ3 */
2645
+
#define WM2200_DSP_IRQ2 0x0001 /* DSP_IRQ2 */
2646
+
#define WM2200_DSP_IRQ2_MASK 0x0001 /* DSP_IRQ2 */
2647
+
#define WM2200_DSP_IRQ2_SHIFT 0 /* DSP_IRQ2 */
2648
+
#define WM2200_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */
2649
+
2650
+
/*
2651
+
* R1801 (0x709) - Misc Pad Ctrl 1
2652
+
*/
2653
+
#define WM2200_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
2654
+
#define WM2200_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
2655
+
#define WM2200_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
2656
+
#define WM2200_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
2657
+
#define WM2200_MCLK2_PD 0x2000 /* MCLK2_PD */
2658
+
#define WM2200_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
2659
+
#define WM2200_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
2660
+
#define WM2200_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
2661
+
#define WM2200_MCLK1_PD 0x1000 /* MCLK1_PD */
2662
+
#define WM2200_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
2663
+
#define WM2200_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
2664
+
#define WM2200_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
2665
+
#define WM2200_DACLRCLK1_PU 0x0400 /* DACLRCLK1_PU */
2666
+
#define WM2200_DACLRCLK1_PU_MASK 0x0400 /* DACLRCLK1_PU */
2667
+
#define WM2200_DACLRCLK1_PU_SHIFT 10 /* DACLRCLK1_PU */
2668
+
#define WM2200_DACLRCLK1_PU_WIDTH 1 /* DACLRCLK1_PU */
2669
+
#define WM2200_DACLRCLK1_PD 0x0200 /* DACLRCLK1_PD */
2670
+
#define WM2200_DACLRCLK1_PD_MASK 0x0200 /* DACLRCLK1_PD */
2671
+
#define WM2200_DACLRCLK1_PD_SHIFT 9 /* DACLRCLK1_PD */
2672
+
#define WM2200_DACLRCLK1_PD_WIDTH 1 /* DACLRCLK1_PD */
2673
+
#define WM2200_BCLK1_PU 0x0100 /* BCLK1_PU */
2674
+
#define WM2200_BCLK1_PU_MASK 0x0100 /* BCLK1_PU */
2675
+
#define WM2200_BCLK1_PU_SHIFT 8 /* BCLK1_PU */
2676
+
#define WM2200_BCLK1_PU_WIDTH 1 /* BCLK1_PU */
2677
+
#define WM2200_BCLK1_PD 0x0080 /* BCLK1_PD */
2678
+
#define WM2200_BCLK1_PD_MASK 0x0080 /* BCLK1_PD */
2679
+
#define WM2200_BCLK1_PD_SHIFT 7 /* BCLK1_PD */
2680
+
#define WM2200_BCLK1_PD_WIDTH 1 /* BCLK1_PD */
2681
+
#define WM2200_DACDAT1_PU 0x0040 /* DACDAT1_PU */
2682
+
#define WM2200_DACDAT1_PU_MASK 0x0040 /* DACDAT1_PU */
2683
+
#define WM2200_DACDAT1_PU_SHIFT 6 /* DACDAT1_PU */
2684
+
#define WM2200_DACDAT1_PU_WIDTH 1 /* DACDAT1_PU */
2685
+
#define WM2200_DACDAT1_PD 0x0020 /* DACDAT1_PD */
2686
+
#define WM2200_DACDAT1_PD_MASK 0x0020 /* DACDAT1_PD */
2687
+
#define WM2200_DACDAT1_PD_SHIFT 5 /* DACDAT1_PD */
2688
+
#define WM2200_DACDAT1_PD_WIDTH 1 /* DACDAT1_PD */
2689
+
#define WM2200_DMICDAT3_PD 0x0010 /* DMICDAT3_PD */
2690
+
#define WM2200_DMICDAT3_PD_MASK 0x0010 /* DMICDAT3_PD */
2691
+
#define WM2200_DMICDAT3_PD_SHIFT 4 /* DMICDAT3_PD */
2692
+
#define WM2200_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
2693
+
#define WM2200_DMICDAT2_PD 0x0008 /* DMICDAT2_PD */
2694
+
#define WM2200_DMICDAT2_PD_MASK 0x0008 /* DMICDAT2_PD */
2695
+
#define WM2200_DMICDAT2_PD_SHIFT 3 /* DMICDAT2_PD */
2696
+
#define WM2200_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
2697
+
#define WM2200_DMICDAT1_PD 0x0004 /* DMICDAT1_PD */
2698
+
#define WM2200_DMICDAT1_PD_MASK 0x0004 /* DMICDAT1_PD */
2699
+
#define WM2200_DMICDAT1_PD_SHIFT 2 /* DMICDAT1_PD */
2700
+
#define WM2200_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
2701
+
#define WM2200_RSTB_PU 0x0002 /* RSTB_PU */
2702
+
#define WM2200_RSTB_PU_MASK 0x0002 /* RSTB_PU */
2703
+
#define WM2200_RSTB_PU_SHIFT 1 /* RSTB_PU */
2704
+
#define WM2200_RSTB_PU_WIDTH 1 /* RSTB_PU */
2705
+
#define WM2200_ADDR_PD 0x0001 /* ADDR_PD */
2706
+
#define WM2200_ADDR_PD_MASK 0x0001 /* ADDR_PD */
2707
+
#define WM2200_ADDR_PD_SHIFT 0 /* ADDR_PD */
2708
+
#define WM2200_ADDR_PD_WIDTH 1 /* ADDR_PD */
2709
+
2710
+
/*
2711
+
* R2048 (0x800) - Interrupt Status 1
2712
+
*/
2713
+
#define WM2200_DSP_IRQ0_EINT 0x0080 /* DSP_IRQ0_EINT */
2714
+
#define WM2200_DSP_IRQ0_EINT_MASK 0x0080 /* DSP_IRQ0_EINT */
2715
+
#define WM2200_DSP_IRQ0_EINT_SHIFT 7 /* DSP_IRQ0_EINT */
2716
+
#define WM2200_DSP_IRQ0_EINT_WIDTH 1 /* DSP_IRQ0_EINT */
2717
+
#define WM2200_DSP_IRQ1_EINT 0x0040 /* DSP_IRQ1_EINT */
2718
+
#define WM2200_DSP_IRQ1_EINT_MASK 0x0040 /* DSP_IRQ1_EINT */
2719
+
#define WM2200_DSP_IRQ1_EINT_SHIFT 6 /* DSP_IRQ1_EINT */
2720
+
#define WM2200_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */
2721
+
#define WM2200_DSP_IRQ2_EINT 0x0020 /* DSP_IRQ2_EINT */
2722
+
#define WM2200_DSP_IRQ2_EINT_MASK 0x0020 /* DSP_IRQ2_EINT */
2723
+
#define WM2200_DSP_IRQ2_EINT_SHIFT 5 /* DSP_IRQ2_EINT */
2724
+
#define WM2200_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */
2725
+
#define WM2200_DSP_IRQ3_EINT 0x0010 /* DSP_IRQ3_EINT */
2726
+
#define WM2200_DSP_IRQ3_EINT_MASK 0x0010 /* DSP_IRQ3_EINT */
2727
+
#define WM2200_DSP_IRQ3_EINT_SHIFT 4 /* DSP_IRQ3_EINT */
2728
+
#define WM2200_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */
2729
+
#define WM2200_GP4_EINT 0x0008 /* GP4_EINT */
2730
+
#define WM2200_GP4_EINT_MASK 0x0008 /* GP4_EINT */
2731
+
#define WM2200_GP4_EINT_SHIFT 3 /* GP4_EINT */
2732
+
#define WM2200_GP4_EINT_WIDTH 1 /* GP4_EINT */
2733
+
#define WM2200_GP3_EINT 0x0004 /* GP3_EINT */
2734
+
#define WM2200_GP3_EINT_MASK 0x0004 /* GP3_EINT */
2735
+
#define WM2200_GP3_EINT_SHIFT 2 /* GP3_EINT */
2736
+
#define WM2200_GP3_EINT_WIDTH 1 /* GP3_EINT */
2737
+
#define WM2200_GP2_EINT 0x0002 /* GP2_EINT */
2738
+
#define WM2200_GP2_EINT_MASK 0x0002 /* GP2_EINT */
2739
+
#define WM2200_GP2_EINT_SHIFT 1 /* GP2_EINT */
2740
+
#define WM2200_GP2_EINT_WIDTH 1 /* GP2_EINT */
2741
+
#define WM2200_GP1_EINT 0x0001 /* GP1_EINT */
2742
+
#define WM2200_GP1_EINT_MASK 0x0001 /* GP1_EINT */
2743
+
#define WM2200_GP1_EINT_SHIFT 0 /* GP1_EINT */
2744
+
#define WM2200_GP1_EINT_WIDTH 1 /* GP1_EINT */
2745
+
2746
+
/*
2747
+
* R2049 (0x801) - Interrupt Status 1 Mask
2748
+
*/
2749
+
#define WM2200_IM_DSP_IRQ0_EINT 0x0080 /* IM_DSP_IRQ0_EINT */
2750
+
#define WM2200_IM_DSP_IRQ0_EINT_MASK 0x0080 /* IM_DSP_IRQ0_EINT */
2751
+
#define WM2200_IM_DSP_IRQ0_EINT_SHIFT 7 /* IM_DSP_IRQ0_EINT */
2752
+
#define WM2200_IM_DSP_IRQ0_EINT_WIDTH 1 /* IM_DSP_IRQ0_EINT */
2753
+
#define WM2200_IM_DSP_IRQ1_EINT 0x0040 /* IM_DSP_IRQ1_EINT */
2754
+
#define WM2200_IM_DSP_IRQ1_EINT_MASK 0x0040 /* IM_DSP_IRQ1_EINT */
2755
+
#define WM2200_IM_DSP_IRQ1_EINT_SHIFT 6 /* IM_DSP_IRQ1_EINT */
2756
+
#define WM2200_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */
2757
+
#define WM2200_IM_DSP_IRQ2_EINT 0x0020 /* IM_DSP_IRQ2_EINT */
2758
+
#define WM2200_IM_DSP_IRQ2_EINT_MASK 0x0020 /* IM_DSP_IRQ2_EINT */
2759
+
#define WM2200_IM_DSP_IRQ2_EINT_SHIFT 5 /* IM_DSP_IRQ2_EINT */
2760
+
#define WM2200_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */
2761
+
#define WM2200_IM_DSP_IRQ3_EINT 0x0010 /* IM_DSP_IRQ3_EINT */
2762
+
#define WM2200_IM_DSP_IRQ3_EINT_MASK 0x0010 /* IM_DSP_IRQ3_EINT */
2763
+
#define WM2200_IM_DSP_IRQ3_EINT_SHIFT 4 /* IM_DSP_IRQ3_EINT */
2764
+
#define WM2200_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */
2765
+
#define WM2200_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
2766
+
#define WM2200_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
2767
+
#define WM2200_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
2768
+
#define WM2200_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
2769
+
#define WM2200_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
2770
+
#define WM2200_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
2771
+
#define WM2200_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
2772
+
#define WM2200_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
2773
+
#define WM2200_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
2774
+
#define WM2200_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
2775
+
#define WM2200_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
2776
+
#define WM2200_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
2777
+
#define WM2200_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
2778
+
#define WM2200_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
2779
+
#define WM2200_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
2780
+
#define WM2200_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
2781
+
2782
+
/*
2783
+
* R2050 (0x802) - Interrupt Status 2
2784
+
*/
2785
+
#define WM2200_WSEQ_BUSY_EINT 0x0100 /* WSEQ_BUSY_EINT */
2786
+
#define WM2200_WSEQ_BUSY_EINT_MASK 0x0100 /* WSEQ_BUSY_EINT */
2787
+
#define WM2200_WSEQ_BUSY_EINT_SHIFT 8 /* WSEQ_BUSY_EINT */
2788
+
#define WM2200_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */
2789
+
#define WM2200_FLL_LOCK_EINT 0x0002 /* FLL_LOCK_EINT */
2790
+
#define WM2200_FLL_LOCK_EINT_MASK 0x0002 /* FLL_LOCK_EINT */
2791
+
#define WM2200_FLL_LOCK_EINT_SHIFT 1 /* FLL_LOCK_EINT */
2792
+
#define WM2200_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */
2793
+
#define WM2200_CLKGEN_EINT 0x0001 /* CLKGEN_EINT */
2794
+
#define WM2200_CLKGEN_EINT_MASK 0x0001 /* CLKGEN_EINT */
2795
+
#define WM2200_CLKGEN_EINT_SHIFT 0 /* CLKGEN_EINT */
2796
+
#define WM2200_CLKGEN_EINT_WIDTH 1 /* CLKGEN_EINT */
2797
+
2798
+
/*
2799
+
* R2051 (0x803) - Interrupt Raw Status 2
2800
+
*/
2801
+
#define WM2200_WSEQ_BUSY_STS 0x0100 /* WSEQ_BUSY_STS */
2802
+
#define WM2200_WSEQ_BUSY_STS_MASK 0x0100 /* WSEQ_BUSY_STS */
2803
+
#define WM2200_WSEQ_BUSY_STS_SHIFT 8 /* WSEQ_BUSY_STS */
2804
+
#define WM2200_WSEQ_BUSY_STS_WIDTH 1 /* WSEQ_BUSY_STS */
2805
+
#define WM2200_FLL_LOCK_STS 0x0002 /* FLL_LOCK_STS */
2806
+
#define WM2200_FLL_LOCK_STS_MASK 0x0002 /* FLL_LOCK_STS */
2807
+
#define WM2200_FLL_LOCK_STS_SHIFT 1 /* FLL_LOCK_STS */
2808
+
#define WM2200_FLL_LOCK_STS_WIDTH 1 /* FLL_LOCK_STS */
2809
+
#define WM2200_CLKGEN_STS 0x0001 /* CLKGEN_STS */
2810
+
#define WM2200_CLKGEN_STS_MASK 0x0001 /* CLKGEN_STS */
2811
+
#define WM2200_CLKGEN_STS_SHIFT 0 /* CLKGEN_STS */
2812
+
#define WM2200_CLKGEN_STS_WIDTH 1 /* CLKGEN_STS */
2813
+
2814
+
/*
2815
+
* R2052 (0x804) - Interrupt Status 2 Mask
2816
+
*/
2817
+
#define WM2200_IM_WSEQ_BUSY_EINT 0x0100 /* IM_WSEQ_BUSY_EINT */
2818
+
#define WM2200_IM_WSEQ_BUSY_EINT_MASK 0x0100 /* IM_WSEQ_BUSY_EINT */
2819
+
#define WM2200_IM_WSEQ_BUSY_EINT_SHIFT 8 /* IM_WSEQ_BUSY_EINT */
2820
+
#define WM2200_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */
2821
+
#define WM2200_IM_FLL_LOCK_EINT 0x0002 /* IM_FLL_LOCK_EINT */
2822
+
#define WM2200_IM_FLL_LOCK_EINT_MASK 0x0002 /* IM_FLL_LOCK_EINT */
2823
+
#define WM2200_IM_FLL_LOCK_EINT_SHIFT 1 /* IM_FLL_LOCK_EINT */
2824
+
#define WM2200_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */
2825
+
#define WM2200_IM_CLKGEN_EINT 0x0001 /* IM_CLKGEN_EINT */
2826
+
#define WM2200_IM_CLKGEN_EINT_MASK 0x0001 /* IM_CLKGEN_EINT */
2827
+
#define WM2200_IM_CLKGEN_EINT_SHIFT 0 /* IM_CLKGEN_EINT */
2828
+
#define WM2200_IM_CLKGEN_EINT_WIDTH 1 /* IM_CLKGEN_EINT */
2829
+
2830
+
/*
2831
+
* R2056 (0x808) - Interrupt Control
2832
+
*/
2833
+
#define WM2200_IM_IRQ 0x0001 /* IM_IRQ */
2834
+
#define WM2200_IM_IRQ_MASK 0x0001 /* IM_IRQ */
2835
+
#define WM2200_IM_IRQ_SHIFT 0 /* IM_IRQ */
2836
+
#define WM2200_IM_IRQ_WIDTH 1 /* IM_IRQ */
2837
+
2838
+
/*
2839
+
* R2304 (0x900) - EQL_1
2840
+
*/
2841
+
#define WM2200_EQL_B1_GAIN_MASK 0xF800 /* EQL_B1_GAIN - [15:11] */
2842
+
#define WM2200_EQL_B1_GAIN_SHIFT 11 /* EQL_B1_GAIN - [15:11] */
2843
+
#define WM2200_EQL_B1_GAIN_WIDTH 5 /* EQL_B1_GAIN - [15:11] */
2844
+
#define WM2200_EQL_B2_GAIN_MASK 0x07C0 /* EQL_B2_GAIN - [10:6] */
2845
+
#define WM2200_EQL_B2_GAIN_SHIFT 6 /* EQL_B2_GAIN - [10:6] */
2846
+
#define WM2200_EQL_B2_GAIN_WIDTH 5 /* EQL_B2_GAIN - [10:6] */
2847
+
#define WM2200_EQL_B3_GAIN_MASK 0x003E /* EQL_B3_GAIN - [5:1] */
2848
+
#define WM2200_EQL_B3_GAIN_SHIFT 1 /* EQL_B3_GAIN - [5:1] */
2849
+
#define WM2200_EQL_B3_GAIN_WIDTH 5 /* EQL_B3_GAIN - [5:1] */
2850
+
#define WM2200_EQL_ENA 0x0001 /* EQL_ENA */
2851
+
#define WM2200_EQL_ENA_MASK 0x0001 /* EQL_ENA */
2852
+
#define WM2200_EQL_ENA_SHIFT 0 /* EQL_ENA */
2853
+
#define WM2200_EQL_ENA_WIDTH 1 /* EQL_ENA */
2854
+
2855
+
/*
2856
+
* R2305 (0x901) - EQL_2
2857
+
*/
2858
+
#define WM2200_EQL_B4_GAIN_MASK 0xF800 /* EQL_B4_GAIN - [15:11] */
2859
+
#define WM2200_EQL_B4_GAIN_SHIFT 11 /* EQL_B4_GAIN - [15:11] */
2860
+
#define WM2200_EQL_B4_GAIN_WIDTH 5 /* EQL_B4_GAIN - [15:11] */
2861
+
#define WM2200_EQL_B5_GAIN_MASK 0x07C0 /* EQL_B5_GAIN - [10:6] */
2862
+
#define WM2200_EQL_B5_GAIN_SHIFT 6 /* EQL_B5_GAIN - [10:6] */
2863
+
#define WM2200_EQL_B5_GAIN_WIDTH 5 /* EQL_B5_GAIN - [10:6] */
2864
+
2865
+
/*
2866
+
* R2306 (0x902) - EQL_3
2867
+
*/
2868
+
#define WM2200_EQL_B1_A_MASK 0xFFFF /* EQL_B1_A - [15:0] */
2869
+
#define WM2200_EQL_B1_A_SHIFT 0 /* EQL_B1_A - [15:0] */
2870
+
#define WM2200_EQL_B1_A_WIDTH 16 /* EQL_B1_A - [15:0] */
2871
+
2872
+
/*
2873
+
* R2307 (0x903) - EQL_4
2874
+
*/
2875
+
#define WM2200_EQL_B1_B_MASK 0xFFFF /* EQL_B1_B - [15:0] */
2876
+
#define WM2200_EQL_B1_B_SHIFT 0 /* EQL_B1_B - [15:0] */
2877
+
#define WM2200_EQL_B1_B_WIDTH 16 /* EQL_B1_B - [15:0] */
2878
+
2879
+
/*
2880
+
* R2308 (0x904) - EQL_5
2881
+
*/
2882
+
#define WM2200_EQL_B1_PG_MASK 0xFFFF /* EQL_B1_PG - [15:0] */
2883
+
#define WM2200_EQL_B1_PG_SHIFT 0 /* EQL_B1_PG - [15:0] */
2884
+
#define WM2200_EQL_B1_PG_WIDTH 16 /* EQL_B1_PG - [15:0] */
2885
+
2886
+
/*
2887
+
* R2309 (0x905) - EQL_6
2888
+
*/
2889
+
#define WM2200_EQL_B2_A_MASK 0xFFFF /* EQL_B2_A - [15:0] */
2890
+
#define WM2200_EQL_B2_A_SHIFT 0 /* EQL_B2_A - [15:0] */
2891
+
#define WM2200_EQL_B2_A_WIDTH 16 /* EQL_B2_A - [15:0] */
2892
+
2893
+
/*
2894
+
* R2310 (0x906) - EQL_7
2895
+
*/
2896
+
#define WM2200_EQL_B2_B_MASK 0xFFFF /* EQL_B2_B - [15:0] */
2897
+
#define WM2200_EQL_B2_B_SHIFT 0 /* EQL_B2_B - [15:0] */
2898
+
#define WM2200_EQL_B2_B_WIDTH 16 /* EQL_B2_B - [15:0] */
2899
+
2900
+
/*
2901
+
* R2311 (0x907) - EQL_8
2902
+
*/
2903
+
#define WM2200_EQL_B2_C_MASK 0xFFFF /* EQL_B2_C - [15:0] */
2904
+
#define WM2200_EQL_B2_C_SHIFT 0 /* EQL_B2_C - [15:0] */
2905
+
#define WM2200_EQL_B2_C_WIDTH 16 /* EQL_B2_C - [15:0] */
2906
+
2907
+
/*
2908
+
* R2312 (0x908) - EQL_9
2909
+
*/
2910
+
#define WM2200_EQL_B2_PG_MASK 0xFFFF /* EQL_B2_PG - [15:0] */
2911
+
#define WM2200_EQL_B2_PG_SHIFT 0 /* EQL_B2_PG - [15:0] */
2912
+
#define WM2200_EQL_B2_PG_WIDTH 16 /* EQL_B2_PG - [15:0] */
2913
+
2914
+
/*
2915
+
* R2313 (0x909) - EQL_10
2916
+
*/
2917
+
#define WM2200_EQL_B3_A_MASK 0xFFFF /* EQL_B3_A - [15:0] */
2918
+
#define WM2200_EQL_B3_A_SHIFT 0 /* EQL_B3_A - [15:0] */
2919
+
#define WM2200_EQL_B3_A_WIDTH 16 /* EQL_B3_A - [15:0] */
2920
+
2921
+
/*
2922
+
* R2314 (0x90A) - EQL_11
2923
+
*/
2924
+
#define WM2200_EQL_B3_B_MASK 0xFFFF /* EQL_B3_B - [15:0] */
2925
+
#define WM2200_EQL_B3_B_SHIFT 0 /* EQL_B3_B - [15:0] */
2926
+
#define WM2200_EQL_B3_B_WIDTH 16 /* EQL_B3_B - [15:0] */
2927
+
2928
+
/*
2929
+
* R2315 (0x90B) - EQL_12
2930
+
*/
2931
+
#define WM2200_EQL_B3_C_MASK 0xFFFF /* EQL_B3_C - [15:0] */
2932
+
#define WM2200_EQL_B3_C_SHIFT 0 /* EQL_B3_C - [15:0] */
2933
+
#define WM2200_EQL_B3_C_WIDTH 16 /* EQL_B3_C - [15:0] */
2934
+
2935
+
/*
2936
+
* R2316 (0x90C) - EQL_13
2937
+
*/
2938
+
#define WM2200_EQL_B3_PG_MASK 0xFFFF /* EQL_B3_PG - [15:0] */
2939
+
#define WM2200_EQL_B3_PG_SHIFT 0 /* EQL_B3_PG - [15:0] */
2940
+
#define WM2200_EQL_B3_PG_WIDTH 16 /* EQL_B3_PG - [15:0] */
2941
+
2942
+
/*
2943
+
* R2317 (0x90D) - EQL_14
2944
+
*/
2945
+
#define WM2200_EQL_B4_A_MASK 0xFFFF /* EQL_B4_A - [15:0] */
2946
+
#define WM2200_EQL_B4_A_SHIFT 0 /* EQL_B4_A - [15:0] */
2947
+
#define WM2200_EQL_B4_A_WIDTH 16 /* EQL_B4_A - [15:0] */
2948
+
2949
+
/*
2950
+
* R2318 (0x90E) - EQL_15
2951
+
*/
2952
+
#define WM2200_EQL_B4_B_MASK 0xFFFF /* EQL_B4_B - [15:0] */
2953
+
#define WM2200_EQL_B4_B_SHIFT 0 /* EQL_B4_B - [15:0] */
2954
+
#define WM2200_EQL_B4_B_WIDTH 16 /* EQL_B4_B - [15:0] */
2955
+
2956
+
/*
2957
+
* R2319 (0x90F) - EQL_16
2958
+
*/
2959
+
#define WM2200_EQL_B4_C_MASK 0xFFFF /* EQL_B4_C - [15:0] */
2960
+
#define WM2200_EQL_B4_C_SHIFT 0 /* EQL_B4_C - [15:0] */
2961
+
#define WM2200_EQL_B4_C_WIDTH 16 /* EQL_B4_C - [15:0] */
2962
+
2963
+
/*
2964
+
* R2320 (0x910) - EQL_17
2965
+
*/
2966
+
#define WM2200_EQL_B4_PG_MASK 0xFFFF /* EQL_B4_PG - [15:0] */
2967
+
#define WM2200_EQL_B4_PG_SHIFT 0 /* EQL_B4_PG - [15:0] */
2968
+
#define WM2200_EQL_B4_PG_WIDTH 16 /* EQL_B4_PG - [15:0] */
2969
+
2970
+
/*
2971
+
* R2321 (0x911) - EQL_18
2972
+
*/
2973
+
#define WM2200_EQL_B5_A_MASK 0xFFFF /* EQL_B5_A - [15:0] */
2974
+
#define WM2200_EQL_B5_A_SHIFT 0 /* EQL_B5_A - [15:0] */
2975
+
#define WM2200_EQL_B5_A_WIDTH 16 /* EQL_B5_A - [15:0] */
2976
+
2977
+
/*
2978
+
* R2322 (0x912) - EQL_19
2979
+
*/
2980
+
#define WM2200_EQL_B5_B_MASK 0xFFFF /* EQL_B5_B - [15:0] */
2981
+
#define WM2200_EQL_B5_B_SHIFT 0 /* EQL_B5_B - [15:0] */
2982
+
#define WM2200_EQL_B5_B_WIDTH 16 /* EQL_B5_B - [15:0] */
2983
+
2984
+
/*
2985
+
* R2323 (0x913) - EQL_20
2986
+
*/
2987
+
#define WM2200_EQL_B5_PG_MASK 0xFFFF /* EQL_B5_PG - [15:0] */
2988
+
#define WM2200_EQL_B5_PG_SHIFT 0 /* EQL_B5_PG - [15:0] */
2989
+
#define WM2200_EQL_B5_PG_WIDTH 16 /* EQL_B5_PG - [15:0] */
2990
+
2991
+
/*
2992
+
* R2326 (0x916) - EQR_1
2993
+
*/
2994
+
#define WM2200_EQR_B1_GAIN_MASK 0xF800 /* EQR_B1_GAIN - [15:11] */
2995
+
#define WM2200_EQR_B1_GAIN_SHIFT 11 /* EQR_B1_GAIN - [15:11] */
2996
+
#define WM2200_EQR_B1_GAIN_WIDTH 5 /* EQR_B1_GAIN - [15:11] */
2997
+
#define WM2200_EQR_B2_GAIN_MASK 0x07C0 /* EQR_B2_GAIN - [10:6] */
2998
+
#define WM2200_EQR_B2_GAIN_SHIFT 6 /* EQR_B2_GAIN - [10:6] */
2999
+
#define WM2200_EQR_B2_GAIN_WIDTH 5 /* EQR_B2_GAIN - [10:6] */
3000
+
#define WM2200_EQR_B3_GAIN_MASK 0x003E /* EQR_B3_GAIN - [5:1] */
3001
+
#define WM2200_EQR_B3_GAIN_SHIFT 1 /* EQR_B3_GAIN - [5:1] */
3002
+
#define WM2200_EQR_B3_GAIN_WIDTH 5 /* EQR_B3_GAIN - [5:1] */
3003
+
#define WM2200_EQR_ENA 0x0001 /* EQR_ENA */
3004
+
#define WM2200_EQR_ENA_MASK 0x0001 /* EQR_ENA */
3005
+
#define WM2200_EQR_ENA_SHIFT 0 /* EQR_ENA */
3006
+
#define WM2200_EQR_ENA_WIDTH 1 /* EQR_ENA */
3007
+
3008
+
/*
3009
+
* R2327 (0x917) - EQR_2
3010
+
*/
3011
+
#define WM2200_EQR_B4_GAIN_MASK 0xF800 /* EQR_B4_GAIN - [15:11] */
3012
+
#define WM2200_EQR_B4_GAIN_SHIFT 11 /* EQR_B4_GAIN - [15:11] */
3013
+
#define WM2200_EQR_B4_GAIN_WIDTH 5 /* EQR_B4_GAIN - [15:11] */
3014
+
#define WM2200_EQR_B5_GAIN_MASK 0x07C0 /* EQR_B5_GAIN - [10:6] */
3015
+
#define WM2200_EQR_B5_GAIN_SHIFT 6 /* EQR_B5_GAIN - [10:6] */
3016
+
#define WM2200_EQR_B5_GAIN_WIDTH 5 /* EQR_B5_GAIN - [10:6] */
3017
+
3018
+
/*
3019
+
* R2328 (0x918) - EQR_3
3020
+
*/
3021
+
#define WM2200_EQR_B1_A_MASK 0xFFFF /* EQR_B1_A - [15:0] */
3022
+
#define WM2200_EQR_B1_A_SHIFT 0 /* EQR_B1_A - [15:0] */
3023
+
#define WM2200_EQR_B1_A_WIDTH 16 /* EQR_B1_A - [15:0] */
3024
+
3025
+
/*
3026
+
* R2329 (0x919) - EQR_4
3027
+
*/
3028
+
#define WM2200_EQR_B1_B_MASK 0xFFFF /* EQR_B1_B - [15:0] */
3029
+
#define WM2200_EQR_B1_B_SHIFT 0 /* EQR_B1_B - [15:0] */
3030
+
#define WM2200_EQR_B1_B_WIDTH 16 /* EQR_B1_B - [15:0] */
3031
+
3032
+
/*
3033
+
* R2330 (0x91A) - EQR_5
3034
+
*/
3035
+
#define WM2200_EQR_B1_PG_MASK 0xFFFF /* EQR_B1_PG - [15:0] */
3036
+
#define WM2200_EQR_B1_PG_SHIFT 0 /* EQR_B1_PG - [15:0] */
3037
+
#define WM2200_EQR_B1_PG_WIDTH 16 /* EQR_B1_PG - [15:0] */
3038
+
3039
+
/*
3040
+
* R2331 (0x91B) - EQR_6
3041
+
*/
3042
+
#define WM2200_EQR_B2_A_MASK 0xFFFF /* EQR_B2_A - [15:0] */
3043
+
#define WM2200_EQR_B2_A_SHIFT 0 /* EQR_B2_A - [15:0] */
3044
+
#define WM2200_EQR_B2_A_WIDTH 16 /* EQR_B2_A - [15:0] */
3045
+
3046
+
/*
3047
+
* R2332 (0x91C) - EQR_7
3048
+
*/
3049
+
#define WM2200_EQR_B2_B_MASK 0xFFFF /* EQR_B2_B - [15:0] */
3050
+
#define WM2200_EQR_B2_B_SHIFT 0 /* EQR_B2_B - [15:0] */
3051
+
#define WM2200_EQR_B2_B_WIDTH 16 /* EQR_B2_B - [15:0] */
3052
+
3053
+
/*
3054
+
* R2333 (0x91D) - EQR_8
3055
+
*/
3056
+
#define WM2200_EQR_B2_C_MASK 0xFFFF /* EQR_B2_C - [15:0] */
3057
+
#define WM2200_EQR_B2_C_SHIFT 0 /* EQR_B2_C - [15:0] */
3058
+
#define WM2200_EQR_B2_C_WIDTH 16 /* EQR_B2_C - [15:0] */
3059
+
3060
+
/*
3061
+
* R2334 (0x91E) - EQR_9
3062
+
*/
3063
+
#define WM2200_EQR_B2_PG_MASK 0xFFFF /* EQR_B2_PG - [15:0] */
3064
+
#define WM2200_EQR_B2_PG_SHIFT 0 /* EQR_B2_PG - [15:0] */
3065
+
#define WM2200_EQR_B2_PG_WIDTH 16 /* EQR_B2_PG - [15:0] */
3066
+
3067
+
/*
3068
+
* R2335 (0x91F) - EQR_10
3069
+
*/
3070
+
#define WM2200_EQR_B3_A_MASK 0xFFFF /* EQR_B3_A - [15:0] */
3071
+
#define WM2200_EQR_B3_A_SHIFT 0 /* EQR_B3_A - [15:0] */
3072
+
#define WM2200_EQR_B3_A_WIDTH 16 /* EQR_B3_A - [15:0] */
3073
+
3074
+
/*
3075
+
* R2336 (0x920) - EQR_11
3076
+
*/
3077
+
#define WM2200_EQR_B3_B_MASK 0xFFFF /* EQR_B3_B - [15:0] */
3078
+
#define WM2200_EQR_B3_B_SHIFT 0 /* EQR_B3_B - [15:0] */
3079
+
#define WM2200_EQR_B3_B_WIDTH 16 /* EQR_B3_B - [15:0] */
3080
+
3081
+
/*
3082
+
* R2337 (0x921) - EQR_12
3083
+
*/
3084
+
#define WM2200_EQR_B3_C_MASK 0xFFFF /* EQR_B3_C - [15:0] */
3085
+
#define WM2200_EQR_B3_C_SHIFT 0 /* EQR_B3_C - [15:0] */
3086
+
#define WM2200_EQR_B3_C_WIDTH 16 /* EQR_B3_C - [15:0] */
3087
+
3088
+
/*
3089
+
* R2338 (0x922) - EQR_13
3090
+
*/
3091
+
#define WM2200_EQR_B3_PG_MASK 0xFFFF /* EQR_B3_PG - [15:0] */
3092
+
#define WM2200_EQR_B3_PG_SHIFT 0 /* EQR_B3_PG - [15:0] */
3093
+
#define WM2200_EQR_B3_PG_WIDTH 16 /* EQR_B3_PG - [15:0] */
3094
+
3095
+
/*
3096
+
* R2339 (0x923) - EQR_14
3097
+
*/
3098
+
#define WM2200_EQR_B4_A_MASK 0xFFFF /* EQR_B4_A - [15:0] */
3099
+
#define WM2200_EQR_B4_A_SHIFT 0 /* EQR_B4_A - [15:0] */
3100
+
#define WM2200_EQR_B4_A_WIDTH 16 /* EQR_B4_A - [15:0] */
3101
+
3102
+
/*
3103
+
* R2340 (0x924) - EQR_15
3104
+
*/
3105
+
#define WM2200_EQR_B4_B_MASK 0xFFFF /* EQR_B4_B - [15:0] */
3106
+
#define WM2200_EQR_B4_B_SHIFT 0 /* EQR_B4_B - [15:0] */
3107
+
#define WM2200_EQR_B4_B_WIDTH 16 /* EQR_B4_B - [15:0] */
3108
+
3109
+
/*
3110
+
* R2341 (0x925) - EQR_16
3111
+
*/
3112
+
#define WM2200_EQR_B4_C_MASK 0xFFFF /* EQR_B4_C - [15:0] */
3113
+
#define WM2200_EQR_B4_C_SHIFT 0 /* EQR_B4_C - [15:0] */
3114
+
#define WM2200_EQR_B4_C_WIDTH 16 /* EQR_B4_C - [15:0] */
3115
+
3116
+
/*
3117
+
* R2342 (0x926) - EQR_17
3118
+
*/
3119
+
#define WM2200_EQR_B4_PG_MASK 0xFFFF /* EQR_B4_PG - [15:0] */
3120
+
#define WM2200_EQR_B4_PG_SHIFT 0 /* EQR_B4_PG - [15:0] */
3121
+
#define WM2200_EQR_B4_PG_WIDTH 16 /* EQR_B4_PG - [15:0] */
3122
+
3123
+
/*
3124
+
* R2343 (0x927) - EQR_18
3125
+
*/
3126
+
#define WM2200_EQR_B5_A_MASK 0xFFFF /* EQR_B5_A - [15:0] */
3127
+
#define WM2200_EQR_B5_A_SHIFT 0 /* EQR_B5_A - [15:0] */
3128
+
#define WM2200_EQR_B5_A_WIDTH 16 /* EQR_B5_A - [15:0] */
3129
+
3130
+
/*
3131
+
* R2344 (0x928) - EQR_19
3132
+
*/
3133
+
#define WM2200_EQR_B5_B_MASK 0xFFFF /* EQR_B5_B - [15:0] */
3134
+
#define WM2200_EQR_B5_B_SHIFT 0 /* EQR_B5_B - [15:0] */
3135
+
#define WM2200_EQR_B5_B_WIDTH 16 /* EQR_B5_B - [15:0] */
3136
+
3137
+
/*
3138
+
* R2345 (0x929) - EQR_20
3139
+
*/
3140
+
#define WM2200_EQR_B5_PG_MASK 0xFFFF /* EQR_B5_PG - [15:0] */
3141
+
#define WM2200_EQR_B5_PG_SHIFT 0 /* EQR_B5_PG - [15:0] */
3142
+
#define WM2200_EQR_B5_PG_WIDTH 16 /* EQR_B5_PG - [15:0] */
3143
+
3144
+
/*
3145
+
* R2366 (0x93E) - HPLPF1_1
3146
+
*/
3147
+
#define WM2200_LHPF1_MODE 0x0002 /* LHPF1_MODE */
3148
+
#define WM2200_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
3149
+
#define WM2200_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
3150
+
#define WM2200_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
3151
+
#define WM2200_LHPF1_ENA 0x0001 /* LHPF1_ENA */
3152
+
#define WM2200_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
3153
+
#define WM2200_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
3154
+
#define WM2200_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
3155
+
3156
+
/*
3157
+
* R2367 (0x93F) - HPLPF1_2
3158
+
*/
3159
+
#define WM2200_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
3160
+
#define WM2200_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
3161
+
#define WM2200_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
3162
+
3163
+
/*
3164
+
* R2370 (0x942) - HPLPF2_1
3165
+
*/
3166
+
#define WM2200_LHPF2_MODE 0x0002 /* LHPF2_MODE */
3167
+
#define WM2200_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
3168
+
#define WM2200_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
3169
+
#define WM2200_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
3170
+
#define WM2200_LHPF2_ENA 0x0001 /* LHPF2_ENA */
3171
+
#define WM2200_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
3172
+
#define WM2200_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
3173
+
#define WM2200_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
3174
+
3175
+
/*
3176
+
* R2371 (0x943) - HPLPF2_2
3177
+
*/
3178
+
#define WM2200_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
3179
+
#define WM2200_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
3180
+
#define WM2200_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
3181
+
3182
+
/*
3183
+
* R2560 (0xA00) - DSP1 Control 1
3184
+
*/
3185
+
#define WM2200_DSP1_RW_SEQUENCE_ENA 0x0001 /* DSP1_RW_SEQUENCE_ENA */
3186
+
#define WM2200_DSP1_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP1_RW_SEQUENCE_ENA */
3187
+
#define WM2200_DSP1_RW_SEQUENCE_ENA_SHIFT 0 /* DSP1_RW_SEQUENCE_ENA */
3188
+
#define WM2200_DSP1_RW_SEQUENCE_ENA_WIDTH 1 /* DSP1_RW_SEQUENCE_ENA */
3189
+
3190
+
/*
3191
+
* R2562 (0xA02) - DSP1 Control 2
3192
+
*/
3193
+
#define WM2200_DSP1_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_PM - [15:8] */
3194
+
#define WM2200_DSP1_PAGE_BASE_PM_0_SHIFT 8 /* DSP1_PAGE_BASE_PM - [15:8] */
3195
+
#define WM2200_DSP1_PAGE_BASE_PM_0_WIDTH 8 /* DSP1_PAGE_BASE_PM - [15:8] */
3196
+
3197
+
/*
3198
+
* R2563 (0xA03) - DSP1 Control 3
3199
+
*/
3200
+
#define WM2200_DSP1_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_DM - [15:8] */
3201
+
#define WM2200_DSP1_PAGE_BASE_DM_0_SHIFT 8 /* DSP1_PAGE_BASE_DM - [15:8] */
3202
+
#define WM2200_DSP1_PAGE_BASE_DM_0_WIDTH 8 /* DSP1_PAGE_BASE_DM - [15:8] */
3203
+
3204
+
/*
3205
+
* R2564 (0xA04) - DSP1 Control 4
3206
+
*/
3207
+
#define WM2200_DSP1_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP1_PAGE_BASE_ZM - [15:8] */
3208
+
#define WM2200_DSP1_PAGE_BASE_ZM_0_SHIFT 8 /* DSP1_PAGE_BASE_ZM - [15:8] */
3209
+
#define WM2200_DSP1_PAGE_BASE_ZM_0_WIDTH 8 /* DSP1_PAGE_BASE_ZM - [15:8] */
3210
+
3211
+
/*
3212
+
* R2566 (0xA06) - DSP1 Control 5
3213
+
*/
3214
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3215
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3216
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3217
+
3218
+
/*
3219
+
* R2567 (0xA07) - DSP1 Control 6
3220
+
*/
3221
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3222
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3223
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3224
+
3225
+
/*
3226
+
* R2568 (0xA08) - DSP1 Control 7
3227
+
*/
3228
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3229
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3230
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3231
+
3232
+
/*
3233
+
* R2569 (0xA09) - DSP1 Control 8
3234
+
*/
3235
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3236
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3237
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3238
+
3239
+
/*
3240
+
* R2570 (0xA0A) - DSP1 Control 9
3241
+
*/
3242
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3243
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3244
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3245
+
3246
+
/*
3247
+
* R2571 (0xA0B) - DSP1 Control 10
3248
+
*/
3249
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3250
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3251
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3252
+
3253
+
/*
3254
+
* R2572 (0xA0C) - DSP1 Control 11
3255
+
*/
3256
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3257
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3258
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3259
+
3260
+
/*
3261
+
* R2573 (0xA0D) - DSP1 Control 12
3262
+
*/
3263
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3264
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3265
+
#define WM2200_DSP1_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP1_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3266
+
3267
+
/*
3268
+
* R2575 (0xA0F) - DSP1 Control 13
3269
+
*/
3270
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3271
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3272
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3273
+
3274
+
/*
3275
+
* R2576 (0xA10) - DSP1 Control 14
3276
+
*/
3277
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3278
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3279
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3280
+
3281
+
/*
3282
+
* R2577 (0xA11) - DSP1 Control 15
3283
+
*/
3284
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3285
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3286
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3287
+
3288
+
/*
3289
+
* R2578 (0xA12) - DSP1 Control 16
3290
+
*/
3291
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3292
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3293
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3294
+
3295
+
/*
3296
+
* R2579 (0xA13) - DSP1 Control 17
3297
+
*/
3298
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3299
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3300
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3301
+
3302
+
/*
3303
+
* R2580 (0xA14) - DSP1 Control 18
3304
+
*/
3305
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3306
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3307
+
#define WM2200_DSP1_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP1_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3308
+
3309
+
/*
3310
+
* R2582 (0xA16) - DSP1 Control 19
3311
+
*/
3312
+
#define WM2200_DSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3313
+
#define WM2200_DSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3314
+
#define WM2200_DSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
3315
+
3316
+
/*
3317
+
* R2583 (0xA17) - DSP1 Control 20
3318
+
*/
3319
+
#define WM2200_DSP1_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3320
+
#define WM2200_DSP1_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3321
+
#define WM2200_DSP1_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP1_WDMA_CHANNEL_ENABLE - [7:0] */
3322
+
3323
+
/*
3324
+
* R2584 (0xA18) - DSP1 Control 21
3325
+
*/
3326
+
#define WM2200_DSP1_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3327
+
#define WM2200_DSP1_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3328
+
#define WM2200_DSP1_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP1_RDMA_CHANNEL_ENABLE - [5:0] */
3329
+
3330
+
/*
3331
+
* R2586 (0xA1A) - DSP1 Control 22
3332
+
*/
3333
+
#define WM2200_DSP1_DM_SIZE_MASK 0xFFFF /* DSP1_DM_SIZE - [15:0] */
3334
+
#define WM2200_DSP1_DM_SIZE_SHIFT 0 /* DSP1_DM_SIZE - [15:0] */
3335
+
#define WM2200_DSP1_DM_SIZE_WIDTH 16 /* DSP1_DM_SIZE - [15:0] */
3336
+
3337
+
/*
3338
+
* R2587 (0xA1B) - DSP1 Control 23
3339
+
*/
3340
+
#define WM2200_DSP1_PM_SIZE_MASK 0xFFFF /* DSP1_PM_SIZE - [15:0] */
3341
+
#define WM2200_DSP1_PM_SIZE_SHIFT 0 /* DSP1_PM_SIZE - [15:0] */
3342
+
#define WM2200_DSP1_PM_SIZE_WIDTH 16 /* DSP1_PM_SIZE - [15:0] */
3343
+
3344
+
/*
3345
+
* R2588 (0xA1C) - DSP1 Control 24
3346
+
*/
3347
+
#define WM2200_DSP1_ZM_SIZE_MASK 0xFFFF /* DSP1_ZM_SIZE - [15:0] */
3348
+
#define WM2200_DSP1_ZM_SIZE_SHIFT 0 /* DSP1_ZM_SIZE - [15:0] */
3349
+
#define WM2200_DSP1_ZM_SIZE_WIDTH 16 /* DSP1_ZM_SIZE - [15:0] */
3350
+
3351
+
/*
3352
+
* R2590 (0xA1E) - DSP1 Control 25
3353
+
*/
3354
+
#define WM2200_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
3355
+
#define WM2200_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
3356
+
#define WM2200_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */
3357
+
#define WM2200_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */
3358
+
#define WM2200_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
3359
+
#define WM2200_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
3360
+
#define WM2200_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */
3361
+
#define WM2200_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */
3362
+
#define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3363
+
#define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3364
+
#define WM2200_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
3365
+
3366
+
/*
3367
+
* R2592 (0xA20) - DSP1 Control 26
3368
+
*/
3369
+
#define WM2200_DSP1_SCRATCH_0_MASK 0xFFFF /* DSP1_SCRATCH_0 - [15:0] */
3370
+
#define WM2200_DSP1_SCRATCH_0_SHIFT 0 /* DSP1_SCRATCH_0 - [15:0] */
3371
+
#define WM2200_DSP1_SCRATCH_0_WIDTH 16 /* DSP1_SCRATCH_0 - [15:0] */
3372
+
3373
+
/*
3374
+
* R2593 (0xA21) - DSP1 Control 27
3375
+
*/
3376
+
#define WM2200_DSP1_SCRATCH_1_MASK 0xFFFF /* DSP1_SCRATCH_1 - [15:0] */
3377
+
#define WM2200_DSP1_SCRATCH_1_SHIFT 0 /* DSP1_SCRATCH_1 - [15:0] */
3378
+
#define WM2200_DSP1_SCRATCH_1_WIDTH 16 /* DSP1_SCRATCH_1 - [15:0] */
3379
+
3380
+
/*
3381
+
* R2594 (0xA22) - DSP1 Control 28
3382
+
*/
3383
+
#define WM2200_DSP1_SCRATCH_2_MASK 0xFFFF /* DSP1_SCRATCH_2 - [15:0] */
3384
+
#define WM2200_DSP1_SCRATCH_2_SHIFT 0 /* DSP1_SCRATCH_2 - [15:0] */
3385
+
#define WM2200_DSP1_SCRATCH_2_WIDTH 16 /* DSP1_SCRATCH_2 - [15:0] */
3386
+
3387
+
/*
3388
+
* R2595 (0xA23) - DSP1 Control 29
3389
+
*/
3390
+
#define WM2200_DSP1_SCRATCH_3_MASK 0xFFFF /* DSP1_SCRATCH_3 - [15:0] */
3391
+
#define WM2200_DSP1_SCRATCH_3_SHIFT 0 /* DSP1_SCRATCH_3 - [15:0] */
3392
+
#define WM2200_DSP1_SCRATCH_3_WIDTH 16 /* DSP1_SCRATCH_3 - [15:0] */
3393
+
3394
+
/*
3395
+
* R2596 (0xA24) - DSP1 Control 30
3396
+
*/
3397
+
#define WM2200_DSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
3398
+
#define WM2200_DSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
3399
+
#define WM2200_DSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
3400
+
#define WM2200_DSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
3401
+
#define WM2200_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
3402
+
#define WM2200_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
3403
+
#define WM2200_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
3404
+
#define WM2200_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
3405
+
#define WM2200_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
3406
+
#define WM2200_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
3407
+
#define WM2200_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
3408
+
#define WM2200_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
3409
+
#define WM2200_DSP1_START 0x0001 /* DSP1_START */
3410
+
#define WM2200_DSP1_START_MASK 0x0001 /* DSP1_START */
3411
+
#define WM2200_DSP1_START_SHIFT 0 /* DSP1_START */
3412
+
#define WM2200_DSP1_START_WIDTH 1 /* DSP1_START */
3413
+
3414
+
/*
3415
+
* R2598 (0xA26) - DSP1 Control 31
3416
+
*/
3417
+
#define WM2200_DSP1_CLK_RATE_MASK 0x0018 /* DSP1_CLK_RATE - [4:3] */
3418
+
#define WM2200_DSP1_CLK_RATE_SHIFT 3 /* DSP1_CLK_RATE - [4:3] */
3419
+
#define WM2200_DSP1_CLK_RATE_WIDTH 2 /* DSP1_CLK_RATE - [4:3] */
3420
+
#define WM2200_DSP1_CLK_AVAIL 0x0004 /* DSP1_CLK_AVAIL */
3421
+
#define WM2200_DSP1_CLK_AVAIL_MASK 0x0004 /* DSP1_CLK_AVAIL */
3422
+
#define WM2200_DSP1_CLK_AVAIL_SHIFT 2 /* DSP1_CLK_AVAIL */
3423
+
#define WM2200_DSP1_CLK_AVAIL_WIDTH 1 /* DSP1_CLK_AVAIL */
3424
+
#define WM2200_DSP1_CLK_REQ_MASK 0x0003 /* DSP1_CLK_REQ - [1:0] */
3425
+
#define WM2200_DSP1_CLK_REQ_SHIFT 0 /* DSP1_CLK_REQ - [1:0] */
3426
+
#define WM2200_DSP1_CLK_REQ_WIDTH 2 /* DSP1_CLK_REQ - [1:0] */
3427
+
3428
+
/*
3429
+
* R2816 (0xB00) - DSP2 Control 1
3430
+
*/
3431
+
#define WM2200_DSP2_RW_SEQUENCE_ENA 0x0001 /* DSP2_RW_SEQUENCE_ENA */
3432
+
#define WM2200_DSP2_RW_SEQUENCE_ENA_MASK 0x0001 /* DSP2_RW_SEQUENCE_ENA */
3433
+
#define WM2200_DSP2_RW_SEQUENCE_ENA_SHIFT 0 /* DSP2_RW_SEQUENCE_ENA */
3434
+
#define WM2200_DSP2_RW_SEQUENCE_ENA_WIDTH 1 /* DSP2_RW_SEQUENCE_ENA */
3435
+
3436
+
/*
3437
+
* R2818 (0xB02) - DSP2 Control 2
3438
+
*/
3439
+
#define WM2200_DSP2_PAGE_BASE_PM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_PM - [15:8] */
3440
+
#define WM2200_DSP2_PAGE_BASE_PM_0_SHIFT 8 /* DSP2_PAGE_BASE_PM - [15:8] */
3441
+
#define WM2200_DSP2_PAGE_BASE_PM_0_WIDTH 8 /* DSP2_PAGE_BASE_PM - [15:8] */
3442
+
3443
+
/*
3444
+
* R2819 (0xB03) - DSP2 Control 3
3445
+
*/
3446
+
#define WM2200_DSP2_PAGE_BASE_DM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_DM - [15:8] */
3447
+
#define WM2200_DSP2_PAGE_BASE_DM_0_SHIFT 8 /* DSP2_PAGE_BASE_DM - [15:8] */
3448
+
#define WM2200_DSP2_PAGE_BASE_DM_0_WIDTH 8 /* DSP2_PAGE_BASE_DM - [15:8] */
3449
+
3450
+
/*
3451
+
* R2820 (0xB04) - DSP2 Control 4
3452
+
*/
3453
+
#define WM2200_DSP2_PAGE_BASE_ZM_0_MASK 0xFF00 /* DSP2_PAGE_BASE_ZM - [15:8] */
3454
+
#define WM2200_DSP2_PAGE_BASE_ZM_0_SHIFT 8 /* DSP2_PAGE_BASE_ZM - [15:8] */
3455
+
#define WM2200_DSP2_PAGE_BASE_ZM_0_WIDTH 8 /* DSP2_PAGE_BASE_ZM - [15:8] */
3456
+
3457
+
/*
3458
+
* R2822 (0xB06) - DSP2 Control 5
3459
+
*/
3460
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3461
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3462
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_0 - [13:0] */
3463
+
3464
+
/*
3465
+
* R2823 (0xB07) - DSP2 Control 6
3466
+
*/
3467
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3468
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3469
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_1 - [13:0] */
3470
+
3471
+
/*
3472
+
* R2824 (0xB08) - DSP2 Control 7
3473
+
*/
3474
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3475
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3476
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_2 - [13:0] */
3477
+
3478
+
/*
3479
+
* R2825 (0xB09) - DSP2 Control 8
3480
+
*/
3481
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3482
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3483
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_3 - [13:0] */
3484
+
3485
+
/*
3486
+
* R2826 (0xB0A) - DSP2 Control 9
3487
+
*/
3488
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3489
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3490
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_4 - [13:0] */
3491
+
3492
+
/*
3493
+
* R2827 (0xB0B) - DSP2 Control 10
3494
+
*/
3495
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3496
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3497
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_5 - [13:0] */
3498
+
3499
+
/*
3500
+
* R2828 (0xB0C) - DSP2 Control 11
3501
+
*/
3502
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3503
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3504
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_6_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_6 - [13:0] */
3505
+
3506
+
/*
3507
+
* R2829 (0xB0D) - DSP2 Control 12
3508
+
*/
3509
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_MASK 0x3FFF /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3510
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_SHIFT 0 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3511
+
#define WM2200_DSP2_START_ADDRESS_WDMA_BUFFER_7_WIDTH 14 /* DSP2_START_ADDRESS_WDMA_BUFFER_7 - [13:0] */
3512
+
3513
+
/*
3514
+
* R2831 (0xB0F) - DSP2 Control 13
3515
+
*/
3516
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3517
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3518
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_0_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_0 - [13:0] */
3519
+
3520
+
/*
3521
+
* R2832 (0xB10) - DSP2 Control 14
3522
+
*/
3523
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3524
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3525
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_1_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_1 - [13:0] */
3526
+
3527
+
/*
3528
+
* R2833 (0xB11) - DSP2 Control 15
3529
+
*/
3530
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3531
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3532
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_2_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_2 - [13:0] */
3533
+
3534
+
/*
3535
+
* R2834 (0xB12) - DSP2 Control 16
3536
+
*/
3537
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3538
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3539
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_3_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_3 - [13:0] */
3540
+
3541
+
/*
3542
+
* R2835 (0xB13) - DSP2 Control 17
3543
+
*/
3544
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3545
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3546
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_4_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_4 - [13:0] */
3547
+
3548
+
/*
3549
+
* R2836 (0xB14) - DSP2 Control 18
3550
+
*/
3551
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_MASK 0x3FFF /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3552
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_SHIFT 0 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3553
+
#define WM2200_DSP2_START_ADDRESS_RDMA_BUFFER_5_WIDTH 14 /* DSP2_START_ADDRESS_RDMA_BUFFER_5 - [13:0] */
3554
+
3555
+
/*
3556
+
* R2838 (0xB16) - DSP2 Control 19
3557
+
*/
3558
+
#define WM2200_DSP2_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3559
+
#define WM2200_DSP2_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3560
+
#define WM2200_DSP2_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP2_WDMA_BUFFER_LENGTH - [7:0] */
3561
+
3562
+
/*
3563
+
* R2839 (0xB17) - DSP2 Control 20
3564
+
*/
3565
+
#define WM2200_DSP2_WDMA_CHANNEL_ENABLE_MASK 0x00FF /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3566
+
#define WM2200_DSP2_WDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3567
+
#define WM2200_DSP2_WDMA_CHANNEL_ENABLE_WIDTH 8 /* DSP2_WDMA_CHANNEL_ENABLE - [7:0] */
3568
+
3569
+
/*
3570
+
* R2840 (0xB18) - DSP2 Control 21
3571
+
*/
3572
+
#define WM2200_DSP2_RDMA_CHANNEL_ENABLE_MASK 0x003F /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3573
+
#define WM2200_DSP2_RDMA_CHANNEL_ENABLE_SHIFT 0 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3574
+
#define WM2200_DSP2_RDMA_CHANNEL_ENABLE_WIDTH 6 /* DSP2_RDMA_CHANNEL_ENABLE - [5:0] */
3575
+
3576
+
/*
3577
+
* R2842 (0xB1A) - DSP2 Control 22
3578
+
*/
3579
+
#define WM2200_DSP2_DM_SIZE_MASK 0xFFFF /* DSP2_DM_SIZE - [15:0] */
3580
+
#define WM2200_DSP2_DM_SIZE_SHIFT 0 /* DSP2_DM_SIZE - [15:0] */
3581
+
#define WM2200_DSP2_DM_SIZE_WIDTH 16 /* DSP2_DM_SIZE - [15:0] */
3582
+
3583
+
/*
3584
+
* R2843 (0xB1B) - DSP2 Control 23
3585
+
*/
3586
+
#define WM2200_DSP2_PM_SIZE_MASK 0xFFFF /* DSP2_PM_SIZE - [15:0] */
3587
+
#define WM2200_DSP2_PM_SIZE_SHIFT 0 /* DSP2_PM_SIZE - [15:0] */
3588
+
#define WM2200_DSP2_PM_SIZE_WIDTH 16 /* DSP2_PM_SIZE - [15:0] */
3589
+
3590
+
/*
3591
+
* R2844 (0xB1C) - DSP2 Control 24
3592
+
*/
3593
+
#define WM2200_DSP2_ZM_SIZE_MASK 0xFFFF /* DSP2_ZM_SIZE - [15:0] */
3594
+
#define WM2200_DSP2_ZM_SIZE_SHIFT 0 /* DSP2_ZM_SIZE - [15:0] */
3595
+
#define WM2200_DSP2_ZM_SIZE_WIDTH 16 /* DSP2_ZM_SIZE - [15:0] */
3596
+
3597
+
/*
3598
+
* R2846 (0xB1E) - DSP2 Control 25
3599
+
*/
3600
+
#define WM2200_DSP2_PING_FULL 0x8000 /* DSP2_PING_FULL */
3601
+
#define WM2200_DSP2_PING_FULL_MASK 0x8000 /* DSP2_PING_FULL */
3602
+
#define WM2200_DSP2_PING_FULL_SHIFT 15 /* DSP2_PING_FULL */
3603
+
#define WM2200_DSP2_PING_FULL_WIDTH 1 /* DSP2_PING_FULL */
3604
+
#define WM2200_DSP2_PONG_FULL 0x4000 /* DSP2_PONG_FULL */
3605
+
#define WM2200_DSP2_PONG_FULL_MASK 0x4000 /* DSP2_PONG_FULL */
3606
+
#define WM2200_DSP2_PONG_FULL_SHIFT 14 /* DSP2_PONG_FULL */
3607
+
#define WM2200_DSP2_PONG_FULL_WIDTH 1 /* DSP2_PONG_FULL */
3608
+
#define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3609
+
#define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3610
+
#define WM2200_DSP2_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP2_WDMA_ACTIVE_CHANNELS - [7:0] */
3611
+
3612
+
/*
3613
+
* R2848 (0xB20) - DSP2 Control 26
3614
+
*/
3615
+
#define WM2200_DSP2_SCRATCH_0_MASK 0xFFFF /* DSP2_SCRATCH_0 - [15:0] */
3616
+
#define WM2200_DSP2_SCRATCH_0_SHIFT 0 /* DSP2_SCRATCH_0 - [15:0] */
3617
+
#define WM2200_DSP2_SCRATCH_0_WIDTH 16 /* DSP2_SCRATCH_0 - [15:0] */
3618
+
3619
+
/*
3620
+
* R2849 (0xB21) - DSP2 Control 27
3621
+
*/
3622
+
#define WM2200_DSP2_SCRATCH_1_MASK 0xFFFF /* DSP2_SCRATCH_1 - [15:0] */
3623
+
#define WM2200_DSP2_SCRATCH_1_SHIFT 0 /* DSP2_SCRATCH_1 - [15:0] */
3624
+
#define WM2200_DSP2_SCRATCH_1_WIDTH 16 /* DSP2_SCRATCH_1 - [15:0] */
3625
+
3626
+
/*
3627
+
* R2850 (0xB22) - DSP2 Control 28
3628
+
*/
3629
+
#define WM2200_DSP2_SCRATCH_2_MASK 0xFFFF /* DSP2_SCRATCH_2 - [15:0] */
3630
+
#define WM2200_DSP2_SCRATCH_2_SHIFT 0 /* DSP2_SCRATCH_2 - [15:0] */
3631
+
#define WM2200_DSP2_SCRATCH_2_WIDTH 16 /* DSP2_SCRATCH_2 - [15:0] */
3632
+
3633
+
/*
3634
+
* R2851 (0xB23) - DSP2 Control 29
3635
+
*/
3636
+
#define WM2200_DSP2_SCRATCH_3_MASK 0xFFFF /* DSP2_SCRATCH_3 - [15:0] */
3637
+
#define WM2200_DSP2_SCRATCH_3_SHIFT 0 /* DSP2_SCRATCH_3 - [15:0] */
3638
+
#define WM2200_DSP2_SCRATCH_3_WIDTH 16 /* DSP2_SCRATCH_3 - [15:0] */
3639
+
3640
+
/*
3641
+
* R2852 (0xB24) - DSP2 Control 30
3642
+
*/
3643
+
#define WM2200_DSP2_DBG_CLK_ENA 0x0008 /* DSP2_DBG_CLK_ENA */
3644
+
#define WM2200_DSP2_DBG_CLK_ENA_MASK 0x0008 /* DSP2_DBG_CLK_ENA */
3645
+
#define WM2200_DSP2_DBG_CLK_ENA_SHIFT 3 /* DSP2_DBG_CLK_ENA */
3646
+
#define WM2200_DSP2_DBG_CLK_ENA_WIDTH 1 /* DSP2_DBG_CLK_ENA */
3647
+
#define WM2200_DSP2_SYS_ENA 0x0004 /* DSP2_SYS_ENA */
3648
+
#define WM2200_DSP2_SYS_ENA_MASK 0x0004 /* DSP2_SYS_ENA */
3649
+
#define WM2200_DSP2_SYS_ENA_SHIFT 2 /* DSP2_SYS_ENA */
3650
+
#define WM2200_DSP2_SYS_ENA_WIDTH 1 /* DSP2_SYS_ENA */
3651
+
#define WM2200_DSP2_CORE_ENA 0x0002 /* DSP2_CORE_ENA */
3652
+
#define WM2200_DSP2_CORE_ENA_MASK 0x0002 /* DSP2_CORE_ENA */
3653
+
#define WM2200_DSP2_CORE_ENA_SHIFT 1 /* DSP2_CORE_ENA */
3654
+
#define WM2200_DSP2_CORE_ENA_WIDTH 1 /* DSP2_CORE_ENA */
3655
+
#define WM2200_DSP2_START 0x0001 /* DSP2_START */
3656
+
#define WM2200_DSP2_START_MASK 0x0001 /* DSP2_START */
3657
+
#define WM2200_DSP2_START_SHIFT 0 /* DSP2_START */
3658
+
#define WM2200_DSP2_START_WIDTH 1 /* DSP2_START */
3659
+
3660
+
/*
3661
+
* R2854 (0xB26) - DSP2 Control 31
3662
+
*/
3663
+
#define WM2200_DSP2_CLK_RATE_MASK 0x0018 /* DSP2_CLK_RATE - [4:3] */
3664
+
#define WM2200_DSP2_CLK_RATE_SHIFT 3 /* DSP2_CLK_RATE - [4:3] */
3665
+
#define WM2200_DSP2_CLK_RATE_WIDTH 2 /* DSP2_CLK_RATE - [4:3] */
3666
+
#define WM2200_DSP2_CLK_AVAIL 0x0004 /* DSP2_CLK_AVAIL */
3667
+
#define WM2200_DSP2_CLK_AVAIL_MASK 0x0004 /* DSP2_CLK_AVAIL */
3668
+
#define WM2200_DSP2_CLK_AVAIL_SHIFT 2 /* DSP2_CLK_AVAIL */
3669
+
#define WM2200_DSP2_CLK_AVAIL_WIDTH 1 /* DSP2_CLK_AVAIL */
3670
+
#define WM2200_DSP2_CLK_REQ_MASK 0x0003 /* DSP2_CLK_REQ - [1:0] */
3671
+
#define WM2200_DSP2_CLK_REQ_SHIFT 0 /* DSP2_CLK_REQ - [1:0] */
3672
+
#define WM2200_DSP2_CLK_REQ_WIDTH 2 /* DSP2_CLK_REQ - [1:0] */
3673
+
3674
+
#endif