drm/amdgpu: add xcc index argument to select_sh_se function v2

tjh.dev / kernel

fork atom

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

fork atom

drm/amdgpu: add xcc index argument to select_sh_se function v2

v1: To support multiple XCD case (Le)
v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking)

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Le Ma and committed by

Alex Deucher 3 years ago d51ac6d0 ec08571a

+110 -106

18 changed files

expand all collapse all

drivers

gpu

drm

amd

amdgpu

amdgpu_amdkfd_gfx_v9.c

amdgpu_debugfs.c

amdgpu_gfx.h

cik.c

gfx_v10_0.c

gfx_v11_0.c

gfx_v6_0.c

gfx_v7_0.c

gfx_v8_0.c

gfx_v9_0.c

gfx_v9_0.h

gfx_v9_4_2.c

gfx_v9_4_3.c

nv.c

si.c

soc15.c

soc21.c

vi.c

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

reviewed

··· 787 787 for (se_idx = 0; se_idx < se_cnt; se_idx++) { 788 788 for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) { 789 789 790 790 - amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff); 790 790 + amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff, 0); 791 791 queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS); 792 792 793 793 /* ··· 820 820 } 821 821 } 822 822 823 823 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 823 823 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 824 824 soc15_grbm_select(adev, 0, 0, 0, 0, 0); 825 825 unlock_spi_csq_mutexes(adev); 826 826

+8 -8

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

reviewed

··· 136 136 } 137 137 mutex_lock(&adev->grbm_idx_mutex); 138 138 amdgpu_gfx_select_se_sh(adev, se_bank, 139 139 - sh_bank, instance_bank); 139 139 + sh_bank, instance_bank, 0); 140 140 } else if (use_ring) { 141 141 mutex_lock(&adev->srbm_mutex); 142 142 amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue, vmid); ··· 169 169 170 170 end: 171 171 if (use_bank) { 172 172 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 172 172 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 173 173 mutex_unlock(&adev->grbm_idx_mutex); 174 174 } else if (use_ring) { 175 175 amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0, 0); ··· 263 263 mutex_lock(&adev->grbm_idx_mutex); 264 264 amdgpu_gfx_select_se_sh(adev, rd->id.grbm.se, 265 265 rd->id.grbm.sh, 266 266 - rd->id.grbm.instance); 266 266 + rd->id.grbm.instance, 0); 267 267 } 268 268 269 269 if (rd->id.use_srbm) { ··· 295 295 } 296 296 end: 297 297 if (rd->id.use_grbm) { 298 298 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 298 298 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 299 299 mutex_unlock(&adev->grbm_idx_mutex); 300 300 } 301 301 ··· 907 907 908 908 /* switch to the specific se/sh/cu */ 909 909 mutex_lock(&adev->grbm_idx_mutex); 910 910 - amdgpu_gfx_select_se_sh(adev, se, sh, cu); 910 910 + amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0); 911 911 912 912 x = 0; 913 913 if (adev->gfx.funcs->read_wave_data) 914 914 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x); 915 915 916 916 - amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 916 916 + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0); 917 917 mutex_unlock(&adev->grbm_idx_mutex); 918 918 919 919 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev); ··· 1001 1001 1002 1002 /* switch to the specific se/sh/cu */ 1003 1003 mutex_lock(&adev->grbm_idx_mutex); 1004 1004 - amdgpu_gfx_select_se_sh(adev, se, sh, cu); 1004 1004 + amdgpu_gfx_select_se_sh(adev, se, sh, cu, 0); 1005 1005 1006 1006 if (bank == 0) { 1007 1007 if (adev->gfx.funcs->read_wave_vgprs) ··· 1011 1011 adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data); 1012 1012 } 1013 1013 1014 1014 - amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF); 1014 1014 + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0); 1015 1015 mutex_unlock(&adev->grbm_idx_mutex); 1016 1016 1017 1017 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);

+2 -2

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

reviewed

··· 237 237 /* get the gpu clock counter */ 238 238 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 239 239 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, 240 240 - u32 sh_num, u32 instance); 240 240 + u32 sh_num, u32 instance, int xcc_id); 241 241 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, 242 242 uint32_t wave, uint32_t *dst, int *no_fields); 243 243 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, ··· 386 386 }; 387 387 388 388 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 389 389 - #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 389 389 + #define amdgpu_gfx_select_se_sh(adev, se, sh, instance, xcc_id) ((adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance), (xcc_id))) 390 390 #define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q, vmid) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q), (vmid)) 391 391 #define amdgpu_gfx_init_spm_golden(adev) (adev)->gfx.funcs->init_spm_golden((adev)) 392 392

+2 -2

drivers/gpu/drm/amd/amdgpu/cik.c

reviewed

··· 1141 1141 1142 1142 mutex_lock(&adev->grbm_idx_mutex); 1143 1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1144 1144 - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1144 1144 + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 1145 1145 1146 1146 val = RREG32(reg_offset); 1147 1147 1148 1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1149 1149 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1149 1149 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1150 1150 mutex_unlock(&adev->grbm_idx_mutex); 1151 1151 return val; 1152 1152 } else {

+8 -8

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

reviewed

··· 3490 3490 struct amdgpu_cu_info *cu_info); 3491 3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3492 3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3493 3493 - u32 sh_num, u32 instance); 3493 3493 + u32 sh_num, u32 instance, int xcc_id); 3494 3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3495 3495 3496 3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); ··· 4712 4712 } 4713 4713 4714 4714 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4715 4715 - u32 sh_num, u32 instance) 4715 4715 + u32 sh_num, u32 instance, int xcc_id) 4716 4716 { 4717 4717 u32 data; 4718 4718 ··· 4772 4772 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4773 4773 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4774 4774 continue; 4775 4775 - gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4775 4775 + gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4776 4776 data = gfx_v10_0_get_rb_active_bitmap(adev); 4777 4777 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4778 4778 rb_bitmap_width_per_sh); 4779 4779 } 4780 4780 } 4781 4781 - gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4781 4781 + gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4782 4782 mutex_unlock(&adev->grbm_idx_mutex); 4783 4783 4784 4784 adev->gfx.config.backend_enable_mask = active_rbs; ··· 4907 4907 mutex_lock(&adev->grbm_idx_mutex); 4908 4908 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4909 4909 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4910 4910 - gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4910 4910 + gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 4911 4911 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4912 4912 /* 4913 4913 * Set corresponding TCP bits for the inactive WGPs in ··· 4940 4940 } 4941 4941 } 4942 4942 4943 4943 - gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4943 4943 + gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 4944 4944 mutex_unlock(&adev->grbm_idx_mutex); 4945 4945 } 4946 4946 ··· 9540 9540 mask = 1; 9541 9541 ao_bitmap = 0; 9542 9542 counter = 0; 9543 9543 - gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9543 9543 + gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff, 0); 9544 9544 if (i < 4 && j < 2) 9545 9545 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9546 9546 adev, disable_masks[i * 2 + j]); ··· 9561 9561 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9562 9562 } 9563 9563 } 9564 9564 - gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9564 9564 + gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 9565 9565 mutex_unlock(&adev->grbm_idx_mutex); 9566 9566 9567 9567 cu_info->number = active_cu_number;

+4 -4

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

reviewed

··· 112 112 struct amdgpu_cu_info *cu_info); 113 113 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev); 114 114 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 115 115 - u32 sh_num, u32 instance); 115 115 + u32 sh_num, u32 instance, int xcc_id); 116 116 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 117 117 118 118 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); ··· 1484 1484 } 1485 1485 1486 1486 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1487 1487 - u32 sh_num, u32 instance) 1487 1487 + u32 sh_num, u32 instance, int xcc_id) 1488 1488 { 1489 1489 u32 data; 1490 1490 ··· 6473 6473 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 6474 6474 mask = 1; 6475 6475 counter = 0; 6476 6476 - gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); 6476 6476 + gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0); 6477 6477 if (i < 8 && j < 2) 6478 6478 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh( 6479 6479 adev, disable_masks[i * 2 + j]); ··· 6505 6505 active_cu_number += counter; 6506 6506 } 6507 6507 } 6508 6508 - gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6508 6508 + gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6509 6509 mutex_unlock(&adev->grbm_idx_mutex); 6510 6510 6511 6511 cu_info->number = active_cu_number;

+12 -12

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

reviewed

··· 1285 1285 } 1286 1286 1287 1287 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1288 1288 - u32 sh_num, u32 instance) 1288 1288 + u32 sh_num, u32 instance, int xcc_id) 1289 1289 { 1290 1290 u32 data; 1291 1291 ··· 1438 1438 } 1439 1439 1440 1440 /* GRBM_GFX_INDEX has a different offset on SI */ 1441 1441 - gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1441 1441 + gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1442 1442 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1443 1443 } 1444 1444 1445 1445 /* GRBM_GFX_INDEX has a different offset on SI */ 1446 1446 - gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1446 1446 + gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1447 1447 } 1448 1448 1449 1449 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev) ··· 1459 1459 mutex_lock(&adev->grbm_idx_mutex); 1460 1460 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1461 1461 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1462 1462 - gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1462 1462 + gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1463 1463 data = gfx_v6_0_get_rb_active_bitmap(adev); 1464 1464 active_rbs |= data << 1465 1465 ((i * adev->gfx.config.max_sh_per_se + j) * 1466 1466 rb_bitmap_width_per_sh); 1467 1467 } 1468 1468 } 1469 1469 - gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1469 1469 + gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1470 1470 1471 1471 adev->gfx.config.backend_enable_mask = active_rbs; 1472 1472 adev->gfx.config.num_rbs = hweight32(active_rbs); ··· 1487 1487 /* cache the values for userspace */ 1488 1488 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1489 1489 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1490 1490 - gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1490 1490 + gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1491 1491 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1492 1492 RREG32(mmCC_RB_BACKEND_DISABLE); 1493 1493 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = ··· 1496 1496 RREG32(mmPA_SC_RASTER_CONFIG); 1497 1497 } 1498 1498 } 1499 1499 - gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1499 1499 + gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1500 1500 mutex_unlock(&adev->grbm_idx_mutex); 1501 1501 } 1502 1502 ··· 1535 1535 mutex_lock(&adev->grbm_idx_mutex); 1536 1536 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1537 1537 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1538 1538 - gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 1538 1538 + gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1539 1539 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3); 1540 1540 active_cu = gfx_v6_0_get_cu_enabled(adev); 1541 1541 ··· 1550 1550 } 1551 1551 } 1552 1552 } 1553 1553 - gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1553 1553 + gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1554 1554 mutex_unlock(&adev->grbm_idx_mutex); 1555 1555 } 1556 1556 ··· 2391 2391 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); 2392 2392 2393 2393 if (!enable) { 2394 2394 - gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2394 2394 + gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2395 2395 WREG32(mmSPI_LB_CU_MASK, 0x00ff); 2396 2396 } 2397 2397 } ··· 3571 3571 mask = 1; 3572 3572 ao_bitmap = 0; 3573 3573 counter = 0; 3574 3574 - gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff); 3574 3574 + gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3575 3575 if (i < 4 && j < 2) 3576 3576 gfx_v6_0_set_user_cu_inactive_bitmap( 3577 3577 adev, disable_masks[i * 2 + j]); ··· 3593 3593 } 3594 3594 } 3595 3595 3596 3596 - gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3596 3596 + gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3597 3597 mutex_unlock(&adev->grbm_idx_mutex); 3598 3598 3599 3599 cu_info->number = active_cu_number;

+17 -16

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

reviewed

··· 1552 1552 * Select which SE, SH combinations to address. 1553 1553 */ 1554 1554 static void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, 1555 1555 - u32 se_num, u32 sh_num, u32 instance) 1555 1555 + u32 se_num, u32 sh_num, u32 instance, 1556 1556 + int xcc_id) 1556 1557 { 1557 1558 u32 data; 1558 1559 ··· 1733 1732 } 1734 1733 1735 1734 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1736 1736 - gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 1735 1735 + gfx_v7_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 1737 1736 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 1738 1737 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 1739 1738 } 1740 1739 1741 1740 /* GRBM_GFX_INDEX has a different offset on CI+ */ 1742 1742 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1741 1741 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1743 1742 } 1744 1743 1745 1744 /** ··· 1762 1761 mutex_lock(&adev->grbm_idx_mutex); 1763 1762 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1764 1763 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1765 1765 - gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1764 1764 + gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1766 1765 data = gfx_v7_0_get_rb_active_bitmap(adev); 1767 1766 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1768 1767 rb_bitmap_width_per_sh); 1769 1768 } 1770 1769 } 1771 1771 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1770 1770 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1772 1771 1773 1772 adev->gfx.config.backend_enable_mask = active_rbs; 1774 1773 adev->gfx.config.num_rbs = hweight32(active_rbs); ··· 1791 1790 /* cache the values for userspace */ 1792 1791 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1793 1792 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1794 1794 - gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 1793 1793 + gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 1795 1794 adev->gfx.config.rb_config[i][j].rb_backend_disable = 1796 1795 RREG32(mmCC_RB_BACKEND_DISABLE); 1797 1796 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = ··· 1802 1801 RREG32(mmPA_SC_RASTER_CONFIG_1); 1803 1802 } 1804 1803 } 1805 1805 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1804 1804 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1806 1805 mutex_unlock(&adev->grbm_idx_mutex); 1807 1806 } 1808 1807 ··· 1912 1911 * making sure that the following register writes will be broadcasted 1913 1912 * to all the shaders 1914 1913 */ 1915 1915 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1914 1914 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1916 1915 1917 1916 /* XXX SH_MEM regs */ 1918 1917 /* where to put LDS, scratch, GPUVM in FSA64 space */ ··· 3302 3301 mutex_lock(&adev->grbm_idx_mutex); 3303 3302 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3304 3303 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3305 3305 - gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 3304 3304 + gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3306 3305 for (k = 0; k < adev->usec_timeout; k++) { 3307 3306 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3308 3307 break; ··· 3310 3309 } 3311 3310 } 3312 3311 } 3313 3313 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3312 3312 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3314 3313 mutex_unlock(&adev->grbm_idx_mutex); 3315 3314 3316 3315 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | ··· 3475 3474 WREG32(mmRLC_LB_CNTR_MAX, 0x00008000); 3476 3475 3477 3476 mutex_lock(&adev->grbm_idx_mutex); 3478 3478 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3477 3477 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3479 3478 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff); 3480 3479 WREG32(mmRLC_LB_PARAMS, 0x00600408); 3481 3480 WREG32(mmRLC_LB_CNTL, 0x80000004); ··· 3531 3530 tmp = gfx_v7_0_halt_rlc(adev); 3532 3531 3533 3532 mutex_lock(&adev->grbm_idx_mutex); 3534 3534 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3533 3533 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3535 3534 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3536 3535 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3537 3536 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | ··· 3585 3584 tmp = gfx_v7_0_halt_rlc(adev); 3586 3585 3587 3586 mutex_lock(&adev->grbm_idx_mutex); 3588 3588 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3587 3587 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3589 3588 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3590 3589 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3591 3590 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | ··· 3636 3635 tmp = gfx_v7_0_halt_rlc(adev); 3637 3636 3638 3637 mutex_lock(&adev->grbm_idx_mutex); 3639 3639 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3638 3638 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3640 3639 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 3641 3640 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); 3642 3641 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK; ··· 5116 5115 mask = 1; 5117 5116 ao_bitmap = 0; 5118 5117 counter = 0; 5119 5119 - gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff); 5118 5118 + gfx_v7_0_select_se_sh(adev, i, j, 0xffffffff, 0); 5120 5119 if (i < 4 && j < 2) 5121 5120 gfx_v7_0_set_user_cu_inactive_bitmap( 5122 5121 adev, disable_masks[i * 2 + j]); ··· 5137 5136 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5138 5137 } 5139 5138 } 5140 5140 - gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5139 5139 + gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5141 5140 mutex_unlock(&adev->grbm_idx_mutex); 5142 5141 5143 5142 cu_info->number = active_cu_number;

+17 -16

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

reviewed

··· 3395 3395 } 3396 3396 3397 3397 static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, 3398 3398 - u32 se_num, u32 sh_num, u32 instance) 3398 3398 + u32 se_num, u32 sh_num, u32 instance, 3399 3399 + int xcc_id) 3399 3400 { 3400 3401 u32 data; 3401 3402 ··· 3580 3579 } 3581 3580 3582 3581 /* GRBM_GFX_INDEX has a different offset on VI */ 3583 3583 - gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); 3582 3582 + gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0); 3584 3583 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se); 3585 3584 WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1); 3586 3585 } 3587 3586 3588 3587 /* GRBM_GFX_INDEX has a different offset on VI */ 3589 3589 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3588 3588 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3590 3589 } 3591 3590 3592 3591 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) ··· 3602 3601 mutex_lock(&adev->grbm_idx_mutex); 3603 3602 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3604 3603 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3605 3605 - gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 3604 3604 + gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3606 3605 data = gfx_v8_0_get_rb_active_bitmap(adev); 3607 3606 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 3608 3607 rb_bitmap_width_per_sh); 3609 3608 } 3610 3609 } 3611 3611 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3610 3610 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3612 3611 3613 3612 adev->gfx.config.backend_enable_mask = active_rbs; 3614 3613 adev->gfx.config.num_rbs = hweight32(active_rbs); ··· 3631 3630 /* cache the values for userspace */ 3632 3631 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3633 3632 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3634 3634 - gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 3633 3633 + gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3635 3634 adev->gfx.config.rb_config[i][j].rb_backend_disable = 3636 3635 RREG32(mmCC_RB_BACKEND_DISABLE); 3637 3636 adev->gfx.config.rb_config[i][j].user_rb_backend_disable = ··· 3642 3641 RREG32(mmPA_SC_RASTER_CONFIG_1); 3643 3642 } 3644 3643 } 3645 3645 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3644 3644 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3646 3645 mutex_unlock(&adev->grbm_idx_mutex); 3647 3646 } 3648 3647 ··· 3789 3788 * making sure that the following register writes will be broadcasted 3790 3789 * to all the shaders 3791 3790 */ 3792 3792 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3791 3791 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3793 3792 3794 3793 WREG32(mmPA_SC_FIFO_SIZE, 3795 3794 (adev->gfx.config.sc_prim_fifo_size_frontend << ··· 3820 3819 mutex_lock(&adev->grbm_idx_mutex); 3821 3820 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3822 3821 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3823 3823 - gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 3822 3822 + gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 3824 3823 for (k = 0; k < adev->usec_timeout; k++) { 3825 3824 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0) 3826 3825 break; ··· 3828 3827 } 3829 3828 if (k == adev->usec_timeout) { 3830 3829 gfx_v8_0_select_se_sh(adev, 0xffffffff, 3831 3831 - 0xffffffff, 0xffffffff); 3830 3830 + 0xffffffff, 0xffffffff, 0); 3832 3831 mutex_unlock(&adev->grbm_idx_mutex); 3833 3832 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 3834 3833 i, j); ··· 3836 3835 } 3837 3836 } 3838 3837 } 3839 3839 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3838 3838 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3840 3839 mutex_unlock(&adev->grbm_idx_mutex); 3841 3840 3842 3841 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | ··· 5482 5481 { 5483 5482 uint32_t data; 5484 5483 5485 5485 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5484 5484 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 5486 5485 5487 5486 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); 5488 5487 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); ··· 6724 6723 */ 6725 6724 if (from_wq) { 6726 6725 mutex_lock(&adev->grbm_idx_mutex); 6727 6727 - gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id); 6726 6726 + gfx_v8_0_select_se_sh(adev, se_id, sh_id, cu_id, 0); 6728 6727 6729 6728 sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE); 6730 6729 6731 6731 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6730 6730 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6732 6731 mutex_unlock(&adev->grbm_idx_mutex); 6733 6732 } 6734 6733 ··· 7117 7116 mask = 1; 7118 7117 ao_bitmap = 0; 7119 7118 counter = 0; 7120 7120 - gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); 7119 7119 + gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff, 0); 7121 7120 if (i < 4 && j < 2) 7122 7121 gfx_v8_0_set_user_cu_inactive_bitmap( 7123 7122 adev, disable_masks[i * 2 + j]); ··· 7138 7137 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 7139 7138 } 7140 7139 } 7141 7141 - gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7140 7140 + gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7142 7141 mutex_unlock(&adev->grbm_idx_mutex); 7143 7142 7144 7143 cu_info->number = active_cu_number;

+15 -15

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

reviewed

··· 1504 1504 mask = 1; 1505 1505 cu_bitmap = 0; 1506 1506 counter = 0; 1507 1507 - amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 1507 1507 + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 1508 1508 1509 1509 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { 1510 1510 if (cu_info->bitmap[i][j] & mask) { ··· 1523 1523 cu_info->ao_cu_bitmap[i][j] = cu_bitmap; 1524 1524 } 1525 1525 } 1526 1526 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1526 1526 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1527 1527 mutex_unlock(&adev->grbm_idx_mutex); 1528 1528 } 1529 1529 ··· 1545 1545 1546 1546 mutex_lock(&adev->grbm_idx_mutex); 1547 1547 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1548 1548 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1548 1548 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1549 1549 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1550 1550 1551 1551 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ ··· 1594 1594 1595 1595 mutex_lock(&adev->grbm_idx_mutex); 1596 1596 /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/ 1597 1597 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1597 1597 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1598 1598 WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff); 1599 1599 1600 1600 /* set mmRLC_LB_PARAMS = 0x003F_1006 */ ··· 2241 2241 } 2242 2242 2243 2243 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 2244 2244 - u32 instance) 2244 2244 + u32 instance, int xcc_id) 2245 2245 { 2246 2246 u32 data; 2247 2247 ··· 2290 2290 mutex_lock(&adev->grbm_idx_mutex); 2291 2291 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2292 2292 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2293 2293 - amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2293 2293 + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 2294 2294 data = gfx_v9_0_get_rb_active_bitmap(adev); 2295 2295 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 2296 2296 rb_bitmap_width_per_sh); 2297 2297 } 2298 2298 } 2299 2299 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2299 2299 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2300 2300 mutex_unlock(&adev->grbm_idx_mutex); 2301 2301 2302 2302 adev->gfx.config.backend_enable_mask = active_rbs; ··· 2433 2433 mutex_lock(&adev->grbm_idx_mutex); 2434 2434 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 2435 2435 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 2436 2436 - amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 2436 2436 + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 2437 2437 for (k = 0; k < adev->usec_timeout; k++) { 2438 2438 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0) 2439 2439 break; ··· 2441 2441 } 2442 2442 if (k == adev->usec_timeout) { 2443 2443 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 2444 2444 - 0xffffffff, 0xffffffff); 2444 2444 + 0xffffffff, 0xffffffff, 0); 2445 2445 mutex_unlock(&adev->grbm_idx_mutex); 2446 2446 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 2447 2447 i, j); ··· 2449 2449 } 2450 2450 } 2451 2451 } 2452 2452 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 2452 2452 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 2453 2453 mutex_unlock(&adev->grbm_idx_mutex); 2454 2454 2455 2455 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | ··· 6608 6608 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6609 6609 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6610 6610 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6611 6611 - amdgpu_gfx_select_se_sh(adev, j, 0x0, k); 6611 6611 + amdgpu_gfx_select_se_sh(adev, j, 0x0, k, 0); 6612 6612 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6613 6613 } 6614 6614 } ··· 6670 6670 for (i = 0; i < ARRAY_SIZE(gfx_v9_0_edc_counter_regs); i++) { 6671 6671 for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { 6672 6672 for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { 6673 6673 - amdgpu_gfx_select_se_sh(adev, j, 0, k); 6673 6673 + amdgpu_gfx_select_se_sh(adev, j, 0, k, 0); 6674 6674 reg_value = 6675 6675 RREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_0_edc_counter_regs[i])); 6676 6676 if (reg_value) ··· 6685 6685 err_data->ce_count += sec_count; 6686 6686 err_data->ue_count += ded_count; 6687 6687 6688 6688 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 6688 6688 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 6689 6689 mutex_unlock(&adev->grbm_idx_mutex); 6690 6690 6691 6691 gfx_v9_0_query_utc_edc_status(adev, err_data); ··· 7145 7145 mask = 1; 7146 7146 ao_bitmap = 0; 7147 7147 counter = 0; 7148 7148 - amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff); 7148 7148 + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, 0); 7149 7149 gfx_v9_0_set_user_cu_inactive_bitmap( 7150 7150 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 7151 7151 bitmap = gfx_v9_0_get_cu_active_bitmap(adev); ··· 7178 7178 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 7179 7179 } 7180 7180 } 7181 7181 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 7181 7181 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 7182 7182 mutex_unlock(&adev->grbm_idx_mutex); 7183 7183 7184 7184 cu_info->number = active_cu_number;

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h

reviewed

··· 27 27 extern const struct amdgpu_ip_block_version gfx_v9_0_ip_block; 28 28 29 29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, 30 30 - u32 instance); 30 30 + u32 instance, int xcc_id); 31 31 32 32 #endif

+1 -1

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c

reviewed

··· 777 777 { 778 778 u32 tmp; 779 779 780 780 - gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 780 780 + gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 781 781 782 782 tmp = 0; 783 783 tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);

+11 -9

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

reviewed

··· 568 568 static void gfx_v9_4_3_select_se_sh(struct amdgpu_device *adev, 569 569 u32 se_num, 570 570 u32 sh_num, 571 571 - u32 instance) 571 571 + u32 instance, 572 572 + int xcc_id) 572 573 { 573 574 u32 data; 574 575 ··· 592 591 else 593 592 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); 594 593 595 595 - WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data); 594 594 + WREG32_SOC15_RLC_SHADOW_EX(reg, GC, xcc_id, regGRBM_GFX_INDEX, data); 596 595 } 597 596 598 597 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) ··· 908 907 mutex_lock(&adev->grbm_idx_mutex); 909 908 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 910 909 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 911 911 - gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff); 910 910 + gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 912 911 data = gfx_v9_4_3_get_rb_active_bitmap(adev); 913 912 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 914 913 rb_bitmap_width_per_sh); 915 914 } 916 915 } 917 917 - gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 916 916 + gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 918 917 mutex_unlock(&adev->grbm_idx_mutex); 919 918 920 919 adev->gfx.config.backend_enable_mask = active_rbs; ··· 1147 1146 mutex_lock(&adev->grbm_idx_mutex); 1148 1147 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1149 1148 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1150 1150 - gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff); 1149 1149 + gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 1151 1150 for (k = 0; k < adev->usec_timeout; k++) { 1152 1151 if (RREG32_SOC15(GC, 0, regRLC_SERDES_CU_MASTER_BUSY) == 0) 1153 1152 break; ··· 1155 1154 } 1156 1155 if (k == adev->usec_timeout) { 1157 1156 gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 1158 1158 - 0xffffffff, 0xffffffff); 1157 1157 + 0xffffffff, 0xffffffff, 1158 1158 + xcc_id); 1159 1159 mutex_unlock(&adev->grbm_idx_mutex); 1160 1160 DRM_INFO("Timeout wait for RLC serdes %u,%u\n", 1161 1161 i, j); ··· 1164 1162 } 1165 1163 } 1166 1164 } 1167 1167 - gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1165 1165 + gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 1168 1166 mutex_unlock(&adev->grbm_idx_mutex); 1169 1167 1170 1168 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK | ··· 3067 3065 mask = 1; 3068 3066 ao_bitmap = 0; 3069 3067 counter = 0; 3070 3070 - gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff); 3068 3068 + gfx_v9_4_3_select_se_sh(adev, i, j, 0xffffffff, 0); 3071 3069 gfx_v9_4_3_set_user_cu_inactive_bitmap( 3072 3070 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]); 3073 3071 bitmap = gfx_v9_4_3_get_cu_active_bitmap(adev); ··· 3100 3098 cu_info->ao_cu_bitmap[i % 4][j + i / 4] = ao_bitmap; 3101 3099 } 3102 3100 } 3103 3103 - gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 3101 3101 + gfx_v9_4_3_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 3104 3102 mutex_unlock(&adev->grbm_idx_mutex); 3105 3103 3106 3104 cu_info->number = active_cu_number;

+2 -2

drivers/gpu/drm/amd/amdgpu/nv.c

reviewed

··· 371 371 372 372 mutex_lock(&adev->grbm_idx_mutex); 373 373 if (se_num != 0xffffffff || sh_num != 0xffffffff) 374 374 - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 374 374 + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 375 375 376 376 val = RREG32(reg_offset); 377 377 378 378 if (se_num != 0xffffffff || sh_num != 0xffffffff) 379 379 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 379 379 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 380 380 mutex_unlock(&adev->grbm_idx_mutex); 381 381 return val; 382 382 }

+2 -2

drivers/gpu/drm/amd/amdgpu/si.c

reviewed

··· 1181 1181 1182 1182 mutex_lock(&adev->grbm_idx_mutex); 1183 1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1184 1184 - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1184 1184 + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 1185 1185 1186 1186 val = RREG32(reg_offset); 1187 1187 1188 1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1189 1189 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1189 1189 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 1190 1190 mutex_unlock(&adev->grbm_idx_mutex); 1191 1191 return val; 1192 1192 } else {

+2 -2

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 363 363 364 364 mutex_lock(&adev->grbm_idx_mutex); 365 365 if (se_num != 0xffffffff || sh_num != 0xffffffff) 366 366 - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 366 366 + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 367 367 368 368 val = RREG32(reg_offset); 369 369 370 370 if (se_num != 0xffffffff || sh_num != 0xffffffff) 371 371 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 371 371 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 372 372 mutex_unlock(&adev->grbm_idx_mutex); 373 373 return val; 374 374 }

+2 -2

drivers/gpu/drm/amd/amdgpu/soc21.c

reviewed

··· 288 288 289 289 mutex_lock(&adev->grbm_idx_mutex); 290 290 if (se_num != 0xffffffff || sh_num != 0xffffffff) 291 291 - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 291 291 + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 292 292 293 293 val = RREG32(reg_offset); 294 294 295 295 if (se_num != 0xffffffff || sh_num != 0xffffffff) 296 296 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 296 296 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 297 297 mutex_unlock(&adev->grbm_idx_mutex); 298 298 return val; 299 299 }

+2 -2

drivers/gpu/drm/amd/amdgpu/vi.c

reviewed

··· 762 762 763 763 mutex_lock(&adev->grbm_idx_mutex); 764 764 if (se_num != 0xffffffff || sh_num != 0xffffffff) 765 765 - amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 765 765 + amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); 766 766 767 767 val = RREG32(reg_offset); 768 768 769 769 if (se_num != 0xffffffff || sh_num != 0xffffffff) 770 770 - amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 770 770 + amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); 771 771 mutex_unlock(&adev->grbm_idx_mutex); 772 772 return val; 773 773 } else {