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drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine

Drop use of LEFT/RIGHT VDSC engine and use VDSC0/VDSC1 instead.
While at it, use REG_BIT macro for the bits.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-4-ankit.k.nautiyal@intel.com

Ankit Nautiyal d457918c a64d9afc

+6 -6
+4 -4
drivers/gpu/drm/i915/display/intel_vdsc.c
··· 770 770 771 771 intel_dsc_pps_configure(crtc_state); 772 772 773 - dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; 773 + dss_ctl2_val |= VDSC0_ENABLE; 774 774 if (vdsc_instances_per_pipe > 1) { 775 - dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; 775 + dss_ctl2_val |= VDSC1_ENABLE; 776 776 dss_ctl1_val |= JOINER_ENABLE; 777 777 } 778 778 if (crtc_state->joiner_pipes) { ··· 972 972 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg(crtc, cpu_transcoder)); 973 973 dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg(crtc, cpu_transcoder)); 974 974 975 - crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; 975 + crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE; 976 976 if (!crtc_state->dsc.compression_enable) 977 977 goto out; 978 978 979 - if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) 979 + if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE) 980 980 crtc_state->dsc.num_streams = 2; 981 981 else 982 982 crtc_state->dsc.num_streams = 1;
+2 -2
drivers/gpu/drm/i915/display/intel_vdsc_regs.h
··· 21 21 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 22 22 23 23 #define DSS_CTL2 _MMIO(0x67404) 24 - #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 25 - #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 24 + #define VDSC0_ENABLE REG_BIT(31) 25 + #define VDSC1_ENABLE REG_BIT(15) 26 26 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 27 27 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 28 28