tjh.dev / kernel
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ARM: 6942/1: mm: make TTBR1 always point to swapper_pg_dir on ARMv6/7

This patch makes TTBR1 point to swapper_pg_dir so that global, kernel
mappings can be used exclusively on v6 and v7 cores where they are
needed.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

authored by

Catalin Marinas and committed by
Russell King d427958a a248b13b

+13 -4
+1
arch/arm/include/asm/smp.h
··· 70 70 */ 71 71 struct secondary_data { 72 72 unsigned long pgdir; 73 + unsigned long swapper_pg_dir; 73 74 void *stack; 74 75 }; 75 76 extern struct secondary_data secondary_data;
+5 -2
arch/arm/kernel/head.S
··· 113 113 ldr r13, =__mmap_switched @ address to jump to after 114 114 @ mmu has been enabled 115 115 adr lr, BSYM(1f) @ return (PIC) address 116 + mov r8, r4 @ set TTBR1 to swapper_pg_dir 116 117 ARM( add pc, r10, #PROCINFO_INITFUNC ) 117 118 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 118 119 THUMB( mov pc, r12 ) ··· 303 302 */ 304 303 adr r4, __secondary_data 305 304 ldmia r4, {r5, r7, r12} @ address to jump to after 306 - sub r4, r4, r5 @ mmu has been enabled 307 - ldr r4, [r7, r4] @ get secondary_data.pgdir 305 + sub lr, r4, r5 @ mmu has been enabled 306 + ldr r4, [r7, lr] @ get secondary_data.pgdir 307 + add r7, r7, #4 308 + ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir 308 309 adr lr, BSYM(__enable_mmu) @ return address 309 310 mov r13, r12 @ __secondary_switched address 310 311 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
+1
arch/arm/kernel/smp.c
··· 105 105 */ 106 106 secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; 107 107 secondary_data.pgdir = virt_to_phys(pgd); 108 + secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir); 108 109 __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data)); 109 110 outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1)); 110 111
+3 -1
arch/arm/mm/proc-v6.S
··· 213 213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 214 214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 215 215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 216 - mcr p15, 0, r4, c2, c0, 1 @ load TTB1 216 + ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 217 + ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 218 + mcr p15, 0, r8, c2, c0, 1 @ load TTB1 217 219 #endif /* CONFIG_MMU */ 218 220 adr r5, v6_crval 219 221 ldmia r5, {r5, r6}
+3 -1
arch/arm/mm/proc-v7.S
··· 368 368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 369 369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 370 370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 371 - mcr p15, 0, r4, c2, c0, 1 @ load TTB1 371 + ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 372 + ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 373 + mcr p15, 0, r8, c2, c0, 1 @ load TTB1 372 374 ldr r5, =PRRR @ PRRR 373 375 ldr r6, =NMRR @ NMRR 374 376 mcr p15, 0, r5, c10, c2, 0 @ write PRRR