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kernel
os
linux
dmaengine: IOATDMA: Cleanup pre v3.0 chansts register reads
Remove pre-3.0 channel status reads. 3.0 and later chansts register
is 64bit and can be read 64bit. This was clarified with the hardware
architects and since the driver now only support 3.0+ we don't need the
legacy support
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
authored by
Dave Jiang
and committed by
Vinod Koul
d3cd63f9
8005c49d
+4
-46
+1
-33
drivers/dma/ioat/dma.h
+1
-33
drivers/dma/ioat/dma.h
···
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return ioat_dma->idx[index];
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}
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-
static inline u64 ioat_chansts_32(struct ioatdma_chan *ioat_chan)
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-
{
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-
u8 ver = ioat_chan->ioat_dma->version;
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-
u64 status;
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u32 status_lo;
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-
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/* We need to read the low address first as this causes the
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* chipset to latch the upper bits for the subsequent read
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*/
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status_lo = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
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-
status = readl(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
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status <<= 32;
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status |= status_lo;
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-
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return status;
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}
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-
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#if BITS_PER_LONG == 64
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-
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static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
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{
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u8 ver = ioat_chan->ioat_dma->version;
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u64 status;
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-
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/* With IOAT v3.3 the status register is 64bit. */
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if (ver >= IOAT_VER_3_3)
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status = readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET(ver));
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else
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status = ioat_chansts_32(ioat_chan);
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-
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return status;
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+
return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
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}
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-
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#else
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#define ioat_chansts ioat_chansts_32
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-
#endif
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static inline u64 ioat_chansts_to_addr(u64 status)
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{
+3
-13
drivers/dma/ioat/registers.h
+3
-13
drivers/dma/ioat/registers.h
···
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#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
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#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */
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-
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#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
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#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
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#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
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? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
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-
#define IOAT1_CHANSTS_OFFSET_LOW 0x04
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-
#define IOAT2_CHANSTS_OFFSET_LOW 0x08
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#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
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? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
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-
#define IOAT1_CHANSTS_OFFSET_HIGH 0x08
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#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C
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#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
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-
? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
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+
/* IOAT1 define left for i7300_idle driver to not fail compiling */
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+
#define IOAT1_CHANSTS_OFFSET 0x04
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+
#define IOAT_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
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#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR (~0x3fULL)
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#define IOAT_CHANSTS_SOFT_ERR 0x10ULL
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#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x8ULL