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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
drm/amdgpu: enable clock gating for HDP 6.0
Enable HDP 6.0 clock gating.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Evan Quan
and committed by
Alex Deucher
d386f645
20139069
+73
-30
+71
-29
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
+71
-29
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
···
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}
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static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
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bool enable)
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bool enable)
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{
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uint32_t hdp_clk_cntl;
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uint32_t hdp_clk_cntl, hdp_clk_cntl1;
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uint32_t hdp_mem_pwr_cntl;
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if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
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if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
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AMD_CG_SUPPORT_HDP_DS |
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AMD_CG_SUPPORT_HDP_SD)))
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return;
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hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);
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hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
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/* Before doing clock/power mode switch,
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* forced on IPH & RC clock */
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hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
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RC_MEM_CLK_SOFT_OVERRIDE, 1);
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WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
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/* disable clock and power gating before any changing */
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_CTRL_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_LS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_DS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_SD_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_CTRL_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_LS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_DS_EN, 0);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_SD_EN, 0);
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WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
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/* Already disabled above. The actions below are for "enabled" only */
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if (enable) {
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hdp_clk_cntl &=
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~(uint32_t)
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(HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
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} else {
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hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
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/* only one clock gating mode (LS/DS/SD) can be enabled */
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if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_SD_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_SD_EN, 1);
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} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_LS_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_LS_EN, 1);
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} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_DS_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
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HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_DS_EN, 1);
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}
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/* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
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* be set for SRAM LS/DS/SD */
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if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
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AMD_CG_SUPPORT_HDP_SD)) {
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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ATOMIC_MEM_POWER_CTRL_EN, 1);
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hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
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RC_MEM_POWER_CTRL_EN, 1);
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WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
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}
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}
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/* disable IPH & RC clock override after clock/power mode changing */
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hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
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RC_MEM_CLK_SOFT_OVERRIDE, 0);
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WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
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}
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···
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u64 *flags)
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{
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uint32_t tmp;
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/* AMD_CG_SUPPORT_HDP_MGCG */
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tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
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if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
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HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
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*flags |= AMD_CG_SUPPORT_HDP_MGCG;
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/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
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tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
+2
-1
drivers/gpu/drm/amd/amdgpu/soc21.c
+2
-1
drivers/gpu/drm/amd/amdgpu/soc21.c