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linux
phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Abel Vesa
and committed by
Vinod Koul
d38360e1
cea3e943
+33
+32
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
+32
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
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#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
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#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
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#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
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#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
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#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
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#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
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#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
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#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
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#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
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#endif