tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

nvidiafb/rivafb: switch to pci_get refcounting

Switch to pci_get refcounting APIs

[adaplas]
Fix a long-standing bug where the return value of
pci_find_slot()/pci_get_bus_and_slot() is ignored.

Signed-off-by: Alan Cox <alan@redhat.com>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

authored by

Alan Cox and committed by
Linus Torvalds d3736340 dbe7e429

+23 -13
+9 -6
drivers/video/nvidia/nv_hw.c
··· 686 686 687 687 if ((par->Chipset & 0x0FF0) == 0x01A0) { 688 688 unsigned int uMClkPostDiv; 689 - dev = pci_find_slot(0, 3); 689 + dev = pci_get_bus_and_slot(0, 3); 690 690 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 691 691 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 692 692 ··· 694 694 uMClkPostDiv = 4; 695 695 MClk = 400000 / uMClkPostDiv; 696 696 } else { 697 - dev = pci_find_slot(0, 5); 697 + dev = pci_get_bus_and_slot(0, 5); 698 698 pci_read_config_dword(dev, 0x4c, &MClk); 699 699 MClk /= 1000; 700 700 } 701 - 701 + pci_dev_put(dev); 702 702 pll = NV_RD32(par->PRAMDAC0, 0x0500); 703 703 M = (pll >> 0) & 0xFF; 704 704 N = (pll >> 8) & 0xFF; ··· 707 707 sim_data.pix_bpp = (char)pixelDepth; 708 708 sim_data.enable_video = 0; 709 709 sim_data.enable_mp = 0; 710 - pci_find_slot(0, 1); 710 + dev = pci_get_bus_and_slot(0, 1); 711 711 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 712 + pci_dev_put(dev); 712 713 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 713 714 sim_data.memory_width = 64; 714 715 715 - dev = pci_find_slot(0, 3); 716 + dev = pci_get_bus_and_slot(0, 3); 716 717 pci_read_config_dword(dev, 0, &memctrl); 718 + pci_dev_put(dev); 717 719 memctrl >>= 16; 718 720 719 721 if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) { 720 722 int dimm[3]; 721 723 722 - pci_find_slot(0, 2); 724 + dev = pci_get_bus_and_slot(0, 2); 723 725 pci_read_config_dword(dev, 0x40, &dimm[0]); 724 726 dimm[0] = (dimm[0] >> 8) & 0x4f; 725 727 pci_read_config_dword(dev, 0x44, &dimm[1]); ··· 733 731 printk("nvidiafb: your nForce DIMMs are not arranged " 734 732 "in optimal banks!\n"); 735 733 } 734 + pci_dev_put(dev); 736 735 } 737 736 738 737 sim_data.mem_latency = 3;
+2 -1
drivers/video/nvidia/nv_setup.c
··· 261 261 } 262 262 #endif 263 263 264 - dev = pci_find_slot(0, 1); 264 + dev = pci_get_bus_and_slot(0, 1); 265 265 if ((par->Chipset & 0xffff) == 0x01a0) { 266 266 int amt = 0; 267 267 ··· 276 276 par->RamAmountKBytes = 277 277 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; 278 278 } 279 + pci_dev_put(dev); 279 280 280 281 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? 281 282 14318 : 13500;
+4 -2
drivers/video/riva/nv_driver.c
··· 231 231 case NV_ARCH_30: 232 232 if(chipset == NV_CHIP_IGEFORCE2) { 233 233 234 - dev = pci_find_slot(0, 1); 234 + dev = pci_get_bus_and_slot(0, 1); 235 235 pci_read_config_dword(dev, 0x7C, &amt); 236 + pci_dev_put(dev); 236 237 memlen = (((amt >> 6) & 31) + 1) * 1024; 237 238 } else if (chipset == NV_CHIP_0x01F0) { 238 - dev = pci_find_slot(0, 1); 239 + dev = pci_get_bus_and_slot(0, 1); 239 240 pci_read_config_dword(dev, 0x84, &amt); 241 + pci_dev_put(dev); 240 242 memlen = (((amt >> 4) & 127) + 1) * 1024; 241 243 } else { 242 244 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
+8 -4
drivers/video/riva/riva_hw.c
··· 1118 1118 unsigned int uMClkPostDiv; 1119 1119 struct pci_dev *dev; 1120 1120 1121 - dev = pci_find_slot(0, 3); 1121 + dev = pci_get_bus_and_slot(0, 3); 1122 1122 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 1123 + pci_dev_put(dev); 1123 1124 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 1124 1125 1125 1126 if(!uMClkPostDiv) uMClkPostDiv = 4; ··· 1133 1132 sim_data.enable_video = 0; 1134 1133 sim_data.enable_mp = 0; 1135 1134 1136 - dev = pci_find_slot(0, 1); 1135 + dev = pci_get_bus_and_slot(0, 1); 1137 1136 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 1137 + pci_dev_put(dev); 1138 1138 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 1139 1139 1140 1140 sim_data.memory_width = 64; ··· 2114 2112 * Fill in chip configuration. 2115 2113 */ 2116 2114 if(chipset == NV_CHIP_IGEFORCE2) { 2117 - dev = pci_find_slot(0, 1); 2115 + dev = pci_get_bus_and_slot(0, 1); 2118 2116 pci_read_config_dword(dev, 0x7C, &amt); 2117 + pci_dev_put(dev); 2119 2118 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 2120 2119 } else if(chipset == NV_CHIP_0x01F0) { 2121 - dev = pci_find_slot(0, 1); 2120 + dev = pci_get_bus_and_slot(0, 1); 2122 2121 pci_read_config_dword(dev, 0x84, &amt); 2122 + pci_dev_put(dev); 2123 2123 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 2124 2124 } else { 2125 2125 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)