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linux
phy: usb: update Broadcom driver table to use designated initializers
The Broadcom USB PHY driver contains a lookup table
(`reg_bits_map_tables`) to resolve register bitmaps unique to certain
versions of the USB PHY as found in various Broadcom chip families.
Historically, this table was just kept carefully in sync with the
"selector" enum every time the latter changed to ensure consistency.
However, a recent commit [1] introduced two new enumerators but did not
adjust the array for BCM4908, thus breaking the xHCI controller (and
boot process) on this platform and revealing the fragility of this
approach.
Since these arrays are a little sparse (many elements are zero) and the
position of the array elements is significant only insofar as they agree
with the enumerators, designated initializers are a better fit than
positional initializers here. Convert this table accordingly.
[1] 4536fe9640b6 ("phy: usb: suppress OC condition for 7439b2")
Signed-off-by: Sam Edwards <CFSworks@gmail.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Justin Chen <justin.chen@broadcom.com>
Link: https://lore.kernel.org/r/20241004034131.1363813-3-CFSworks@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Sam Edwards
and committed by
Vinod Koul
d3712b35
cb4c7df5
+215
-220
+215
-220
drivers/phy/broadcom/phy-brcm-usb-init.c
+215
-220
drivers/phy/broadcom/phy-brcm-usb-init.c
···
193
193
usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
194
194
/* 3390B0 */
195
195
[BRCM_FAMILY_3390A0] = {
196
-
USB_CTRL_SETUP_SCB1_EN_MASK,
197
-
USB_CTRL_SETUP_SCB2_EN_MASK,
198
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
199
-
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
200
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
201
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
202
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
203
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
204
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
205
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
206
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
207
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
208
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
209
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
210
-
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
211
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
212
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
213
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
214
-
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
215
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
196
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
197
+
USB_CTRL_SETUP_SCB1_EN_MASK,
198
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
199
+
USB_CTRL_SETUP_SCB2_EN_MASK,
200
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
201
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
202
+
[USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
203
+
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
204
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
205
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
206
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
207
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
208
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
209
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
210
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
211
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
212
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
213
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
214
+
[USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
215
+
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
216
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
217
+
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
218
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
216
219
},
217
220
/* 4908 */
218
221
[BRCM_FAMILY_4908] = {
219
-
0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
220
-
0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
221
-
0, /* USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
222
-
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
223
-
0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */
224
-
0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */
225
-
0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
226
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
227
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
228
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
229
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
230
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
231
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
232
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
233
-
0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
234
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
235
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
236
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
237
-
0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK */
238
-
0, /* USB_CTRL_SETUP ENDIAN bits */
222
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
223
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
224
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
225
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
239
226
},
240
227
/* 7250b0 */
241
228
[BRCM_FAMILY_7250B0] = {
242
-
USB_CTRL_SETUP_SCB1_EN_MASK,
243
-
USB_CTRL_SETUP_SCB2_EN_MASK,
244
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
245
-
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
246
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
247
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
248
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
249
-
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
250
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
251
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
252
-
0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
253
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
254
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
255
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
256
-
0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
257
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
258
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
259
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
260
-
USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
261
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
229
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
230
+
USB_CTRL_SETUP_SCB1_EN_MASK,
231
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
232
+
USB_CTRL_SETUP_SCB2_EN_MASK,
233
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
234
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
235
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
236
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
237
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
238
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
239
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
240
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
241
+
[USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
242
+
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
243
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
244
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
245
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
246
+
USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
247
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
262
248
},
263
249
/* 7271a0 */
264
250
[BRCM_FAMILY_7271A0] = {
265
-
0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
266
-
0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
267
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
268
-
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
269
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
270
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
271
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
272
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
273
-
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
274
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
275
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
276
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
277
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
278
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
279
-
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
280
-
USB_CTRL_USB_PM_SOFT_RESET_MASK,
281
-
USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
282
-
USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
283
-
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
284
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
251
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
252
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
253
+
[USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
254
+
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
255
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
256
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
257
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
258
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
259
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
260
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
261
+
[USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
262
+
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
263
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
264
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
265
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
266
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
267
+
[USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
268
+
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
269
+
[USB_CTRL_USB_PM_SOFT_RESET_SELECTOR] =
270
+
USB_CTRL_USB_PM_SOFT_RESET_MASK,
271
+
[USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR] =
272
+
USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
273
+
[USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR] =
274
+
USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
275
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
276
+
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
277
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
285
278
},
286
279
/* 7364a0 */
287
280
[BRCM_FAMILY_7364A0] = {
288
-
USB_CTRL_SETUP_SCB1_EN_MASK,
289
-
USB_CTRL_SETUP_SCB2_EN_MASK,
290
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
291
-
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
292
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
293
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
294
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
295
-
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
296
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
297
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
298
-
0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
299
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
300
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
301
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
302
-
0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
303
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
304
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
305
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
306
-
USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
307
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
281
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
282
+
USB_CTRL_SETUP_SCB1_EN_MASK,
283
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
284
+
USB_CTRL_SETUP_SCB2_EN_MASK,
285
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
286
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
287
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
288
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
289
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
290
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
291
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
292
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
293
+
[USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
294
+
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
295
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
296
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
297
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
298
+
USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
299
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
308
300
},
309
301
/* 7366c0 */
310
302
[BRCM_FAMILY_7366C0] = {
311
-
USB_CTRL_SETUP_SCB1_EN_MASK,
312
-
USB_CTRL_SETUP_SCB2_EN_MASK,
313
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
314
-
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
315
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
316
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
317
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
318
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
319
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
320
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
321
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
322
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
323
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
324
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
325
-
0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
326
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
327
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
328
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
329
-
USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
330
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
303
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
304
+
USB_CTRL_SETUP_SCB1_EN_MASK,
305
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
306
+
USB_CTRL_SETUP_SCB2_EN_MASK,
307
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
308
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
309
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
310
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
311
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
312
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
313
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
314
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
315
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
316
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
317
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
318
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
319
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
320
+
USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
321
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
331
322
},
332
323
/* 74371A0 */
333
324
[BRCM_FAMILY_74371A0] = {
334
-
USB_CTRL_SETUP_SCB1_EN_MASK,
335
-
USB_CTRL_SETUP_SCB2_EN_MASK,
336
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
337
-
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
338
-
0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */
339
-
0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */
340
-
0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
341
-
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
342
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
343
-
0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
344
-
0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
345
-
USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
346
-
USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
347
-
USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
348
-
0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
349
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
350
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
351
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
352
-
0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
353
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
325
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
326
+
USB_CTRL_SETUP_SCB1_EN_MASK,
327
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
328
+
USB_CTRL_SETUP_SCB2_EN_MASK,
329
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
330
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
331
+
[USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
332
+
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
333
+
[USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR] =
334
+
USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
335
+
[USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR] =
336
+
USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
337
+
[USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR] =
338
+
USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
339
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
354
340
},
355
341
/* 7439B0 */
356
342
[BRCM_FAMILY_7439B0] = {
357
-
USB_CTRL_SETUP_SCB1_EN_MASK,
358
-
USB_CTRL_SETUP_SCB2_EN_MASK,
359
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
360
-
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
361
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
362
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
363
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
364
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
365
-
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
366
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
367
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
368
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
369
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
370
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
371
-
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
372
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
373
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
374
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
375
-
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
376
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
343
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
344
+
USB_CTRL_SETUP_SCB1_EN_MASK,
345
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
346
+
USB_CTRL_SETUP_SCB2_EN_MASK,
347
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
348
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
349
+
[USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
350
+
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
351
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
352
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
353
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
354
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
355
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
356
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
357
+
[USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
358
+
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
359
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
360
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
361
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
362
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
363
+
[USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
364
+
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
365
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
366
+
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
367
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
377
368
},
378
369
/* 7445d0 */
379
370
[BRCM_FAMILY_7445D0] = {
380
-
USB_CTRL_SETUP_SCB1_EN_MASK,
381
-
USB_CTRL_SETUP_SCB2_EN_MASK,
382
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
383
-
0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
384
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
385
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
386
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
387
-
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
388
-
0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
389
-
0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
390
-
0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
391
-
USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
392
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
393
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
394
-
0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
395
-
0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
396
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
397
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
398
-
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
399
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
371
+
[USB_CTRL_SETUP_SCB1_EN_SELECTOR] =
372
+
USB_CTRL_SETUP_SCB1_EN_MASK,
373
+
[USB_CTRL_SETUP_SCB2_EN_SELECTOR] =
374
+
USB_CTRL_SETUP_SCB2_EN_MASK,
375
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
376
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
377
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
378
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
379
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
380
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
381
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
382
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
383
+
[USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR] =
384
+
USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
385
+
[USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR] =
386
+
USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
387
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
388
+
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
389
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
400
390
},
401
391
/* 7260a0 */
402
392
[BRCM_FAMILY_7260A0] = {
403
-
0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
404
-
0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
405
-
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
406
-
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
407
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
408
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
409
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
410
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
411
-
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
412
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
413
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
414
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
415
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
416
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
417
-
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
418
-
USB_CTRL_USB_PM_SOFT_RESET_MASK,
419
-
USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
420
-
USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
421
-
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
422
-
ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
393
+
[USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR] =
394
+
USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
395
+
[USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
396
+
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
397
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
398
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
399
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
400
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
401
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
402
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
403
+
[USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
404
+
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
405
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
406
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
407
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
408
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
409
+
[USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
410
+
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
411
+
[USB_CTRL_USB_PM_SOFT_RESET_SELECTOR] =
412
+
USB_CTRL_USB_PM_SOFT_RESET_MASK,
413
+
[USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR] =
414
+
USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
415
+
[USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR] =
416
+
USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
417
+
[USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR] =
418
+
USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
419
+
[USB_CTRL_SETUP_ENDIAN_SELECTOR] = ENDIAN_SETTINGS,
423
420
},
424
421
/* 7278a0 */
425
422
[BRCM_FAMILY_7278A0] = {
426
-
0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
427
-
0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
428
-
0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
429
-
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
430
-
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
431
-
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
432
-
USB_CTRL_SETUP_OC3_DISABLE_MASK,
433
-
0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
434
-
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
435
-
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
436
-
USB_CTRL_USB_PM_USB_PWRDN_MASK,
437
-
0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
438
-
0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
439
-
0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
440
-
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
441
-
USB_CTRL_USB_PM_SOFT_RESET_MASK,
442
-
0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
443
-
0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
444
-
0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
445
-
0, /* USB_CTRL_SETUP ENDIAN bits */
423
+
[USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR] =
424
+
USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
425
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT0_SELECTOR] =
426
+
USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK,
427
+
[USB_CTRL_SETUP_OC3_DISABLE_PORT1_SELECTOR] =
428
+
USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK,
429
+
[USB_CTRL_SETUP_OC3_DISABLE_SELECTOR] =
430
+
USB_CTRL_SETUP_OC3_DISABLE_MASK,
431
+
[USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR] =
432
+
USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
433
+
[USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR] =
434
+
USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
435
+
[USB_CTRL_USB_PM_USB_PWRDN_SELECTOR] =
436
+
USB_CTRL_USB_PM_USB_PWRDN_MASK,
437
+
[USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR] =
438
+
USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
439
+
[USB_CTRL_USB_PM_SOFT_RESET_SELECTOR] =
440
+
USB_CTRL_USB_PM_SOFT_RESET_MASK,
446
441
},
447
442
};
448
443