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kernel os linux

phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask

Use GENMASK() macro to generate bits mask

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-17-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Chunfeng Yun and committed by
Vinod Koul
d36d69a5 bd4ba730

+3 -3
+3 -3
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
··· 18 18 #define RG_DSI_PAD_TIEL_SEL BIT(8) 19 19 20 20 #define MIPITX_VOLTAGE_SEL 0x0010 21 - #define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6) 21 + #define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6) 22 22 23 23 #define MIPITX_PLL_PWR 0x0028 24 24 #define MIPITX_PLL_CON0 0x002c ··· 26 26 #define MIPITX_PLL_CON2 0x0034 27 27 #define MIPITX_PLL_CON3 0x0038 28 28 #define MIPITX_PLL_CON4 0x003c 29 - #define RG_DSI_PLL_IBIAS (3 << 10) 29 + #define RG_DSI_PLL_IBIAS GENMASK(11, 10) 30 30 31 31 #define MIPITX_D2P_RTCODE 0x0100 32 32 #define MIPITX_D2_SW_CTL_EN 0x0144 ··· 41 41 #define AD_DSI_PLL_SDM_ISO_EN BIT(1) 42 42 43 43 #define RG_DSI_PLL_EN BIT(4) 44 - #define RG_DSI_PLL_POSDIV (0x7 << 8) 44 + #define RG_DSI_PLL_POSDIV GENMASK(10, 8) 45 45 46 46 static int mtk_mipi_tx_pll_enable(struct clk_hw *hw) 47 47 {