tjh.dev / kernel
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drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)

v2: fix register access

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Ken Wang <ken.wang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Junwei Zhang and committed by
Alex Deucher d33bba4d 9483ce7c

+5 -4
+5 -4
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
··· 1068 1068 adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); 1069 1069 adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; 1070 1070 adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; 1071 - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); 1072 - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; 1071 + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); 1072 + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); 1073 1073 1074 1074 /* Primitive Buffer */ 1075 1075 r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], ··· 1181 1181 1182 1182 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1183 1183 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1184 + PACKET3_DMA_DATA_DST_SEL(1) | 1184 1185 PACKET3_DMA_DATA_SRC_SEL(2))); 1185 1186 amdgpu_ring_write(ring, 0); 1186 1187 amdgpu_ring_write(ring, 0); 1187 1188 amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); 1188 1189 amdgpu_ring_write(ring, 0); 1189 - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); 1190 - 1190 + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | 1191 + adev->gfx.ngg.gds_reserve_size); 1191 1192 1192 1193 gfx_v9_0_write_data_to_reg(ring, 0, false, 1193 1194 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);