tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: add MP 11.0 register headers

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Hawking Zhang and committed by
Alex Deucher d33ad040 2a3196f1

+429
+429
drivers/gpu/drm/amd/include/asic_reg/mp/mp_11_0_sh_mask.h
··· 262 262 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 263 263 264 264 265 + //MP1_FIRMWARE_FLAGS 266 + #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 267 + #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 268 + #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 269 + #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 270 + //MP1_PUB_SCRATCH0 271 + #define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 272 + #define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL 273 + //MP1_PUB_SCRATCH1 274 + #define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 275 + #define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL 276 + //MP1_PUB_SCRATCH2 277 + #define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 278 + #define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL 279 + //MP1_PUB_SCRATCH3 280 + #define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 281 + #define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL 282 + //MP1_C2PMSG_0 283 + #define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 284 + #define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 285 + //MP1_C2PMSG_1 286 + #define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 287 + #define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 288 + //MP1_C2PMSG_2 289 + #define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 290 + #define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 291 + //MP1_C2PMSG_3 292 + #define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 293 + #define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 294 + //MP1_C2PMSG_4 295 + #define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 296 + #define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 297 + //MP1_C2PMSG_5 298 + #define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 299 + #define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 300 + //MP1_C2PMSG_6 301 + #define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 302 + #define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 303 + //MP1_C2PMSG_7 304 + #define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 305 + #define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 306 + //MP1_C2PMSG_8 307 + #define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 308 + #define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 309 + //MP1_C2PMSG_9 310 + #define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 311 + #define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 312 + //MP1_C2PMSG_10 313 + #define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 314 + #define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 315 + //MP1_C2PMSG_11 316 + #define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 317 + #define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 318 + //MP1_C2PMSG_12 319 + #define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 320 + #define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 321 + //MP1_C2PMSG_13 322 + #define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 323 + #define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 324 + //MP1_C2PMSG_14 325 + #define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 326 + #define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 327 + //MP1_C2PMSG_15 328 + #define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 329 + #define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 330 + //MP1_C2PMSG_16 331 + #define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 332 + #define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 333 + //MP1_C2PMSG_17 334 + #define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 335 + #define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 336 + //MP1_C2PMSG_18 337 + #define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 338 + #define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 339 + //MP1_C2PMSG_19 340 + #define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 341 + #define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 342 + //MP1_C2PMSG_20 343 + #define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 344 + #define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 345 + //MP1_C2PMSG_21 346 + #define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 347 + #define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 348 + //MP1_C2PMSG_22 349 + #define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 350 + #define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 351 + //MP1_C2PMSG_23 352 + #define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 353 + #define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 354 + //MP1_C2PMSG_24 355 + #define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 356 + #define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 357 + //MP1_C2PMSG_25 358 + #define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 359 + #define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 360 + //MP1_C2PMSG_26 361 + #define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 362 + #define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 363 + //MP1_C2PMSG_27 364 + #define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 365 + #define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 366 + //MP1_C2PMSG_28 367 + #define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 368 + #define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 369 + //MP1_C2PMSG_29 370 + #define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 371 + #define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 372 + //MP1_C2PMSG_30 373 + #define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 374 + #define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 375 + //MP1_C2PMSG_31 376 + #define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 377 + #define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 378 + //MP1_P2CMSG_0 379 + #define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 380 + #define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL 381 + //MP1_P2CMSG_1 382 + #define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 383 + #define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL 384 + //MP1_P2CMSG_2 385 + #define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 386 + #define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL 387 + //MP1_P2CMSG_3 388 + #define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 389 + #define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL 390 + //MP1_P2CMSG_INTEN 391 + #define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 392 + #define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL 393 + //MP1_P2CMSG_INTSTS 394 + #define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 395 + #define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 396 + #define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 397 + #define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 398 + #define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L 399 + #define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L 400 + #define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L 401 + #define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L 402 + //MP1_P2SMSG_0 403 + #define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 404 + #define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL 405 + //MP1_P2SMSG_1 406 + #define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 407 + #define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL 408 + //MP1_P2SMSG_2 409 + #define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 410 + #define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL 411 + //MP1_P2SMSG_3 412 + #define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 413 + #define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL 414 + //MP1_P2SMSG_INTSTS 415 + #define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 416 + #define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 417 + #define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 418 + #define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 419 + #define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L 420 + #define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L 421 + #define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L 422 + #define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L 423 + //MP1_S2PMSG_0 424 + #define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 425 + #define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 426 + //MP1_C2PMSG_32 427 + #define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 428 + #define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 429 + //MP1_C2PMSG_33 430 + #define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 431 + #define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 432 + //MP1_C2PMSG_34 433 + #define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 434 + #define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 435 + //MP1_C2PMSG_35 436 + #define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 437 + #define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 438 + //MP1_C2PMSG_36 439 + #define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 440 + #define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 441 + //MP1_C2PMSG_37 442 + #define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 443 + #define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 444 + //MP1_C2PMSG_38 445 + #define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 446 + #define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 447 + //MP1_C2PMSG_39 448 + #define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 449 + #define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 450 + //MP1_C2PMSG_40 451 + #define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 452 + #define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 453 + //MP1_C2PMSG_41 454 + #define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 455 + #define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 456 + //MP1_C2PMSG_42 457 + #define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 458 + #define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 459 + //MP1_C2PMSG_43 460 + #define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 461 + #define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 462 + //MP1_C2PMSG_44 463 + #define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 464 + #define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 465 + //MP1_C2PMSG_45 466 + #define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 467 + #define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 468 + //MP1_C2PMSG_46 469 + #define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 470 + #define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 471 + //MP1_C2PMSG_47 472 + #define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 473 + #define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 474 + //MP1_C2PMSG_48 475 + #define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 476 + #define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 477 + //MP1_C2PMSG_49 478 + #define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 479 + #define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 480 + //MP1_C2PMSG_50 481 + #define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 482 + #define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 483 + //MP1_C2PMSG_51 484 + #define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 485 + #define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 486 + //MP1_C2PMSG_52 487 + #define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 488 + #define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 489 + //MP1_C2PMSG_53 490 + #define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 491 + #define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 492 + //MP1_C2PMSG_54 493 + #define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 494 + #define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 495 + //MP1_C2PMSG_55 496 + #define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 497 + #define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 498 + //MP1_C2PMSG_56 499 + #define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 500 + #define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 501 + //MP1_C2PMSG_57 502 + #define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 503 + #define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 504 + //MP1_C2PMSG_58 505 + #define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 506 + #define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 507 + //MP1_C2PMSG_59 508 + #define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 509 + #define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 510 + //MP1_C2PMSG_60 511 + #define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 512 + #define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 513 + //MP1_C2PMSG_61 514 + #define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 515 + #define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 516 + //MP1_C2PMSG_62 517 + #define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 518 + #define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 519 + //MP1_C2PMSG_63 520 + #define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 521 + #define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 522 + //MP1_C2PMSG_64 523 + #define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 524 + #define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 525 + //MP1_C2PMSG_65 526 + #define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 527 + #define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 528 + //MP1_C2PMSG_66 529 + #define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 530 + #define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 531 + //MP1_C2PMSG_67 532 + #define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 533 + #define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 534 + //MP1_C2PMSG_68 535 + #define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 536 + #define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 537 + //MP1_C2PMSG_69 538 + #define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 539 + #define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 540 + //MP1_C2PMSG_70 541 + #define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 542 + #define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 543 + //MP1_C2PMSG_71 544 + #define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 545 + #define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 546 + //MP1_C2PMSG_72 547 + #define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 548 + #define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 549 + //MP1_C2PMSG_73 550 + #define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 551 + #define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 552 + //MP1_C2PMSG_74 553 + #define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 554 + #define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 555 + //MP1_C2PMSG_75 556 + #define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 557 + #define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 558 + //MP1_C2PMSG_76 559 + #define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 560 + #define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 561 + //MP1_C2PMSG_77 562 + #define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 563 + #define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 564 + //MP1_C2PMSG_78 565 + #define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 566 + #define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 567 + //MP1_C2PMSG_79 568 + #define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 569 + #define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 570 + //MP1_C2PMSG_80 571 + #define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 572 + #define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 573 + //MP1_C2PMSG_81 574 + #define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 575 + #define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 576 + //MP1_C2PMSG_82 577 + #define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 578 + #define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 579 + //MP1_C2PMSG_83 580 + #define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 581 + #define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 582 + //MP1_C2PMSG_84 583 + #define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 584 + #define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 585 + //MP1_C2PMSG_85 586 + #define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 587 + #define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 588 + //MP1_C2PMSG_86 589 + #define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 590 + #define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 591 + //MP1_C2PMSG_87 592 + #define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 593 + #define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 594 + //MP1_C2PMSG_88 595 + #define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 596 + #define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 597 + //MP1_C2PMSG_89 598 + #define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 599 + #define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 600 + //MP1_C2PMSG_90 601 + #define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 602 + #define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 603 + //MP1_C2PMSG_91 604 + #define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 605 + #define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 606 + //MP1_C2PMSG_92 607 + #define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 608 + #define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 609 + //MP1_C2PMSG_93 610 + #define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 611 + #define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 612 + //MP1_C2PMSG_94 613 + #define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 614 + #define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 615 + //MP1_C2PMSG_95 616 + #define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 617 + #define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 618 + //MP1_C2PMSG_96 619 + #define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 620 + #define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 621 + //MP1_C2PMSG_97 622 + #define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 623 + #define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 624 + //MP1_C2PMSG_98 625 + #define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 626 + #define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 627 + //MP1_C2PMSG_99 628 + #define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 629 + #define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 630 + //MP1_C2PMSG_100 631 + #define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 632 + #define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 633 + //MP1_C2PMSG_101 634 + #define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 635 + #define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 636 + //MP1_C2PMSG_102 637 + #define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 638 + #define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 639 + //MP1_C2PMSG_103 640 + #define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 641 + #define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 642 + //MP1_ACTIVE_FCN_ID 643 + #define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 644 + #define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f 645 + #define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL 646 + #define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L 647 + //MP1_IH_CREDIT 648 + #define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 649 + #define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 650 + #define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 651 + #define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 652 + //MP1_IH_SW_INT 653 + #define MP1_IH_SW_INT__ID__SHIFT 0x0 654 + #define MP1_IH_SW_INT__VALID__SHIFT 0x8 655 + #define MP1_IH_SW_INT__ID_MASK 0x000000FFL 656 + #define MP1_IH_SW_INT__VALID_MASK 0x00000100L 657 + //MP1_IH_SW_INT_CTRL 658 + #define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 659 + #define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 660 + #define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 661 + #define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 662 + //MP1_FPS_CNT 663 + #define MP1_FPS_CNT__COUNT__SHIFT 0x0 664 + #define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 665 + //MP1_PUB_CTRL 666 + #define MP1_PUB_CTRL__RESET__SHIFT 0x0 667 + #define MP1_PUB_CTRL__RESET_MASK 0x00000001L 668 + //MP1_EXT_SCRATCH0 669 + #define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 670 + #define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 671 + //MP1_EXT_SCRATCH1 672 + #define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 673 + #define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 674 + //MP1_EXT_SCRATCH2 675 + #define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 676 + #define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 677 + //MP1_EXT_SCRATCH3 678 + #define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 679 + #define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 680 + //MP1_EXT_SCRATCH4 681 + #define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 682 + #define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 683 + //MP1_EXT_SCRATCH5 684 + #define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 685 + #define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 686 + //MP1_EXT_SCRATCH6 687 + #define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 688 + #define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 689 + //MP1_EXT_SCRATCH7 690 + #define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 691 + #define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 692 + 693 + 265 694 // addressBlock: mp_SmuMp1_SmnDec 266 695 //MP1_SMN_C2PMSG_32 267 696 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0