tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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MIPS: Move unaligned load/store helpers to inst.h

Move unaligned load/store helpers from unaligned.c to inst.h, then
other parts of the kernel can use these helpers.

Use __ASSEMBLY__ to guard the definition of "LONG" in asm.h to avoid
build error on IPxx platforms.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Pei Huang <huangpei@loongson.cn>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Huacai Chen and committed by
Thomas Bogendoerfer d339cd02 c05b5940

+777 -775
+4
arch/mips/include/asm/asm.h
··· 202 202 #define LONG_SRA sra 203 203 #define LONG_SRAV srav 204 204 205 + #ifdef __ASSEMBLY__ 205 206 #define LONG .word 207 + #endif 206 208 #define LONGSIZE 4 207 209 #define LONGMASK 3 208 210 #define LONGLOG 2 ··· 227 225 #define LONG_SRA dsra 228 226 #define LONG_SRAV dsrav 229 227 228 + #ifdef __ASSEMBLY__ 230 229 #define LONG .dword 230 + #endif 231 231 #define LONGSIZE 8 232 232 #define LONGMASK 7 233 233 #define LONGLOG 3
+773
arch/mips/include/asm/inst.h
··· 11 11 #ifndef _ASM_INST_H 12 12 #define _ASM_INST_H 13 13 14 + #include <asm/asm.h> 14 15 #include <uapi/asm/inst.h> 15 16 16 17 /* HACHACHAHCAHC ... */ ··· 85 84 86 85 /* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */ 87 86 extern const int reg16to32[]; 87 + 88 + #ifdef __BIG_ENDIAN 89 + #define _LoadHW(addr, value, res, type) \ 90 + do { \ 91 + __asm__ __volatile__ (".set\tnoat\n" \ 92 + "1:\t"type##_lb("%0", "0(%2)")"\n" \ 93 + "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ 94 + "sll\t%0, 0x8\n\t" \ 95 + "or\t%0, $1\n\t" \ 96 + "li\t%1, 0\n" \ 97 + "3:\t.set\tat\n\t" \ 98 + ".insn\n\t" \ 99 + ".section\t.fixup,\"ax\"\n\t" \ 100 + "4:\tli\t%1, %3\n\t" \ 101 + "j\t3b\n\t" \ 102 + ".previous\n\t" \ 103 + ".section\t__ex_table,\"a\"\n\t" \ 104 + STR(PTR)"\t1b, 4b\n\t" \ 105 + STR(PTR)"\t2b, 4b\n\t" \ 106 + ".previous" \ 107 + : "=&r" (value), "=r" (res) \ 108 + : "r" (addr), "i" (-EFAULT)); \ 109 + } while (0) 110 + 111 + #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 112 + #define _LoadW(addr, value, res, type) \ 113 + do { \ 114 + __asm__ __volatile__ ( \ 115 + "1:\t"type##_lwl("%0", "(%2)")"\n" \ 116 + "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ 117 + "li\t%1, 0\n" \ 118 + "3:\n\t" \ 119 + ".insn\n\t" \ 120 + ".section\t.fixup,\"ax\"\n\t" \ 121 + "4:\tli\t%1, %3\n\t" \ 122 + "j\t3b\n\t" \ 123 + ".previous\n\t" \ 124 + ".section\t__ex_table,\"a\"\n\t" \ 125 + STR(PTR)"\t1b, 4b\n\t" \ 126 + STR(PTR)"\t2b, 4b\n\t" \ 127 + ".previous" \ 128 + : "=&r" (value), "=r" (res) \ 129 + : "r" (addr), "i" (-EFAULT)); \ 130 + } while (0) 131 + 132 + #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 133 + /* For CPUs without lwl instruction */ 134 + #define _LoadW(addr, value, res, type) \ 135 + do { \ 136 + __asm__ __volatile__ ( \ 137 + ".set\tpush\n" \ 138 + ".set\tnoat\n\t" \ 139 + "1:"type##_lb("%0", "0(%2)")"\n\t" \ 140 + "2:"type##_lbu("$1", "1(%2)")"\n\t" \ 141 + "sll\t%0, 0x8\n\t" \ 142 + "or\t%0, $1\n\t" \ 143 + "3:"type##_lbu("$1", "2(%2)")"\n\t" \ 144 + "sll\t%0, 0x8\n\t" \ 145 + "or\t%0, $1\n\t" \ 146 + "4:"type##_lbu("$1", "3(%2)")"\n\t" \ 147 + "sll\t%0, 0x8\n\t" \ 148 + "or\t%0, $1\n\t" \ 149 + "li\t%1, 0\n" \ 150 + ".set\tpop\n" \ 151 + "10:\n\t" \ 152 + ".insn\n\t" \ 153 + ".section\t.fixup,\"ax\"\n\t" \ 154 + "11:\tli\t%1, %3\n\t" \ 155 + "j\t10b\n\t" \ 156 + ".previous\n\t" \ 157 + ".section\t__ex_table,\"a\"\n\t" \ 158 + STR(PTR)"\t1b, 11b\n\t" \ 159 + STR(PTR)"\t2b, 11b\n\t" \ 160 + STR(PTR)"\t3b, 11b\n\t" \ 161 + STR(PTR)"\t4b, 11b\n\t" \ 162 + ".previous" \ 163 + : "=&r" (value), "=r" (res) \ 164 + : "r" (addr), "i" (-EFAULT)); \ 165 + } while (0) 166 + 167 + #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 168 + 169 + #define _LoadHWU(addr, value, res, type) \ 170 + do { \ 171 + __asm__ __volatile__ ( \ 172 + ".set\tnoat\n" \ 173 + "1:\t"type##_lbu("%0", "0(%2)")"\n" \ 174 + "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ 175 + "sll\t%0, 0x8\n\t" \ 176 + "or\t%0, $1\n\t" \ 177 + "li\t%1, 0\n" \ 178 + "3:\n\t" \ 179 + ".insn\n\t" \ 180 + ".set\tat\n\t" \ 181 + ".section\t.fixup,\"ax\"\n\t" \ 182 + "4:\tli\t%1, %3\n\t" \ 183 + "j\t3b\n\t" \ 184 + ".previous\n\t" \ 185 + ".section\t__ex_table,\"a\"\n\t" \ 186 + STR(PTR)"\t1b, 4b\n\t" \ 187 + STR(PTR)"\t2b, 4b\n\t" \ 188 + ".previous" \ 189 + : "=&r" (value), "=r" (res) \ 190 + : "r" (addr), "i" (-EFAULT)); \ 191 + } while (0) 192 + 193 + #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 194 + #define _LoadWU(addr, value, res, type) \ 195 + do { \ 196 + __asm__ __volatile__ ( \ 197 + "1:\t"type##_lwl("%0", "(%2)")"\n" \ 198 + "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ 199 + "dsll\t%0, %0, 32\n\t" \ 200 + "dsrl\t%0, %0, 32\n\t" \ 201 + "li\t%1, 0\n" \ 202 + "3:\n\t" \ 203 + ".insn\n\t" \ 204 + "\t.section\t.fixup,\"ax\"\n\t" \ 205 + "4:\tli\t%1, %3\n\t" \ 206 + "j\t3b\n\t" \ 207 + ".previous\n\t" \ 208 + ".section\t__ex_table,\"a\"\n\t" \ 209 + STR(PTR)"\t1b, 4b\n\t" \ 210 + STR(PTR)"\t2b, 4b\n\t" \ 211 + ".previous" \ 212 + : "=&r" (value), "=r" (res) \ 213 + : "r" (addr), "i" (-EFAULT)); \ 214 + } while (0) 215 + 216 + #define _LoadDW(addr, value, res) \ 217 + do { \ 218 + __asm__ __volatile__ ( \ 219 + "1:\tldl\t%0, (%2)\n" \ 220 + "2:\tldr\t%0, 7(%2)\n\t" \ 221 + "li\t%1, 0\n" \ 222 + "3:\n\t" \ 223 + ".insn\n\t" \ 224 + "\t.section\t.fixup,\"ax\"\n\t" \ 225 + "4:\tli\t%1, %3\n\t" \ 226 + "j\t3b\n\t" \ 227 + ".previous\n\t" \ 228 + ".section\t__ex_table,\"a\"\n\t" \ 229 + STR(PTR)"\t1b, 4b\n\t" \ 230 + STR(PTR)"\t2b, 4b\n\t" \ 231 + ".previous" \ 232 + : "=&r" (value), "=r" (res) \ 233 + : "r" (addr), "i" (-EFAULT)); \ 234 + } while (0) 235 + 236 + #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 237 + /* For CPUs without lwl and ldl instructions */ 238 + #define _LoadWU(addr, value, res, type) \ 239 + do { \ 240 + __asm__ __volatile__ ( \ 241 + ".set\tpush\n\t" \ 242 + ".set\tnoat\n\t" \ 243 + "1:"type##_lbu("%0", "0(%2)")"\n\t" \ 244 + "2:"type##_lbu("$1", "1(%2)")"\n\t" \ 245 + "sll\t%0, 0x8\n\t" \ 246 + "or\t%0, $1\n\t" \ 247 + "3:"type##_lbu("$1", "2(%2)")"\n\t" \ 248 + "sll\t%0, 0x8\n\t" \ 249 + "or\t%0, $1\n\t" \ 250 + "4:"type##_lbu("$1", "3(%2)")"\n\t" \ 251 + "sll\t%0, 0x8\n\t" \ 252 + "or\t%0, $1\n\t" \ 253 + "li\t%1, 0\n" \ 254 + ".set\tpop\n" \ 255 + "10:\n\t" \ 256 + ".insn\n\t" \ 257 + ".section\t.fixup,\"ax\"\n\t" \ 258 + "11:\tli\t%1, %3\n\t" \ 259 + "j\t10b\n\t" \ 260 + ".previous\n\t" \ 261 + ".section\t__ex_table,\"a\"\n\t" \ 262 + STR(PTR)"\t1b, 11b\n\t" \ 263 + STR(PTR)"\t2b, 11b\n\t" \ 264 + STR(PTR)"\t3b, 11b\n\t" \ 265 + STR(PTR)"\t4b, 11b\n\t" \ 266 + ".previous" \ 267 + : "=&r" (value), "=r" (res) \ 268 + : "r" (addr), "i" (-EFAULT)); \ 269 + } while (0) 270 + 271 + #define _LoadDW(addr, value, res) \ 272 + do { \ 273 + __asm__ __volatile__ ( \ 274 + ".set\tpush\n\t" \ 275 + ".set\tnoat\n\t" \ 276 + "1:lb\t%0, 0(%2)\n\t" \ 277 + "2:lbu\t $1, 1(%2)\n\t" \ 278 + "dsll\t%0, 0x8\n\t" \ 279 + "or\t%0, $1\n\t" \ 280 + "3:lbu\t$1, 2(%2)\n\t" \ 281 + "dsll\t%0, 0x8\n\t" \ 282 + "or\t%0, $1\n\t" \ 283 + "4:lbu\t$1, 3(%2)\n\t" \ 284 + "dsll\t%0, 0x8\n\t" \ 285 + "or\t%0, $1\n\t" \ 286 + "5:lbu\t$1, 4(%2)\n\t" \ 287 + "dsll\t%0, 0x8\n\t" \ 288 + "or\t%0, $1\n\t" \ 289 + "6:lbu\t$1, 5(%2)\n\t" \ 290 + "dsll\t%0, 0x8\n\t" \ 291 + "or\t%0, $1\n\t" \ 292 + "7:lbu\t$1, 6(%2)\n\t" \ 293 + "dsll\t%0, 0x8\n\t" \ 294 + "or\t%0, $1\n\t" \ 295 + "8:lbu\t$1, 7(%2)\n\t" \ 296 + "dsll\t%0, 0x8\n\t" \ 297 + "or\t%0, $1\n\t" \ 298 + "li\t%1, 0\n" \ 299 + ".set\tpop\n\t" \ 300 + "10:\n\t" \ 301 + ".insn\n\t" \ 302 + ".section\t.fixup,\"ax\"\n\t" \ 303 + "11:\tli\t%1, %3\n\t" \ 304 + "j\t10b\n\t" \ 305 + ".previous\n\t" \ 306 + ".section\t__ex_table,\"a\"\n\t" \ 307 + STR(PTR)"\t1b, 11b\n\t" \ 308 + STR(PTR)"\t2b, 11b\n\t" \ 309 + STR(PTR)"\t3b, 11b\n\t" \ 310 + STR(PTR)"\t4b, 11b\n\t" \ 311 + STR(PTR)"\t5b, 11b\n\t" \ 312 + STR(PTR)"\t6b, 11b\n\t" \ 313 + STR(PTR)"\t7b, 11b\n\t" \ 314 + STR(PTR)"\t8b, 11b\n\t" \ 315 + ".previous" \ 316 + : "=&r" (value), "=r" (res) \ 317 + : "r" (addr), "i" (-EFAULT)); \ 318 + } while (0) 319 + 320 + #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 321 + 322 + 323 + #define _StoreHW(addr, value, res, type) \ 324 + do { \ 325 + __asm__ __volatile__ ( \ 326 + ".set\tnoat\n" \ 327 + "1:\t"type##_sb("%1", "1(%2)")"\n" \ 328 + "srl\t$1, %1, 0x8\n" \ 329 + "2:\t"type##_sb("$1", "0(%2)")"\n" \ 330 + ".set\tat\n\t" \ 331 + "li\t%0, 0\n" \ 332 + "3:\n\t" \ 333 + ".insn\n\t" \ 334 + ".section\t.fixup,\"ax\"\n\t" \ 335 + "4:\tli\t%0, %3\n\t" \ 336 + "j\t3b\n\t" \ 337 + ".previous\n\t" \ 338 + ".section\t__ex_table,\"a\"\n\t" \ 339 + STR(PTR)"\t1b, 4b\n\t" \ 340 + STR(PTR)"\t2b, 4b\n\t" \ 341 + ".previous" \ 342 + : "=r" (res) \ 343 + : "r" (value), "r" (addr), "i" (-EFAULT));\ 344 + } while (0) 345 + 346 + #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 347 + #define _StoreW(addr, value, res, type) \ 348 + do { \ 349 + __asm__ __volatile__ ( \ 350 + "1:\t"type##_swl("%1", "(%2)")"\n" \ 351 + "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ 352 + "li\t%0, 0\n" \ 353 + "3:\n\t" \ 354 + ".insn\n\t" \ 355 + ".section\t.fixup,\"ax\"\n\t" \ 356 + "4:\tli\t%0, %3\n\t" \ 357 + "j\t3b\n\t" \ 358 + ".previous\n\t" \ 359 + ".section\t__ex_table,\"a\"\n\t" \ 360 + STR(PTR)"\t1b, 4b\n\t" \ 361 + STR(PTR)"\t2b, 4b\n\t" \ 362 + ".previous" \ 363 + : "=r" (res) \ 364 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 365 + } while (0) 366 + 367 + #define _StoreDW(addr, value, res) \ 368 + do { \ 369 + __asm__ __volatile__ ( \ 370 + "1:\tsdl\t%1,(%2)\n" \ 371 + "2:\tsdr\t%1, 7(%2)\n\t" \ 372 + "li\t%0, 0\n" \ 373 + "3:\n\t" \ 374 + ".insn\n\t" \ 375 + ".section\t.fixup,\"ax\"\n\t" \ 376 + "4:\tli\t%0, %3\n\t" \ 377 + "j\t3b\n\t" \ 378 + ".previous\n\t" \ 379 + ".section\t__ex_table,\"a\"\n\t" \ 380 + STR(PTR)"\t1b, 4b\n\t" \ 381 + STR(PTR)"\t2b, 4b\n\t" \ 382 + ".previous" \ 383 + : "=r" (res) \ 384 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 385 + } while (0) 386 + 387 + #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 388 + #define _StoreW(addr, value, res, type) \ 389 + do { \ 390 + __asm__ __volatile__ ( \ 391 + ".set\tpush\n\t" \ 392 + ".set\tnoat\n\t" \ 393 + "1:"type##_sb("%1", "3(%2)")"\n\t" \ 394 + "srl\t$1, %1, 0x8\n\t" \ 395 + "2:"type##_sb("$1", "2(%2)")"\n\t" \ 396 + "srl\t$1, $1, 0x8\n\t" \ 397 + "3:"type##_sb("$1", "1(%2)")"\n\t" \ 398 + "srl\t$1, $1, 0x8\n\t" \ 399 + "4:"type##_sb("$1", "0(%2)")"\n\t" \ 400 + ".set\tpop\n\t" \ 401 + "li\t%0, 0\n" \ 402 + "10:\n\t" \ 403 + ".insn\n\t" \ 404 + ".section\t.fixup,\"ax\"\n\t" \ 405 + "11:\tli\t%0, %3\n\t" \ 406 + "j\t10b\n\t" \ 407 + ".previous\n\t" \ 408 + ".section\t__ex_table,\"a\"\n\t" \ 409 + STR(PTR)"\t1b, 11b\n\t" \ 410 + STR(PTR)"\t2b, 11b\n\t" \ 411 + STR(PTR)"\t3b, 11b\n\t" \ 412 + STR(PTR)"\t4b, 11b\n\t" \ 413 + ".previous" \ 414 + : "=&r" (res) \ 415 + : "r" (value), "r" (addr), "i" (-EFAULT) \ 416 + : "memory"); \ 417 + } while (0) 418 + 419 + #define _StoreDW(addr, value, res) \ 420 + do { \ 421 + __asm__ __volatile__ ( \ 422 + ".set\tpush\n\t" \ 423 + ".set\tnoat\n\t" \ 424 + "1:sb\t%1, 7(%2)\n\t" \ 425 + "dsrl\t$1, %1, 0x8\n\t" \ 426 + "2:sb\t$1, 6(%2)\n\t" \ 427 + "dsrl\t$1, $1, 0x8\n\t" \ 428 + "3:sb\t$1, 5(%2)\n\t" \ 429 + "dsrl\t$1, $1, 0x8\n\t" \ 430 + "4:sb\t$1, 4(%2)\n\t" \ 431 + "dsrl\t$1, $1, 0x8\n\t" \ 432 + "5:sb\t$1, 3(%2)\n\t" \ 433 + "dsrl\t$1, $1, 0x8\n\t" \ 434 + "6:sb\t$1, 2(%2)\n\t" \ 435 + "dsrl\t$1, $1, 0x8\n\t" \ 436 + "7:sb\t$1, 1(%2)\n\t" \ 437 + "dsrl\t$1, $1, 0x8\n\t" \ 438 + "8:sb\t$1, 0(%2)\n\t" \ 439 + "dsrl\t$1, $1, 0x8\n\t" \ 440 + ".set\tpop\n\t" \ 441 + "li\t%0, 0\n" \ 442 + "10:\n\t" \ 443 + ".insn\n\t" \ 444 + ".section\t.fixup,\"ax\"\n\t" \ 445 + "11:\tli\t%0, %3\n\t" \ 446 + "j\t10b\n\t" \ 447 + ".previous\n\t" \ 448 + ".section\t__ex_table,\"a\"\n\t" \ 449 + STR(PTR)"\t1b, 11b\n\t" \ 450 + STR(PTR)"\t2b, 11b\n\t" \ 451 + STR(PTR)"\t3b, 11b\n\t" \ 452 + STR(PTR)"\t4b, 11b\n\t" \ 453 + STR(PTR)"\t5b, 11b\n\t" \ 454 + STR(PTR)"\t6b, 11b\n\t" \ 455 + STR(PTR)"\t7b, 11b\n\t" \ 456 + STR(PTR)"\t8b, 11b\n\t" \ 457 + ".previous" \ 458 + : "=&r" (res) \ 459 + : "r" (value), "r" (addr), "i" (-EFAULT) \ 460 + : "memory"); \ 461 + } while (0) 462 + 463 + #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 464 + 465 + #else /* __BIG_ENDIAN */ 466 + 467 + #define _LoadHW(addr, value, res, type) \ 468 + do { \ 469 + __asm__ __volatile__ (".set\tnoat\n" \ 470 + "1:\t"type##_lb("%0", "1(%2)")"\n" \ 471 + "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ 472 + "sll\t%0, 0x8\n\t" \ 473 + "or\t%0, $1\n\t" \ 474 + "li\t%1, 0\n" \ 475 + "3:\t.set\tat\n\t" \ 476 + ".insn\n\t" \ 477 + ".section\t.fixup,\"ax\"\n\t" \ 478 + "4:\tli\t%1, %3\n\t" \ 479 + "j\t3b\n\t" \ 480 + ".previous\n\t" \ 481 + ".section\t__ex_table,\"a\"\n\t" \ 482 + STR(PTR)"\t1b, 4b\n\t" \ 483 + STR(PTR)"\t2b, 4b\n\t" \ 484 + ".previous" \ 485 + : "=&r" (value), "=r" (res) \ 486 + : "r" (addr), "i" (-EFAULT)); \ 487 + } while (0) 488 + 489 + #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 490 + #define _LoadW(addr, value, res, type) \ 491 + do { \ 492 + __asm__ __volatile__ ( \ 493 + "1:\t"type##_lwl("%0", "3(%2)")"\n" \ 494 + "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ 495 + "li\t%1, 0\n" \ 496 + "3:\n\t" \ 497 + ".insn\n\t" \ 498 + ".section\t.fixup,\"ax\"\n\t" \ 499 + "4:\tli\t%1, %3\n\t" \ 500 + "j\t3b\n\t" \ 501 + ".previous\n\t" \ 502 + ".section\t__ex_table,\"a\"\n\t" \ 503 + STR(PTR)"\t1b, 4b\n\t" \ 504 + STR(PTR)"\t2b, 4b\n\t" \ 505 + ".previous" \ 506 + : "=&r" (value), "=r" (res) \ 507 + : "r" (addr), "i" (-EFAULT)); \ 508 + } while (0) 509 + 510 + #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 511 + /* For CPUs without lwl instruction */ 512 + #define _LoadW(addr, value, res, type) \ 513 + do { \ 514 + __asm__ __volatile__ ( \ 515 + ".set\tpush\n" \ 516 + ".set\tnoat\n\t" \ 517 + "1:"type##_lb("%0", "3(%2)")"\n\t" \ 518 + "2:"type##_lbu("$1", "2(%2)")"\n\t" \ 519 + "sll\t%0, 0x8\n\t" \ 520 + "or\t%0, $1\n\t" \ 521 + "3:"type##_lbu("$1", "1(%2)")"\n\t" \ 522 + "sll\t%0, 0x8\n\t" \ 523 + "or\t%0, $1\n\t" \ 524 + "4:"type##_lbu("$1", "0(%2)")"\n\t" \ 525 + "sll\t%0, 0x8\n\t" \ 526 + "or\t%0, $1\n\t" \ 527 + "li\t%1, 0\n" \ 528 + ".set\tpop\n" \ 529 + "10:\n\t" \ 530 + ".insn\n\t" \ 531 + ".section\t.fixup,\"ax\"\n\t" \ 532 + "11:\tli\t%1, %3\n\t" \ 533 + "j\t10b\n\t" \ 534 + ".previous\n\t" \ 535 + ".section\t__ex_table,\"a\"\n\t" \ 536 + STR(PTR)"\t1b, 11b\n\t" \ 537 + STR(PTR)"\t2b, 11b\n\t" \ 538 + STR(PTR)"\t3b, 11b\n\t" \ 539 + STR(PTR)"\t4b, 11b\n\t" \ 540 + ".previous" \ 541 + : "=&r" (value), "=r" (res) \ 542 + : "r" (addr), "i" (-EFAULT)); \ 543 + } while (0) 544 + 545 + #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 546 + 547 + 548 + #define _LoadHWU(addr, value, res, type) \ 549 + do { \ 550 + __asm__ __volatile__ ( \ 551 + ".set\tnoat\n" \ 552 + "1:\t"type##_lbu("%0", "1(%2)")"\n" \ 553 + "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ 554 + "sll\t%0, 0x8\n\t" \ 555 + "or\t%0, $1\n\t" \ 556 + "li\t%1, 0\n" \ 557 + "3:\n\t" \ 558 + ".insn\n\t" \ 559 + ".set\tat\n\t" \ 560 + ".section\t.fixup,\"ax\"\n\t" \ 561 + "4:\tli\t%1, %3\n\t" \ 562 + "j\t3b\n\t" \ 563 + ".previous\n\t" \ 564 + ".section\t__ex_table,\"a\"\n\t" \ 565 + STR(PTR)"\t1b, 4b\n\t" \ 566 + STR(PTR)"\t2b, 4b\n\t" \ 567 + ".previous" \ 568 + : "=&r" (value), "=r" (res) \ 569 + : "r" (addr), "i" (-EFAULT)); \ 570 + } while (0) 571 + 572 + #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 573 + #define _LoadWU(addr, value, res, type) \ 574 + do { \ 575 + __asm__ __volatile__ ( \ 576 + "1:\t"type##_lwl("%0", "3(%2)")"\n" \ 577 + "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ 578 + "dsll\t%0, %0, 32\n\t" \ 579 + "dsrl\t%0, %0, 32\n\t" \ 580 + "li\t%1, 0\n" \ 581 + "3:\n\t" \ 582 + ".insn\n\t" \ 583 + "\t.section\t.fixup,\"ax\"\n\t" \ 584 + "4:\tli\t%1, %3\n\t" \ 585 + "j\t3b\n\t" \ 586 + ".previous\n\t" \ 587 + ".section\t__ex_table,\"a\"\n\t" \ 588 + STR(PTR)"\t1b, 4b\n\t" \ 589 + STR(PTR)"\t2b, 4b\n\t" \ 590 + ".previous" \ 591 + : "=&r" (value), "=r" (res) \ 592 + : "r" (addr), "i" (-EFAULT)); \ 593 + } while (0) 594 + 595 + #define _LoadDW(addr, value, res) \ 596 + do { \ 597 + __asm__ __volatile__ ( \ 598 + "1:\tldl\t%0, 7(%2)\n" \ 599 + "2:\tldr\t%0, (%2)\n\t" \ 600 + "li\t%1, 0\n" \ 601 + "3:\n\t" \ 602 + ".insn\n\t" \ 603 + "\t.section\t.fixup,\"ax\"\n\t" \ 604 + "4:\tli\t%1, %3\n\t" \ 605 + "j\t3b\n\t" \ 606 + ".previous\n\t" \ 607 + ".section\t__ex_table,\"a\"\n\t" \ 608 + STR(PTR)"\t1b, 4b\n\t" \ 609 + STR(PTR)"\t2b, 4b\n\t" \ 610 + ".previous" \ 611 + : "=&r" (value), "=r" (res) \ 612 + : "r" (addr), "i" (-EFAULT)); \ 613 + } while (0) 614 + 615 + #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 616 + /* For CPUs without lwl and ldl instructions */ 617 + #define _LoadWU(addr, value, res, type) \ 618 + do { \ 619 + __asm__ __volatile__ ( \ 620 + ".set\tpush\n\t" \ 621 + ".set\tnoat\n\t" \ 622 + "1:"type##_lbu("%0", "3(%2)")"\n\t" \ 623 + "2:"type##_lbu("$1", "2(%2)")"\n\t" \ 624 + "sll\t%0, 0x8\n\t" \ 625 + "or\t%0, $1\n\t" \ 626 + "3:"type##_lbu("$1", "1(%2)")"\n\t" \ 627 + "sll\t%0, 0x8\n\t" \ 628 + "or\t%0, $1\n\t" \ 629 + "4:"type##_lbu("$1", "0(%2)")"\n\t" \ 630 + "sll\t%0, 0x8\n\t" \ 631 + "or\t%0, $1\n\t" \ 632 + "li\t%1, 0\n" \ 633 + ".set\tpop\n" \ 634 + "10:\n\t" \ 635 + ".insn\n\t" \ 636 + ".section\t.fixup,\"ax\"\n\t" \ 637 + "11:\tli\t%1, %3\n\t" \ 638 + "j\t10b\n\t" \ 639 + ".previous\n\t" \ 640 + ".section\t__ex_table,\"a\"\n\t" \ 641 + STR(PTR)"\t1b, 11b\n\t" \ 642 + STR(PTR)"\t2b, 11b\n\t" \ 643 + STR(PTR)"\t3b, 11b\n\t" \ 644 + STR(PTR)"\t4b, 11b\n\t" \ 645 + ".previous" \ 646 + : "=&r" (value), "=r" (res) \ 647 + : "r" (addr), "i" (-EFAULT)); \ 648 + } while (0) 649 + 650 + #define _LoadDW(addr, value, res) \ 651 + do { \ 652 + __asm__ __volatile__ ( \ 653 + ".set\tpush\n\t" \ 654 + ".set\tnoat\n\t" \ 655 + "1:lb\t%0, 7(%2)\n\t" \ 656 + "2:lbu\t$1, 6(%2)\n\t" \ 657 + "dsll\t%0, 0x8\n\t" \ 658 + "or\t%0, $1\n\t" \ 659 + "3:lbu\t$1, 5(%2)\n\t" \ 660 + "dsll\t%0, 0x8\n\t" \ 661 + "or\t%0, $1\n\t" \ 662 + "4:lbu\t$1, 4(%2)\n\t" \ 663 + "dsll\t%0, 0x8\n\t" \ 664 + "or\t%0, $1\n\t" \ 665 + "5:lbu\t$1, 3(%2)\n\t" \ 666 + "dsll\t%0, 0x8\n\t" \ 667 + "or\t%0, $1\n\t" \ 668 + "6:lbu\t$1, 2(%2)\n\t" \ 669 + "dsll\t%0, 0x8\n\t" \ 670 + "or\t%0, $1\n\t" \ 671 + "7:lbu\t$1, 1(%2)\n\t" \ 672 + "dsll\t%0, 0x8\n\t" \ 673 + "or\t%0, $1\n\t" \ 674 + "8:lbu\t$1, 0(%2)\n\t" \ 675 + "dsll\t%0, 0x8\n\t" \ 676 + "or\t%0, $1\n\t" \ 677 + "li\t%1, 0\n" \ 678 + ".set\tpop\n\t" \ 679 + "10:\n\t" \ 680 + ".insn\n\t" \ 681 + ".section\t.fixup,\"ax\"\n\t" \ 682 + "11:\tli\t%1, %3\n\t" \ 683 + "j\t10b\n\t" \ 684 + ".previous\n\t" \ 685 + ".section\t__ex_table,\"a\"\n\t" \ 686 + STR(PTR)"\t1b, 11b\n\t" \ 687 + STR(PTR)"\t2b, 11b\n\t" \ 688 + STR(PTR)"\t3b, 11b\n\t" \ 689 + STR(PTR)"\t4b, 11b\n\t" \ 690 + STR(PTR)"\t5b, 11b\n\t" \ 691 + STR(PTR)"\t6b, 11b\n\t" \ 692 + STR(PTR)"\t7b, 11b\n\t" \ 693 + STR(PTR)"\t8b, 11b\n\t" \ 694 + ".previous" \ 695 + : "=&r" (value), "=r" (res) \ 696 + : "r" (addr), "i" (-EFAULT)); \ 697 + } while (0) 698 + #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 699 + 700 + #define _StoreHW(addr, value, res, type) \ 701 + do { \ 702 + __asm__ __volatile__ ( \ 703 + ".set\tnoat\n" \ 704 + "1:\t"type##_sb("%1", "0(%2)")"\n" \ 705 + "srl\t$1,%1, 0x8\n" \ 706 + "2:\t"type##_sb("$1", "1(%2)")"\n" \ 707 + ".set\tat\n\t" \ 708 + "li\t%0, 0\n" \ 709 + "3:\n\t" \ 710 + ".insn\n\t" \ 711 + ".section\t.fixup,\"ax\"\n\t" \ 712 + "4:\tli\t%0, %3\n\t" \ 713 + "j\t3b\n\t" \ 714 + ".previous\n\t" \ 715 + ".section\t__ex_table,\"a\"\n\t" \ 716 + STR(PTR)"\t1b, 4b\n\t" \ 717 + STR(PTR)"\t2b, 4b\n\t" \ 718 + ".previous" \ 719 + : "=r" (res) \ 720 + : "r" (value), "r" (addr), "i" (-EFAULT));\ 721 + } while (0) 722 + 723 + #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 724 + #define _StoreW(addr, value, res, type) \ 725 + do { \ 726 + __asm__ __volatile__ ( \ 727 + "1:\t"type##_swl("%1", "3(%2)")"\n" \ 728 + "2:\t"type##_swr("%1", "(%2)")"\n\t"\ 729 + "li\t%0, 0\n" \ 730 + "3:\n\t" \ 731 + ".insn\n\t" \ 732 + ".section\t.fixup,\"ax\"\n\t" \ 733 + "4:\tli\t%0, %3\n\t" \ 734 + "j\t3b\n\t" \ 735 + ".previous\n\t" \ 736 + ".section\t__ex_table,\"a\"\n\t" \ 737 + STR(PTR)"\t1b, 4b\n\t" \ 738 + STR(PTR)"\t2b, 4b\n\t" \ 739 + ".previous" \ 740 + : "=r" (res) \ 741 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 742 + } while (0) 743 + 744 + #define _StoreDW(addr, value, res) \ 745 + do { \ 746 + __asm__ __volatile__ ( \ 747 + "1:\tsdl\t%1, 7(%2)\n" \ 748 + "2:\tsdr\t%1, (%2)\n\t" \ 749 + "li\t%0, 0\n" \ 750 + "3:\n\t" \ 751 + ".insn\n\t" \ 752 + ".section\t.fixup,\"ax\"\n\t" \ 753 + "4:\tli\t%0, %3\n\t" \ 754 + "j\t3b\n\t" \ 755 + ".previous\n\t" \ 756 + ".section\t__ex_table,\"a\"\n\t" \ 757 + STR(PTR)"\t1b, 4b\n\t" \ 758 + STR(PTR)"\t2b, 4b\n\t" \ 759 + ".previous" \ 760 + : "=r" (res) \ 761 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 762 + } while (0) 763 + 764 + #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 765 + /* For CPUs without swl and sdl instructions */ 766 + #define _StoreW(addr, value, res, type) \ 767 + do { \ 768 + __asm__ __volatile__ ( \ 769 + ".set\tpush\n\t" \ 770 + ".set\tnoat\n\t" \ 771 + "1:"type##_sb("%1", "0(%2)")"\n\t" \ 772 + "srl\t$1, %1, 0x8\n\t" \ 773 + "2:"type##_sb("$1", "1(%2)")"\n\t" \ 774 + "srl\t$1, $1, 0x8\n\t" \ 775 + "3:"type##_sb("$1", "2(%2)")"\n\t" \ 776 + "srl\t$1, $1, 0x8\n\t" \ 777 + "4:"type##_sb("$1", "3(%2)")"\n\t" \ 778 + ".set\tpop\n\t" \ 779 + "li\t%0, 0\n" \ 780 + "10:\n\t" \ 781 + ".insn\n\t" \ 782 + ".section\t.fixup,\"ax\"\n\t" \ 783 + "11:\tli\t%0, %3\n\t" \ 784 + "j\t10b\n\t" \ 785 + ".previous\n\t" \ 786 + ".section\t__ex_table,\"a\"\n\t" \ 787 + STR(PTR)"\t1b, 11b\n\t" \ 788 + STR(PTR)"\t2b, 11b\n\t" \ 789 + STR(PTR)"\t3b, 11b\n\t" \ 790 + STR(PTR)"\t4b, 11b\n\t" \ 791 + ".previous" \ 792 + : "=&r" (res) \ 793 + : "r" (value), "r" (addr), "i" (-EFAULT) \ 794 + : "memory"); \ 795 + } while (0) 796 + 797 + #define _StoreDW(addr, value, res) \ 798 + do { \ 799 + __asm__ __volatile__ ( \ 800 + ".set\tpush\n\t" \ 801 + ".set\tnoat\n\t" \ 802 + "1:sb\t%1, 0(%2)\n\t" \ 803 + "dsrl\t$1, %1, 0x8\n\t" \ 804 + "2:sb\t$1, 1(%2)\n\t" \ 805 + "dsrl\t$1, $1, 0x8\n\t" \ 806 + "3:sb\t$1, 2(%2)\n\t" \ 807 + "dsrl\t$1, $1, 0x8\n\t" \ 808 + "4:sb\t$1, 3(%2)\n\t" \ 809 + "dsrl\t$1, $1, 0x8\n\t" \ 810 + "5:sb\t$1, 4(%2)\n\t" \ 811 + "dsrl\t$1, $1, 0x8\n\t" \ 812 + "6:sb\t$1, 5(%2)\n\t" \ 813 + "dsrl\t$1, $1, 0x8\n\t" \ 814 + "7:sb\t$1, 6(%2)\n\t" \ 815 + "dsrl\t$1, $1, 0x8\n\t" \ 816 + "8:sb\t$1, 7(%2)\n\t" \ 817 + "dsrl\t$1, $1, 0x8\n\t" \ 818 + ".set\tpop\n\t" \ 819 + "li\t%0, 0\n" \ 820 + "10:\n\t" \ 821 + ".insn\n\t" \ 822 + ".section\t.fixup,\"ax\"\n\t" \ 823 + "11:\tli\t%0, %3\n\t" \ 824 + "j\t10b\n\t" \ 825 + ".previous\n\t" \ 826 + ".section\t__ex_table,\"a\"\n\t" \ 827 + STR(PTR)"\t1b, 11b\n\t" \ 828 + STR(PTR)"\t2b, 11b\n\t" \ 829 + STR(PTR)"\t3b, 11b\n\t" \ 830 + STR(PTR)"\t4b, 11b\n\t" \ 831 + STR(PTR)"\t5b, 11b\n\t" \ 832 + STR(PTR)"\t6b, 11b\n\t" \ 833 + STR(PTR)"\t7b, 11b\n\t" \ 834 + STR(PTR)"\t8b, 11b\n\t" \ 835 + ".previous" \ 836 + : "=&r" (res) \ 837 + : "r" (value), "r" (addr), "i" (-EFAULT) \ 838 + : "memory"); \ 839 + } while (0) 840 + 841 + #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 842 + #endif 843 + 844 + #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel) 845 + #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user) 846 + #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel) 847 + #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user) 848 + #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel) 849 + #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user) 850 + #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel) 851 + #define LoadWE(addr, value, res) _LoadW(addr, value, res, user) 852 + #define LoadDW(addr, value, res) _LoadDW(addr, value, res) 853 + 854 + #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel) 855 + #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user) 856 + #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel) 857 + #define StoreWE(addr, value, res) _StoreW(addr, value, res, user) 858 + #define StoreDW(addr, value, res) _StoreDW(addr, value, res) 88 859 89 860 #endif /* _ASM_INST_H */
-775
arch/mips/kernel/unaligned.c
··· 92 92 #include <asm/mmu_context.h> 93 93 #include <linux/uaccess.h> 94 94 95 - #define STR(x) __STR(x) 96 - #define __STR(x) #x 97 - 98 95 enum { 99 96 UNALIGNED_ACTION_QUIET, 100 97 UNALIGNED_ACTION_SIGNAL, ··· 104 107 #define unaligned_action UNALIGNED_ACTION_QUIET 105 108 #endif 106 109 extern void show_registers(struct pt_regs *regs); 107 - 108 - #ifdef __BIG_ENDIAN 109 - #define _LoadHW(addr, value, res, type) \ 110 - do { \ 111 - __asm__ __volatile__ (".set\tnoat\n" \ 112 - "1:\t"type##_lb("%0", "0(%2)")"\n" \ 113 - "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ 114 - "sll\t%0, 0x8\n\t" \ 115 - "or\t%0, $1\n\t" \ 116 - "li\t%1, 0\n" \ 117 - "3:\t.set\tat\n\t" \ 118 - ".insn\n\t" \ 119 - ".section\t.fixup,\"ax\"\n\t" \ 120 - "4:\tli\t%1, %3\n\t" \ 121 - "j\t3b\n\t" \ 122 - ".previous\n\t" \ 123 - ".section\t__ex_table,\"a\"\n\t" \ 124 - STR(PTR)"\t1b, 4b\n\t" \ 125 - STR(PTR)"\t2b, 4b\n\t" \ 126 - ".previous" \ 127 - : "=&r" (value), "=r" (res) \ 128 - : "r" (addr), "i" (-EFAULT)); \ 129 - } while(0) 130 - 131 - #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 132 - #define _LoadW(addr, value, res, type) \ 133 - do { \ 134 - __asm__ __volatile__ ( \ 135 - "1:\t"type##_lwl("%0", "(%2)")"\n" \ 136 - "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ 137 - "li\t%1, 0\n" \ 138 - "3:\n\t" \ 139 - ".insn\n\t" \ 140 - ".section\t.fixup,\"ax\"\n\t" \ 141 - "4:\tli\t%1, %3\n\t" \ 142 - "j\t3b\n\t" \ 143 - ".previous\n\t" \ 144 - ".section\t__ex_table,\"a\"\n\t" \ 145 - STR(PTR)"\t1b, 4b\n\t" \ 146 - STR(PTR)"\t2b, 4b\n\t" \ 147 - ".previous" \ 148 - : "=&r" (value), "=r" (res) \ 149 - : "r" (addr), "i" (-EFAULT)); \ 150 - } while(0) 151 - 152 - #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 153 - /* For CPUs without lwl instruction */ 154 - #define _LoadW(addr, value, res, type) \ 155 - do { \ 156 - __asm__ __volatile__ ( \ 157 - ".set\tpush\n" \ 158 - ".set\tnoat\n\t" \ 159 - "1:"type##_lb("%0", "0(%2)")"\n\t" \ 160 - "2:"type##_lbu("$1", "1(%2)")"\n\t" \ 161 - "sll\t%0, 0x8\n\t" \ 162 - "or\t%0, $1\n\t" \ 163 - "3:"type##_lbu("$1", "2(%2)")"\n\t" \ 164 - "sll\t%0, 0x8\n\t" \ 165 - "or\t%0, $1\n\t" \ 166 - "4:"type##_lbu("$1", "3(%2)")"\n\t" \ 167 - "sll\t%0, 0x8\n\t" \ 168 - "or\t%0, $1\n\t" \ 169 - "li\t%1, 0\n" \ 170 - ".set\tpop\n" \ 171 - "10:\n\t" \ 172 - ".insn\n\t" \ 173 - ".section\t.fixup,\"ax\"\n\t" \ 174 - "11:\tli\t%1, %3\n\t" \ 175 - "j\t10b\n\t" \ 176 - ".previous\n\t" \ 177 - ".section\t__ex_table,\"a\"\n\t" \ 178 - STR(PTR)"\t1b, 11b\n\t" \ 179 - STR(PTR)"\t2b, 11b\n\t" \ 180 - STR(PTR)"\t3b, 11b\n\t" \ 181 - STR(PTR)"\t4b, 11b\n\t" \ 182 - ".previous" \ 183 - : "=&r" (value), "=r" (res) \ 184 - : "r" (addr), "i" (-EFAULT)); \ 185 - } while(0) 186 - 187 - #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 188 - 189 - #define _LoadHWU(addr, value, res, type) \ 190 - do { \ 191 - __asm__ __volatile__ ( \ 192 - ".set\tnoat\n" \ 193 - "1:\t"type##_lbu("%0", "0(%2)")"\n" \ 194 - "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ 195 - "sll\t%0, 0x8\n\t" \ 196 - "or\t%0, $1\n\t" \ 197 - "li\t%1, 0\n" \ 198 - "3:\n\t" \ 199 - ".insn\n\t" \ 200 - ".set\tat\n\t" \ 201 - ".section\t.fixup,\"ax\"\n\t" \ 202 - "4:\tli\t%1, %3\n\t" \ 203 - "j\t3b\n\t" \ 204 - ".previous\n\t" \ 205 - ".section\t__ex_table,\"a\"\n\t" \ 206 - STR(PTR)"\t1b, 4b\n\t" \ 207 - STR(PTR)"\t2b, 4b\n\t" \ 208 - ".previous" \ 209 - : "=&r" (value), "=r" (res) \ 210 - : "r" (addr), "i" (-EFAULT)); \ 211 - } while(0) 212 - 213 - #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 214 - #define _LoadWU(addr, value, res, type) \ 215 - do { \ 216 - __asm__ __volatile__ ( \ 217 - "1:\t"type##_lwl("%0", "(%2)")"\n" \ 218 - "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ 219 - "dsll\t%0, %0, 32\n\t" \ 220 - "dsrl\t%0, %0, 32\n\t" \ 221 - "li\t%1, 0\n" \ 222 - "3:\n\t" \ 223 - ".insn\n\t" \ 224 - "\t.section\t.fixup,\"ax\"\n\t" \ 225 - "4:\tli\t%1, %3\n\t" \ 226 - "j\t3b\n\t" \ 227 - ".previous\n\t" \ 228 - ".section\t__ex_table,\"a\"\n\t" \ 229 - STR(PTR)"\t1b, 4b\n\t" \ 230 - STR(PTR)"\t2b, 4b\n\t" \ 231 - ".previous" \ 232 - : "=&r" (value), "=r" (res) \ 233 - : "r" (addr), "i" (-EFAULT)); \ 234 - } while(0) 235 - 236 - #define _LoadDW(addr, value, res) \ 237 - do { \ 238 - __asm__ __volatile__ ( \ 239 - "1:\tldl\t%0, (%2)\n" \ 240 - "2:\tldr\t%0, 7(%2)\n\t" \ 241 - "li\t%1, 0\n" \ 242 - "3:\n\t" \ 243 - ".insn\n\t" \ 244 - "\t.section\t.fixup,\"ax\"\n\t" \ 245 - "4:\tli\t%1, %3\n\t" \ 246 - "j\t3b\n\t" \ 247 - ".previous\n\t" \ 248 - ".section\t__ex_table,\"a\"\n\t" \ 249 - STR(PTR)"\t1b, 4b\n\t" \ 250 - STR(PTR)"\t2b, 4b\n\t" \ 251 - ".previous" \ 252 - : "=&r" (value), "=r" (res) \ 253 - : "r" (addr), "i" (-EFAULT)); \ 254 - } while(0) 255 - 256 - #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 257 - /* For CPUs without lwl and ldl instructions */ 258 - #define _LoadWU(addr, value, res, type) \ 259 - do { \ 260 - __asm__ __volatile__ ( \ 261 - ".set\tpush\n\t" \ 262 - ".set\tnoat\n\t" \ 263 - "1:"type##_lbu("%0", "0(%2)")"\n\t" \ 264 - "2:"type##_lbu("$1", "1(%2)")"\n\t" \ 265 - "sll\t%0, 0x8\n\t" \ 266 - "or\t%0, $1\n\t" \ 267 - "3:"type##_lbu("$1", "2(%2)")"\n\t" \ 268 - "sll\t%0, 0x8\n\t" \ 269 - "or\t%0, $1\n\t" \ 270 - "4:"type##_lbu("$1", "3(%2)")"\n\t" \ 271 - "sll\t%0, 0x8\n\t" \ 272 - "or\t%0, $1\n\t" \ 273 - "li\t%1, 0\n" \ 274 - ".set\tpop\n" \ 275 - "10:\n\t" \ 276 - ".insn\n\t" \ 277 - ".section\t.fixup,\"ax\"\n\t" \ 278 - "11:\tli\t%1, %3\n\t" \ 279 - "j\t10b\n\t" \ 280 - ".previous\n\t" \ 281 - ".section\t__ex_table,\"a\"\n\t" \ 282 - STR(PTR)"\t1b, 11b\n\t" \ 283 - STR(PTR)"\t2b, 11b\n\t" \ 284 - STR(PTR)"\t3b, 11b\n\t" \ 285 - STR(PTR)"\t4b, 11b\n\t" \ 286 - ".previous" \ 287 - : "=&r" (value), "=r" (res) \ 288 - : "r" (addr), "i" (-EFAULT)); \ 289 - } while(0) 290 - 291 - #define _LoadDW(addr, value, res) \ 292 - do { \ 293 - __asm__ __volatile__ ( \ 294 - ".set\tpush\n\t" \ 295 - ".set\tnoat\n\t" \ 296 - "1:lb\t%0, 0(%2)\n\t" \ 297 - "2:lbu\t $1, 1(%2)\n\t" \ 298 - "dsll\t%0, 0x8\n\t" \ 299 - "or\t%0, $1\n\t" \ 300 - "3:lbu\t$1, 2(%2)\n\t" \ 301 - "dsll\t%0, 0x8\n\t" \ 302 - "or\t%0, $1\n\t" \ 303 - "4:lbu\t$1, 3(%2)\n\t" \ 304 - "dsll\t%0, 0x8\n\t" \ 305 - "or\t%0, $1\n\t" \ 306 - "5:lbu\t$1, 4(%2)\n\t" \ 307 - "dsll\t%0, 0x8\n\t" \ 308 - "or\t%0, $1\n\t" \ 309 - "6:lbu\t$1, 5(%2)\n\t" \ 310 - "dsll\t%0, 0x8\n\t" \ 311 - "or\t%0, $1\n\t" \ 312 - "7:lbu\t$1, 6(%2)\n\t" \ 313 - "dsll\t%0, 0x8\n\t" \ 314 - "or\t%0, $1\n\t" \ 315 - "8:lbu\t$1, 7(%2)\n\t" \ 316 - "dsll\t%0, 0x8\n\t" \ 317 - "or\t%0, $1\n\t" \ 318 - "li\t%1, 0\n" \ 319 - ".set\tpop\n\t" \ 320 - "10:\n\t" \ 321 - ".insn\n\t" \ 322 - ".section\t.fixup,\"ax\"\n\t" \ 323 - "11:\tli\t%1, %3\n\t" \ 324 - "j\t10b\n\t" \ 325 - ".previous\n\t" \ 326 - ".section\t__ex_table,\"a\"\n\t" \ 327 - STR(PTR)"\t1b, 11b\n\t" \ 328 - STR(PTR)"\t2b, 11b\n\t" \ 329 - STR(PTR)"\t3b, 11b\n\t" \ 330 - STR(PTR)"\t4b, 11b\n\t" \ 331 - STR(PTR)"\t5b, 11b\n\t" \ 332 - STR(PTR)"\t6b, 11b\n\t" \ 333 - STR(PTR)"\t7b, 11b\n\t" \ 334 - STR(PTR)"\t8b, 11b\n\t" \ 335 - ".previous" \ 336 - : "=&r" (value), "=r" (res) \ 337 - : "r" (addr), "i" (-EFAULT)); \ 338 - } while(0) 339 - 340 - #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 341 - 342 - 343 - #define _StoreHW(addr, value, res, type) \ 344 - do { \ 345 - __asm__ __volatile__ ( \ 346 - ".set\tnoat\n" \ 347 - "1:\t"type##_sb("%1", "1(%2)")"\n" \ 348 - "srl\t$1, %1, 0x8\n" \ 349 - "2:\t"type##_sb("$1", "0(%2)")"\n" \ 350 - ".set\tat\n\t" \ 351 - "li\t%0, 0\n" \ 352 - "3:\n\t" \ 353 - ".insn\n\t" \ 354 - ".section\t.fixup,\"ax\"\n\t" \ 355 - "4:\tli\t%0, %3\n\t" \ 356 - "j\t3b\n\t" \ 357 - ".previous\n\t" \ 358 - ".section\t__ex_table,\"a\"\n\t" \ 359 - STR(PTR)"\t1b, 4b\n\t" \ 360 - STR(PTR)"\t2b, 4b\n\t" \ 361 - ".previous" \ 362 - : "=r" (res) \ 363 - : "r" (value), "r" (addr), "i" (-EFAULT));\ 364 - } while(0) 365 - 366 - #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 367 - #define _StoreW(addr, value, res, type) \ 368 - do { \ 369 - __asm__ __volatile__ ( \ 370 - "1:\t"type##_swl("%1", "(%2)")"\n" \ 371 - "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ 372 - "li\t%0, 0\n" \ 373 - "3:\n\t" \ 374 - ".insn\n\t" \ 375 - ".section\t.fixup,\"ax\"\n\t" \ 376 - "4:\tli\t%0, %3\n\t" \ 377 - "j\t3b\n\t" \ 378 - ".previous\n\t" \ 379 - ".section\t__ex_table,\"a\"\n\t" \ 380 - STR(PTR)"\t1b, 4b\n\t" \ 381 - STR(PTR)"\t2b, 4b\n\t" \ 382 - ".previous" \ 383 - : "=r" (res) \ 384 - : "r" (value), "r" (addr), "i" (-EFAULT)); \ 385 - } while(0) 386 - 387 - #define _StoreDW(addr, value, res) \ 388 - do { \ 389 - __asm__ __volatile__ ( \ 390 - "1:\tsdl\t%1,(%2)\n" \ 391 - "2:\tsdr\t%1, 7(%2)\n\t" \ 392 - "li\t%0, 0\n" \ 393 - "3:\n\t" \ 394 - ".insn\n\t" \ 395 - ".section\t.fixup,\"ax\"\n\t" \ 396 - "4:\tli\t%0, %3\n\t" \ 397 - "j\t3b\n\t" \ 398 - ".previous\n\t" \ 399 - ".section\t__ex_table,\"a\"\n\t" \ 400 - STR(PTR)"\t1b, 4b\n\t" \ 401 - STR(PTR)"\t2b, 4b\n\t" \ 402 - ".previous" \ 403 - : "=r" (res) \ 404 - : "r" (value), "r" (addr), "i" (-EFAULT)); \ 405 - } while(0) 406 - 407 - #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 408 - #define _StoreW(addr, value, res, type) \ 409 - do { \ 410 - __asm__ __volatile__ ( \ 411 - ".set\tpush\n\t" \ 412 - ".set\tnoat\n\t" \ 413 - "1:"type##_sb("%1", "3(%2)")"\n\t" \ 414 - "srl\t$1, %1, 0x8\n\t" \ 415 - "2:"type##_sb("$1", "2(%2)")"\n\t" \ 416 - "srl\t$1, $1, 0x8\n\t" \ 417 - "3:"type##_sb("$1", "1(%2)")"\n\t" \ 418 - "srl\t$1, $1, 0x8\n\t" \ 419 - "4:"type##_sb("$1", "0(%2)")"\n\t" \ 420 - ".set\tpop\n\t" \ 421 - "li\t%0, 0\n" \ 422 - "10:\n\t" \ 423 - ".insn\n\t" \ 424 - ".section\t.fixup,\"ax\"\n\t" \ 425 - "11:\tli\t%0, %3\n\t" \ 426 - "j\t10b\n\t" \ 427 - ".previous\n\t" \ 428 - ".section\t__ex_table,\"a\"\n\t" \ 429 - STR(PTR)"\t1b, 11b\n\t" \ 430 - STR(PTR)"\t2b, 11b\n\t" \ 431 - STR(PTR)"\t3b, 11b\n\t" \ 432 - STR(PTR)"\t4b, 11b\n\t" \ 433 - ".previous" \ 434 - : "=&r" (res) \ 435 - : "r" (value), "r" (addr), "i" (-EFAULT) \ 436 - : "memory"); \ 437 - } while(0) 438 - 439 - #define _StoreDW(addr, value, res) \ 440 - do { \ 441 - __asm__ __volatile__ ( \ 442 - ".set\tpush\n\t" \ 443 - ".set\tnoat\n\t" \ 444 - "1:sb\t%1, 7(%2)\n\t" \ 445 - "dsrl\t$1, %1, 0x8\n\t" \ 446 - "2:sb\t$1, 6(%2)\n\t" \ 447 - "dsrl\t$1, $1, 0x8\n\t" \ 448 - "3:sb\t$1, 5(%2)\n\t" \ 449 - "dsrl\t$1, $1, 0x8\n\t" \ 450 - "4:sb\t$1, 4(%2)\n\t" \ 451 - "dsrl\t$1, $1, 0x8\n\t" \ 452 - "5:sb\t$1, 3(%2)\n\t" \ 453 - "dsrl\t$1, $1, 0x8\n\t" \ 454 - "6:sb\t$1, 2(%2)\n\t" \ 455 - "dsrl\t$1, $1, 0x8\n\t" \ 456 - "7:sb\t$1, 1(%2)\n\t" \ 457 - "dsrl\t$1, $1, 0x8\n\t" \ 458 - "8:sb\t$1, 0(%2)\n\t" \ 459 - "dsrl\t$1, $1, 0x8\n\t" \ 460 - ".set\tpop\n\t" \ 461 - "li\t%0, 0\n" \ 462 - "10:\n\t" \ 463 - ".insn\n\t" \ 464 - ".section\t.fixup,\"ax\"\n\t" \ 465 - "11:\tli\t%0, %3\n\t" \ 466 - "j\t10b\n\t" \ 467 - ".previous\n\t" \ 468 - ".section\t__ex_table,\"a\"\n\t" \ 469 - STR(PTR)"\t1b, 11b\n\t" \ 470 - STR(PTR)"\t2b, 11b\n\t" \ 471 - STR(PTR)"\t3b, 11b\n\t" \ 472 - STR(PTR)"\t4b, 11b\n\t" \ 473 - STR(PTR)"\t5b, 11b\n\t" \ 474 - STR(PTR)"\t6b, 11b\n\t" \ 475 - STR(PTR)"\t7b, 11b\n\t" \ 476 - STR(PTR)"\t8b, 11b\n\t" \ 477 - ".previous" \ 478 - : "=&r" (res) \ 479 - : "r" (value), "r" (addr), "i" (-EFAULT) \ 480 - : "memory"); \ 481 - } while(0) 482 - 483 - #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 484 - 485 - #else /* __BIG_ENDIAN */ 486 - 487 - #define _LoadHW(addr, value, res, type) \ 488 - do { \ 489 - __asm__ __volatile__ (".set\tnoat\n" \ 490 - "1:\t"type##_lb("%0", "1(%2)")"\n" \ 491 - "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ 492 - "sll\t%0, 0x8\n\t" \ 493 - "or\t%0, $1\n\t" \ 494 - "li\t%1, 0\n" \ 495 - "3:\t.set\tat\n\t" \ 496 - ".insn\n\t" \ 497 - ".section\t.fixup,\"ax\"\n\t" \ 498 - "4:\tli\t%1, %3\n\t" \ 499 - "j\t3b\n\t" \ 500 - ".previous\n\t" \ 501 - ".section\t__ex_table,\"a\"\n\t" \ 502 - STR(PTR)"\t1b, 4b\n\t" \ 503 - STR(PTR)"\t2b, 4b\n\t" \ 504 - ".previous" \ 505 - : "=&r" (value), "=r" (res) \ 506 - : "r" (addr), "i" (-EFAULT)); \ 507 - } while(0) 508 - 509 - #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 510 - #define _LoadW(addr, value, res, type) \ 511 - do { \ 512 - __asm__ __volatile__ ( \ 513 - "1:\t"type##_lwl("%0", "3(%2)")"\n" \ 514 - "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ 515 - "li\t%1, 0\n" \ 516 - "3:\n\t" \ 517 - ".insn\n\t" \ 518 - ".section\t.fixup,\"ax\"\n\t" \ 519 - "4:\tli\t%1, %3\n\t" \ 520 - "j\t3b\n\t" \ 521 - ".previous\n\t" \ 522 - ".section\t__ex_table,\"a\"\n\t" \ 523 - STR(PTR)"\t1b, 4b\n\t" \ 524 - STR(PTR)"\t2b, 4b\n\t" \ 525 - ".previous" \ 526 - : "=&r" (value), "=r" (res) \ 527 - : "r" (addr), "i" (-EFAULT)); \ 528 - } while(0) 529 - 530 - #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 531 - /* For CPUs without lwl instruction */ 532 - #define _LoadW(addr, value, res, type) \ 533 - do { \ 534 - __asm__ __volatile__ ( \ 535 - ".set\tpush\n" \ 536 - ".set\tnoat\n\t" \ 537 - "1:"type##_lb("%0", "3(%2)")"\n\t" \ 538 - "2:"type##_lbu("$1", "2(%2)")"\n\t" \ 539 - "sll\t%0, 0x8\n\t" \ 540 - "or\t%0, $1\n\t" \ 541 - "3:"type##_lbu("$1", "1(%2)")"\n\t" \ 542 - "sll\t%0, 0x8\n\t" \ 543 - "or\t%0, $1\n\t" \ 544 - "4:"type##_lbu("$1", "0(%2)")"\n\t" \ 545 - "sll\t%0, 0x8\n\t" \ 546 - "or\t%0, $1\n\t" \ 547 - "li\t%1, 0\n" \ 548 - ".set\tpop\n" \ 549 - "10:\n\t" \ 550 - ".insn\n\t" \ 551 - ".section\t.fixup,\"ax\"\n\t" \ 552 - "11:\tli\t%1, %3\n\t" \ 553 - "j\t10b\n\t" \ 554 - ".previous\n\t" \ 555 - ".section\t__ex_table,\"a\"\n\t" \ 556 - STR(PTR)"\t1b, 11b\n\t" \ 557 - STR(PTR)"\t2b, 11b\n\t" \ 558 - STR(PTR)"\t3b, 11b\n\t" \ 559 - STR(PTR)"\t4b, 11b\n\t" \ 560 - ".previous" \ 561 - : "=&r" (value), "=r" (res) \ 562 - : "r" (addr), "i" (-EFAULT)); \ 563 - } while(0) 564 - 565 - #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 566 - 567 - 568 - #define _LoadHWU(addr, value, res, type) \ 569 - do { \ 570 - __asm__ __volatile__ ( \ 571 - ".set\tnoat\n" \ 572 - "1:\t"type##_lbu("%0", "1(%2)")"\n" \ 573 - "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ 574 - "sll\t%0, 0x8\n\t" \ 575 - "or\t%0, $1\n\t" \ 576 - "li\t%1, 0\n" \ 577 - "3:\n\t" \ 578 - ".insn\n\t" \ 579 - ".set\tat\n\t" \ 580 - ".section\t.fixup,\"ax\"\n\t" \ 581 - "4:\tli\t%1, %3\n\t" \ 582 - "j\t3b\n\t" \ 583 - ".previous\n\t" \ 584 - ".section\t__ex_table,\"a\"\n\t" \ 585 - STR(PTR)"\t1b, 4b\n\t" \ 586 - STR(PTR)"\t2b, 4b\n\t" \ 587 - ".previous" \ 588 - : "=&r" (value), "=r" (res) \ 589 - : "r" (addr), "i" (-EFAULT)); \ 590 - } while(0) 591 - 592 - #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 593 - #define _LoadWU(addr, value, res, type) \ 594 - do { \ 595 - __asm__ __volatile__ ( \ 596 - "1:\t"type##_lwl("%0", "3(%2)")"\n" \ 597 - "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ 598 - "dsll\t%0, %0, 32\n\t" \ 599 - "dsrl\t%0, %0, 32\n\t" \ 600 - "li\t%1, 0\n" \ 601 - "3:\n\t" \ 602 - ".insn\n\t" \ 603 - "\t.section\t.fixup,\"ax\"\n\t" \ 604 - "4:\tli\t%1, %3\n\t" \ 605 - "j\t3b\n\t" \ 606 - ".previous\n\t" \ 607 - ".section\t__ex_table,\"a\"\n\t" \ 608 - STR(PTR)"\t1b, 4b\n\t" \ 609 - STR(PTR)"\t2b, 4b\n\t" \ 610 - ".previous" \ 611 - : "=&r" (value), "=r" (res) \ 612 - : "r" (addr), "i" (-EFAULT)); \ 613 - } while(0) 614 - 615 - #define _LoadDW(addr, value, res) \ 616 - do { \ 617 - __asm__ __volatile__ ( \ 618 - "1:\tldl\t%0, 7(%2)\n" \ 619 - "2:\tldr\t%0, (%2)\n\t" \ 620 - "li\t%1, 0\n" \ 621 - "3:\n\t" \ 622 - ".insn\n\t" \ 623 - "\t.section\t.fixup,\"ax\"\n\t" \ 624 - "4:\tli\t%1, %3\n\t" \ 625 - "j\t3b\n\t" \ 626 - ".previous\n\t" \ 627 - ".section\t__ex_table,\"a\"\n\t" \ 628 - STR(PTR)"\t1b, 4b\n\t" \ 629 - STR(PTR)"\t2b, 4b\n\t" \ 630 - ".previous" \ 631 - : "=&r" (value), "=r" (res) \ 632 - : "r" (addr), "i" (-EFAULT)); \ 633 - } while(0) 634 - 635 - #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 636 - /* For CPUs without lwl and ldl instructions */ 637 - #define _LoadWU(addr, value, res, type) \ 638 - do { \ 639 - __asm__ __volatile__ ( \ 640 - ".set\tpush\n\t" \ 641 - ".set\tnoat\n\t" \ 642 - "1:"type##_lbu("%0", "3(%2)")"\n\t" \ 643 - "2:"type##_lbu("$1", "2(%2)")"\n\t" \ 644 - "sll\t%0, 0x8\n\t" \ 645 - "or\t%0, $1\n\t" \ 646 - "3:"type##_lbu("$1", "1(%2)")"\n\t" \ 647 - "sll\t%0, 0x8\n\t" \ 648 - "or\t%0, $1\n\t" \ 649 - "4:"type##_lbu("$1", "0(%2)")"\n\t" \ 650 - "sll\t%0, 0x8\n\t" \ 651 - "or\t%0, $1\n\t" \ 652 - "li\t%1, 0\n" \ 653 - ".set\tpop\n" \ 654 - "10:\n\t" \ 655 - ".insn\n\t" \ 656 - ".section\t.fixup,\"ax\"\n\t" \ 657 - "11:\tli\t%1, %3\n\t" \ 658 - "j\t10b\n\t" \ 659 - ".previous\n\t" \ 660 - ".section\t__ex_table,\"a\"\n\t" \ 661 - STR(PTR)"\t1b, 11b\n\t" \ 662 - STR(PTR)"\t2b, 11b\n\t" \ 663 - STR(PTR)"\t3b, 11b\n\t" \ 664 - STR(PTR)"\t4b, 11b\n\t" \ 665 - ".previous" \ 666 - : "=&r" (value), "=r" (res) \ 667 - : "r" (addr), "i" (-EFAULT)); \ 668 - } while(0) 669 - 670 - #define _LoadDW(addr, value, res) \ 671 - do { \ 672 - __asm__ __volatile__ ( \ 673 - ".set\tpush\n\t" \ 674 - ".set\tnoat\n\t" \ 675 - "1:lb\t%0, 7(%2)\n\t" \ 676 - "2:lbu\t$1, 6(%2)\n\t" \ 677 - "dsll\t%0, 0x8\n\t" \ 678 - "or\t%0, $1\n\t" \ 679 - "3:lbu\t$1, 5(%2)\n\t" \ 680 - "dsll\t%0, 0x8\n\t" \ 681 - "or\t%0, $1\n\t" \ 682 - "4:lbu\t$1, 4(%2)\n\t" \ 683 - "dsll\t%0, 0x8\n\t" \ 684 - "or\t%0, $1\n\t" \ 685 - "5:lbu\t$1, 3(%2)\n\t" \ 686 - "dsll\t%0, 0x8\n\t" \ 687 - "or\t%0, $1\n\t" \ 688 - "6:lbu\t$1, 2(%2)\n\t" \ 689 - "dsll\t%0, 0x8\n\t" \ 690 - "or\t%0, $1\n\t" \ 691 - "7:lbu\t$1, 1(%2)\n\t" \ 692 - "dsll\t%0, 0x8\n\t" \ 693 - "or\t%0, $1\n\t" \ 694 - "8:lbu\t$1, 0(%2)\n\t" \ 695 - "dsll\t%0, 0x8\n\t" \ 696 - "or\t%0, $1\n\t" \ 697 - "li\t%1, 0\n" \ 698 - ".set\tpop\n\t" \ 699 - "10:\n\t" \ 700 - ".insn\n\t" \ 701 - ".section\t.fixup,\"ax\"\n\t" \ 702 - "11:\tli\t%1, %3\n\t" \ 703 - "j\t10b\n\t" \ 704 - ".previous\n\t" \ 705 - ".section\t__ex_table,\"a\"\n\t" \ 706 - STR(PTR)"\t1b, 11b\n\t" \ 707 - STR(PTR)"\t2b, 11b\n\t" \ 708 - STR(PTR)"\t3b, 11b\n\t" \ 709 - STR(PTR)"\t4b, 11b\n\t" \ 710 - STR(PTR)"\t5b, 11b\n\t" \ 711 - STR(PTR)"\t6b, 11b\n\t" \ 712 - STR(PTR)"\t7b, 11b\n\t" \ 713 - STR(PTR)"\t8b, 11b\n\t" \ 714 - ".previous" \ 715 - : "=&r" (value), "=r" (res) \ 716 - : "r" (addr), "i" (-EFAULT)); \ 717 - } while(0) 718 - #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 719 - 720 - #define _StoreHW(addr, value, res, type) \ 721 - do { \ 722 - __asm__ __volatile__ ( \ 723 - ".set\tnoat\n" \ 724 - "1:\t"type##_sb("%1", "0(%2)")"\n" \ 725 - "srl\t$1,%1, 0x8\n" \ 726 - "2:\t"type##_sb("$1", "1(%2)")"\n" \ 727 - ".set\tat\n\t" \ 728 - "li\t%0, 0\n" \ 729 - "3:\n\t" \ 730 - ".insn\n\t" \ 731 - ".section\t.fixup,\"ax\"\n\t" \ 732 - "4:\tli\t%0, %3\n\t" \ 733 - "j\t3b\n\t" \ 734 - ".previous\n\t" \ 735 - ".section\t__ex_table,\"a\"\n\t" \ 736 - STR(PTR)"\t1b, 4b\n\t" \ 737 - STR(PTR)"\t2b, 4b\n\t" \ 738 - ".previous" \ 739 - : "=r" (res) \ 740 - : "r" (value), "r" (addr), "i" (-EFAULT));\ 741 - } while(0) 742 - 743 - #ifndef CONFIG_CPU_NO_LOAD_STORE_LR 744 - #define _StoreW(addr, value, res, type) \ 745 - do { \ 746 - __asm__ __volatile__ ( \ 747 - "1:\t"type##_swl("%1", "3(%2)")"\n" \ 748 - "2:\t"type##_swr("%1", "(%2)")"\n\t"\ 749 - "li\t%0, 0\n" \ 750 - "3:\n\t" \ 751 - ".insn\n\t" \ 752 - ".section\t.fixup,\"ax\"\n\t" \ 753 - "4:\tli\t%0, %3\n\t" \ 754 - "j\t3b\n\t" \ 755 - ".previous\n\t" \ 756 - ".section\t__ex_table,\"a\"\n\t" \ 757 - STR(PTR)"\t1b, 4b\n\t" \ 758 - STR(PTR)"\t2b, 4b\n\t" \ 759 - ".previous" \ 760 - : "=r" (res) \ 761 - : "r" (value), "r" (addr), "i" (-EFAULT)); \ 762 - } while(0) 763 - 764 - #define _StoreDW(addr, value, res) \ 765 - do { \ 766 - __asm__ __volatile__ ( \ 767 - "1:\tsdl\t%1, 7(%2)\n" \ 768 - "2:\tsdr\t%1, (%2)\n\t" \ 769 - "li\t%0, 0\n" \ 770 - "3:\n\t" \ 771 - ".insn\n\t" \ 772 - ".section\t.fixup,\"ax\"\n\t" \ 773 - "4:\tli\t%0, %3\n\t" \ 774 - "j\t3b\n\t" \ 775 - ".previous\n\t" \ 776 - ".section\t__ex_table,\"a\"\n\t" \ 777 - STR(PTR)"\t1b, 4b\n\t" \ 778 - STR(PTR)"\t2b, 4b\n\t" \ 779 - ".previous" \ 780 - : "=r" (res) \ 781 - : "r" (value), "r" (addr), "i" (-EFAULT)); \ 782 - } while(0) 783 - 784 - #else /* CONFIG_CPU_NO_LOAD_STORE_LR */ 785 - /* For CPUs without swl and sdl instructions */ 786 - #define _StoreW(addr, value, res, type) \ 787 - do { \ 788 - __asm__ __volatile__ ( \ 789 - ".set\tpush\n\t" \ 790 - ".set\tnoat\n\t" \ 791 - "1:"type##_sb("%1", "0(%2)")"\n\t" \ 792 - "srl\t$1, %1, 0x8\n\t" \ 793 - "2:"type##_sb("$1", "1(%2)")"\n\t" \ 794 - "srl\t$1, $1, 0x8\n\t" \ 795 - "3:"type##_sb("$1", "2(%2)")"\n\t" \ 796 - "srl\t$1, $1, 0x8\n\t" \ 797 - "4:"type##_sb("$1", "3(%2)")"\n\t" \ 798 - ".set\tpop\n\t" \ 799 - "li\t%0, 0\n" \ 800 - "10:\n\t" \ 801 - ".insn\n\t" \ 802 - ".section\t.fixup,\"ax\"\n\t" \ 803 - "11:\tli\t%0, %3\n\t" \ 804 - "j\t10b\n\t" \ 805 - ".previous\n\t" \ 806 - ".section\t__ex_table,\"a\"\n\t" \ 807 - STR(PTR)"\t1b, 11b\n\t" \ 808 - STR(PTR)"\t2b, 11b\n\t" \ 809 - STR(PTR)"\t3b, 11b\n\t" \ 810 - STR(PTR)"\t4b, 11b\n\t" \ 811 - ".previous" \ 812 - : "=&r" (res) \ 813 - : "r" (value), "r" (addr), "i" (-EFAULT) \ 814 - : "memory"); \ 815 - } while(0) 816 - 817 - #define _StoreDW(addr, value, res) \ 818 - do { \ 819 - __asm__ __volatile__ ( \ 820 - ".set\tpush\n\t" \ 821 - ".set\tnoat\n\t" \ 822 - "1:sb\t%1, 0(%2)\n\t" \ 823 - "dsrl\t$1, %1, 0x8\n\t" \ 824 - "2:sb\t$1, 1(%2)\n\t" \ 825 - "dsrl\t$1, $1, 0x8\n\t" \ 826 - "3:sb\t$1, 2(%2)\n\t" \ 827 - "dsrl\t$1, $1, 0x8\n\t" \ 828 - "4:sb\t$1, 3(%2)\n\t" \ 829 - "dsrl\t$1, $1, 0x8\n\t" \ 830 - "5:sb\t$1, 4(%2)\n\t" \ 831 - "dsrl\t$1, $1, 0x8\n\t" \ 832 - "6:sb\t$1, 5(%2)\n\t" \ 833 - "dsrl\t$1, $1, 0x8\n\t" \ 834 - "7:sb\t$1, 6(%2)\n\t" \ 835 - "dsrl\t$1, $1, 0x8\n\t" \ 836 - "8:sb\t$1, 7(%2)\n\t" \ 837 - "dsrl\t$1, $1, 0x8\n\t" \ 838 - ".set\tpop\n\t" \ 839 - "li\t%0, 0\n" \ 840 - "10:\n\t" \ 841 - ".insn\n\t" \ 842 - ".section\t.fixup,\"ax\"\n\t" \ 843 - "11:\tli\t%0, %3\n\t" \ 844 - "j\t10b\n\t" \ 845 - ".previous\n\t" \ 846 - ".section\t__ex_table,\"a\"\n\t" \ 847 - STR(PTR)"\t1b, 11b\n\t" \ 848 - STR(PTR)"\t2b, 11b\n\t" \ 849 - STR(PTR)"\t3b, 11b\n\t" \ 850 - STR(PTR)"\t4b, 11b\n\t" \ 851 - STR(PTR)"\t5b, 11b\n\t" \ 852 - STR(PTR)"\t6b, 11b\n\t" \ 853 - STR(PTR)"\t7b, 11b\n\t" \ 854 - STR(PTR)"\t8b, 11b\n\t" \ 855 - ".previous" \ 856 - : "=&r" (res) \ 857 - : "r" (value), "r" (addr), "i" (-EFAULT) \ 858 - : "memory"); \ 859 - } while(0) 860 - 861 - #endif /* CONFIG_CPU_NO_LOAD_STORE_LR */ 862 - #endif 863 - 864 - #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel) 865 - #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user) 866 - #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel) 867 - #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user) 868 - #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel) 869 - #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user) 870 - #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel) 871 - #define LoadWE(addr, value, res) _LoadW(addr, value, res, user) 872 - #define LoadDW(addr, value, res) _LoadDW(addr, value, res) 873 - 874 - #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel) 875 - #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user) 876 - #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel) 877 - #define StoreWE(addr, value, res) _StoreW(addr, value, res, user) 878 - #define StoreDW(addr, value, res) _StoreDW(addr, value, res) 879 110 880 111 static void emulate_load_store_insn(struct pt_regs *regs, 881 112 void __user *addr, unsigned int __user *pc)