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phy: renesas: r8a779f0-ether-serdes: add USXGMII mode

The initial driver implementation was limited to SGMII and 1GBit/s. The
new mode allows speeds up to 2.5GBit/s on R-Car S4-8 SOCs.

Signed-off-by: Michael Dege <michael.dege@renesas.com>
Link: https://lore.kernel.org/r/20250703-renesas-serdes-update-v4-1-1db5629cac2b@renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Michael Dege and committed by
Vinod Koul d337c557 f0c6d776

+57 -12
+57 -12
drivers/phy/renesas/r8a779f0-ether-serdes.c
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 /* Renesas Ethernet SERDES device driver 3 3 * 4 - * Copyright (C) 2022 Renesas Electronics Corporation 4 + * Copyright (C) 2022-2025 Renesas Electronics Corporation 5 5 */ 6 6 7 7 #include <linux/delay.h> ··· 92 92 { 93 93 struct r8a779f0_eth_serdes_drv_data *dd = channel->dd; 94 94 95 - switch (channel->phy_interface) { 96 - case PHY_INTERFACE_MODE_SGMII: 97 - r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x0097); 98 - r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060); 99 - r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200); 100 - r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000); 101 - r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d); 102 - return 0; 103 - default: 104 - return -EOPNOTSUPP; 105 - } 95 + /* Set combination mode */ 96 + r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x00d7); 97 + r8a779f0_eth_serdes_write32(dd->addr, 0x01cc, 0x180, 0xc200); 98 + r8a779f0_eth_serdes_write32(dd->addr, 0x01c4, 0x180, 0x0042); 99 + r8a779f0_eth_serdes_write32(dd->addr, 0x01c8, 0x180, 0x0000); 100 + r8a779f0_eth_serdes_write32(dd->addr, 0x01dc, 0x180, 0x002f); 101 + r8a779f0_eth_serdes_write32(dd->addr, 0x01d0, 0x180, 0x0060); 102 + r8a779f0_eth_serdes_write32(dd->addr, 0x01d8, 0x180, 0x2200); 103 + r8a779f0_eth_serdes_write32(dd->addr, 0x01d4, 0x180, 0x0000); 104 + r8a779f0_eth_serdes_write32(dd->addr, 0x01e0, 0x180, 0x003d); 105 + 106 + return 0; 106 107 } 107 108 108 109 static int ··· 156 155 r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1); 157 156 r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208); 158 157 break; 158 + 159 + case PHY_INTERFACE_MODE_USXGMII: 160 + r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0000); 161 + r8a779f0_eth_serdes_write32(channel->addr, 0x0014, 0x380, 0x0050); 162 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2200); 163 + r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x380, 0x0400); 164 + r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0001); 165 + r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x056a); 166 + r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015); 167 + r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x1100); 168 + r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0001); 169 + r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0001); 170 + r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0001); 171 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0300); 172 + r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0300); 173 + r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000); 174 + r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0004); 175 + r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000); 176 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310); 177 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0301); 178 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x180, BIT(0), 0); 179 + if (ret) 180 + return ret; 181 + r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0301); 182 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x180, BIT(0), 0); 183 + if (ret) 184 + return ret; 185 + r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310); 186 + r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800); 187 + r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000); 188 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2300); 189 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(8), 0); 190 + if (ret) 191 + return ret; 192 + break; 193 + 159 194 default: 160 195 return -EOPNOTSUPP; 161 196 } ··· 215 178 if (ret) 216 179 return ret; 217 180 r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000); 181 + break; 182 + case PHY_INTERFACE_MODE_USXGMII: 183 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0120); 184 + usleep_range(10, 20); 185 + r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2600); 186 + ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x380, BIT(10), 0); 187 + if (ret) 188 + return ret; 218 189 break; 219 190 default: 220 191 return -EOPNOTSUPP;