tjh.dev
+16
-8
drivers/irqchip/irq-atmel-aic5.c
+16
-8
drivers/irqchip/irq-atmel-aic5.c
···
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88
{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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-
struct irq_chip_generic *gc = dgc->gc[0];
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+
struct irq_chip_generic *bgc = dgc->gc[0];
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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-
/* Disable interrupt on AIC5 */
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-
irq_gc_lock(gc);
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+
/*
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* Disable interrupt on AIC5. We always take the lock of the
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+
* first irq chip as all chips share the same registers.
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+
*/
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+
irq_gc_lock(bgc);
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irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
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irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
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gc->mask_cache &= ~d->mask;
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-
irq_gc_unlock(gc);
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+
irq_gc_unlock(bgc);
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103
}
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static void aic5_unmask(struct irq_data *d)
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{
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struct irq_domain *domain = d->domain;
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struct irq_domain_chip_generic *dgc = domain->gc;
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-
struct irq_chip_generic *gc = dgc->gc[0];
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+
struct irq_chip_generic *bgc = dgc->gc[0];
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+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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-
/* Enable interrupt on AIC5 */
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irq_gc_lock(gc);
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+
/*
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* Enable interrupt on AIC5. We always take the lock of the
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+
* first irq chip as all chips share the same registers.
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+
*/
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+
irq_gc_lock(bgc);
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irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
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irq_reg_writel(gc, 1, AT91_AIC5_IECR);
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gc->mask_cache |= d->mask;
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-
irq_gc_unlock(gc);
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irq_gc_unlock(bgc);
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}
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static int aic5_retrigger(struct irq_data *d)