Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging: rtl8732au: Partial clean up of rtl8723a_rf6052.c

Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Jes Sorensen and committed by
Greg Kroah-Hartman
d3220b71 7114ca14

+123 -106
+123 -106
drivers/staging/rtl8723au/hal/rtl8723a_rf6052.c
··· 42 42 #include <rtl8723a_hal.h> 43 43 #include <usb_ops_linux.h> 44 44 45 - /*---------------------------Define Local Constant---------------------------*/ 46 - /* Define local structure for debug!!!!! */ 47 - struct rf_shadow_compare_map { 48 - /* Shadow register value */ 49 - u32 Value; 50 - /* Compare or not flag */ 51 - u8 Compare; 52 - /* Record If it had ever modified unpredicted */ 53 - u8 ErrorOrNot; 54 - /* Recorver Flag */ 55 - u8 Recorver; 56 - /* */ 57 - u8 Driver_Write; 58 - }; 59 - 60 45 /*----------------------------------------------------------------------------- 61 46 * Function: PHY_RF6052SetBandwidth() 62 47 * ··· 56 71 * 57 72 * Note: For RF type 0222D 58 73 *---------------------------------------------------------------------------*/ 59 - void rtl8723a_phy_rf6052set_bw( 60 - struct rtw_adapter *Adapter, 61 - enum ht_channel_width Bandwidth) /* 20M or 40M */ 74 + void rtl8723a_phy_rf6052set_bw(struct rtw_adapter *Adapter, 75 + enum ht_channel_width Bandwidth) /* 20M or 40M */ 62 76 { 63 - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 77 + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 64 78 65 79 switch (Bandwidth) { 66 80 case HT_CHANNEL_WIDTH_20: 67 - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400); 68 - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 81 + pHalData->RfRegChnlVal[0] = 82 + (pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400; 83 + PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 84 + pHalData->RfRegChnlVal[0]); 69 85 break; 70 86 case HT_CHANNEL_WIDTH_40: 71 - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)); 72 - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); 87 + pHalData->RfRegChnlVal[0] = 88 + (pHalData->RfRegChnlVal[0] & 0xfffff3ff); 89 + PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 90 + pHalData->RfRegChnlVal[0]); 73 91 break; 74 92 default: 75 93 break; ··· 96 108 * 97 109 *---------------------------------------------------------------------------*/ 98 110 99 - void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, u8 *pPowerlevel) 111 + void rtl823a_phy_rf6052setccktxpower(struct rtw_adapter *Adapter, 112 + u8 *pPowerlevel) 100 113 { 101 114 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 102 115 struct dm_priv *pdmpriv = &pHalData->dmpriv; ··· 107 118 u8 idx1, idx2; 108 119 u8 *ptr; 109 120 110 - /* According to SD3 eechou's suggestion, we need to disable turbo scan for RU. */ 121 + /* According to SD3 eechou's suggestion, we need to disable 122 + turbo scan for RU. */ 111 123 /* Otherwise, external PA will be broken if power index > 0x20. */ 112 124 if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA) 113 125 TurboScanOff = true; ··· 121 131 122 132 if (TurboScanOff) { 123 133 for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { 124 - TxAGC[idx1] = 125 - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | 126 - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); 127 - /* 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. */ 134 + TxAGC[idx1] = pPowerlevel[idx1] | 135 + (pPowerlevel[idx1] << 8) | 136 + (pPowerlevel[idx1] << 16) | 137 + (pPowerlevel[idx1] << 24); 138 + /* 2010/10/18 MH For external PA module. 139 + We need to limit power index to be less 140 + than 0x20. */ 128 141 if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) 129 142 TxAGC[idx1] = 0x20; 130 143 } 131 144 } 132 145 } else { 133 - /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ 134 - /* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ 135 - /* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ 146 + /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx 147 + * power. It shall be determined by power training mechanism. */ 148 + /* Currently, we cannot fully disable driver dynamic tx power 149 + * mechanism because it is referenced by BT coexist mechanism. */ 150 + /* In the future, two mechanism shall be separated from each other 151 + * and maintained independantly. Thanks for Lanhsin's reminder. */ 136 152 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) { 137 153 TxAGC[RF_PATH_A] = 0x10101010; 138 154 TxAGC[RF_PATH_B] = 0x10101010; 139 - } else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) { 155 + } else if (pdmpriv->DynamicTxHighPowerLvl == 156 + TxHighPwrLevel_Level2) { 140 157 TxAGC[RF_PATH_A] = 0x00000000; 141 158 TxAGC[RF_PATH_B] = 0x00000000; 142 159 } else { 143 160 for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) { 144 - TxAGC[idx1] = 145 - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | 146 - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); 161 + TxAGC[idx1] = pPowerlevel[idx1] | 162 + (pPowerlevel[idx1] << 8) | 163 + (pPowerlevel[idx1] << 16) | 164 + (pPowerlevel[idx1] << 24); 147 165 } 148 166 149 167 if (pHalData->EEPROMRegulatory == 0) { ··· 176 178 } 177 179 178 180 /* rf-A cck tx power */ 179 - tmpval = TxAGC[RF_PATH_A]&0xff; 181 + tmpval = TxAGC[RF_PATH_A] & 0xff; 180 182 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); 181 - tmpval = TxAGC[RF_PATH_A]>>8; 183 + tmpval = TxAGC[RF_PATH_A] >> 8; 182 184 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); 183 185 184 186 /* rf-B cck tx power */ 185 - tmpval = TxAGC[RF_PATH_B]>>24; 187 + tmpval = TxAGC[RF_PATH_B] >> 24; 186 188 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); 187 - tmpval = TxAGC[RF_PATH_B]&0x00ffffff; 189 + tmpval = TxAGC[RF_PATH_B] & 0x00ffffff; 188 190 PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); 189 191 } /* PHY_RF6052SetCckTxPower */ 190 192 191 193 /* powerbase0 for OFDM rates */ 192 194 /* powerbase1 for HT MCS rates */ 193 - static void getPowerBase( 194 - struct rtw_adapter *Adapter, 195 - u8 *pPowerLevel, 196 - u8 Channel, 197 - u32 *OfdmBase, 198 - u32 *MCSBase 199 - ) 195 + static void getPowerBase(struct rtw_adapter *Adapter, u8 *pPowerLevel, 196 + u8 Channel, u32 *OfdmBase, u32 *MCSBase) 200 197 { 201 - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 198 + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 202 199 u32 powerBase0, powerBase1; 203 200 u8 Legacy_pwrdiff = 0; 204 201 s8 HT20_pwrdiff = 0; ··· 204 211 Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1]; 205 212 powerBase0 = powerlevel[i] + Legacy_pwrdiff; 206 213 207 - powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0; 208 - *(OfdmBase+i) = powerBase0; 214 + powerBase0 = powerBase0 << 24 | powerBase0 << 16 | 215 + powerBase0 << 8 | powerBase0; 216 + *(OfdmBase + i) = powerBase0; 209 217 } 210 218 211 219 for (i = 0; i < 2; i++) { ··· 216 222 powerlevel[i] += HT20_pwrdiff; 217 223 } 218 224 powerBase1 = powerlevel[i]; 219 - powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1; 220 - *(MCSBase+i) = powerBase1; 225 + powerBase1 = powerBase1 << 24 | powerBase1 << 16 | 226 + powerBase1 << 8 | powerBase1; 227 + *(MCSBase + i) = powerBase1; 221 228 } 222 229 } 223 230 224 - static void getTxPowerWriteValByRegulatory( 225 - struct rtw_adapter *Adapter, 226 - u8 Channel, 227 - u8 index, 228 - u32 *powerBase0, 229 - u32 *powerBase1, 230 - u32 *pOutWriteVal 231 - ) 231 + static void 232 + getTxPowerWriteValByRegulatory(struct rtw_adapter *Adapter, u8 Channel, 233 + u8 index, u32 *powerBase0, u32 *powerBase1, 234 + u32 *pOutWriteVal) 232 235 { 233 - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 236 + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 234 237 struct dm_priv *pdmpriv = &pHalData->dmpriv; 235 - u8 i, chnlGroup = 0, pwr_diff_limit[4]; 236 - u32 writeVal, customer_limit, rf; 238 + u8 i, chnlGroup = 0, pwr_diff_limit[4]; 239 + u32 writeVal, customer_limit, rf; 237 240 238 241 /* Index 0 & 1 = legacy OFDM, 2-5 = HT_MCS rate */ 239 242 for (rf = 0; rf < 2; rf++) { 240 243 switch (pHalData->EEPROMRegulatory) { 241 244 case 0: /* Realtek better performance */ 242 - /* increase power diff defined by Realtek for large power */ 245 + /* increase power diff defined by Realtek for 246 + * large power */ 243 247 chnlGroup = 0; 244 248 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + 245 249 ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 246 250 break; 247 251 case 1: /* Realtek regulatory */ 248 - /* increase power diff defined by Realtek for regulatory */ 252 + /* increase power diff defined by Realtek for 253 + * regulatory */ 249 254 if (pHalData->pwrGroupCnt == 1) 250 255 chnlGroup = 0; 251 256 if (pHalData->pwrGroupCnt >= 3) { ··· 255 262 else if (Channel > 9) 256 263 chnlGroup = 2; 257 264 258 - if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) 265 + if (pHalData->CurrentChannelBW == 266 + HT_CHANNEL_WIDTH_20) 259 267 chnlGroup++; 260 268 else 261 269 chnlGroup += 4; 262 270 } 263 271 writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + 264 - ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 272 + ((index < 2) ? powerBase0[rf] : 273 + powerBase1[rf]); 265 274 break; 266 275 case 2: /* Better regulatory */ 267 - /* don't increase any power diff */ 268 - writeVal = ((index < 2) ? powerBase0[rf] : powerBase1[rf]); 276 + /* don't increase any power diff */ 277 + writeVal = ((index < 2) ? powerBase0[rf] : 278 + powerBase1[rf]); 269 279 break; 270 280 case 3: /* Customer defined power diff. */ 271 281 chnlGroup = 0; ··· 295 299 break; 296 300 } 297 301 298 - /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */ 299 - /* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */ 300 - /* In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. */ 302 + /* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. 303 + It shall be determined by power training mechanism. */ 304 + /* Currently, we cannot fully disable driver dynamic tx power mechanism 305 + because it is referenced by BT coexist mechanism. */ 306 + /* In the future, two mechanism shall be separated from each other and 307 + maintained independantly. Thanks for Lanhsin's reminder. */ 301 308 302 309 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) 303 310 writeVal = 0x14141414; 304 - else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) 311 + else if (pdmpriv->DynamicTxHighPowerLvl == 312 + TxHighPwrLevel_Level2) 305 313 writeVal = 0x00000000; 306 314 307 - /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ 308 - /* This mechanism is only applied when Driver-Highpower-Mechanism is OFF. */ 315 + /* 20100628 Joseph: High power mode for BT-Coexist mechanism. */ 316 + /* This mechanism is only applied when 317 + Driver-Highpower-Mechanism is OFF. */ 309 318 if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) 310 319 writeVal = writeVal - 0x06060606; 311 320 else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) 312 321 writeVal = writeVal; 313 - *(pOutWriteVal+rf) = writeVal; 322 + *(pOutWriteVal + rf) = writeVal; 314 323 } 315 324 } 316 325 317 - static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, u32 *pValue) 326 + static void writeOFDMPowerReg(struct rtw_adapter *Adapter, u8 index, 327 + u32 *pValue) 318 328 { 319 - struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 329 + struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 320 330 u16 RegOffset_A[6] = { 321 331 rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, 322 332 rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, ··· 340 338 for (rf = 0; rf < 2; rf++) { 341 339 writeVal = pValue[rf]; 342 340 for (i = 0; i < 4; i++) { 343 - pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); 344 - if (pwr_val[i] > RF6052_MAX_TX_PWR) 341 + pwr_val[i] = (u8)((writeVal & 342 + (0x7f << (i * 8))) >> (i * 8)); 343 + if (pwr_val[i] > RF6052_MAX_TX_PWR) 345 344 pwr_val[i] = RF6052_MAX_TX_PWR; 346 345 } 347 - writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) | 348 - (pwr_val[1]<<8) | pwr_val[0]; 346 + writeVal = pwr_val[3] << 24 | pwr_val[2] << 16 | 347 + pwr_val[1] << 8 | pwr_val[0]; 349 348 350 349 if (rf == 0) 351 350 RegOffset = RegOffset_A[index]; ··· 355 352 356 353 PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); 357 354 358 - /* 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. */ 355 + /* 201005115 Joseph: Set Tx Power diff for Tx power 356 + training mechanism. */ 359 357 if (((pHalData->rf_type == RF_2T2R) && 360 358 (RegOffset == rTxAGC_A_Mcs15_Mcs12 || 361 359 RegOffset == rTxAGC_B_Mcs15_Mcs12)) || ··· 364 360 (RegOffset == rTxAGC_A_Mcs07_Mcs04 || 365 361 RegOffset == rTxAGC_B_Mcs07_Mcs04))) { 366 362 writeVal = pwr_val[3]; 367 - if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) 363 + if (RegOffset == rTxAGC_A_Mcs15_Mcs12 || 364 + RegOffset == rTxAGC_A_Mcs07_Mcs04) 368 365 RegOffset = 0xc90; 369 - if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) 366 + if (RegOffset == rTxAGC_B_Mcs15_Mcs12 || 367 + RegOffset == rTxAGC_B_Mcs07_Mcs04) 370 368 RegOffset = 0xc98; 371 369 for (i = 0; i < 3; i++) { 372 370 if (i != 2) 373 - writeVal = (writeVal > 8) ? (writeVal-8) : 0; 371 + writeVal = (writeVal > 8) ? 372 + (writeVal - 8) : 0; 374 373 else 375 - writeVal = (writeVal > 6) ? (writeVal-6) : 0; 374 + writeVal = (writeVal > 6) ? 375 + (writeVal - 6) : 0; 376 376 rtl8723au_write8(Adapter, RegOffset + i, 377 377 (u8)writeVal); 378 378 } ··· 387 379 * Function: PHY_RF6052SetOFDMTxPower 388 380 * 389 381 * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for 390 - * different channel and read original value in TX power register area from 391 - * 0xe00. We increase offset and original value to be correct tx pwr. 382 + * different channel and read original value in TX power 383 + * register area from 0xe00. We increase offset and 384 + * original value to be correct tx pwr. 392 385 * 393 386 * Input: NONE 394 387 * ··· 398 389 * Return: NONE 399 390 * 400 391 * Revised History: 401 - * When Who Remark 402 - * 11/05/2008 MHC Simulate 8192 series method. 403 - * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to 404 - * A/B pwr difference or legacy/HT pwr diff. 405 - * 2. We concern with path B legacy/HT OFDM difference. 406 - * 01/22/2009 MHC Support new EPRO format from SD3. 392 + * When Remark 393 + * 11/05/2008 MHC Simulate 8192 series method. 394 + * 01/06/2009 MHC 1. Prevent Path B tx power overflow or 395 + * underflow dure to A/B pwr difference or 396 + * legacy/HT pwr diff. 397 + * 2. We concern with path B legacy/HT OFDM difference. 398 + * 01/22/2009 MHC Support new EPRO format from SD3. 407 399 * 408 400 *---------------------------------------------------------------------------*/ 409 - void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, u8 *pPowerLevel, u8 Channel) 401 + void rtl8723a_PHY_RF6052SetOFDMTxPower(struct rtw_adapter *Adapter, 402 + u8 *pPowerLevel, u8 Channel) 410 403 { 411 404 u32 writeVal[2], powerBase0[2], powerBase1[2]; 412 405 u8 index = 0; 413 406 414 - getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]); 407 + getPowerBase(Adapter, pPowerLevel, Channel, 408 + &powerBase0[0], &powerBase1[0]); 415 409 416 410 for (index = 0; index < 6; index++) { 417 411 getTxPowerWriteValByRegulatory(Adapter, Channel, index, ··· 428 416 { 429 417 u32 u4RegValue = 0; 430 418 u8 eRFPath; 431 - struct bb_reg_define *pPhyReg; 419 + struct bb_reg_define *pPhyReg; 432 420 int rtStatus = _SUCCESS; 433 421 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter); 434 422 ··· 442 430 /*----Store original RFENV control type----*/ 443 431 switch (eRFPath) { 444 432 case RF_PATH_A: 445 - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); 433 + u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, 434 + bRFSI_RFENV); 446 435 break; 447 436 case RF_PATH_B: 448 - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); 437 + u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, 438 + bRFSI_RFENV << 16); 449 439 break; 450 440 } 451 441 452 442 /*----Set RF_ENV enable----*/ 453 - PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); 443 + PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); 454 444 udelay(1);/* PlatformStallExecution(1); */ 455 445 456 446 /*----Set RF_ENV output high----*/ ··· 460 446 udelay(1);/* PlatformStallExecution(1); */ 461 447 462 448 /* Set bit number of Address and Data for RF register */ 463 - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ 449 + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 450 + 0x0); /* Set 1 to 4 bits for 8255 */ 464 451 udelay(1);/* PlatformStallExecution(1); */ 465 452 466 - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ 453 + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 454 + 0x0); /* Set 0 to 12 bits for 8255 */ 467 455 udelay(1);/* PlatformStallExecution(1); */ 468 456 469 457 /*----Initialize RF fom connfiguration file----*/ ··· 480 464 /*----Restore RFENV control type----*/; 481 465 switch (eRFPath) { 482 466 case RF_PATH_A: 483 - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); 467 + PHY_SetBBReg(Adapter, pPhyReg->rfintfs, 468 + bRFSI_RFENV, u4RegValue); 484 469 break; 485 470 case RF_PATH_B: 486 - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); 471 + PHY_SetBBReg(Adapter, pPhyReg->rfintfs, 472 + bRFSI_RFENV << 16, u4RegValue); 487 473 break; 488 474 } 489 475 490 476 if (rtStatus != _SUCCESS) { 491 - /* RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */ 492 477 goto phy_RF6052_Config_ParaFile_Fail; 493 478 } 494 479 }