tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Blackfin arch: Fix PM building on BF52x: No ROTWE on BF52x, add USBWE

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

authored by Michael Hennerich and committed by Bryan Wu d310fb4b 226a6ec3

+89 -98
unified split
+88 -97
arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
··· 151 151 #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ 152 152 #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ 153 153 #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ 154 - #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ 154 + #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ 155 155 156 156 #define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ 157 157 #define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ ··· 634 634 /* PLL_DIV Macros */ 635 635 #define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */ 636 636 637 - /* VR_CTL Masks */ 638 - #define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */ 637 + /* VR_CTL Masks */ 638 + #define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */ 639 639 #define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */ 640 - #define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */ 641 - #define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */ 642 - #define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */ 643 - 644 - #define GAIN 0x000C /* Voltage Level Gain */ 645 - #define GAIN_5 0x0000 /* GAIN = 5 */ 646 - #define GAIN_10 0x0004 /* GAIN = 10 */ 647 - #define GAIN_20 0x0008 /* GAIN = 20 */ 648 - #define GAIN_50 0x000C /* GAIN = 50 */ 649 640 650 641 #define VLEV 0x00F0 /* Internal Voltage Level */ 651 642 #define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */ ··· 651 660 #define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 652 661 653 662 #define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 654 - #define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */ 663 + #define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */ 655 664 #define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */ 656 665 #define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */ 657 666 #define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */ ··· 688 697 689 698 #define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */ 690 699 #define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */ 691 - #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ 692 - #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ 693 - #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ 700 + #define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */ 701 + #define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */ 702 + #define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */ 694 703 #define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */ 695 704 #define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */ 696 705 697 706 #define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */ 698 707 #define IRQ_TWI 0x00000200 /* TWI Interrupt */ 699 708 #define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */ 700 - #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ 709 + #define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */ 701 710 #define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */ 702 711 #define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */ 703 712 #define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */ ··· 792 801 #define WDEV_NONE 0x0006 /* no event on roll over */ 793 802 #define WDEN 0x0FF0 /* enable watchdog */ 794 803 #define WDDIS 0x0AD0 /* disable watchdog */ 795 - #define WDRO 0x8000 /* watchdog rolled over latch */ 804 + #define WDRO 0x8000 /* watchdog rolled over latch */ 796 805 797 806 /* depreciated WDOG_CTL Register Masks for legacy code */ 798 807 ··· 873 882 #define NINT 0x01 /* Pending Interrupt */ 874 883 #define IIR_TX_READY 0x02 /* UART_THR empty */ 875 884 #define IIR_RX_READY 0x04 /* Receive data ready */ 876 - #define IIR_LINE_CHANGE 0x06 /* Receive line status */ 885 + #define IIR_LINE_CHANGE 0x06 /* Receive line status */ 877 886 #define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */ 878 887 879 888 /* UARTx_GCTL Masks */ ··· 1629 1638 1630 1639 /* entry addresses of the user-callable Boot ROM functions */ 1631 1640 1632 - #define _BOOTROM_RESET 0xEF000000 1633 - #define _BOOTROM_FINAL_INIT 0xEF000002 1641 + #define _BOOTROM_RESET 0xEF000000 1642 + #define _BOOTROM_FINAL_INIT 0xEF000002 1634 1643 #define _BOOTROM_DO_MEMORY_DMA 0xEF000006 1635 - #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 1636 - #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 1637 - #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 1644 + #define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 1645 + #define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 1646 + #define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 1638 1647 #define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010 1639 1648 #define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012 1640 1649 #define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014 ··· 1762 1771 /* Bit masks for CNT_CONFIG */ 1763 1772 1764 1773 #define CNTE 0x1 /* Counter Enable */ 1765 - #define nCNTE 0x0 1774 + #define nCNTE 0x0 1766 1775 #define DEBE 0x2 /* Debounce Enable */ 1767 - #define nDEBE 0x0 1776 + #define nDEBE 0x0 1768 1777 #define CDGINV 0x10 /* CDG Pin Polarity Invert */ 1769 - #define nCDGINV 0x0 1778 + #define nCDGINV 0x0 1770 1779 #define CUDINV 0x20 /* CUD Pin Polarity Invert */ 1771 - #define nCUDINV 0x0 1780 + #define nCUDINV 0x0 1772 1781 #define CZMINV 0x40 /* CZM Pin Polarity Invert */ 1773 - #define nCZMINV 0x0 1782 + #define nCZMINV 0x0 1774 1783 #define CNTMODE 0x700 /* Counter Operating Mode */ 1775 1784 #define ZMZC 0x800 /* CZM Zeroes Counter Enable */ 1776 - #define nZMZC 0x0 1785 + #define nZMZC 0x0 1777 1786 #define BNDMODE 0x3000 /* Boundary register Mode */ 1778 1787 #define INPDIS 0x8000 /* CUG and CDG Input Disable */ 1779 - #define nINPDIS 0x0 1788 + #define nINPDIS 0x0 1780 1789 1781 1790 /* Bit masks for CNT_IMASK */ 1782 1791 1783 1792 #define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ 1784 - #define nICIE 0x0 1793 + #define nICIE 0x0 1785 1794 #define UCIE 0x2 /* Up count Interrupt Enable */ 1786 - #define nUCIE 0x0 1795 + #define nUCIE 0x0 1787 1796 #define DCIE 0x4 /* Down count Interrupt Enable */ 1788 - #define nDCIE 0x0 1797 + #define nDCIE 0x0 1789 1798 #define MINCIE 0x8 /* Min Count Interrupt Enable */ 1790 - #define nMINCIE 0x0 1799 + #define nMINCIE 0x0 1791 1800 #define MAXCIE 0x10 /* Max Count Interrupt Enable */ 1792 - #define nMAXCIE 0x0 1801 + #define nMAXCIE 0x0 1793 1802 #define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ 1794 - #define nCOV31IE 0x0 1803 + #define nCOV31IE 0x0 1795 1804 #define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ 1796 - #define nCOV15IE 0x0 1805 + #define nCOV15IE 0x0 1797 1806 #define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ 1798 - #define nCZEROIE 0x0 1807 + #define nCZEROIE 0x0 1799 1808 #define CZMIE 0x100 /* CZM Pin Interrupt Enable */ 1800 - #define nCZMIE 0x0 1809 + #define nCZMIE 0x0 1801 1810 #define CZMEIE 0x200 /* CZM Error Interrupt Enable */ 1802 - #define nCZMEIE 0x0 1811 + #define nCZMEIE 0x0 1803 1812 #define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ 1804 - #define nCZMZIE 0x0 1813 + #define nCZMZIE 0x0 1805 1814 1806 1815 /* Bit masks for CNT_STATUS */ 1807 1816 1808 1817 #define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ 1809 - #define nICII 0x0 1818 + #define nICII 0x0 1810 1819 #define UCII 0x2 /* Up count Interrupt Identifier */ 1811 - #define nUCII 0x0 1820 + #define nUCII 0x0 1812 1821 #define DCII 0x4 /* Down count Interrupt Identifier */ 1813 - #define nDCII 0x0 1822 + #define nDCII 0x0 1814 1823 #define MINCII 0x8 /* Min Count Interrupt Identifier */ 1815 - #define nMINCII 0x0 1824 + #define nMINCII 0x0 1816 1825 #define MAXCII 0x10 /* Max Count Interrupt Identifier */ 1817 - #define nMAXCII 0x0 1826 + #define nMAXCII 0x0 1818 1827 #define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ 1819 - #define nCOV31II 0x0 1828 + #define nCOV31II 0x0 1820 1829 #define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ 1821 - #define nCOV15II 0x0 1830 + #define nCOV15II 0x0 1822 1831 #define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ 1823 - #define nCZEROII 0x0 1832 + #define nCZEROII 0x0 1824 1833 #define CZMII 0x100 /* CZM Pin Interrupt Identifier */ 1825 - #define nCZMII 0x0 1834 + #define nCZMII 0x0 1826 1835 #define CZMEII 0x200 /* CZM Error Interrupt Identifier */ 1827 - #define nCZMEII 0x0 1836 + #define nCZMEII 0x0 1828 1837 #define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ 1829 - #define nCZMZII 0x0 1838 + #define nCZMZII 0x0 1830 1839 1831 1840 /* Bit masks for CNT_COMMAND */ 1832 1841 ··· 1834 1843 #define W1LMIN 0xf0 /* Load Min Register */ 1835 1844 #define W1LMAX 0xf00 /* Load Max Register */ 1836 1845 #define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ 1837 - #define nW1ZMONCE 0x0 1846 + #define nW1ZMONCE 0x0 1838 1847 1839 1848 /* Bit masks for CNT_DEBOUNCE */ 1840 1849 ··· 1844 1853 1845 1854 #define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ 1846 1855 #define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ 1847 - #define nFIEN 0x0 1856 + #define nFIEN 0x0 1848 1857 #define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ 1849 - #define nFTESTDEC 0x0 1858 + #define nFTESTDEC 0x0 1850 1859 #define FWRTEST 0x2000 /* OTP/Fuse Write Test */ 1851 - #define nFWRTEST 0x0 1860 + #define nFWRTEST 0x0 1852 1861 #define FRDEN 0x4000 /* OTP/Fuse Read Enable */ 1853 - #define nFRDEN 0x0 1862 + #define nFRDEN 0x0 1854 1863 #define FWREN 0x8000 /* OTP/Fuse Write Enable */ 1855 - #define nFWREN 0x0 1864 + #define nFWREN 0x0 1856 1865 1857 1866 /* Bit masks for OTP_BEN */ 1858 1867 ··· 1861 1870 /* Bit masks for OTP_STATUS */ 1862 1871 1863 1872 #define FCOMP 0x1 /* OTP/Fuse Access Complete */ 1864 - #define nFCOMP 0x0 1873 + #define nFCOMP 0x0 1865 1874 #define FERROR 0x2 /* OTP/Fuse Access Error */ 1866 - #define nFERROR 0x0 1875 + #define nFERROR 0x0 1867 1876 #define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ 1868 - #define nMMRGLOAD 0x0 1877 + #define nMMRGLOAD 0x0 1869 1878 #define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ 1870 - #define nMMRGLOCK 0x0 1879 + #define nMMRGLOCK 0x0 1871 1880 #define FPGMEN 0x40 /* OTP/Fuse Program Enable */ 1872 - #define nFPGMEN 0x0 1881 + #define nFPGMEN 0x0 1873 1882 1874 1883 /* Bit masks for OTP_TIMING */ 1875 1884 ··· 1883 1892 /* Bit masks for SECURE_SYSSWT */ 1884 1893 1885 1894 #define EMUDABL 0x1 /* Emulation Disable. */ 1886 - #define nEMUDABL 0x0 1895 + #define nEMUDABL 0x0 1887 1896 #define RSTDABL 0x2 /* Reset Disable */ 1888 - #define nRSTDABL 0x0 1897 + #define nRSTDABL 0x0 1889 1898 #define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ 1890 1899 #define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ 1891 1900 #define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ 1892 1901 #define DMA0OVR 0x800 /* DMA0 Memory Access Override */ 1893 - #define nDMA0OVR 0x0 1902 + #define nDMA0OVR 0x0 1894 1903 #define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ 1895 - #define nDMA1OVR 0x0 1904 + #define nDMA1OVR 0x0 1896 1905 #define EMUOVR 0x4000 /* Emulation Override */ 1897 - #define nEMUOVR 0x0 1906 + #define nEMUOVR 0x0 1898 1907 #define OTPSEN 0x8000 /* OTP Secrets Enable. */ 1899 - #define nOTPSEN 0x0 1908 + #define nOTPSEN 0x0 1900 1909 #define L2DABL 0x70000 /* L2 Memory Disable. */ 1901 1910 1902 1911 /* Bit masks for SECURE_CONTROL */ 1903 1912 1904 1913 #define SECURE0 0x1 /* SECURE 0 */ 1905 - #define nSECURE0 0x0 1914 + #define nSECURE0 0x0 1906 1915 #define SECURE1 0x2 /* SECURE 1 */ 1907 - #define nSECURE1 0x0 1916 + #define nSECURE1 0x0 1908 1917 #define SECURE2 0x4 /* SECURE 2 */ 1909 - #define nSECURE2 0x0 1918 + #define nSECURE2 0x0 1910 1919 #define SECURE3 0x8 /* SECURE 3 */ 1911 - #define nSECURE3 0x0 1920 + #define nSECURE3 0x0 1912 1921 1913 1922 /* Bit masks for SECURE_STATUS */ 1914 1923 1915 1924 #define SECMODE 0x3 /* Secured Mode Control State */ 1916 1925 #define NMI 0x4 /* Non Maskable Interrupt */ 1917 - #define nNMI 0x0 1926 + #define nNMI 0x0 1918 1927 #define AFVALID 0x8 /* Authentication Firmware Valid */ 1919 - #define nAFVALID 0x0 1928 + #define nAFVALID 0x0 1920 1929 #define AFEXIT 0x10 /* Authentication Firmware Exit */ 1921 - #define nAFEXIT 0x0 1930 + #define nAFEXIT 0x0 1922 1931 #define SECSTAT 0xe0 /* Secure Status */ 1923 1932 1924 1933 /* Bit masks for NFC_CTL */ ··· 1926 1935 #define WR_DLY 0xf /* Write Strobe Delay */ 1927 1936 #define RD_DLY 0xf0 /* Read Strobe Delay */ 1928 1937 #define NWIDTH 0x100 /* NAND Data Width */ 1929 - #define nNWIDTH 0x0 1938 + #define nNWIDTH 0x0 1930 1939 #define PG_SIZE 0x200 /* Page Size */ 1931 - #define nPG_SIZE 0x0 1940 + #define nPG_SIZE 0x0 1932 1941 1933 1942 /* Bit masks for NFC_STAT */ 1934 1943 1935 1944 #define NBUSY 0x1 /* Not Busy */ 1936 - #define nNBUSY 0x0 1945 + #define nNBUSY 0x0 1937 1946 #define WB_FULL 0x2 /* Write Buffer Full */ 1938 - #define nWB_FULL 0x0 1947 + #define nWB_FULL 0x0 1939 1948 #define PG_WR_STAT 0x4 /* Page Write Pending */ 1940 - #define nPG_WR_STAT 0x0 1949 + #define nPG_WR_STAT 0x0 1941 1950 #define PG_RD_STAT 0x8 /* Page Read Pending */ 1942 - #define nPG_RD_STAT 0x0 1951 + #define nPG_RD_STAT 0x0 1943 1952 #define WB_EMPTY 0x10 /* Write Buffer Empty */ 1944 - #define nWB_EMPTY 0x0 1953 + #define nWB_EMPTY 0x0 1945 1954 1946 1955 /* Bit masks for NFC_IRQSTAT */ 1947 1956 1948 1957 #define NBUSYIRQ 0x1 /* Not Busy IRQ */ 1949 - #define nNBUSYIRQ 0x0 1958 + #define nNBUSYIRQ 0x0 1950 1959 #define WB_OVF 0x2 /* Write Buffer Overflow */ 1951 - #define nWB_OVF 0x0 1960 + #define nWB_OVF 0x0 1952 1961 #define WB_EDGE 0x4 /* Write Buffer Edge Detect */ 1953 - #define nWB_EDGE 0x0 1962 + #define nWB_EDGE 0x0 1954 1963 #define RD_RDY 0x8 /* Read Data Ready */ 1955 - #define nRD_RDY 0x0 1964 + #define nRD_RDY 0x0 1956 1965 #define WR_DONE 0x10 /* Page Write Done */ 1957 - #define nWR_DONE 0x0 1966 + #define nWR_DONE 0x0 1958 1967 1959 1968 /* Bit masks for NFC_IRQMASK */ 1960 1969 1961 1970 #define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ 1962 - #define nMASK_BUSYIRQ 0x0 1971 + #define nMASK_BUSYIRQ 0x0 1963 1972 #define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ 1964 - #define nMASK_WBOVF 0x0 1973 + #define nMASK_WBOVF 0x0 1965 1974 #define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ 1966 - #define nMASK_WBEMPTY 0x0 1975 + #define nMASK_WBEMPTY 0x0 1967 1976 #define MASK_RDRDY 0x8 /* Mask Read Data Ready */ 1968 - #define nMASK_RDRDY 0x0 1977 + #define nMASK_RDRDY 0x0 1969 1978 #define MASK_WRDONE 0x10 /* Mask Write Done */ 1970 - #define nMASK_WRDONE 0x0 1979 + #define nMASK_WRDONE 0x0 1971 1980 1972 1981 /* Bit masks for NFC_RST */ 1973 1982 1974 1983 #define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ 1975 - #define nECC_RST 0x0 1984 + #define nECC_RST 0x0 1976 1985 1977 1986 /* Bit masks for NFC_PGCTL */ 1978 1987 1979 1988 #define PG_RD_START 0x1 /* Page Read Start */ 1980 - #define nPG_RD_START 0x0 1989 + #define nPG_RD_START 0x0 1981 1990 #define PG_WR_START 0x2 /* Page Write Start */ 1982 - #define nPG_WR_START 0x0 1991 + #define nPG_WR_START 0x0 1983 1992 1984 1993 /* Bit masks for NFC_ECC0 */ 1985 1994
+1 -1
arch/blackfin/mach-common/ints-priority.c
··· 216 216 wakeup |= KPADWE; 217 217 break; 218 218 #endif 219 - #ifdef IRQ_CNT 219 + #ifdef CONFIG_BF54x 220 220 case IRQ_CNT: 221 221 wakeup |= ROTWE; 222 222 break;