tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

alpha: sable: remove early machine support

The sable family (Alphaserver 2000 and 2100) comes in variants for
EV4, EV45, EV5 and EV56. Drop support for the earlier ones that
lack support for the BWX extension but keep the later 'gamma'
variant around since that works with EV56 CPUs.

Acked-by: Paul E. McKenney <paulmck@kernel.org>
Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann d2b1e353 f81f335a

+11 -333
+7 -22
arch/alpha/Kconfig
··· 100 100 EB66 EB66 21066 evaluation board 101 101 EB66+ EB66+ 21066 evaluation board 102 102 LX164 AlphaPC164-LX 103 - Lynx AS 2100A 104 103 Miata Personal Workstation 433/500/600 a/au 105 104 Marvel AlphaServer ES47 / ES80 / GS1280 106 105 Mikasa AS 1000 ··· 201 202 help 202 203 A technical overview of this board is available at 203 204 <http://www.unix-ag.org/Linux-Alpha/Architectures/LX164.html>. 204 - 205 - config ALPHA_LYNX 206 - bool "Lynx" 207 - select HAVE_EISA 208 - help 209 - AlphaServer 2100A-based systems. 210 205 211 206 config ALPHA_MARVEL 212 207 bool "Marvel" ··· 318 325 319 326 config ALPHA_EV4 320 327 bool 321 - depends on (ALPHA_SABLE && !ALPHA_GAMMA) || ALPHA_LYNX || ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K 322 - default y if !ALPHA_LYNX 323 - default y if !ALPHA_EV5 328 + depends on ALPHA_NORITAKE && !ALPHA_PRIMO || ALPHA_MIKASA && !ALPHA_PRIMO || ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P_CH || ALPHA_XL || ALPHA_NONAME || ALPHA_EB66 || ALPHA_EB66P || ALPHA_P2K 329 + default y 324 330 325 331 config ALPHA_LCA 326 332 bool ··· 344 352 Runs from standard PC power supply. 345 353 346 354 config ALPHA_EV5 347 - bool "EV5 CPU(s) (model 5/xxx)?" if ALPHA_LYNX 348 - default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE && ALPHA_GAMMA || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR 355 + bool 356 + default y if ALPHA_RX164 || ALPHA_RAWHIDE || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_RUFFIAN || ALPHA_SABLE || ALPHA_NORITAKE && ALPHA_PRIMO || ALPHA_MIKASA && ALPHA_PRIMO || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR 349 357 350 358 config ALPHA_CIA 351 359 bool ··· 370 378 help 371 379 Say Y if you have an AS 1000 5/xxx or an AS 1000A 5/xxx. 372 380 373 - config ALPHA_GAMMA 374 - bool "EV5 CPU(s) (model 5/xxx)?" if ALPHA_SABLE 375 - depends on ALPHA_SABLE || ALPHA_LYNX 376 - default ALPHA_LYNX 377 - help 378 - Say Y if you have an AS 2000 5/xxx or an AS 2100 5/xxx. 379 - 380 381 config ALPHA_T2 381 382 bool 382 - depends on ALPHA_SABLE || ALPHA_LYNX 383 + depends on ALPHA_SABLE 383 384 default y 384 385 385 386 config ALPHA_PYXIS ··· 456 471 config ALPHA_SRM 457 472 bool "Use SRM as bootloader" if ALPHA_CABRIOLET || ALPHA_AVANTI_CH || ALPHA_EB64P || ALPHA_PC164 || ALPHA_TAKARA || ALPHA_EB164 || ALPHA_ALCOR || ALPHA_MIATA || ALPHA_LX164 || ALPHA_SX164 || ALPHA_NAUTILUS || ALPHA_NONAME 458 473 depends on TTY 459 - default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_LYNX || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL 474 + default y if ALPHA_MIKASA || ALPHA_SABLE || ALPHA_NORITAKE || ALPHA_DP264 || ALPHA_RAWHIDE || ALPHA_EIGER || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_SHARK || ALPHA_MARVEL 460 475 help 461 476 There are two different types of booting firmware on Alphas: SRM, 462 477 which is command line driven, and ARC, which uses menus and arrow ··· 482 497 483 498 config SMP 484 499 bool "Symmetric multi-processing support" 485 - depends on ALPHA_SABLE || ALPHA_LYNX || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL 500 + depends on ALPHA_SABLE || ALPHA_RAWHIDE || ALPHA_DP264 || ALPHA_WILDFIRE || ALPHA_TITAN || ALPHA_GENERIC || ALPHA_SHARK || ALPHA_MARVEL 486 501 help 487 502 This enables support for systems with more than one CPU. If you have 488 503 a system with only one CPU, say N. If you have a system with more
-8
arch/alpha/include/asm/core_t2.h
··· 25 25 #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */ 26 26 27 27 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */ 28 - /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ 29 28 #define _GAMMA_BIAS 0x8000000000UL 30 - 31 - #if defined(CONFIG_ALPHA_GENERIC) 32 - #define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias 33 - #elif defined(CONFIG_ALPHA_GAMMA) 34 29 #define GAMMA_BIAS _GAMMA_BIAS 35 - #else 36 - #define GAMMA_BIAS 0 37 - #endif 38 30 39 31 /* 40 32 * Memory spaces:
-1
arch/alpha/include/asm/irq.h
··· 55 55 # define NR_IRQS 40 56 56 57 57 #elif defined(CONFIG_ALPHA_DP264) || \ 58 - defined(CONFIG_ALPHA_LYNX) || \ 59 58 defined(CONFIG_ALPHA_SHARK) 60 59 # define NR_IRQS 64 61 60
-1
arch/alpha/kernel/Makefile
··· 88 88 obj-$(CONFIG_ALPHA_RUFFIAN) += sys_ruffian.o irq_pyxis.o irq_i8259.o 89 89 obj-$(CONFIG_ALPHA_RX164) += sys_rx164.o irq_i8259.o 90 90 obj-$(CONFIG_ALPHA_SABLE) += sys_sable.o 91 - obj-$(CONFIG_ALPHA_LYNX) += sys_sable.o 92 91 obj-$(CONFIG_ALPHA_BOOK1) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o 93 92 obj-$(CONFIG_ALPHA_AVANTI) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o 94 93 obj-$(CONFIG_ALPHA_NONAME) += sys_sio.o irq_i8259.o irq_srm.o pc873xx.o
+2 -9
arch/alpha/kernel/setup.c
··· 182 182 WEAK(eb66p_mv); 183 183 WEAK(eiger_mv); 184 184 WEAK(lx164_mv); 185 - WEAK(lynx_mv); 186 185 WEAK(marvel_ev7_mv); 187 186 WEAK(miata_mv); 188 187 WEAK(mikasa_mv); ··· 197 198 WEAK(rawhide_mv); 198 199 WEAK(ruffian_mv); 199 200 WEAK(rx164_mv); 200 - WEAK(sable_mv); 201 201 WEAK(sable_gamma_mv); 202 202 WEAK(shark_mv); 203 203 WEAK(sx164_mv); ··· 749 751 &alphabook1_mv, 750 752 &rawhide_mv, 751 753 NULL, /* K2 */ 752 - &lynx_mv, /* Lynx */ 754 + NULL, /* Lynx */ 753 755 &xl_mv, 754 756 NULL, /* EB164 -- see variation. */ 755 757 NULL, /* Noritake -- see below. */ ··· 903 905 vec = &noritake_mv; 904 906 break; 905 907 case ST_DEC_2100_A500: 906 - if (cpu == EV5_CPU || cpu == EV56_CPU) 907 - vec = &sable_gamma_mv; 908 - else 909 - vec = &sable_mv; 908 + vec = &sable_gamma_mv; 910 909 break; 911 910 } 912 911 } ··· 927 932 &eb66p_mv, 928 933 &eiger_mv, 929 934 &lx164_mv, 930 - &lynx_mv, 931 935 &miata_mv, 932 936 &mikasa_mv, 933 937 &mikasa_primo_mv, ··· 941 947 &rawhide_mv, 942 948 &ruffian_mv, 943 949 &rx164_mv, 944 - &sable_mv, 945 950 &sable_gamma_mv, 946 951 &shark_mv, 947 952 &sx164_mv,
+2 -292
arch/alpha/kernel/sys_sable.c
··· 212 212 } 213 213 #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */ 214 214 215 - #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) 216 - 217 - /***********************************************************************/ 218 - /* LYNX hardware specifics 219 - */ 220 - /* 221 - * For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC. 222 - * 223 - * Bit Meaning Kernel IRQ 224 - *------------------------------------------ 225 - * 0 226 - * 1 227 - * 2 228 - * 3 mouse 12 229 - * 4 230 - * 5 231 - * 6 keyboard 1 232 - * 7 floppy 6 233 - * 8 COM2 3 234 - * 9 parallel port 7 235 - *10 EISA irq 3 - 236 - *11 EISA irq 4 - 237 - *12 EISA irq 5 5 238 - *13 EISA irq 6 - 239 - *14 EISA irq 7 - 240 - *15 COM1 4 241 - *16 EISA irq 9 9 242 - *17 EISA irq 10 10 243 - *18 EISA irq 11 11 244 - *19 EISA irq 12 - 245 - *20 246 - *21 EISA irq 14 14 247 - *22 EISA irq 15 15 248 - *23 IIC - 249 - *24 VGA (builtin) - 250 - *25 251 - *26 252 - *27 253 - *28 NCR810 (builtin) 28 254 - *29 255 - *30 256 - *31 257 - *32 PCI 0 slot 4 A primary bus 32 258 - *33 PCI 0 slot 4 B primary bus 33 259 - *34 PCI 0 slot 4 C primary bus 34 260 - *35 PCI 0 slot 4 D primary bus 261 - *36 PCI 0 slot 5 A primary bus 262 - *37 PCI 0 slot 5 B primary bus 263 - *38 PCI 0 slot 5 C primary bus 264 - *39 PCI 0 slot 5 D primary bus 265 - *40 PCI 0 slot 6 A primary bus 266 - *41 PCI 0 slot 6 B primary bus 267 - *42 PCI 0 slot 6 C primary bus 268 - *43 PCI 0 slot 6 D primary bus 269 - *44 PCI 0 slot 7 A primary bus 270 - *45 PCI 0 slot 7 B primary bus 271 - *46 PCI 0 slot 7 C primary bus 272 - *47 PCI 0 slot 7 D primary bus 273 - *48 PCI 0 slot 0 A secondary bus 274 - *49 PCI 0 slot 0 B secondary bus 275 - *50 PCI 0 slot 0 C secondary bus 276 - *51 PCI 0 slot 0 D secondary bus 277 - *52 PCI 0 slot 1 A secondary bus 278 - *53 PCI 0 slot 1 B secondary bus 279 - *54 PCI 0 slot 1 C secondary bus 280 - *55 PCI 0 slot 1 D secondary bus 281 - *56 PCI 0 slot 2 A secondary bus 282 - *57 PCI 0 slot 2 B secondary bus 283 - *58 PCI 0 slot 2 C secondary bus 284 - *59 PCI 0 slot 2 D secondary bus 285 - *60 PCI 0 slot 3 A secondary bus 286 - *61 PCI 0 slot 3 B secondary bus 287 - *62 PCI 0 slot 3 C secondary bus 288 - *63 PCI 0 slot 3 D secondary bus 289 - */ 290 - 291 - static void 292 - lynx_update_irq_hw(unsigned long bit, unsigned long mask) 293 - { 294 - /* 295 - * Write the AIR register on the T3/T4 with the 296 - * address of the IC mask register (offset 0x40) 297 - */ 298 - *(vulp)T2_AIR = 0x40; 299 - mb(); 300 - *(vulp)T2_AIR; /* re-read to force write */ 301 - mb(); 302 - *(vulp)T2_DIR = mask; 303 - mb(); 304 - mb(); 305 - } 306 - 307 - static void 308 - lynx_ack_irq_hw(unsigned long bit) 309 - { 310 - *(vulp)T2_VAR = (u_long) bit; 311 - mb(); 312 - mb(); 313 - } 314 - 315 - static irq_swizzle_t lynx_irq_swizzle = { 316 - { /* irq_to_mask */ 317 - -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */ 318 - -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */ 319 - -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo */ 320 - -1, -1, -1, -1, 28, -1, -1, -1, /* pseudo */ 321 - 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */ 322 - 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */ 323 - 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */ 324 - 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */ 325 - }, 326 - { /* mask_to_irq */ 327 - -1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */ 328 - 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */ 329 - 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */ 330 - -1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */ 331 - 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */ 332 - 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */ 333 - 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */ 334 - 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */ 335 - }, 336 - -1, 337 - lynx_update_irq_hw, 338 - lynx_ack_irq_hw 339 - }; 340 - 341 - static void __init 342 - lynx_init_irq(void) 343 - { 344 - sable_lynx_irq_swizzle = &lynx_irq_swizzle; 345 - sable_lynx_init_irq(64); 346 - } 347 - 348 - /* 349 - * PCI Fixup configuration for ALPHA LYNX (2100A) 350 - * 351 - * The device to slot mapping looks like: 352 - * 353 - * Slot Device 354 - * 0 none 355 - * 1 none 356 - * 2 PCI-EISA bridge 357 - * 3 PCI-PCI bridge 358 - * 4 NCR 810 (Demi-Lynx only) 359 - * 5 none 360 - * 6 PCI on board slot 4 361 - * 7 PCI on board slot 5 362 - * 8 PCI on board slot 6 363 - * 9 PCI on board slot 7 364 - * 365 - * And behind the PPB we have: 366 - * 367 - * 11 PCI on board slot 0 368 - * 12 PCI on board slot 1 369 - * 13 PCI on board slot 2 370 - * 14 PCI on board slot 3 371 - */ 372 - /* 373 - * NOTE: the IRQ assignments below are arbitrary, but need to be consistent 374 - * with the values in the irq swizzling tables above. 375 - */ 376 - 377 - static int 378 - lynx_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 379 - { 380 - static char irq_tab[19][5] = { 381 - /*INT INTA INTB INTC INTD */ 382 - { -1, -1, -1, -1, -1}, /* IdSel 13, PCEB */ 383 - { -1, -1, -1, -1, -1}, /* IdSel 14, PPB */ 384 - { 28, 28, 28, 28, 28}, /* IdSel 15, NCR demi */ 385 - { -1, -1, -1, -1, -1}, /* IdSel 16, none */ 386 - { 32, 32, 33, 34, 35}, /* IdSel 17, slot 4 */ 387 - { 36, 36, 37, 38, 39}, /* IdSel 18, slot 5 */ 388 - { 40, 40, 41, 42, 43}, /* IdSel 19, slot 6 */ 389 - { 44, 44, 45, 46, 47}, /* IdSel 20, slot 7 */ 390 - { -1, -1, -1, -1, -1}, /* IdSel 22, none */ 391 - /* The following are actually behind the PPB. */ 392 - { -1, -1, -1, -1, -1}, /* IdSel 16 none */ 393 - { 28, 28, 28, 28, 28}, /* IdSel 17 NCR lynx */ 394 - { -1, -1, -1, -1, -1}, /* IdSel 18 none */ 395 - { -1, -1, -1, -1, -1}, /* IdSel 19 none */ 396 - { -1, -1, -1, -1, -1}, /* IdSel 20 none */ 397 - { -1, -1, -1, -1, -1}, /* IdSel 21 none */ 398 - { 48, 48, 49, 50, 51}, /* IdSel 22 slot 0 */ 399 - { 52, 52, 53, 54, 55}, /* IdSel 23 slot 1 */ 400 - { 56, 56, 57, 58, 59}, /* IdSel 24 slot 2 */ 401 - { 60, 60, 61, 62, 63} /* IdSel 25 slot 3 */ 402 - }; 403 - const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5; 404 - return COMMON_TABLE_LOOKUP; 405 - } 406 - 407 - static u8 408 - lynx_swizzle(struct pci_dev *dev, u8 *pinp) 409 - { 410 - int slot, pin = *pinp; 411 - 412 - if (dev->bus->number == 0) { 413 - slot = PCI_SLOT(dev->devfn); 414 - } 415 - /* Check for the built-in bridge */ 416 - else if (PCI_SLOT(dev->bus->self->devfn) == 3) { 417 - slot = PCI_SLOT(dev->devfn) + 11; 418 - } 419 - else 420 - { 421 - /* Must be a card-based bridge. */ 422 - do { 423 - if (PCI_SLOT(dev->bus->self->devfn) == 3) { 424 - slot = PCI_SLOT(dev->devfn) + 11; 425 - break; 426 - } 427 - pin = pci_swizzle_interrupt_pin(dev, pin); 428 - 429 - /* Move up the chain of bridges. */ 430 - dev = dev->bus->self; 431 - /* Slot of the next bridge. */ 432 - slot = PCI_SLOT(dev->devfn); 433 - } while (dev->bus->self); 434 - } 435 - *pinp = pin; 436 - return slot; 437 - } 438 - 439 - #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */ 440 - 441 215 /***********************************************************************/ 442 216 /* GENERIC irq routines */ 443 217 ··· 313 539 * these games with GAMMA_BIAS. 314 540 */ 315 541 316 - #if defined(CONFIG_ALPHA_GENERIC) || \ 317 - (defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA)) 318 - #undef GAMMA_BIAS 319 - #define GAMMA_BIAS 0 320 - struct alpha_machine_vector sable_mv __initmv = { 321 - .vector_name = "Sable", 322 - DO_EV4_MMU, 323 - DO_DEFAULT_RTC, 324 - DO_T2_IO, 325 - .machine_check = t2_machine_check, 326 - .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS, 327 - .min_io_address = EISA_DEFAULT_IO_BASE, 328 - .min_mem_address = T2_DEFAULT_MEM_BASE, 329 - 330 - .nr_irqs = 40, 331 - .device_interrupt = sable_lynx_srm_device_interrupt, 332 - 333 - .init_arch = t2_init_arch, 334 - .init_irq = sable_init_irq, 335 - .init_rtc = common_init_rtc, 336 - .init_pci = sable_lynx_init_pci, 337 - .kill_arch = t2_kill_arch, 338 - .pci_map_irq = sable_map_irq, 339 - .pci_swizzle = common_swizzle, 340 - 341 - .sys = { .t2 = { 342 - .gamma_bias = 0 343 - } } 344 - }; 345 - ALIAS_MV(sable) 346 - #endif /* GENERIC || (SABLE && !GAMMA) */ 347 - 348 - #if defined(CONFIG_ALPHA_GENERIC) || \ 349 - (defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA)) 542 + #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) 350 543 #undef GAMMA_BIAS 351 544 #define GAMMA_BIAS _GAMMA_BIAS 352 545 struct alpha_machine_vector sable_gamma_mv __initmv = { ··· 342 601 } } 343 602 }; 344 603 ALIAS_MV(sable_gamma) 345 - #endif /* GENERIC || (SABLE && GAMMA) */ 346 - 347 - #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) 348 - #undef GAMMA_BIAS 349 - #define GAMMA_BIAS _GAMMA_BIAS 350 - struct alpha_machine_vector lynx_mv __initmv = { 351 - .vector_name = "Lynx", 352 - DO_EV4_MMU, 353 - DO_DEFAULT_RTC, 354 - DO_T2_IO, 355 - .machine_check = t2_machine_check, 356 - .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS, 357 - .min_io_address = EISA_DEFAULT_IO_BASE, 358 - .min_mem_address = T2_DEFAULT_MEM_BASE, 359 - 360 - .nr_irqs = 64, 361 - .device_interrupt = sable_lynx_srm_device_interrupt, 362 - 363 - .init_arch = t2_init_arch, 364 - .init_irq = lynx_init_irq, 365 - .init_rtc = common_init_rtc, 366 - .init_pci = sable_lynx_init_pci, 367 - .kill_arch = t2_kill_arch, 368 - .pci_map_irq = lynx_map_irq, 369 - .pci_swizzle = lynx_swizzle, 370 - 371 - .sys = { .t2 = { 372 - .gamma_bias = _GAMMA_BIAS 373 - } } 374 - }; 375 - ALIAS_MV(lynx) 376 - #endif /* GENERIC || LYNX */ 604 + #endif /* GENERIC || SABLE */