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dt-bindings: firmware: tegra: Convert to json-schema
Convert the NVIDIA Tegra186 (and later) BPMP bindings from the free-form
text format to json-schema.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
+186
-107
-107
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
-107
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
···
1
-
NVIDIA Tegra Boot and Power Management Processor (BPMP)
2
-
3
-
The BPMP is a specific processor in Tegra chip, which is designed for
4
-
booting process handling and offloading the power management, clock
5
-
management, and reset control tasks from the CPU. The binding document
6
-
defines the resources that would be used by the BPMP firmware driver,
7
-
which can create the interprocessor communication (IPC) between the CPU
8
-
and BPMP.
9
-
10
-
Required properties:
11
-
- compatible
12
-
Array of strings
13
-
One of:
14
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- "nvidia,tegra186-bpmp"
15
-
- mboxes : The phandle of mailbox controller and the mailbox specifier.
16
-
- shmem : List of the phandle of the TX and RX shared memory area that
17
-
the IPC between CPU and BPMP is based on.
18
-
- #clock-cells : Should be 1.
19
-
- #power-domain-cells : Should be 1.
20
-
- #reset-cells : Should be 1.
21
-
22
-
This node is a mailbox consumer. See the following files for details of
23
-
the mailbox subsystem, and the specifiers implemented by the relevant
24
-
provider(s):
25
-
26
-
- .../mailbox/mailbox.txt
27
-
- .../mailbox/nvidia,tegra186-hsp.txt
28
-
29
-
This node is a clock, power domain, and reset provider. See the following
30
-
files for general documentation of those features, and the specifiers
31
-
implemented by this node:
32
-
33
-
- .../clock/clock-bindings.txt
34
-
- <dt-bindings/clock/tegra186-clock.h>
35
-
- ../power/power-domain.yaml
36
-
- <dt-bindings/power/tegra186-powergate.h>
37
-
- .../reset/reset.txt
38
-
- <dt-bindings/reset/tegra186-reset.h>
39
-
40
-
The BPMP implements some services which must be represented by separate nodes.
41
-
For example, it can provide access to certain I2C controllers, and the I2C
42
-
bindings represent each I2C controller as a device tree node. Such nodes should
43
-
be nested directly inside the main BPMP node.
44
-
45
-
Software can determine whether a child node of the BPMP node represents a device
46
-
by checking for a compatible property. Any node with a compatible property
47
-
represents a device that can be instantiated. Nodes without a compatible
48
-
property may be used to provide configuration information regarding the BPMP
49
-
itself, although no such configuration nodes are currently defined by this
50
-
binding.
51
-
52
-
The BPMP firmware defines no single global name-/numbering-space for such
53
-
services. Put another way, the numbering scheme for I2C buses is distinct from
54
-
the numbering scheme for any other service the BPMP may provide (e.g. a future
55
-
hypothetical SPI bus service). As such, child device nodes will have no reg
56
-
property, and the BPMP node will have no #address-cells or #size-cells property.
57
-
58
-
The shared memory bindings for BPMP
59
-
-----------------------------------
60
-
61
-
The shared memory area for the IPC TX and RX between CPU and BPMP are
62
-
predefined and work on top of sysram, which is an SRAM inside the chip.
63
-
64
-
See ".../sram/sram.txt" for the bindings.
65
-
66
-
Example:
67
-
68
-
hsp_top0: hsp@3c00000 {
69
-
...
70
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#mbox-cells = <2>;
71
-
};
72
-
73
-
sysram@30000000 {
74
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compatible = "nvidia,tegra186-sysram", "mmio-sram";
75
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reg = <0x0 0x30000000 0x0 0x50000>;
76
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#address-cells = <2>;
77
-
#size-cells = <2>;
78
-
ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
79
-
80
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cpu_bpmp_tx: shmem@4e000 {
81
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compatible = "nvidia,tegra186-bpmp-shmem";
82
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reg = <0x0 0x4e000 0x0 0x1000>;
83
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label = "cpu-bpmp-tx";
84
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pool;
85
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};
86
-
87
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cpu_bpmp_rx: shmem@4f000 {
88
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compatible = "nvidia,tegra186-bpmp-shmem";
89
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reg = <0x0 0x4f000 0x0 0x1000>;
90
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label = "cpu-bpmp-rx";
91
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pool;
92
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};
93
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};
94
-
95
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bpmp {
96
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compatible = "nvidia,tegra186-bpmp";
97
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mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
98
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shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
99
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#clock-cells = <1>;
100
-
#power-domain-cells = <1>;
101
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#reset-cells = <1>;
102
-
103
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i2c {
104
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compatible = "...";
105
-
...
106
-
};
107
-
};
+186
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+186
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
8
+
9
+
maintainers:
10
+
- Thierry Reding <thierry.reding@gmail.com>
11
+
- Jon Hunter <jonathanh@nvidia.com>
12
+
13
+
description: |
14
+
The BPMP is a specific processor in Tegra chip, which is designed for
15
+
booting process handling and offloading the power management, clock
16
+
management, and reset control tasks from the CPU. The binding document
17
+
defines the resources that would be used by the BPMP firmware driver,
18
+
which can create the interprocessor communication (IPC) between the
19
+
CPU and BPMP.
20
+
21
+
This node is a mailbox consumer. See the following files for details
22
+
of the mailbox subsystem, and the specifiers implemented by the
23
+
relevant provider(s):
24
+
25
+
- .../mailbox/mailbox.txt
26
+
- .../mailbox/nvidia,tegra186-hsp.yaml
27
+
28
+
This node is a clock, power domain, and reset provider. See the
29
+
following files for general documentation of those features, and the
30
+
specifiers implemented by this node:
31
+
32
+
- .../clock/clock-bindings.txt
33
+
- <dt-bindings/clock/tegra186-clock.h>
34
+
- ../power/power-domain.yaml
35
+
- <dt-bindings/power/tegra186-powergate.h>
36
+
- .../reset/reset.txt
37
+
- <dt-bindings/reset/tegra186-reset.h>
38
+
39
+
The BPMP implements some services which must be represented by
40
+
separate nodes. For example, it can provide access to certain I2C
41
+
controllers, and the I2C bindings represent each I2C controller as a
42
+
device tree node. Such nodes should be nested directly inside the main
43
+
BPMP node.
44
+
45
+
Software can determine whether a child node of the BPMP node
46
+
represents a device by checking for a compatible property. Any node
47
+
with a compatible property represents a device that can be
48
+
instantiated. Nodes without a compatible property may be used to
49
+
provide configuration information regarding the BPMP itself, although
50
+
no such configuration nodes are currently defined by this binding.
51
+
52
+
The BPMP firmware defines no single global name-/numbering-space for
53
+
such services. Put another way, the numbering scheme for I2C buses is
54
+
distinct from the numbering scheme for any other service the BPMP may
55
+
provide (e.g. a future hypothetical SPI bus service). As such, child
56
+
device nodes will have no reg property, and the BPMP node will have no
57
+
"#address-cells" or "#size-cells" property.
58
+
59
+
The shared memory area for the IPC TX and RX between CPU and BPMP are
60
+
predefined and work on top of sysram, which is an SRAM inside the
61
+
chip. See ".../sram/sram.yaml" for the bindings.
62
+
63
+
properties:
64
+
compatible:
65
+
oneOf:
66
+
- items:
67
+
- enum:
68
+
- nvidia,tegra194-bpmp
69
+
- nvidia,tegra234-bpmp
70
+
- const: nvidia,tegra186-bpmp
71
+
- const: nvidia,tegra186-bpmp
72
+
73
+
mboxes:
74
+
description: A phandle and channel specifier for the mailbox used to
75
+
communicate with the BPMP.
76
+
maxItems: 1
77
+
78
+
shmem:
79
+
description: List of the phandle to the TX and RX shared memory area
80
+
that the IPC between CPU and BPMP is based on.
81
+
minItems: 2
82
+
maxItems: 2
83
+
84
+
"#clock-cells":
85
+
const: 1
86
+
87
+
"#power-domain-cells":
88
+
const: 1
89
+
90
+
"#reset-cells":
91
+
const: 1
92
+
93
+
interconnects:
94
+
items:
95
+
- description: memory read client
96
+
- description: memory write client
97
+
- description: DMA read client
98
+
- description: DMA write client
99
+
100
+
interconnect-names:
101
+
items:
102
+
- const: read
103
+
- const: write
104
+
- const: dma-mem # dma-read
105
+
- const: dma-write
106
+
107
+
iommus:
108
+
maxItems: 1
109
+
110
+
i2c:
111
+
type: object
112
+
113
+
thermal:
114
+
type: object
115
+
116
+
additionalProperties: false
117
+
118
+
required:
119
+
- compatible
120
+
- mboxes
121
+
- shmem
122
+
- "#clock-cells"
123
+
- "#power-domain-cells"
124
+
- "#reset-cells"
125
+
126
+
examples:
127
+
- |
128
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
129
+
#include <dt-bindings/mailbox/tegra186-hsp.h>
130
+
#include <dt-bindings/memory/tegra186-mc.h>
131
+
132
+
hsp_top0: hsp@3c00000 {
133
+
compatible = "nvidia,tegra186-hsp";
134
+
reg = <0x03c00000 0xa0000>;
135
+
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
136
+
interrupt-names = "doorbell";
137
+
#mbox-cells = <2>;
138
+
};
139
+
140
+
sram@30000000 {
141
+
compatible = "nvidia,tegra186-sysram", "mmio-sram";
142
+
reg = <0x30000000 0x50000>;
143
+
#address-cells = <1>;
144
+
#size-cells = <1>;
145
+
ranges = <0x0 0x30000000 0x50000>;
146
+
147
+
cpu_bpmp_tx: sram@4e000 {
148
+
reg = <0x4e000 0x1000>;
149
+
label = "cpu-bpmp-tx";
150
+
pool;
151
+
};
152
+
153
+
cpu_bpmp_rx: sram@4f000 {
154
+
reg = <0x4f000 0x1000>;
155
+
label = "cpu-bpmp-rx";
156
+
pool;
157
+
};
158
+
};
159
+
160
+
bpmp {
161
+
compatible = "nvidia,tegra186-bpmp";
162
+
interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
163
+
<&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
164
+
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
165
+
<&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
166
+
interconnect-names = "read", "write", "dma-mem", "dma-write";
167
+
iommus = <&smmu TEGRA186_SID_BPMP>;
168
+
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
169
+
TEGRA_HSP_DB_MASTER_BPMP>;
170
+
shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
171
+
#clock-cells = <1>;
172
+
#power-domain-cells = <1>;
173
+
#reset-cells = <1>;
174
+
175
+
i2c {
176
+
compatible = "nvidia,tegra186-bpmp-i2c";
177
+
nvidia,bpmp-bus-id = <5>;
178
+
#address-cells = <1>;
179
+
#size-cells = <0>;
180
+
};
181
+
182
+
thermal {
183
+
compatible = "nvidia,tegra186-bpmp-thermal";
184
+
#thermal-sensor-cells = <1>;
185
+
};
186
+
};