···124124 return 1;125125}126126127127-static inline void __ipipe_lock_root(void)128128-{129129- set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));130130-}131131-132132-static inline void __ipipe_unlock_root(void)133133-{134134- clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));135135-}136136-137127void __ipipe_enable_pipeline(void);138128139129#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
+7-15
arch/blackfin/include/asm/ipipe_base.h
···51515252extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */53535454-#define __ipipe_stall_root() \5555- do { \5656- volatile unsigned long *p = &__ipipe_root_status; \5757- set_bit(0, p); \5858- } while (0)5454+void __ipipe_stall_root(void);59556060-#define __ipipe_test_and_stall_root() \6161- ({ \6262- volatile unsigned long *p = &__ipipe_root_status; \6363- test_and_set_bit(0, p); \6464- })5656+unsigned long __ipipe_test_and_stall_root(void);65576666-#define __ipipe_test_root() \6767- ({ \6868- const unsigned long *p = &__ipipe_root_status; \6969- test_bit(0, p); \7070- })5858+unsigned long __ipipe_test_root(void);5959+6060+void __ipipe_lock_root(void);6161+6262+void __ipipe_unlock_root(void);71637264#endif /* !__ASSEMBLY__ */7365
+67
arch/blackfin/kernel/ipipe.c
···335335 __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));336336 bfin_sti(bfin_irq_flags);337337}338338+339339+/*340340+ * We could use standard atomic bitops in the following root status341341+ * manipulation routines, but let's prepare for SMP support in the342342+ * same move, preventing CPU migration as required.343343+ */344344+void __ipipe_stall_root(void)345345+{346346+ unsigned long *p, flags;347347+348348+ local_irq_save_hw(flags);349349+ p = &__ipipe_root_status;350350+ __set_bit(IPIPE_STALL_FLAG, p);351351+ local_irq_restore_hw(flags);352352+}353353+EXPORT_SYMBOL(__ipipe_stall_root);354354+355355+unsigned long __ipipe_test_and_stall_root(void)356356+{357357+ unsigned long *p, flags;358358+ int x;359359+360360+ local_irq_save_hw(flags);361361+ p = &__ipipe_root_status;362362+ x = __test_and_set_bit(IPIPE_STALL_FLAG, p);363363+ local_irq_restore_hw(flags);364364+365365+ return x;366366+}367367+EXPORT_SYMBOL(__ipipe_test_and_stall_root);368368+369369+unsigned long __ipipe_test_root(void)370370+{371371+ const unsigned long *p;372372+ unsigned long flags;373373+ int x;374374+375375+ local_irq_save_hw_smp(flags);376376+ p = &__ipipe_root_status;377377+ x = test_bit(IPIPE_STALL_FLAG, p);378378+ local_irq_restore_hw_smp(flags);379379+380380+ return x;381381+}382382+EXPORT_SYMBOL(__ipipe_test_root);383383+384384+void __ipipe_lock_root(void)385385+{386386+ unsigned long *p, flags;387387+388388+ local_irq_save_hw(flags);389389+ p = &__ipipe_root_status;390390+ __set_bit(IPIPE_SYNCDEFER_FLAG, p);391391+ local_irq_restore_hw(flags);392392+}393393+EXPORT_SYMBOL(__ipipe_lock_root);394394+395395+void __ipipe_unlock_root(void)396396+{397397+ unsigned long *p, flags;398398+399399+ local_irq_save_hw(flags);400400+ p = &__ipipe_root_status;401401+ __clear_bit(IPIPE_SYNCDEFER_FLAG, p);402402+ local_irq_restore_hw(flags);403403+}404404+EXPORT_SYMBOL(__ipipe_unlock_root);