tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
ARM: STi: STiH416: Add ethernet support.
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+167
+14
arch/arm/boot/dts/stih416-clock.dtsi
+14
arch/arm/boot/dts/stih416-clock.dtsi
···
37
37
clock-frequency = <100000000>;
38
38
clock-output-names = "CLK_S_ICN_REG_0";
39
39
};
40
+
41
+
CLK_S_GMAC0_PHY: clockgenA1@7 {
42
+
#clock-cells = <0>;
43
+
compatible = "fixed-clock";
44
+
clock-frequency = <25000000>;
45
+
clock-output-names = "CLK_S_GMAC0_PHY";
46
+
};
47
+
48
+
CLK_S_ETH1_PHY: clockgenA0@7 {
49
+
#clock-cells = <0>;
50
+
compatible = "fixed-clock";
51
+
clock-frequency = <25000000>;
52
+
clock-output-names = "CLK_S_ETH1_PHY";
53
+
};
40
54
};
41
55
};
+109
arch/arm/boot/dts/stih416-pinctrl.dtsi
+109
arch/arm/boot/dts/stih416-pinctrl.dtsi
···
132
132
};
133
133
};
134
134
};
135
+
136
+
gmac1 {
137
+
pinctrl_mii1: mii1 {
138
+
st,pins {
139
+
txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
140
+
txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
141
+
txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
142
+
txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
143
+
txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
144
+
txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
145
+
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
146
+
col = <&PIO0 7 ALT1 IN BYPASS 1000>;
147
+
148
+
mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>;
149
+
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
150
+
crs = <&PIO1 2 ALT1 IN BYPASS 1000>;
151
+
mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
152
+
rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
153
+
rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
154
+
rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
155
+
rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
156
+
157
+
rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
158
+
rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
159
+
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
160
+
phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
161
+
};
162
+
};
163
+
pinctrl_rgmii1: rgmii1-0 {
164
+
st,pins {
165
+
txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
166
+
txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
167
+
txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
168
+
txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
169
+
txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>;
170
+
txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
171
+
172
+
mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
173
+
mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
174
+
rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
175
+
rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
176
+
rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
177
+
rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
178
+
179
+
rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>;
180
+
rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
181
+
phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>;
182
+
183
+
clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
184
+
};
185
+
};
186
+
};
135
187
};
136
188
137
189
pin-controller-front {
···
371
319
st,pins {
372
320
tx = <&PIO17 4 ALT2 OUT>;
373
321
rx = <&PIO17 5 ALT2 IN>;
322
+
};
323
+
};
324
+
};
325
+
326
+
gmac0 {
327
+
pinctrl_mii0: mii0 {
328
+
st,pins {
329
+
mdint = <&PIO13 6 ALT2 IN BYPASS 0>;
330
+
txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
331
+
txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
332
+
txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
333
+
txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
334
+
txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
335
+
336
+
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
337
+
txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
338
+
crs = <&PIO15 2 ALT2 IN BYPASS 1000>;
339
+
col = <&PIO15 3 ALT2 IN BYPASS 1000>;
340
+
mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
341
+
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
342
+
343
+
rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
344
+
rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
345
+
rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
346
+
rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
347
+
rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
348
+
rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
349
+
rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
350
+
phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
351
+
};
352
+
};
353
+
354
+
pinctrl_gmii0: gmii0 {
355
+
st,pins {
356
+
};
357
+
};
358
+
pinctrl_rgmii0: rgmii0 {
359
+
st,pins {
360
+
phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>;
361
+
txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
362
+
txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
363
+
txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
364
+
txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
365
+
txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
366
+
txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
367
+
368
+
mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
369
+
mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
370
+
371
+
rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
372
+
rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>;
373
+
rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>;
374
+
rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>;
375
+
rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
376
+
rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
377
+
378
+
clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
374
379
};
375
380
};
376
381
};
+44
arch/arm/boot/dts/stih416.dtsi
+44
arch/arm/boot/dts/stih416.dtsi
···
156
156
157
157
status = "disabled";
158
158
};
159
+
160
+
ethernet0: dwmac@fe810000 {
161
+
device_type = "network";
162
+
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
163
+
status = "disabled";
164
+
reg = <0xfe810000 0x8000>, <0x8bc 0x4>;
165
+
reg-names = "stmmaceth", "sti-ethconf";
166
+
167
+
interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
168
+
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
169
+
170
+
snps,pbl = <32>;
171
+
snps,mixed-burst;
172
+
173
+
st,syscon = <&syscfg_rear>;
174
+
resets = <&softreset STIH416_ETH0_SOFTRESET>;
175
+
reset-names = "stmmaceth";
176
+
pinctrl-names = "default";
177
+
pinctrl-0 = <&pinctrl_mii0>;
178
+
clock-names = "stmmaceth";
179
+
clocks = <&CLK_S_GMAC0_PHY>;
180
+
};
181
+
182
+
ethernet1: dwmac@fef08000 {
183
+
device_type = "network";
184
+
compatible = "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
185
+
status = "disabled";
186
+
reg = <0xfef08000 0x8000>, <0x7f0 0x4>;
187
+
reg-names = "stmmaceth", "sti-ethconf";
188
+
interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
189
+
interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
190
+
191
+
snps,pbl = <32>;
192
+
snps,mixed-burst;
193
+
194
+
st,syscon = <&syscfg_sbc>;
195
+
196
+
resets = <&softreset STIH416_ETH1_SOFTRESET>;
197
+
reset-names = "stmmaceth";
198
+
pinctrl-names = "default";
199
+
pinctrl-0 = <&pinctrl_mii1>;
200
+
clock-names = "stmmaceth";
201
+
clocks = <&CLK_S_ETH1_PHY>;
202
+
};
159
203
};
160
204
};