tjh.dev
-66
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
-66
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
···
1
-
Texas Instruments K3 Interrupt Aggregator
2
-
=========================================
3
-
4
-
The Interrupt Aggregator (INTA) provides a centralized machine
5
-
which handles the termination of system events to that they can
6
-
be coherently processed by the host(s) in the system. A maximum
7
-
of 64 events can be mapped to a single interrupt.
8
-
9
-
10
-
Interrupt Aggregator
11
-
+-----------------------------------------+
12
-
| Intmap VINT |
13
-
| +--------------+ +------------+ |
14
-
m ------>| | vint | bit | | 0 |.....|63| vint0 |
15
-
. | +--------------+ +------------+ | +------+
16
-
. | . . | | HOST |
17
-
Globalevents ------>| . . |------>| IRQ |
18
-
. | . . | | CTRL |
19
-
. | . . | +------+
20
-
n ------>| +--------------+ +------------+ |
21
-
| | vint | bit | | 0 |.....|63| vintx |
22
-
| +--------------+ +------------+ |
23
-
| |
24
-
+-----------------------------------------+
25
-
26
-
Configuration of these Intmap registers that maps global events to vint is done
27
-
by a system controller (like the Device Memory and Security Controller on K3
28
-
AM654 SoC). Driver should request the system controller to get the range
29
-
of global events and vints assigned to the requesting host. Management
30
-
of these requested resources should be handled by driver and requests
31
-
system controller to map specific global event to vint, bit pair.
32
-
33
-
Communication between the host processor running an OS and the system
34
-
controller happens through a protocol called TI System Control Interface
35
-
(TISCI protocol). For more details refer:
36
-
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
37
-
38
-
TISCI Interrupt Aggregator Node:
39
-
-------------------------------
40
-
- compatible: Must be "ti,sci-inta".
41
-
- reg: Should contain registers location and length.
42
-
- interrupt-controller: Identifies the node as an interrupt controller
43
-
- msi-controller: Identifies the node as an MSI controller.
44
-
- interrupt-parent: phandle of irq parent.
45
-
- ti,sci: Phandle to TI-SCI compatible System controller node.
46
-
- ti,sci-dev-id: TISCI device ID of the Interrupt Aggregator.
47
-
- ti,sci-rm-range-vint: Array of TISCI subtype ids representing vints(inta
48
-
outputs) range within this INTA, assigned to the
49
-
requesting host context.
50
-
- ti,sci-rm-range-global-event: Array of TISCI subtype ids representing the
51
-
global events range reaching this IA and are assigned
52
-
to the requesting host context.
53
-
54
-
Example:
55
-
--------
56
-
main_udmass_inta: interrupt-controller@33d00000 {
57
-
compatible = "ti,sci-inta";
58
-
reg = <0x0 0x33d00000 0x0 0x100000>;
59
-
interrupt-controller;
60
-
msi-controller;
61
-
interrupt-parent = <&main_navss_intr>;
62
-
ti,sci = <&dmsc>;
63
-
ti,sci-dev-id = <179>;
64
-
ti,sci-rm-range-vint = <0x0>;
65
-
ti,sci-rm-range-global-event = <0x1>;
66
-
};
+98
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
+98
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments K3 Interrupt Aggregator
8
+
9
+
maintainers:
10
+
- Lokesh Vutla <lokeshvutla@ti.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
14
+
15
+
description: |
16
+
The Interrupt Aggregator (INTA) provides a centralized machine
17
+
which handles the termination of system events to that they can
18
+
be coherently processed by the host(s) in the system. A maximum
19
+
of 64 events can be mapped to a single interrupt.
20
+
21
+
Interrupt Aggregator
22
+
+-----------------------------------------+
23
+
| Intmap VINT |
24
+
| +--------------+ +------------+ |
25
+
m ------>| | vint | bit | | 0 |.....|63| vint0 |
26
+
. | +--------------+ +------------+ | +------+
27
+
. | . . | | HOST |
28
+
Globalevents ------>| . . |----->| IRQ |
29
+
. | . . | | CTRL |
30
+
. | . . | +------+
31
+
n ------>| +--------------+ +------------+ |
32
+
| | vint | bit | | 0 |.....|63| vintx |
33
+
| +--------------+ +------------+ |
34
+
| |
35
+
+-----------------------------------------+
36
+
37
+
Configuration of these Intmap registers that maps global events to vint is
38
+
done by a system controller (like the Device Memory and Security Controller
39
+
on AM654 SoC). Driver should request the system controller to get the range
40
+
of global events and vints assigned to the requesting host. Management
41
+
of these requested resources should be handled by driver and requests
42
+
system controller to map specific global event to vint, bit pair.
43
+
44
+
Communication between the host processor running an OS and the system
45
+
controller happens through a protocol called TI System Control Interface
46
+
(TISCI protocol).
47
+
48
+
properties:
49
+
compatible:
50
+
const: ti,sci-inta
51
+
52
+
reg:
53
+
maxItems: 1
54
+
55
+
interrupt-controller: true
56
+
57
+
msi-controller: true
58
+
59
+
ti,interrupt-ranges:
60
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
61
+
description: |
62
+
Interrupt ranges that converts the INTA output hw irq numbers
63
+
to parents's input interrupt numbers.
64
+
items:
65
+
items:
66
+
- description: |
67
+
"output_irq" specifies the base for inta output irq
68
+
- description: |
69
+
"parent's input irq" specifies the base for parent irq
70
+
- description: |
71
+
"limit" specifies the limit for translation
72
+
73
+
required:
74
+
- compatible
75
+
- reg
76
+
- interrupt-controller
77
+
- msi-controller
78
+
- ti,sci
79
+
- ti,sci-dev-id
80
+
- ti,interrupt-ranges
81
+
82
+
examples:
83
+
- |
84
+
bus {
85
+
#address-cells = <2>;
86
+
#size-cells = <2>;
87
+
88
+
main_udmass_inta: msi-controller@33d00000 {
89
+
compatible = "ti,sci-inta";
90
+
reg = <0x0 0x33d00000 0x0 0x100000>;
91
+
interrupt-controller;
92
+
msi-controller;
93
+
interrupt-parent = <&main_navss_intr>;
94
+
ti,sci = <&dmsc>;
95
+
ti,sci-dev-id = <179>;
96
+
ti,interrupt-ranges = <0 0 256>;
97
+
};
98
+
};
-82
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
-82
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
···
1
-
Texas Instruments K3 Interrupt Router
2
-
=====================================
3
-
4
-
The Interrupt Router (INTR) module provides a mechanism to mux M
5
-
interrupt inputs to N interrupt outputs, where all M inputs are selectable
6
-
to be driven per N output. An Interrupt Router can either handle edge triggered
7
-
or level triggered interrupts and that is fixed in hardware.
8
-
9
-
Interrupt Router
10
-
+----------------------+
11
-
| Inputs Outputs |
12
-
+-------+ | +------+ +-----+ |
13
-
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
14
-
+-------+ | +------+ +-----+ | controller
15
-
| . . | +-------+
16
-
+-------+ | . . |----->| IRQ |
17
-
| INTA |----------->| . . | +-------+
18
-
+-------+ | . +-----+ |
19
-
| +------+ | N | |
20
-
| | irqM | +-----+ |
21
-
| +------+ |
22
-
| |
23
-
+----------------------+
24
-
25
-
There is one register per output (MUXCNTL_N) that controls the selection.
26
-
Configuration of these MUXCNTL_N registers is done by a system controller
27
-
(like the Device Memory and Security Controller on K3 AM654 SoC). System
28
-
controller will keep track of the used and unused registers within the Router.
29
-
Driver should request the system controller to get the range of GIC IRQs
30
-
assigned to the requesting hosts. It is the drivers responsibility to keep
31
-
track of Host IRQs.
32
-
33
-
Communication between the host processor running an OS and the system
34
-
controller happens through a protocol called TI System Control Interface
35
-
(TISCI protocol). For more details refer:
36
-
Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
37
-
38
-
TISCI Interrupt Router Node:
39
-
----------------------------
40
-
Required Properties:
41
-
- compatible: Must be "ti,sci-intr".
42
-
- ti,intr-trigger-type: Should be one of the following:
43
-
1: If intr supports edge triggered interrupts.
44
-
4: If intr supports level triggered interrupts.
45
-
- interrupt-controller: Identifies the node as an interrupt controller
46
-
- #interrupt-cells: Specifies the number of cells needed to encode an
47
-
interrupt source. The value should be 2.
48
-
First cell should contain the TISCI device ID of source
49
-
Second cell should contain the interrupt source offset
50
-
within the device.
51
-
- ti,sci: Phandle to TI-SCI compatible System controller node.
52
-
- ti,sci-dst-id: TISCI device ID of the destination IRQ controller.
53
-
- ti,sci-rm-range-girq: Array of TISCI subtype ids representing the host irqs
54
-
assigned to this interrupt router. Each subtype id
55
-
corresponds to a range of host irqs.
56
-
57
-
For more details on TISCI IRQ resource management refer:
58
-
https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
59
-
60
-
Example:
61
-
--------
62
-
The following example demonstrates both interrupt router node and the consumer
63
-
node(main gpio) on the AM654 SoC:
64
-
65
-
main_intr: interrupt-controller0 {
66
-
compatible = "ti,sci-intr";
67
-
ti,intr-trigger-type = <1>;
68
-
interrupt-controller;
69
-
interrupt-parent = <&gic500>;
70
-
#interrupt-cells = <2>;
71
-
ti,sci = <&dmsc>;
72
-
ti,sci-dst-id = <56>;
73
-
ti,sci-rm-range-girq = <0x1>;
74
-
};
75
-
76
-
main_gpio0: gpio@600000 {
77
-
...
78
-
interrupt-parent = <&main_intr>;
79
-
interrupts = <57 256>, <57 257>, <57 258>,
80
-
<57 259>, <57 260>, <57 261>;
81
-
...
82
-
};
+102
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
+102
Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Texas Instruments K3 Interrupt Router
8
+
9
+
maintainers:
10
+
- Lokesh Vutla <lokeshvutla@ti.com>
11
+
12
+
allOf:
13
+
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
14
+
15
+
description: |
16
+
The Interrupt Router (INTR) module provides a mechanism to mux M
17
+
interrupt inputs to N interrupt outputs, where all M inputs are selectable
18
+
to be driven per N output. An Interrupt Router can either handle edge
19
+
triggered or level triggered interrupts and that is fixed in hardware.
20
+
21
+
Interrupt Router
22
+
+----------------------+
23
+
| Inputs Outputs |
24
+
+-------+ | +------+ +-----+ |
25
+
| GPIO |----------->| | irq0 | | 0 | | Host IRQ
26
+
+-------+ | +------+ +-----+ | controller
27
+
| . . | +-------+
28
+
+-------+ | . . |----->| IRQ |
29
+
| INTA |----------->| . . | +-------+
30
+
+-------+ | . +-----+ |
31
+
| +------+ | N | |
32
+
| | irqM | +-----+ |
33
+
| +------+ |
34
+
| |
35
+
+----------------------+
36
+
37
+
There is one register per output (MUXCNTL_N) that controls the selection.
38
+
Configuration of these MUXCNTL_N registers is done by a system controller
39
+
(like the Device Memory and Security Controller on K3 AM654 SoC). System
40
+
controller will keep track of the used and unused registers within the Router.
41
+
Driver should request the system controller to get the range of GIC IRQs
42
+
assigned to the requesting hosts. It is the drivers responsibility to keep
43
+
track of Host IRQs.
44
+
45
+
Communication between the host processor running an OS and the system
46
+
controller happens through a protocol called TI System Control Interface
47
+
(TISCI protocol).
48
+
49
+
properties:
50
+
compatible:
51
+
const: ti,sci-intr
52
+
53
+
ti,intr-trigger-type:
54
+
$ref: /schemas/types.yaml#/definitions/uint32
55
+
enum: [1, 4]
56
+
description: |
57
+
Should be one of the following.
58
+
1 = If intr supports edge triggered interrupts.
59
+
4 = If intr supports level triggered interrupts.
60
+
61
+
interrupt-controller: true
62
+
63
+
'#interrupt-cells':
64
+
const: 1
65
+
description: |
66
+
The 1st cell should contain interrupt router input hw number.
67
+
68
+
ti,interrupt-ranges:
69
+
$ref: /schemas/types.yaml#/definitions/uint32-matrix
70
+
description: |
71
+
Interrupt ranges that converts the INTR output hw irq numbers
72
+
to parents's input interrupt numbers.
73
+
items:
74
+
items:
75
+
- description: |
76
+
"output_irq" specifies the base for intr output irq
77
+
- description: |
78
+
"parent's input irq" specifies the base for parent irq
79
+
- description: |
80
+
"limit" specifies the limit for translation
81
+
82
+
required:
83
+
- compatible
84
+
- ti,intr-trigger-type
85
+
- interrupt-controller
86
+
- '#interrupt-cells'
87
+
- ti,sci
88
+
- ti,sci-dev-id
89
+
- ti,interrupt-ranges
90
+
91
+
examples:
92
+
- |
93
+
main_gpio_intr: interrupt-controller0 {
94
+
compatible = "ti,sci-intr";
95
+
ti,intr-trigger-type = <1>;
96
+
interrupt-controller;
97
+
interrupt-parent = <&gic500>;
98
+
#interrupt-cells = <1>;
99
+
ti,sci = <&dmsc>;
100
+
ti,sci-dev-id = <131>;
101
+
ti,interrupt-ranges = <0 360 32>;
102
+
};
+2
-2
MAINTAINERS
+2
-2
MAINTAINERS
···
17117
17117
F: Documentation/devicetree/bindings/arm/keystone/ti,k3-sci-common.yaml
17118
17118
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
17119
17119
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
17120
-
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt
17121
-
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt
17120
+
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
17121
+
F: Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
17122
17122
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
17123
17123
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
17124
17124
F: drivers/clk/keystone/sci-clk.c
+17
-19
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+17
-19
arch/arm64/boot/dts/ti/k3-am65-main.dtsi
···
417
417
ti,intr-trigger-type = <1>;
418
418
interrupt-controller;
419
419
interrupt-parent = <&gic500>;
420
-
#interrupt-cells = <2>;
420
+
#interrupt-cells = <1>;
421
421
ti,sci = <&dmsc>;
422
-
ti,sci-dst-id = <56>;
423
-
ti,sci-rm-range-girq = <0x1>;
422
+
ti,sci-dev-id = <100>;
423
+
ti,interrupt-ranges = <0 392 32>;
424
424
};
425
425
426
426
main_navss {
···
438
438
ti,intr-trigger-type = <4>;
439
439
interrupt-controller;
440
440
interrupt-parent = <&gic500>;
441
-
#interrupt-cells = <2>;
441
+
#interrupt-cells = <1>;
442
442
ti,sci = <&dmsc>;
443
-
ti,sci-dst-id = <56>;
444
-
ti,sci-rm-range-girq = <0x0>, <0x2>;
443
+
ti,sci-dev-id = <182>;
444
+
ti,interrupt-ranges = <0 64 64>,
445
+
<64 448 64>;
445
446
};
446
447
447
448
inta_main_udmass: interrupt-controller@33d00000 {
···
453
452
msi-controller;
454
453
ti,sci = <&dmsc>;
455
454
ti,sci-dev-id = <179>;
456
-
ti,sci-rm-range-vint = <0x0>;
457
-
ti,sci-rm-range-global-event = <0x1>;
455
+
ti,interrupt-ranges = <0 0 256>;
458
456
};
459
457
460
458
secure_proxy_main: mailbox@32c00000 {
···
589
589
<0x0 0x33000000 0x0 0x40000>;
590
590
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
591
591
ti,num-rings = <818>;
592
-
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
592
+
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
593
593
ti,dma-ring-reset-quirk;
594
594
ti,sci = <&dmsc>;
595
595
ti,sci-dev-id = <187>;
···
609
609
ti,sci-dev-id = <188>;
610
610
ti,ringacc = <&ringacc>;
611
611
612
-
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
613
-
<0x2>; /* TX_CHAN */
614
-
ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
615
-
<0x5>; /* RX_CHAN */
616
-
ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
612
+
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
613
+
<0xd>; /* TX_CHAN */
614
+
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
615
+
<0xa>; /* RX_CHAN */
616
+
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
617
617
};
618
618
619
619
cpts@310d0000 {
···
622
622
reg-names = "cpts";
623
623
clocks = <&main_cpts_mux>;
624
624
clock-names = "cpts";
625
-
interrupts-extended = <&intr_main_navss 163 0>;
625
+
interrupts-extended = <&intr_main_navss 391>;
626
626
interrupt-names = "cpts";
627
627
ti,cpts-periodic-outputs = <6>;
628
628
ti,cpts-ext-ts-inputs = <8>;
···
645
645
gpio-controller;
646
646
#gpio-cells = <2>;
647
647
interrupt-parent = <&intr_main_gpio>;
648
-
interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
649
-
<57 261>;
648
+
interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
650
649
interrupt-controller;
651
650
#interrupt-cells = <2>;
652
651
ti,ngpio = <96>;
···
660
661
gpio-controller;
661
662
#gpio-cells = <2>;
662
663
interrupt-parent = <&intr_main_gpio>;
663
-
interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
664
-
<58 261>;
664
+
interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
665
665
interrupt-controller;
666
666
#interrupt-cells = <2>;
667
667
ti,ngpio = <90>;
+6
-6
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+6
-6
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
···
134
134
<0x0 0x2a500000 0x0 0x40000>;
135
135
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
136
136
ti,num-rings = <286>;
137
-
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
137
+
ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
138
138
ti,dma-ring-reset-quirk;
139
139
ti,sci = <&dmsc>;
140
140
ti,sci-dev-id = <195>;
···
154
154
ti,sci-dev-id = <194>;
155
155
ti,ringacc = <&mcu_ringacc>;
156
156
157
-
ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
158
-
<0x2>; /* TX_CHAN */
159
-
ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
160
-
<0x4>; /* RX_CHAN */
161
-
ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
157
+
ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
158
+
<0xd>; /* TX_CHAN */
159
+
ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
160
+
<0xa>; /* RX_CHAN */
161
+
ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
162
162
};
163
163
};
164
164
+4
-4
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+4
-4
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
···
74
74
ti,intr-trigger-type = <1>;
75
75
interrupt-controller;
76
76
interrupt-parent = <&gic500>;
77
-
#interrupt-cells = <2>;
77
+
#interrupt-cells = <1>;
78
78
ti,sci = <&dmsc>;
79
-
ti,sci-dst-id = <56>;
80
-
ti,sci-rm-range-girq = <0x4>;
79
+
ti,sci-dev-id = <156>;
80
+
ti,interrupt-ranges = <0 712 16>;
81
81
};
82
82
83
83
wkup_gpio0: wkup_gpio0@42110000 {
···
86
86
gpio-controller;
87
87
#gpio-cells = <2>;
88
88
interrupt-parent = <&intr_wkup_gpio>;
89
-
interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
89
+
interrupts = <60>, <61>, <62>, <63>;
90
90
interrupt-controller;
91
91
#interrupt-cells = <2>;
92
92
ti,ngpio = <56>;
+2
-2
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+2
-2
arch/arm64/boot/dts/ti/k3-am654-base-board.dts
···
384
384
};
385
385
386
386
&mailbox0_cluster0 {
387
-
interrupts = <164 0>;
387
+
interrupts = <436>;
388
388
389
389
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
390
390
ti,mbox-tx = <1 0 0>;
···
393
393
};
394
394
395
395
&mailbox0_cluster1 {
396
-
interrupts = <165 0>;
396
+
interrupts = <432>;
397
397
398
398
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
399
399
ti,mbox-tx = <1 0 0>;
+5
-5
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+5
-5
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
···
287
287
};
288
288
289
289
&mailbox0_cluster0 {
290
-
interrupts = <214 0>;
290
+
interrupts = <436>;
291
291
292
292
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
293
293
ti,mbox-rx = <0 0 0>;
···
301
301
};
302
302
303
303
&mailbox0_cluster1 {
304
-
interrupts = <215 0>;
304
+
interrupts = <432>;
305
305
306
306
mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
307
307
ti,mbox-rx = <0 0 0>;
···
315
315
};
316
316
317
317
&mailbox0_cluster2 {
318
-
interrupts = <216 0>;
318
+
interrupts = <428>;
319
319
320
320
mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
321
321
ti,mbox-rx = <0 0 0>;
···
329
329
};
330
330
331
331
&mailbox0_cluster3 {
332
-
interrupts = <217 0>;
332
+
interrupts = <424>;
333
333
334
334
mbox_c66_0: mbox-c66-0 {
335
335
ti,mbox-rx = <0 0 0>;
···
343
343
};
344
344
345
345
&mailbox0_cluster4 {
346
-
interrupts = <218 0>;
346
+
interrupts = <420>;
347
347
348
348
mbox_c71_0: mbox-c71-0 {
349
349
ti,mbox-rx = <0 0 0>;
+22
-21
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+22
-21
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
···
80
80
ti,intr-trigger-type = <1>;
81
81
interrupt-controller;
82
82
interrupt-parent = <&gic500>;
83
-
#interrupt-cells = <2>;
83
+
#interrupt-cells = <1>;
84
84
ti,sci = <&dmsc>;
85
-
ti,sci-dst-id = <14>;
86
-
ti,sci-rm-range-girq = <0x1>;
85
+
ti,sci-dev-id = <131>;
86
+
ti,interrupt-ranges = <8 392 56>;
87
87
};
88
88
89
89
main_navss {
···
101
101
ti,intr-trigger-type = <4>;
102
102
interrupt-controller;
103
103
interrupt-parent = <&gic500>;
104
-
#interrupt-cells = <2>;
104
+
#interrupt-cells = <1>;
105
105
ti,sci = <&dmsc>;
106
-
ti,sci-dst-id = <14>;
107
-
ti,sci-rm-range-girq = <0>, <2>;
106
+
ti,sci-dev-id = <213>;
107
+
ti,interrupt-ranges = <0 64 64>,
108
+
<64 448 64>,
109
+
<128 672 64>;
108
110
};
109
111
110
112
main_udmass_inta: interrupt-controller@33d00000 {
···
117
115
msi-controller;
118
116
ti,sci = <&dmsc>;
119
117
ti,sci-dev-id = <209>;
120
-
ti,sci-rm-range-vint = <0xa>;
121
-
ti,sci-rm-range-global-event = <0xd>;
118
+
ti,interrupt-ranges = <0 0 256>;
122
119
};
123
120
124
121
secure_proxy_main: mailbox@32c00000 {
···
297
296
reg-names = "cpts";
298
297
clocks = <&k3_clks 201 1>;
299
298
clock-names = "cpts";
300
-
interrupts-extended = <&main_navss_intr 201 0>;
299
+
interrupts-extended = <&main_navss_intr 391>;
301
300
interrupt-names = "cpts";
302
301
ti,cpts-periodic-outputs = <6>;
303
302
ti,cpts-ext-ts-inputs = <8>;
···
689
688
gpio-controller;
690
689
#gpio-cells = <2>;
691
690
interrupt-parent = <&main_gpio_intr>;
692
-
interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
693
-
<105 4>, <105 5>, <105 6>, <105 7>;
691
+
interrupts = <256>, <257>, <258>, <259>,
692
+
<260>, <261>, <262>, <263>;
694
693
interrupt-controller;
695
694
#interrupt-cells = <2>;
696
695
ti,ngpio = <128>;
···
706
705
gpio-controller;
707
706
#gpio-cells = <2>;
708
707
interrupt-parent = <&main_gpio_intr>;
709
-
interrupts = <106 0>, <106 1>, <106 2>;
708
+
interrupts = <288>, <289>, <290>;
710
709
interrupt-controller;
711
710
#interrupt-cells = <2>;
712
711
ti,ngpio = <36>;
···
722
721
gpio-controller;
723
722
#gpio-cells = <2>;
724
723
interrupt-parent = <&main_gpio_intr>;
725
-
interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
726
-
<107 4>, <107 5>, <107 6>, <107 7>;
724
+
interrupts = <264>, <265>, <266>, <267>,
725
+
<268>, <269>, <270>, <271>;
727
726
interrupt-controller;
728
727
#interrupt-cells = <2>;
729
728
ti,ngpio = <128>;
···
739
738
gpio-controller;
740
739
#gpio-cells = <2>;
741
740
interrupt-parent = <&main_gpio_intr>;
742
-
interrupts = <108 0>, <108 1>, <108 2>;
741
+
interrupts = <292>, <293>, <294>;
743
742
interrupt-controller;
744
743
#interrupt-cells = <2>;
745
744
ti,ngpio = <36>;
···
755
754
gpio-controller;
756
755
#gpio-cells = <2>;
757
756
interrupt-parent = <&main_gpio_intr>;
758
-
interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
759
-
<109 4>, <109 5>, <109 6>, <109 7>;
757
+
interrupts = <272>, <273>, <274>, <275>,
758
+
<276>, <277>, <278>, <279>;
760
759
interrupt-controller;
761
760
#interrupt-cells = <2>;
762
761
ti,ngpio = <128>;
···
772
771
gpio-controller;
773
772
#gpio-cells = <2>;
774
773
interrupt-parent = <&main_gpio_intr>;
775
-
interrupts = <110 0>, <110 1>, <110 2>;
774
+
interrupts = <296>, <297>, <298>;
776
775
interrupt-controller;
777
776
#interrupt-cells = <2>;
778
777
ti,ngpio = <36>;
···
788
787
gpio-controller;
789
788
#gpio-cells = <2>;
790
789
interrupt-parent = <&main_gpio_intr>;
791
-
interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
792
-
<111 4>, <111 5>, <111 6>, <111 7>;
790
+
interrupts = <280>, <281>, <282>, <283>,
791
+
<284>, <285>, <286>, <287>;
793
792
interrupt-controller;
794
793
#interrupt-cells = <2>;
795
794
ti,ngpio = <128>;
···
805
804
gpio-controller;
806
805
#gpio-cells = <2>;
807
806
interrupt-parent = <&main_gpio_intr>;
808
-
interrupts = <112 0>, <112 1>, <112 2>;
807
+
interrupts = <300>, <301>, <302>;
809
808
interrupt-controller;
810
809
#interrupt-cells = <2>;
811
810
ti,ngpio = <36>;
+5
-7
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+5
-7
arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
···
101
101
ti,intr-trigger-type = <1>;
102
102
interrupt-controller;
103
103
interrupt-parent = <&gic500>;
104
-
#interrupt-cells = <2>;
104
+
#interrupt-cells = <1>;
105
105
ti,sci = <&dmsc>;
106
-
ti,sci-dst-id = <14>;
107
-
ti,sci-rm-range-girq = <0x5>;
106
+
ti,sci-dev-id = <137>;
107
+
ti,interrupt-ranges = <16 960 16>;
108
108
};
109
109
110
110
wkup_gpio0: gpio@42110000 {
···
113
113
gpio-controller;
114
114
#gpio-cells = <2>;
115
115
interrupt-parent = <&wkup_gpio_intr>;
116
-
interrupts = <113 0>, <113 1>, <113 2>,
117
-
<113 3>, <113 4>, <113 5>;
116
+
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
118
117
interrupt-controller;
119
118
#interrupt-cells = <2>;
120
119
ti,ngpio = <84>;
···
129
130
gpio-controller;
130
131
#gpio-cells = <2>;
131
132
interrupt-parent = <&wkup_gpio_intr>;
132
-
interrupts = <114 0>, <114 1>, <114 2>,
133
-
<114 3>, <114 4>, <114 5>;
133
+
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
134
134
interrupt-controller;
135
135
#interrupt-cells = <2>;
136
136
ti,ngpio = <84>;
+68
-87
drivers/firmware/ti_sci.c
+68
-87
drivers/firmware/ti_sci.c
···
65
65
};
66
66
67
67
/**
68
-
* struct ti_sci_rm_type_map - Structure representing TISCI Resource
69
-
* management representation of dev_ids.
70
-
* @dev_id: TISCI device ID
71
-
* @type: Corresponding id as identified by TISCI RM.
72
-
*
73
-
* Note: This is used only as a work around for using RM range apis
74
-
* for AM654 SoC. For future SoCs dev_id will be used as type
75
-
* for RM range APIs. In order to maintain ABI backward compatibility
76
-
* type is not being changed for AM654 SoC.
77
-
*/
78
-
struct ti_sci_rm_type_map {
79
-
u32 dev_id;
80
-
u16 type;
81
-
};
82
-
83
-
/**
84
68
* struct ti_sci_desc - Description of SoC integration
85
69
* @default_host_id: Host identifier representing the compute entity
86
70
* @max_rx_timeout_ms: Timeout for communication with SoC (in Milliseconds)
87
71
* @max_msgs: Maximum number of messages that can be pending
88
72
* simultaneously in the system
89
73
* @max_msg_size: Maximum size of data per message that can be handled.
90
-
* @rm_type_map: RM resource type mapping structure.
91
74
*/
92
75
struct ti_sci_desc {
93
76
u8 default_host_id;
94
77
int max_rx_timeout_ms;
95
78
int max_msgs;
96
79
int max_msg_size;
97
-
struct ti_sci_rm_type_map *rm_type_map;
98
80
};
99
81
100
82
/**
···
1692
1710
return ret;
1693
1711
}
1694
1712
1695
-
static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
1696
-
u16 *type)
1697
-
{
1698
-
struct ti_sci_rm_type_map *rm_type_map = info->desc->rm_type_map;
1699
-
bool found = false;
1700
-
int i;
1701
-
1702
-
/* If map is not provided then assume dev_id is used as type */
1703
-
if (!rm_type_map) {
1704
-
*type = dev_id;
1705
-
return 0;
1706
-
}
1707
-
1708
-
for (i = 0; rm_type_map[i].dev_id; i++) {
1709
-
if (rm_type_map[i].dev_id == dev_id) {
1710
-
*type = rm_type_map[i].type;
1711
-
found = true;
1712
-
break;
1713
-
}
1714
-
}
1715
-
1716
-
if (!found)
1717
-
return -EINVAL;
1718
-
1719
-
return 0;
1720
-
}
1721
-
1722
1713
/**
1723
1714
* ti_sci_get_resource_range - Helper to get a range of resources assigned
1724
1715
* to a host. Resource is uniquely identified by
···
1715
1760
struct ti_sci_xfer *xfer;
1716
1761
struct ti_sci_info *info;
1717
1762
struct device *dev;
1718
-
u16 type;
1719
1763
int ret = 0;
1720
1764
1721
1765
if (IS_ERR(handle))
···
1734
1780
return ret;
1735
1781
}
1736
1782
1737
-
ret = ti_sci_get_resource_type(info, dev_id, &type);
1738
-
if (ret) {
1739
-
dev_err(dev, "rm type lookup failed for %u\n", dev_id);
1740
-
goto fail;
1741
-
}
1742
-
1743
1783
req = (struct ti_sci_msg_req_get_resource_range *)xfer->xfer_buf;
1744
1784
req->secondary_host = s_host;
1745
-
req->type = type & MSG_RM_RESOURCE_TYPE_MASK;
1785
+
req->type = dev_id & MSG_RM_RESOURCE_TYPE_MASK;
1746
1786
req->subtype = subtype & MSG_RM_RESOURCE_SUBTYPE_MASK;
1747
1787
1748
1788
ret = ti_sci_do_xfer(info, xfer);
···
3208
3260
EXPORT_SYMBOL_GPL(ti_sci_get_num_resources);
3209
3261
3210
3262
/**
3211
-
* devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device
3263
+
* devm_ti_sci_get_resource_sets() - Get a TISCI resources assigned to a device
3212
3264
* @handle: TISCI handle
3213
3265
* @dev: Device pointer to which the resource is assigned
3214
3266
* @dev_id: TISCI device id to which the resource is assigned
3215
-
* @of_prop: property name by which the resource are represented
3267
+
* @sub_types: Array of sub_types assigned corresponding to device
3268
+
* @sets: Number of sub_types
3216
3269
*
3217
3270
* Return: Pointer to ti_sci_resource if all went well else appropriate
3218
3271
* error pointer.
3219
3272
*/
3220
-
struct ti_sci_resource *
3221
-
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
3222
-
struct device *dev, u32 dev_id, char *of_prop)
3273
+
static struct ti_sci_resource *
3274
+
devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
3275
+
struct device *dev, u32 dev_id, u32 *sub_types,
3276
+
u32 sets)
3223
3277
{
3224
3278
struct ti_sci_resource *res;
3225
3279
bool valid_set = false;
3226
-
u32 resource_subtype;
3227
3280
int i, ret;
3228
3281
3229
3282
res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
3230
3283
if (!res)
3231
3284
return ERR_PTR(-ENOMEM);
3232
3285
3233
-
ret = of_property_count_elems_of_size(dev_of_node(dev), of_prop,
3234
-
sizeof(u32));
3235
-
if (ret < 0) {
3236
-
dev_err(dev, "%s resource type ids not available\n", of_prop);
3237
-
return ERR_PTR(ret);
3238
-
}
3239
-
res->sets = ret;
3240
-
3286
+
res->sets = sets;
3241
3287
res->desc = devm_kcalloc(dev, res->sets, sizeof(*res->desc),
3242
3288
GFP_KERNEL);
3243
3289
if (!res->desc)
3244
3290
return ERR_PTR(-ENOMEM);
3245
3291
3246
3292
for (i = 0; i < res->sets; i++) {
3247
-
ret = of_property_read_u32_index(dev_of_node(dev), of_prop, i,
3248
-
&resource_subtype);
3249
-
if (ret)
3250
-
return ERR_PTR(-EINVAL);
3251
-
3252
3293
ret = handle->ops.rm_core_ops.get_range(handle, dev_id,
3253
-
resource_subtype,
3294
+
sub_types[i],
3254
3295
&res->desc[i].start,
3255
3296
&res->desc[i].num);
3256
3297
if (ret) {
3257
3298
dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n",
3258
-
dev_id, resource_subtype);
3299
+
dev_id, sub_types[i]);
3259
3300
res->desc[i].start = 0;
3260
3301
res->desc[i].num = 0;
3261
3302
continue;
3262
3303
}
3263
3304
3264
3305
dev_dbg(dev, "dev = %d, subtype = %d, start = %d, num = %d\n",
3265
-
dev_id, resource_subtype, res->desc[i].start,
3306
+
dev_id, sub_types[i], res->desc[i].start,
3266
3307
res->desc[i].num);
3267
3308
3268
3309
valid_set = true;
···
3268
3331
3269
3332
return ERR_PTR(-EINVAL);
3270
3333
}
3334
+
3335
+
/**
3336
+
* devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device
3337
+
* @handle: TISCI handle
3338
+
* @dev: Device pointer to which the resource is assigned
3339
+
* @dev_id: TISCI device id to which the resource is assigned
3340
+
* @of_prop: property name by which the resource are represented
3341
+
*
3342
+
* Return: Pointer to ti_sci_resource if all went well else appropriate
3343
+
* error pointer.
3344
+
*/
3345
+
struct ti_sci_resource *
3346
+
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
3347
+
struct device *dev, u32 dev_id, char *of_prop)
3348
+
{
3349
+
struct ti_sci_resource *res;
3350
+
u32 *sub_types;
3351
+
int sets;
3352
+
3353
+
sets = of_property_count_elems_of_size(dev_of_node(dev), of_prop,
3354
+
sizeof(u32));
3355
+
if (sets < 0) {
3356
+
dev_err(dev, "%s resource type ids not available\n", of_prop);
3357
+
return ERR_PTR(sets);
3358
+
}
3359
+
3360
+
sub_types = kcalloc(sets, sizeof(*sub_types), GFP_KERNEL);
3361
+
if (!sub_types)
3362
+
return ERR_PTR(-ENOMEM);
3363
+
3364
+
of_property_read_u32_array(dev_of_node(dev), of_prop, sub_types, sets);
3365
+
res = devm_ti_sci_get_resource_sets(handle, dev, dev_id, sub_types,
3366
+
sets);
3367
+
3368
+
kfree(sub_types);
3369
+
return res;
3370
+
}
3371
+
EXPORT_SYMBOL_GPL(devm_ti_sci_get_of_resource);
3372
+
3373
+
/**
3374
+
* devm_ti_sci_get_resource() - Get a resource range assigned to the device
3375
+
* @handle: TISCI handle
3376
+
* @dev: Device pointer to which the resource is assigned
3377
+
* @dev_id: TISCI device id to which the resource is assigned
3378
+
* @suub_type: TISCI resource subytpe representing the resource.
3379
+
*
3380
+
* Return: Pointer to ti_sci_resource if all went well else appropriate
3381
+
* error pointer.
3382
+
*/
3383
+
struct ti_sci_resource *
3384
+
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
3385
+
u32 dev_id, u32 sub_type)
3386
+
{
3387
+
return devm_ti_sci_get_resource_sets(handle, dev, dev_id, &sub_type, 1);
3388
+
}
3389
+
EXPORT_SYMBOL_GPL(devm_ti_sci_get_resource);
3271
3390
3272
3391
static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode,
3273
3392
void *cmd)
···
3345
3352
/* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
3346
3353
.max_msgs = 20,
3347
3354
.max_msg_size = 64,
3348
-
.rm_type_map = NULL,
3349
-
};
3350
-
3351
-
static struct ti_sci_rm_type_map ti_sci_am654_rm_type_map[] = {
3352
-
{.dev_id = 56, .type = 0x00b}, /* GIC_IRQ */
3353
-
{.dev_id = 179, .type = 0x000}, /* MAIN_NAV_UDMASS_IA0 */
3354
-
{.dev_id = 187, .type = 0x009}, /* MAIN_NAV_RA */
3355
-
{.dev_id = 188, .type = 0x006}, /* MAIN_NAV_UDMAP */
3356
-
{.dev_id = 194, .type = 0x007}, /* MCU_NAV_UDMAP */
3357
-
{.dev_id = 195, .type = 0x00a}, /* MCU_NAV_RA */
3358
-
{.dev_id = 0, .type = 0x000}, /* end of table */
3359
3355
};
3360
3356
3361
3357
/* Description for AM654 */
···
3355
3373
/* Limited by MBOX_TX_QUEUE_LEN. K2G can handle upto 128 messages! */
3356
3374
.max_msgs = 20,
3357
3375
.max_msg_size = 60,
3358
-
.rm_type_map = ti_sci_am654_rm_type_map,
3359
3376
};
3360
3377
3361
3378
static const struct of_device_id ti_sci_of_match[] = {
+1
-1
drivers/irqchip/Kconfig
+1
-1
drivers/irqchip/Kconfig
+1
-1
drivers/irqchip/irq-ingenic.c
+1
-1
drivers/irqchip/irq-ingenic.c
···
125
125
irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
126
126
}
127
127
128
-
if (request_irq(parent_irq, intc_cascade, 0,
128
+
if (request_irq(parent_irq, intc_cascade, IRQF_NO_SUSPEND,
129
129
"SoC intc cascade interrupt", NULL))
130
130
pr_err("Failed to register SoC intc cascade interrupt\n");
131
131
return 0;
+1
-3
drivers/irqchip/irq-mtk-cirq.c
+1
-3
drivers/irqchip/irq-mtk-cirq.c
+1
-3
drivers/irqchip/irq-mtk-sysirq.c
+1
-3
drivers/irqchip/irq-mtk-sysirq.c
···
231
231
kfree(chip_data);
232
232
return ret;
233
233
}
234
-
IRQCHIP_PLATFORM_DRIVER_BEGIN(mtk_sysirq)
235
-
IRQCHIP_MATCH("mediatek,mt6577-sysirq", mtk_sysirq_of_init)
236
-
IRQCHIP_PLATFORM_DRIVER_END(mtk_sysirq)
234
+
IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);
+12
-2
drivers/irqchip/irq-stm32-exti.c
+12
-2
drivers/irqchip/irq-stm32-exti.c
···
416
416
irq_gc_unlock(gc);
417
417
}
418
418
419
+
/* directly set the target bit without reading first. */
420
+
static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
421
+
{
422
+
struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
423
+
void __iomem *base = chip_data->host_data->base;
424
+
u32 val = BIT(d->hwirq % IRQS_PER_BANK);
425
+
426
+
writel_relaxed(val, base + reg);
427
+
}
428
+
419
429
static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
420
430
{
421
431
struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
···
459
449
460
450
raw_spin_lock(&chip_data->rlock);
461
451
462
-
stm32_exti_set_bit(d, stm32_bank->rpr_ofst);
452
+
stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
463
453
if (stm32_bank->fpr_ofst != UNDEF_REG)
464
-
stm32_exti_set_bit(d, stm32_bank->fpr_ofst);
454
+
stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
465
455
466
456
raw_spin_unlock(&chip_data->rlock);
467
457
+79
-16
drivers/irqchip/irq-ti-sci-inta.c
+79
-16
drivers/irqchip/irq-ti-sci-inta.c
···
8
8
9
9
#include <linux/err.h>
10
10
#include <linux/io.h>
11
+
#include <linux/irq.h>
11
12
#include <linux/irqchip.h>
12
13
#include <linux/irqdomain.h>
13
14
#include <linux/interrupt.h>
···
84
83
* @vint_mutex: Mutex to protect vint_list
85
84
* @base: Base address of the memory mapped IO registers
86
85
* @pdev: Pointer to platform device.
86
+
* @ti_sci_id: TI-SCI device identifier
87
87
*/
88
88
struct ti_sci_inta_irq_domain {
89
89
const struct ti_sci_handle *sci;
···
95
93
struct mutex vint_mutex;
96
94
void __iomem *base;
97
95
struct platform_device *pdev;
96
+
u32 ti_sci_id;
98
97
};
99
98
100
99
#define to_vint_desc(e, i) container_of(e, struct ti_sci_inta_vint_desc, \
···
132
129
}
133
130
134
131
/**
132
+
* ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq.
133
+
* @inta: IRQ domain corresponding to Interrupt Aggregator
134
+
* @irq: Hardware irq corresponding to the above irq domain
135
+
*
136
+
* Return parent irq number if translation is available else -ENOENT.
137
+
*/
138
+
static int ti_sci_inta_xlate_irq(struct ti_sci_inta_irq_domain *inta,
139
+
u16 vint_id)
140
+
{
141
+
struct device_node *np = dev_of_node(&inta->pdev->dev);
142
+
u32 base, parent_base, size;
143
+
const __be32 *range;
144
+
int len;
145
+
146
+
range = of_get_property(np, "ti,interrupt-ranges", &len);
147
+
if (!range)
148
+
return vint_id;
149
+
150
+
for (len /= sizeof(*range); len >= 3; len -= 3) {
151
+
base = be32_to_cpu(*range++);
152
+
parent_base = be32_to_cpu(*range++);
153
+
size = be32_to_cpu(*range++);
154
+
155
+
if (base <= vint_id && vint_id < base + size)
156
+
return vint_id - base + parent_base;
157
+
}
158
+
159
+
return -ENOENT;
160
+
}
161
+
162
+
/**
135
163
* ti_sci_inta_alloc_parent_irq() - Allocate parent irq to Interrupt aggregator
136
164
* @domain: IRQ domain corresponding to Interrupt Aggregator
137
165
*
···
173
139
struct ti_sci_inta_irq_domain *inta = domain->host_data;
174
140
struct ti_sci_inta_vint_desc *vint_desc;
175
141
struct irq_fwspec parent_fwspec;
142
+
struct device_node *parent_node;
176
143
unsigned int parent_virq;
177
-
u16 vint_id;
144
+
u16 vint_id, p_hwirq;
145
+
int ret;
178
146
179
147
vint_id = ti_sci_get_free_resource(inta->vint);
180
148
if (vint_id == TI_SCI_RESOURCE_NULL)
181
149
return ERR_PTR(-EINVAL);
182
150
151
+
p_hwirq = ti_sci_inta_xlate_irq(inta, vint_id);
152
+
if (p_hwirq < 0) {
153
+
ret = p_hwirq;
154
+
goto free_vint;
155
+
}
156
+
183
157
vint_desc = kzalloc(sizeof(*vint_desc), GFP_KERNEL);
184
-
if (!vint_desc)
185
-
return ERR_PTR(-ENOMEM);
158
+
if (!vint_desc) {
159
+
ret = -ENOMEM;
160
+
goto free_vint;
161
+
}
186
162
187
163
vint_desc->domain = domain;
188
164
vint_desc->vint_id = vint_id;
189
165
INIT_LIST_HEAD(&vint_desc->list);
190
166
191
-
parent_fwspec.fwnode = of_node_to_fwnode(of_irq_find_parent(dev_of_node(&inta->pdev->dev)));
192
-
parent_fwspec.param_count = 2;
193
-
parent_fwspec.param[0] = inta->pdev->id;
194
-
parent_fwspec.param[1] = vint_desc->vint_id;
167
+
parent_node = of_irq_find_parent(dev_of_node(&inta->pdev->dev));
168
+
parent_fwspec.fwnode = of_node_to_fwnode(parent_node);
169
+
170
+
if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
171
+
/* Parent is GIC */
172
+
parent_fwspec.param_count = 3;
173
+
parent_fwspec.param[0] = 0;
174
+
parent_fwspec.param[1] = p_hwirq - 32;
175
+
parent_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
176
+
} else {
177
+
/* Parent is Interrupt Router */
178
+
parent_fwspec.param_count = 1;
179
+
parent_fwspec.param[0] = p_hwirq;
180
+
}
195
181
196
182
parent_virq = irq_create_fwspec_mapping(&parent_fwspec);
197
183
if (parent_virq == 0) {
198
-
kfree(vint_desc);
199
-
return ERR_PTR(-EINVAL);
184
+
dev_err(&inta->pdev->dev, "Parent IRQ allocation failed\n");
185
+
ret = -EINVAL;
186
+
goto free_vint_desc;
187
+
200
188
}
201
189
vint_desc->parent_virq = parent_virq;
202
190
···
227
171
ti_sci_inta_irq_handler, vint_desc);
228
172
229
173
return vint_desc;
174
+
free_vint_desc:
175
+
kfree(vint_desc);
176
+
free_vint:
177
+
ti_sci_release_resource(inta->vint, vint_id);
178
+
return ERR_PTR(ret);
230
179
}
231
180
232
181
/**
···
263
202
264
203
err = inta->sci->ops.rm_irq_ops.set_event_map(inta->sci,
265
204
dev_id, dev_index,
266
-
inta->pdev->id,
205
+
inta->ti_sci_id,
267
206
vint_desc->vint_id,
268
207
event_desc->global_event,
269
208
free_bit);
···
360
299
inta->sci->ops.rm_irq_ops.free_event_map(inta->sci,
361
300
HWIRQ_TO_DEVID(hwirq),
362
301
HWIRQ_TO_IRQID(hwirq),
363
-
inta->pdev->id,
302
+
inta->ti_sci_id,
364
303
vint_desc->vint_id,
365
304
event_desc->global_event,
366
305
event_desc->vint_bit);
···
608
547
return ret;
609
548
}
610
549
611
-
ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", &pdev->id);
550
+
ret = of_property_read_u32(dev->of_node, "ti,sci-dev-id", &inta->ti_sci_id);
612
551
if (ret) {
613
552
dev_err(dev, "missing 'ti,sci-dev-id' property\n");
614
553
return -EINVAL;
615
554
}
616
555
617
-
inta->vint = devm_ti_sci_get_of_resource(inta->sci, dev, pdev->id,
618
-
"ti,sci-rm-range-vint");
556
+
inta->vint = devm_ti_sci_get_resource(inta->sci, dev, inta->ti_sci_id,
557
+
TI_SCI_RESASG_SUBTYPE_IA_VINT);
619
558
if (IS_ERR(inta->vint)) {
620
559
dev_err(dev, "VINT resource allocation failed\n");
621
560
return PTR_ERR(inta->vint);
622
561
}
623
562
624
-
inta->global_event = devm_ti_sci_get_of_resource(inta->sci, dev, pdev->id,
625
-
"ti,sci-rm-range-global-event");
563
+
inta->global_event = devm_ti_sci_get_resource(inta->sci, dev, inta->ti_sci_id,
564
+
TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT);
626
565
if (IS_ERR(inta->global_event)) {
627
566
dev_err(dev, "Global event resource allocation failed\n");
628
567
return PTR_ERR(inta->global_event);
···
652
591
653
592
INIT_LIST_HEAD(&inta->vint_list);
654
593
mutex_init(&inta->vint_mutex);
594
+
595
+
dev_info(dev, "Interrupt Aggregator domain %d created\n", pdev->id);
655
596
656
597
return 0;
657
598
}
+93
-59
drivers/irqchip/irq-ti-sci-intr.c
+93
-59
drivers/irqchip/irq-ti-sci-intr.c
···
17
17
#include <linux/of_irq.h>
18
18
#include <linux/soc/ti/ti_sci_protocol.h>
19
19
20
-
#define TI_SCI_DEV_ID_MASK 0xffff
21
-
#define TI_SCI_DEV_ID_SHIFT 16
22
-
#define TI_SCI_IRQ_ID_MASK 0xffff
23
-
#define TI_SCI_IRQ_ID_SHIFT 0
24
-
#define HWIRQ_TO_DEVID(hwirq) (((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \
25
-
(TI_SCI_DEV_ID_MASK))
26
-
#define HWIRQ_TO_IRQID(hwirq) ((hwirq) & (TI_SCI_IRQ_ID_MASK))
27
-
#define TO_HWIRQ(dev, index) ((((dev) & TI_SCI_DEV_ID_MASK) << \
28
-
TI_SCI_DEV_ID_SHIFT) | \
29
-
((index) & TI_SCI_IRQ_ID_MASK))
30
-
31
20
/**
32
21
* struct ti_sci_intr_irq_domain - Structure representing a TISCI based
33
22
* Interrupt Router IRQ domain.
34
23
* @sci: Pointer to TISCI handle
35
-
* @dst_irq: TISCI resource pointer representing GIC irq controller.
36
-
* @dst_id: TISCI device ID of the GIC irq controller.
24
+
* @out_irqs: TISCI resource pointer representing INTR irqs.
25
+
* @dev: Struct device pointer.
26
+
* @ti_sci_id: TI-SCI device identifier
37
27
* @type: Specifies the trigger type supported by this Interrupt Router
38
28
*/
39
29
struct ti_sci_intr_irq_domain {
40
30
const struct ti_sci_handle *sci;
41
-
struct ti_sci_resource *dst_irq;
42
-
u32 dst_id;
31
+
struct ti_sci_resource *out_irqs;
32
+
struct device *dev;
33
+
u32 ti_sci_id;
43
34
u32 type;
44
35
};
45
36
···
61
70
{
62
71
struct ti_sci_intr_irq_domain *intr = domain->host_data;
63
72
64
-
if (fwspec->param_count != 2)
73
+
if (fwspec->param_count != 1)
65
74
return -EINVAL;
66
75
67
-
*hwirq = TO_HWIRQ(fwspec->param[0], fwspec->param[1]);
76
+
*hwirq = fwspec->param[0];
68
77
*type = intr->type;
69
78
70
79
return 0;
80
+
}
81
+
82
+
/**
83
+
* ti_sci_intr_xlate_irq() - Translate hwirq to parent's hwirq.
84
+
* @intr: IRQ domain corresponding to Interrupt Router
85
+
* @irq: Hardware irq corresponding to the above irq domain
86
+
*
87
+
* Return parent irq number if translation is available else -ENOENT.
88
+
*/
89
+
static int ti_sci_intr_xlate_irq(struct ti_sci_intr_irq_domain *intr, u32 irq)
90
+
{
91
+
struct device_node *np = dev_of_node(intr->dev);
92
+
u32 base, pbase, size, len;
93
+
const __be32 *range;
94
+
95
+
range = of_get_property(np, "ti,interrupt-ranges", &len);
96
+
if (!range)
97
+
return irq;
98
+
99
+
for (len /= sizeof(*range); len >= 3; len -= 3) {
100
+
base = be32_to_cpu(*range++);
101
+
pbase = be32_to_cpu(*range++);
102
+
size = be32_to_cpu(*range++);
103
+
104
+
if (base <= irq && irq < base + size)
105
+
return irq - base + pbase;
106
+
}
107
+
108
+
return -ENOENT;
71
109
}
72
110
73
111
/**
···
109
89
unsigned int virq, unsigned int nr_irqs)
110
90
{
111
91
struct ti_sci_intr_irq_domain *intr = domain->host_data;
112
-
struct irq_data *data, *parent_data;
113
-
u16 dev_id, irq_index;
92
+
struct irq_data *data;
93
+
int out_irq;
114
94
115
-
parent_data = irq_domain_get_irq_data(domain->parent, virq);
116
95
data = irq_domain_get_irq_data(domain, virq);
117
-
irq_index = HWIRQ_TO_IRQID(data->hwirq);
118
-
dev_id = HWIRQ_TO_DEVID(data->hwirq);
96
+
out_irq = (uintptr_t)data->chip_data;
119
97
120
-
intr->sci->ops.rm_irq_ops.free_irq(intr->sci, dev_id, irq_index,
121
-
intr->dst_id, parent_data->hwirq);
122
-
ti_sci_release_resource(intr->dst_irq, parent_data->hwirq);
98
+
intr->sci->ops.rm_irq_ops.free_irq(intr->sci,
99
+
intr->ti_sci_id, data->hwirq,
100
+
intr->ti_sci_id, out_irq);
101
+
ti_sci_release_resource(intr->out_irqs, out_irq);
123
102
irq_domain_free_irqs_parent(domain, virq, 1);
124
103
irq_domain_reset_irq_data(data);
125
104
}
126
105
127
106
/**
128
-
* ti_sci_intr_alloc_gic_irq() - Allocate GIC specific IRQ
107
+
* ti_sci_intr_alloc_parent_irq() - Allocate parent IRQ
129
108
* @domain: Pointer to the interrupt router IRQ domain
130
109
* @virq: Corresponding Linux virtual IRQ number
131
110
* @hwirq: Corresponding hwirq for the IRQ within this IRQ domain
132
111
*
133
-
* Returns 0 if all went well else appropriate error pointer.
112
+
* Returns parent irq if all went well else appropriate error pointer.
134
113
*/
135
-
static int ti_sci_intr_alloc_gic_irq(struct irq_domain *domain,
136
-
unsigned int virq, u32 hwirq)
114
+
static int ti_sci_intr_alloc_parent_irq(struct irq_domain *domain,
115
+
unsigned int virq, u32 hwirq)
137
116
{
138
117
struct ti_sci_intr_irq_domain *intr = domain->host_data;
118
+
struct device_node *parent_node;
139
119
struct irq_fwspec fwspec;
140
-
u16 dev_id, irq_index;
141
-
u16 dst_irq;
142
-
int err;
120
+
u16 out_irq, p_hwirq;
121
+
int err = 0;
143
122
144
-
dev_id = HWIRQ_TO_DEVID(hwirq);
145
-
irq_index = HWIRQ_TO_IRQID(hwirq);
146
-
147
-
dst_irq = ti_sci_get_free_resource(intr->dst_irq);
148
-
if (dst_irq == TI_SCI_RESOURCE_NULL)
123
+
out_irq = ti_sci_get_free_resource(intr->out_irqs);
124
+
if (out_irq == TI_SCI_RESOURCE_NULL)
149
125
return -EINVAL;
150
126
151
-
fwspec.fwnode = domain->parent->fwnode;
152
-
fwspec.param_count = 3;
153
-
fwspec.param[0] = 0; /* SPI */
154
-
fwspec.param[1] = dst_irq - 32; /* SPI offset */
155
-
fwspec.param[2] = intr->type;
127
+
p_hwirq = ti_sci_intr_xlate_irq(intr, out_irq);
128
+
if (p_hwirq < 0)
129
+
goto err_irqs;
130
+
131
+
parent_node = of_irq_find_parent(dev_of_node(intr->dev));
132
+
fwspec.fwnode = of_node_to_fwnode(parent_node);
133
+
134
+
if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
135
+
/* Parent is GIC */
136
+
fwspec.param_count = 3;
137
+
fwspec.param[0] = 0; /* SPI */
138
+
fwspec.param[1] = p_hwirq - 32; /* SPI offset */
139
+
fwspec.param[2] = intr->type;
140
+
} else {
141
+
/* Parent is Interrupt Router */
142
+
fwspec.param_count = 1;
143
+
fwspec.param[0] = p_hwirq;
144
+
}
156
145
157
146
err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
158
147
if (err)
159
148
goto err_irqs;
160
149
161
-
err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci, dev_id, irq_index,
162
-
intr->dst_id, dst_irq);
150
+
err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci,
151
+
intr->ti_sci_id, hwirq,
152
+
intr->ti_sci_id, out_irq);
163
153
if (err)
164
154
goto err_msg;
165
155
166
-
return 0;
156
+
return p_hwirq;
167
157
168
158
err_msg:
169
159
irq_domain_free_irqs_parent(domain, virq, 1);
170
160
err_irqs:
171
-
ti_sci_release_resource(intr->dst_irq, dst_irq);
161
+
ti_sci_release_resource(intr->out_irqs, out_irq);
172
162
return err;
173
163
}
174
164
···
198
168
struct irq_fwspec *fwspec = data;
199
169
unsigned long hwirq;
200
170
unsigned int flags;
201
-
int err;
171
+
int err, p_hwirq;
202
172
203
173
err = ti_sci_intr_irq_domain_translate(domain, fwspec, &hwirq, &flags);
204
174
if (err)
205
175
return err;
206
176
207
-
err = ti_sci_intr_alloc_gic_irq(domain, virq, hwirq);
208
-
if (err)
209
-
return err;
177
+
p_hwirq = ti_sci_intr_alloc_parent_irq(domain, virq, hwirq);
178
+
if (p_hwirq < 0)
179
+
return p_hwirq;
210
180
211
181
irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
212
-
&ti_sci_intr_irq_chip, NULL);
182
+
&ti_sci_intr_irq_chip,
183
+
(void *)(uintptr_t)p_hwirq);
213
184
214
185
return 0;
215
186
}
···
245
214
if (!intr)
246
215
return -ENOMEM;
247
216
217
+
intr->dev = dev;
248
218
ret = of_property_read_u32(dev_of_node(dev), "ti,intr-trigger-type",
249
219
&intr->type);
250
220
if (ret) {
···
262
230
return ret;
263
231
}
264
232
265
-
ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dst-id",
266
-
&intr->dst_id);
233
+
ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dev-id",
234
+
&intr->ti_sci_id);
267
235
if (ret) {
268
-
dev_err(dev, "missing 'ti,sci-dst-id' property\n");
236
+
dev_err(dev, "missing 'ti,sci-dev-id' property\n");
269
237
return -EINVAL;
270
238
}
271
239
272
-
intr->dst_irq = devm_ti_sci_get_of_resource(intr->sci, dev,
273
-
intr->dst_id,
274
-
"ti,sci-rm-range-girq");
275
-
if (IS_ERR(intr->dst_irq)) {
240
+
intr->out_irqs = devm_ti_sci_get_resource(intr->sci, dev,
241
+
intr->ti_sci_id,
242
+
TI_SCI_RESASG_SUBTYPE_IR_OUTPUT);
243
+
if (IS_ERR(intr->out_irqs)) {
276
244
dev_err(dev, "Destination irq resource allocation failed\n");
277
-
return PTR_ERR(intr->dst_irq);
245
+
return PTR_ERR(intr->out_irqs);
278
246
}
279
247
280
248
domain = irq_domain_add_hierarchy(parent_domain, 0, 0, dev_of_node(dev),
···
283
251
dev_err(dev, "Failed to allocate IRQ domain\n");
284
252
return -ENOMEM;
285
253
}
254
+
255
+
dev_info(dev, "Interrupt Router %d domain created\n", intr->ti_sci_id);
286
256
287
257
return 0;
288
258
}
+1
-1
drivers/irqchip/irqchip.c
+1
-1
drivers/irqchip/irqchip.c
···
52
52
* interrupt controller. The actual initialization callback of this
53
53
* interrupt controller can check for specific domains as necessary.
54
54
*/
55
-
if (par_np && !irq_find_matching_host(np, DOMAIN_BUS_ANY))
55
+
if (par_np && !irq_find_matching_host(par_np, DOMAIN_BUS_ANY))
56
56
return -EPROBE_DEFER;
57
57
58
58
return irq_init_cb(np, par_np);
+1
-7
drivers/irqchip/qcom-pdc.c
+1
-7
drivers/irqchip/qcom-pdc.c
···
11
11
#include <linux/irqdomain.h>
12
12
#include <linux/io.h>
13
13
#include <linux/kernel.h>
14
-
#include <linux/module.h>
15
14
#include <linux/of.h>
16
15
#include <linux/of_address.h>
17
16
#include <linux/of_device.h>
18
-
#include <linux/of_irq.h>
19
17
#include <linux/soc/qcom/irq.h>
20
18
#include <linux/spinlock.h>
21
19
#include <linux/slab.h>
···
430
432
return ret;
431
433
}
432
434
433
-
IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
434
-
IRQCHIP_MATCH("qcom,pdc", qcom_pdc_init)
435
-
IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
436
-
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
437
-
MODULE_LICENSE("GPL v2");
435
+
IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);
+13
include/linux/soc/ti/ti_sci_protocol.h
+13
include/linux/soc/ti/ti_sci_protocol.h
···
220
220
u16 *range_start, u16 *range_num);
221
221
};
222
222
223
+
#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
224
+
#define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
225
+
#define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
223
226
/**
224
227
* struct ti_sci_rm_irq_ops: IRQ management operations
225
228
* @set_irq: Set an IRQ route between the requested source
···
559
556
struct ti_sci_resource *
560
557
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
561
558
struct device *dev, u32 dev_id, char *of_prop);
559
+
struct ti_sci_resource *
560
+
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
561
+
u32 dev_id, u32 sub_type);
562
562
563
563
#else /* CONFIG_TI_SCI_PROTOCOL */
564
564
···
612
606
static inline struct ti_sci_resource *
613
607
devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
614
608
struct device *dev, u32 dev_id, char *of_prop)
609
+
{
610
+
return ERR_PTR(-EINVAL);
611
+
}
612
+
613
+
static inline struct ti_sci_resource *
614
+
devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
615
+
u32 dev_id, u32 sub_type);
615
616
{
616
617
return ERR_PTR(-EINVAL);
617
618
}