tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: Add Fiji smu 7.1.3 headers (v2)

v2: agd5f: prepare for release

Signed-off-by: David Zhang <david1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

authored by

David Zhang and committed by
Alex Deucher d1c4dcfb aa8a3b53

+8608
+1246
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h
··· 1 + /* 2 + * SMU_7_1_3 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef SMU_7_1_3_D_H 25 + #define SMU_7_1_3_D_H 26 + 27 + #define mmGCK_SMC_IND_INDEX 0x80 28 + #define mmGCK0_GCK_SMC_IND_INDEX 0x80 29 + #define mmGCK1_GCK_SMC_IND_INDEX 0x82 30 + #define mmGCK2_GCK_SMC_IND_INDEX 0x84 31 + #define mmGCK3_GCK_SMC_IND_INDEX 0x86 32 + #define mmGCK_SMC_IND_DATA 0x81 33 + #define mmGCK0_GCK_SMC_IND_DATA 0x81 34 + #define mmGCK1_GCK_SMC_IND_DATA 0x83 35 + #define mmGCK2_GCK_SMC_IND_DATA 0x85 36 + #define mmGCK3_GCK_SMC_IND_DATA 0x87 37 + #define ixGCK_MCLK_FUSES 0xc0500008 38 + #define ixCG_DCLK_CNTL 0xc050009c 39 + #define ixCG_DCLK_STATUS 0xc05000a0 40 + #define ixCG_VCLK_CNTL 0xc05000a4 41 + #define ixCG_VCLK_STATUS 0xc05000a8 42 + #define ixCG_ECLK_CNTL 0xc05000ac 43 + #define ixCG_ECLK_STATUS 0xc05000b0 44 + #define ixCG_ACLK_CNTL 0xc05000dc 45 + #define ixCG_MCLK_CNTL 0xc0500120 46 + #define ixCG_MCLK_STATUS 0xc0500124 47 + #define ixGCK_DFS_BYPASS_CNTL 0xc0500118 48 + #define ixCG_SPLL_FUNC_CNTL 0xc0500140 49 + #define ixCG_SPLL_FUNC_CNTL_2 0xc0500144 50 + #define ixCG_SPLL_FUNC_CNTL_3 0xc0500148 51 + #define ixCG_SPLL_FUNC_CNTL_4 0xc050014c 52 + #define ixCG_SPLL_FUNC_CNTL_5 0xc0500150 53 + #define ixCG_SPLL_FUNC_CNTL_6 0xc0500154 54 + #define ixCG_SPLL_FUNC_CNTL_7 0xc0500158 55 + #define ixSPLL_CNTL_MODE 0xc0500160 56 + #define ixCG_SPLL_SPREAD_SPECTRUM 0xc0500164 57 + #define ixCG_SPLL_SPREAD_SPECTRUM_2 0xc0500168 58 + #define ixMPLL_BYPASSCLK_SEL 0xc050019c 59 + #define ixCG_CLKPIN_CNTL 0xc05001a0 60 + #define ixCG_CLKPIN_CNTL_2 0xc05001a4 61 + #define ixCG_CLKPIN_CNTL_DC 0xc0500204 62 + #define ixTHM_CLK_CNTL 0xc05001a8 63 + #define ixMISC_CLK_CTRL 0xc05001ac 64 + #define ixGCK_PLL_TEST_CNTL 0xc05001c0 65 + #define ixGCK_PLL_TEST_CNTL_2 0xc05001c4 66 + #define ixGCK_ADFS_CLK_BYPASS_CNTL1 0xc05001c8 67 + #define mmSMC_IND_INDEX 0x80 68 + #define mmSMC0_SMC_IND_INDEX 0x80 69 + #define mmSMC1_SMC_IND_INDEX 0x82 70 + #define mmSMC2_SMC_IND_INDEX 0x84 71 + #define mmSMC3_SMC_IND_INDEX 0x86 72 + #define mmSMC_IND_DATA 0x81 73 + #define mmSMC0_SMC_IND_DATA 0x81 74 + #define mmSMC1_SMC_IND_DATA 0x83 75 + #define mmSMC2_SMC_IND_DATA 0x85 76 + #define mmSMC3_SMC_IND_DATA 0x87 77 + #define mmSMC_IND_INDEX_0 0x80 78 + #define mmSMC_IND_DATA_0 0x81 79 + #define mmSMC_IND_INDEX_1 0x82 80 + #define mmSMC_IND_DATA_1 0x83 81 + #define mmSMC_IND_INDEX_2 0x84 82 + #define mmSMC_IND_DATA_2 0x85 83 + #define mmSMC_IND_INDEX_3 0x86 84 + #define mmSMC_IND_DATA_3 0x87 85 + #define mmSMC_IND_INDEX_4 0x88 86 + #define mmSMC_IND_DATA_4 0x89 87 + #define mmSMC_IND_INDEX_5 0x8a 88 + #define mmSMC_IND_DATA_5 0x8b 89 + #define mmSMC_IND_INDEX_6 0x8c 90 + #define mmSMC_IND_DATA_6 0x8d 91 + #define mmSMC_IND_INDEX_7 0x8e 92 + #define mmSMC_IND_DATA_7 0x8f 93 + #define mmSMC_IND_ACCESS_CNTL 0x92 94 + #define mmSMC_MESSAGE_0 0x94 95 + #define mmSMC_RESP_0 0x95 96 + #define mmSMC_MESSAGE_1 0x96 97 + #define mmSMC_RESP_1 0x97 98 + #define mmSMC_MESSAGE_2 0x98 99 + #define mmSMC_RESP_2 0x99 100 + #define mmSMC_MESSAGE_3 0x9a 101 + #define mmSMC_RESP_3 0x9b 102 + #define mmSMC_MESSAGE_4 0x9c 103 + #define mmSMC_RESP_4 0x9d 104 + #define mmSMC_MESSAGE_5 0x9e 105 + #define mmSMC_RESP_5 0x9f 106 + #define mmSMC_MESSAGE_6 0xa0 107 + #define mmSMC_RESP_6 0xa1 108 + #define mmSMC_MESSAGE_7 0xa2 109 + #define mmSMC_RESP_7 0xa3 110 + #define mmSMC_MSG_ARG_0 0xa4 111 + #define mmSMC_MSG_ARG_1 0xa5 112 + #define mmSMC_MSG_ARG_2 0xa6 113 + #define mmSMC_MSG_ARG_3 0xa7 114 + #define mmSMC_MSG_ARG_4 0xa8 115 + #define mmSMC_MSG_ARG_5 0xa9 116 + #define mmSMC_MSG_ARG_6 0xaa 117 + #define mmSMC_MSG_ARG_7 0xab 118 + #define mmSMC_MESSAGE_8 0xb5 119 + #define mmSMC_RESP_8 0xb6 120 + #define mmSMC_MESSAGE_9 0xb7 121 + #define mmSMC_RESP_9 0xb8 122 + #define mmSMC_MESSAGE_10 0xb9 123 + #define mmSMC_RESP_10 0xba 124 + #define mmSMC_MESSAGE_11 0xbb 125 + #define mmSMC_RESP_11 0xbc 126 + #define mmSMC_MSG_ARG_8 0xbd 127 + #define mmSMC_MSG_ARG_9 0xbe 128 + #define mmSMC_MSG_ARG_10 0xbf 129 + #define mmSMC_MSG_ARG_11 0x93 130 + #define ixSMC_SYSCON_RESET_CNTL 0x80000000 131 + #define ixSMC_SYSCON_CLOCK_CNTL_0 0x80000004 132 + #define ixSMC_SYSCON_CLOCK_CNTL_1 0x80000008 133 + #define ixSMC_SYSCON_CLOCK_CNTL_2 0x8000000c 134 + #define ixSMC_SYSCON_MISC_CNTL 0x80000010 135 + #define ixSMC_SYSCON_MSG_ARG_0 0x80000068 136 + #define ixSMC_PC_C 0x80000370 137 + #define ixSMC_SCRATCH9 0x80000424 138 + #define mmGPIOPAD_SW_INT_STAT 0x180 139 + #define mmGPIOPAD_STRENGTH 0x181 140 + #define mmGPIOPAD_MASK 0x182 141 + #define mmGPIOPAD_A 0x183 142 + #define mmGPIOPAD_EN 0x184 143 + #define mmGPIOPAD_Y 0x185 144 + #define mmGPIOPAD_PINSTRAPS 0x186 145 + #define mmGPIOPAD_INT_STAT_EN 0x187 146 + #define mmGPIOPAD_INT_STAT 0x188 147 + #define mmGPIOPAD_INT_STAT_AK 0x189 148 + #define mmGPIOPAD_INT_EN 0x18a 149 + #define mmGPIOPAD_INT_TYPE 0x18b 150 + #define mmGPIOPAD_INT_POLARITY 0x18c 151 + #define mmGPIOPAD_EXTERN_TRIG_CNTL 0x18d 152 + #define mmGPIOPAD_RCVR_SEL 0x191 153 + #define mmGPIOPAD_PU_EN 0x192 154 + #define mmGPIOPAD_PD_EN 0x193 155 + #define mmCG_FPS_CNT 0x1b6 156 + #define mmSMU_IND_INDEX_0 0x1a6 157 + #define mmSMU_IND_DATA_0 0x1a7 158 + #define mmSMU_IND_INDEX_1 0x1a8 159 + #define mmSMU_IND_DATA_1 0x1a9 160 + #define mmSMU_IND_INDEX_2 0x1aa 161 + #define mmSMU_IND_DATA_2 0x1ab 162 + #define mmSMU_IND_INDEX_3 0x1ac 163 + #define mmSMU_IND_DATA_3 0x1ad 164 + #define mmSMU_IND_INDEX_4 0x1ae 165 + #define mmSMU_IND_DATA_4 0x1af 166 + #define mmSMU_IND_INDEX_5 0x1b0 167 + #define mmSMU_IND_DATA_5 0x1b1 168 + #define mmSMU_IND_INDEX_6 0x1b2 169 + #define mmSMU_IND_DATA_6 0x1b3 170 + #define mmSMU_IND_INDEX_7 0x1b4 171 + #define mmSMU_IND_DATA_7 0x1b5 172 + #define mmSMU_SMC_IND_INDEX 0x80 173 + #define mmSMU0_SMU_SMC_IND_INDEX 0x80 174 + #define mmSMU1_SMU_SMC_IND_INDEX 0x82 175 + #define mmSMU2_SMU_SMC_IND_INDEX 0x84 176 + #define mmSMU3_SMU_SMC_IND_INDEX 0x86 177 + #define mmSMU_SMC_IND_DATA 0x81 178 + #define mmSMU0_SMU_SMC_IND_DATA 0x81 179 + #define mmSMU1_SMU_SMC_IND_DATA 0x83 180 + #define mmSMU2_SMU_SMC_IND_DATA 0x85 181 + #define mmSMU3_SMU_SMC_IND_DATA 0x87 182 + #define ixRCU_UC_EVENTS 0xc0000004 183 + #define ixRCU_MISC_CTRL 0xc0000010 184 + #define ixRCU_VIRT_RESET_REQ 0xc0000024 185 + #define ixCC_RCU_FUSES 0xc00c0000 186 + #define ixCC_SMU_MISC_FUSES 0xc00c0004 187 + #define ixCC_SCLK_VID_FUSES 0xc00c0008 188 + #define ixCC_GIO_IOCCFG_FUSES 0xc00c000c 189 + #define ixCC_GIO_IOC_FUSES 0xc00c0010 190 + #define ixCC_SMU_TST_EFUSE1_MISC 0xc00c001c 191 + #define ixCC_TST_ID_STRAPS 0xc00c0020 192 + #define ixCC_FCTRL_FUSES 0xc00c0024 193 + #define ixCC_HARVEST_FUSES 0xc00c0028 194 + #define ixSMU_MAIN_PLL_OP_FREQ 0xe0003020 195 + #define ixSMU_STATUS 0xe0003088 196 + #define ixSMU_FIRMWARE 0xe00030a4 197 + #define ixSMU_INPUT_DATA 0xe00030b8 198 + #define ixSMU_EFUSE_0 0xc0100000 199 + #define ixFIRMWARE_FLAGS 0x3f000 200 + #define ixTDC_STATUS 0x3f004 201 + #define ixTDC_MV_AVERAGE 0x3f008 202 + #define ixTDC_VRM_LIMIT 0x3f00c 203 + #define ixFEATURE_STATUS 0x3f010 204 + #define ixENTITY_TEMPERATURES_1 0x3f014 205 + #define ixMCARB_DRAM_TIMING_TABLE_1 0x3f018 206 + #define ixMCARB_DRAM_TIMING_TABLE_2 0x3f01c 207 + #define ixMCARB_DRAM_TIMING_TABLE_3 0x3f020 208 + #define ixMCARB_DRAM_TIMING_TABLE_4 0x3f024 209 + #define ixMCARB_DRAM_TIMING_TABLE_5 0x3f028 210 + #define ixMCARB_DRAM_TIMING_TABLE_6 0x3f02c 211 + #define ixMCARB_DRAM_TIMING_TABLE_7 0x3f030 212 + #define ixMCARB_DRAM_TIMING_TABLE_8 0x3f034 213 + #define ixMCARB_DRAM_TIMING_TABLE_9 0x3f038 214 + #define ixMCARB_DRAM_TIMING_TABLE_10 0x3f03c 215 + #define ixMCARB_DRAM_TIMING_TABLE_11 0x3f040 216 + #define ixMCARB_DRAM_TIMING_TABLE_12 0x3f044 217 + #define ixMCARB_DRAM_TIMING_TABLE_13 0x3f048 218 + #define ixMCARB_DRAM_TIMING_TABLE_14 0x3f04c 219 + #define ixMCARB_DRAM_TIMING_TABLE_15 0x3f050 220 + #define ixMCARB_DRAM_TIMING_TABLE_16 0x3f054 221 + #define ixMCARB_DRAM_TIMING_TABLE_17 0x3f058 222 + #define ixMCARB_DRAM_TIMING_TABLE_18 0x3f05c 223 + #define ixMCARB_DRAM_TIMING_TABLE_19 0x3f060 224 + #define ixMCARB_DRAM_TIMING_TABLE_20 0x3f064 225 + #define ixMCARB_DRAM_TIMING_TABLE_21 0x3f068 226 + #define ixMCARB_DRAM_TIMING_TABLE_22 0x3f06c 227 + #define ixMCARB_DRAM_TIMING_TABLE_23 0x3f070 228 + #define ixMCARB_DRAM_TIMING_TABLE_24 0x3f074 229 + #define ixMCARB_DRAM_TIMING_TABLE_25 0x3f078 230 + #define ixMCARB_DRAM_TIMING_TABLE_26 0x3f07c 231 + #define ixMCARB_DRAM_TIMING_TABLE_27 0x3f080 232 + #define ixMCARB_DRAM_TIMING_TABLE_28 0x3f084 233 + #define ixMCARB_DRAM_TIMING_TABLE_29 0x3f088 234 + #define ixMCARB_DRAM_TIMING_TABLE_30 0x3f08c 235 + #define ixMCARB_DRAM_TIMING_TABLE_31 0x3f090 236 + #define ixMCARB_DRAM_TIMING_TABLE_32 0x3f094 237 + #define ixMCARB_DRAM_TIMING_TABLE_33 0x3f098 238 + #define ixMCARB_DRAM_TIMING_TABLE_34 0x3f09c 239 + #define ixMCARB_DRAM_TIMING_TABLE_35 0x3f0a0 240 + #define ixMCARB_DRAM_TIMING_TABLE_36 0x3f0a4 241 + #define ixMCARB_DRAM_TIMING_TABLE_37 0x3f0a8 242 + #define ixMCARB_DRAM_TIMING_TABLE_38 0x3f0ac 243 + #define ixMCARB_DRAM_TIMING_TABLE_39 0x3f0b0 244 + #define ixMCARB_DRAM_TIMING_TABLE_40 0x3f0b4 245 + #define ixMCARB_DRAM_TIMING_TABLE_41 0x3f0b8 246 + #define ixMCARB_DRAM_TIMING_TABLE_42 0x3f0bc 247 + #define ixMCARB_DRAM_TIMING_TABLE_43 0x3f0c0 248 + #define ixMCARB_DRAM_TIMING_TABLE_44 0x3f0c4 249 + #define ixMCARB_DRAM_TIMING_TABLE_45 0x3f0c8 250 + #define ixMCARB_DRAM_TIMING_TABLE_46 0x3f0cc 251 + #define ixMCARB_DRAM_TIMING_TABLE_47 0x3f0d0 252 + #define ixMCARB_DRAM_TIMING_TABLE_48 0x3f0d4 253 + #define ixMCARB_DRAM_TIMING_TABLE_49 0x3f0d8 254 + #define ixMCARB_DRAM_TIMING_TABLE_50 0x3f0dc 255 + #define ixMCARB_DRAM_TIMING_TABLE_51 0x3f0e0 256 + #define ixMCARB_DRAM_TIMING_TABLE_52 0x3f0e4 257 + #define ixMCARB_DRAM_TIMING_TABLE_53 0x3f0e8 258 + #define ixMCARB_DRAM_TIMING_TABLE_54 0x3f0ec 259 + #define ixMCARB_DRAM_TIMING_TABLE_55 0x3f0f0 260 + #define ixMCARB_DRAM_TIMING_TABLE_56 0x3f0f4 261 + #define ixMCARB_DRAM_TIMING_TABLE_57 0x3f0f8 262 + #define ixMCARB_DRAM_TIMING_TABLE_58 0x3f0fc 263 + #define ixMCARB_DRAM_TIMING_TABLE_59 0x3f100 264 + #define ixMCARB_DRAM_TIMING_TABLE_60 0x3f104 265 + #define ixMCARB_DRAM_TIMING_TABLE_61 0x3f108 266 + #define ixMCARB_DRAM_TIMING_TABLE_62 0x3f10c 267 + #define ixMCARB_DRAM_TIMING_TABLE_63 0x3f110 268 + #define ixMCARB_DRAM_TIMING_TABLE_64 0x3f114 269 + #define ixMCARB_DRAM_TIMING_TABLE_65 0x3f118 270 + #define ixMCARB_DRAM_TIMING_TABLE_66 0x3f11c 271 + #define ixMCARB_DRAM_TIMING_TABLE_67 0x3f120 272 + #define ixMCARB_DRAM_TIMING_TABLE_68 0x3f124 273 + #define ixMCARB_DRAM_TIMING_TABLE_69 0x3f128 274 + #define ixMCARB_DRAM_TIMING_TABLE_70 0x3f12c 275 + #define ixMCARB_DRAM_TIMING_TABLE_71 0x3f130 276 + #define ixMCARB_DRAM_TIMING_TABLE_72 0x3f134 277 + #define ixMCARB_DRAM_TIMING_TABLE_73 0x3f138 278 + #define ixMCARB_DRAM_TIMING_TABLE_74 0x3f13c 279 + #define ixMCARB_DRAM_TIMING_TABLE_75 0x3f140 280 + #define ixMCARB_DRAM_TIMING_TABLE_76 0x3f144 281 + #define ixMCARB_DRAM_TIMING_TABLE_77 0x3f148 282 + #define ixMCARB_DRAM_TIMING_TABLE_78 0x3f14c 283 + #define ixMCARB_DRAM_TIMING_TABLE_79 0x3f150 284 + #define ixMCARB_DRAM_TIMING_TABLE_80 0x3f154 285 + #define ixMCARB_DRAM_TIMING_TABLE_81 0x3f158 286 + #define ixMCARB_DRAM_TIMING_TABLE_82 0x3f15c 287 + #define ixMCARB_DRAM_TIMING_TABLE_83 0x3f160 288 + #define ixMCARB_DRAM_TIMING_TABLE_84 0x3f164 289 + #define ixMCARB_DRAM_TIMING_TABLE_85 0x3f168 290 + #define ixMCARB_DRAM_TIMING_TABLE_86 0x3f16c 291 + #define ixMCARB_DRAM_TIMING_TABLE_87 0x3f170 292 + #define ixMCARB_DRAM_TIMING_TABLE_88 0x3f174 293 + #define ixMCARB_DRAM_TIMING_TABLE_89 0x3f178 294 + #define ixMCARB_DRAM_TIMING_TABLE_90 0x3f17c 295 + #define ixMCARB_DRAM_TIMING_TABLE_91 0x3f180 296 + #define ixMCARB_DRAM_TIMING_TABLE_92 0x3f184 297 + #define ixMCARB_DRAM_TIMING_TABLE_93 0x3f188 298 + #define ixMCARB_DRAM_TIMING_TABLE_94 0x3f18c 299 + #define ixMCARB_DRAM_TIMING_TABLE_95 0x3f190 300 + #define ixMCARB_DRAM_TIMING_TABLE_96 0x3f194 301 + #define ixDPM_TABLE_1 0x3f198 302 + #define ixDPM_TABLE_2 0x3f19c 303 + #define ixDPM_TABLE_3 0x3f1a0 304 + #define ixDPM_TABLE_4 0x3f1a4 305 + #define ixDPM_TABLE_5 0x3f1a8 306 + #define ixDPM_TABLE_6 0x3f1ac 307 + #define ixDPM_TABLE_7 0x3f1b0 308 + #define ixDPM_TABLE_8 0x3f1b4 309 + #define ixDPM_TABLE_9 0x3f1b8 310 + #define ixDPM_TABLE_10 0x3f1bc 311 + #define ixDPM_TABLE_11 0x3f1c0 312 + #define ixDPM_TABLE_12 0x3f1c4 313 + #define ixDPM_TABLE_13 0x3f1c8 314 + #define ixDPM_TABLE_14 0x3f1cc 315 + #define ixDPM_TABLE_15 0x3f1d0 316 + #define ixDPM_TABLE_16 0x3f1d4 317 + #define ixDPM_TABLE_17 0x3f1d8 318 + #define ixDPM_TABLE_18 0x3f1dc 319 + #define ixDPM_TABLE_19 0x3f1e0 320 + #define ixDPM_TABLE_20 0x3f1e4 321 + #define ixDPM_TABLE_21 0x3f1e8 322 + #define ixDPM_TABLE_22 0x3f1ec 323 + #define ixDPM_TABLE_23 0x3f1f0 324 + #define ixDPM_TABLE_24 0x3f1f4 325 + #define ixDPM_TABLE_25 0x3f1f8 326 + #define ixDPM_TABLE_26 0x3f1fc 327 + #define ixDPM_TABLE_27 0x3f200 328 + #define ixDPM_TABLE_28 0x3f204 329 + #define ixDPM_TABLE_29 0x3f208 330 + #define ixDPM_TABLE_30 0x3f20c 331 + #define ixDPM_TABLE_31 0x3f210 332 + #define ixDPM_TABLE_32 0x3f214 333 + #define ixDPM_TABLE_33 0x3f218 334 + #define ixDPM_TABLE_34 0x3f21c 335 + #define ixDPM_TABLE_35 0x3f220 336 + #define ixDPM_TABLE_36 0x3f224 337 + #define ixDPM_TABLE_37 0x3f228 338 + #define ixDPM_TABLE_38 0x3f22c 339 + #define ixDPM_TABLE_39 0x3f230 340 + #define ixDPM_TABLE_40 0x3f234 341 + #define ixDPM_TABLE_41 0x3f238 342 + #define ixDPM_TABLE_42 0x3f23c 343 + #define ixDPM_TABLE_43 0x3f240 344 + #define ixDPM_TABLE_44 0x3f244 345 + #define ixDPM_TABLE_45 0x3f248 346 + #define ixDPM_TABLE_46 0x3f24c 347 + #define ixDPM_TABLE_47 0x3f250 348 + #define ixDPM_TABLE_48 0x3f254 349 + #define ixDPM_TABLE_49 0x3f258 350 + #define ixDPM_TABLE_50 0x3f25c 351 + #define ixDPM_TABLE_51 0x3f260 352 + #define ixDPM_TABLE_52 0x3f264 353 + #define ixDPM_TABLE_53 0x3f268 354 + #define ixDPM_TABLE_54 0x3f26c 355 + #define ixDPM_TABLE_55 0x3f270 356 + #define ixDPM_TABLE_56 0x3f274 357 + #define ixDPM_TABLE_57 0x3f278 358 + #define ixDPM_TABLE_58 0x3f27c 359 + #define ixDPM_TABLE_59 0x3f280 360 + #define ixDPM_TABLE_60 0x3f284 361 + #define ixDPM_TABLE_61 0x3f288 362 + #define ixDPM_TABLE_62 0x3f28c 363 + #define ixDPM_TABLE_63 0x3f290 364 + #define ixDPM_TABLE_64 0x3f294 365 + #define ixDPM_TABLE_65 0x3f298 366 + #define ixDPM_TABLE_66 0x3f29c 367 + #define ixDPM_TABLE_67 0x3f2a0 368 + #define ixDPM_TABLE_68 0x3f2a4 369 + #define ixDPM_TABLE_69 0x3f2a8 370 + #define ixDPM_TABLE_70 0x3f2ac 371 + #define ixDPM_TABLE_71 0x3f2b0 372 + #define ixDPM_TABLE_72 0x3f2b4 373 + #define ixDPM_TABLE_73 0x3f2b8 374 + #define ixDPM_TABLE_74 0x3f2bc 375 + #define ixDPM_TABLE_75 0x3f2c0 376 + #define ixDPM_TABLE_76 0x3f2c4 377 + #define ixDPM_TABLE_77 0x3f2c8 378 + #define ixDPM_TABLE_78 0x3f2cc 379 + #define ixDPM_TABLE_79 0x3f2d0 380 + #define ixDPM_TABLE_80 0x3f2d4 381 + #define ixDPM_TABLE_81 0x3f2d8 382 + #define ixDPM_TABLE_82 0x3f2dc 383 + #define ixDPM_TABLE_83 0x3f2e0 384 + #define ixDPM_TABLE_84 0x3f2e4 385 + #define ixDPM_TABLE_85 0x3f2e8 386 + #define ixDPM_TABLE_86 0x3f2ec 387 + #define ixDPM_TABLE_87 0x3f2f0 388 + #define ixDPM_TABLE_88 0x3f2f4 389 + #define ixDPM_TABLE_89 0x3f2f8 390 + #define ixDPM_TABLE_90 0x3f2fc 391 + #define ixDPM_TABLE_91 0x3f300 392 + #define ixDPM_TABLE_92 0x3f304 393 + #define ixDPM_TABLE_93 0x3f308 394 + #define ixDPM_TABLE_94 0x3f30c 395 + #define ixDPM_TABLE_95 0x3f310 396 + #define ixDPM_TABLE_96 0x3f314 397 + #define ixDPM_TABLE_97 0x3f318 398 + #define ixDPM_TABLE_98 0x3f31c 399 + #define ixDPM_TABLE_99 0x3f320 400 + #define ixDPM_TABLE_100 0x3f324 401 + #define ixDPM_TABLE_101 0x3f328 402 + #define ixDPM_TABLE_102 0x3f32c 403 + #define ixDPM_TABLE_103 0x3f330 404 + #define ixDPM_TABLE_104 0x3f334 405 + #define ixDPM_TABLE_105 0x3f338 406 + #define ixDPM_TABLE_106 0x3f33c 407 + #define ixDPM_TABLE_107 0x3f340 408 + #define ixDPM_TABLE_108 0x3f344 409 + #define ixDPM_TABLE_109 0x3f348 410 + #define ixDPM_TABLE_110 0x3f34c 411 + #define ixDPM_TABLE_111 0x3f350 412 + #define ixDPM_TABLE_112 0x3f354 413 + #define ixDPM_TABLE_113 0x3f358 414 + #define ixDPM_TABLE_114 0x3f35c 415 + #define ixDPM_TABLE_115 0x3f360 416 + #define ixDPM_TABLE_116 0x3f364 417 + #define ixDPM_TABLE_117 0x3f368 418 + #define ixDPM_TABLE_118 0x3f36c 419 + #define ixDPM_TABLE_119 0x3f370 420 + #define ixDPM_TABLE_120 0x3f374 421 + #define ixDPM_TABLE_121 0x3f378 422 + #define ixDPM_TABLE_122 0x3f37c 423 + #define ixDPM_TABLE_123 0x3f380 424 + #define ixDPM_TABLE_124 0x3f384 425 + #define ixDPM_TABLE_125 0x3f388 426 + #define ixDPM_TABLE_126 0x3f38c 427 + #define ixDPM_TABLE_127 0x3f390 428 + #define ixDPM_TABLE_128 0x3f394 429 + #define ixDPM_TABLE_129 0x3f398 430 + #define ixDPM_TABLE_130 0x3f39c 431 + #define ixDPM_TABLE_131 0x3f3a0 432 + #define ixDPM_TABLE_132 0x3f3a4 433 + #define ixDPM_TABLE_133 0x3f3a8 434 + #define ixDPM_TABLE_134 0x3f3ac 435 + #define ixDPM_TABLE_135 0x3f3b0 436 + #define ixDPM_TABLE_136 0x3f3b4 437 + #define ixDPM_TABLE_137 0x3f3b8 438 + #define ixDPM_TABLE_138 0x3f3bc 439 + #define ixDPM_TABLE_139 0x3f3c0 440 + #define ixDPM_TABLE_140 0x3f3c4 441 + #define ixDPM_TABLE_141 0x3f3c8 442 + #define ixDPM_TABLE_142 0x3f3cc 443 + #define ixDPM_TABLE_143 0x3f3d0 444 + #define ixDPM_TABLE_144 0x3f3d4 445 + #define ixDPM_TABLE_145 0x3f3d8 446 + #define ixDPM_TABLE_146 0x3f3dc 447 + #define ixDPM_TABLE_147 0x3f3e0 448 + #define ixDPM_TABLE_148 0x3f3e4 449 + #define ixDPM_TABLE_149 0x3f3e8 450 + #define ixDPM_TABLE_150 0x3f3ec 451 + #define ixDPM_TABLE_151 0x3f3f0 452 + #define ixDPM_TABLE_152 0x3f3f4 453 + #define ixDPM_TABLE_153 0x3f3f8 454 + #define ixDPM_TABLE_154 0x3f3fc 455 + #define ixDPM_TABLE_155 0x3f400 456 + #define ixDPM_TABLE_156 0x3f404 457 + #define ixDPM_TABLE_157 0x3f408 458 + #define ixDPM_TABLE_158 0x3f40c 459 + #define ixDPM_TABLE_159 0x3f410 460 + #define ixDPM_TABLE_160 0x3f414 461 + #define ixDPM_TABLE_161 0x3f418 462 + #define ixDPM_TABLE_162 0x3f41c 463 + #define ixDPM_TABLE_163 0x3f420 464 + #define ixDPM_TABLE_164 0x3f424 465 + #define ixDPM_TABLE_165 0x3f428 466 + #define ixDPM_TABLE_166 0x3f42c 467 + #define ixDPM_TABLE_167 0x3f430 468 + #define ixDPM_TABLE_168 0x3f434 469 + #define ixDPM_TABLE_169 0x3f438 470 + #define ixDPM_TABLE_170 0x3f43c 471 + #define ixDPM_TABLE_171 0x3f440 472 + #define ixDPM_TABLE_172 0x3f444 473 + #define ixDPM_TABLE_173 0x3f448 474 + #define ixDPM_TABLE_174 0x3f44c 475 + #define ixDPM_TABLE_175 0x3f450 476 + #define ixDPM_TABLE_176 0x3f454 477 + #define ixDPM_TABLE_177 0x3f458 478 + #define ixDPM_TABLE_178 0x3f45c 479 + #define ixDPM_TABLE_179 0x3f460 480 + #define ixDPM_TABLE_180 0x3f464 481 + #define ixDPM_TABLE_181 0x3f468 482 + #define ixDPM_TABLE_182 0x3f46c 483 + #define ixDPM_TABLE_183 0x3f470 484 + #define ixDPM_TABLE_184 0x3f474 485 + #define ixDPM_TABLE_185 0x3f478 486 + #define ixDPM_TABLE_186 0x3f47c 487 + #define ixDPM_TABLE_187 0x3f480 488 + #define ixDPM_TABLE_188 0x3f484 489 + #define ixDPM_TABLE_189 0x3f488 490 + #define ixDPM_TABLE_190 0x3f48c 491 + #define ixDPM_TABLE_191 0x3f490 492 + #define ixDPM_TABLE_192 0x3f494 493 + #define ixDPM_TABLE_193 0x3f498 494 + #define ixDPM_TABLE_194 0x3f49c 495 + #define ixDPM_TABLE_195 0x3f4a0 496 + #define ixDPM_TABLE_196 0x3f4a4 497 + #define ixDPM_TABLE_197 0x3f4a8 498 + #define ixDPM_TABLE_198 0x3f4ac 499 + #define ixDPM_TABLE_199 0x3f4b0 500 + #define ixDPM_TABLE_200 0x3f4b4 501 + #define ixDPM_TABLE_201 0x3f4b8 502 + #define ixDPM_TABLE_202 0x3f4bc 503 + #define ixDPM_TABLE_203 0x3f4c0 504 + #define ixDPM_TABLE_204 0x3f4c4 505 + #define ixDPM_TABLE_205 0x3f4c8 506 + #define ixDPM_TABLE_206 0x3f4cc 507 + #define ixDPM_TABLE_207 0x3f4d0 508 + #define ixDPM_TABLE_208 0x3f4d4 509 + #define ixDPM_TABLE_209 0x3f4d8 510 + #define ixDPM_TABLE_210 0x3f4dc 511 + #define ixDPM_TABLE_211 0x3f4e0 512 + #define ixDPM_TABLE_212 0x3f4e4 513 + #define ixDPM_TABLE_213 0x3f4e8 514 + #define ixDPM_TABLE_214 0x3f4ec 515 + #define ixDPM_TABLE_215 0x3f4f0 516 + #define ixDPM_TABLE_216 0x3f4f4 517 + #define ixDPM_TABLE_217 0x3f4f8 518 + #define ixDPM_TABLE_218 0x3f4fc 519 + #define ixDPM_TABLE_219 0x3f500 520 + #define ixDPM_TABLE_220 0x3f504 521 + #define ixDPM_TABLE_221 0x3f508 522 + #define ixDPM_TABLE_222 0x3f50c 523 + #define ixDPM_TABLE_223 0x3f510 524 + #define ixDPM_TABLE_224 0x3f514 525 + #define ixDPM_TABLE_225 0x3f518 526 + #define ixDPM_TABLE_226 0x3f51c 527 + #define ixDPM_TABLE_227 0x3f520 528 + #define ixDPM_TABLE_228 0x3f524 529 + #define ixDPM_TABLE_229 0x3f528 530 + #define ixDPM_TABLE_230 0x3f52c 531 + #define ixDPM_TABLE_231 0x3f530 532 + #define ixDPM_TABLE_232 0x3f534 533 + #define ixDPM_TABLE_233 0x3f538 534 + #define ixDPM_TABLE_234 0x3f53c 535 + #define ixDPM_TABLE_235 0x3f540 536 + #define ixDPM_TABLE_236 0x3f544 537 + #define ixDPM_TABLE_237 0x3f548 538 + #define ixDPM_TABLE_238 0x3f54c 539 + #define ixDPM_TABLE_239 0x3f550 540 + #define ixDPM_TABLE_240 0x3f554 541 + #define ixDPM_TABLE_241 0x3f558 542 + #define ixDPM_TABLE_242 0x3f55c 543 + #define ixDPM_TABLE_243 0x3f560 544 + #define ixDPM_TABLE_244 0x3f564 545 + #define ixDPM_TABLE_245 0x3f568 546 + #define ixDPM_TABLE_246 0x3f56c 547 + #define ixDPM_TABLE_247 0x3f570 548 + #define ixDPM_TABLE_248 0x3f574 549 + #define ixDPM_TABLE_249 0x3f578 550 + #define ixDPM_TABLE_250 0x3f57c 551 + #define ixDPM_TABLE_251 0x3f580 552 + #define ixDPM_TABLE_252 0x3f584 553 + #define ixDPM_TABLE_253 0x3f588 554 + #define ixDPM_TABLE_254 0x3f58c 555 + #define ixDPM_TABLE_255 0x3f590 556 + #define ixDPM_TABLE_256 0x3f594 557 + #define ixDPM_TABLE_257 0x3f598 558 + #define ixDPM_TABLE_258 0x3f59c 559 + #define ixDPM_TABLE_259 0x3f5a0 560 + #define ixDPM_TABLE_260 0x3f5a4 561 + #define ixDPM_TABLE_261 0x3f5a8 562 + #define ixDPM_TABLE_262 0x3f5ac 563 + #define ixDPM_TABLE_263 0x3f5b0 564 + #define ixDPM_TABLE_264 0x3f5b4 565 + #define ixDPM_TABLE_265 0x3f5b8 566 + #define ixDPM_TABLE_266 0x3f5bc 567 + #define ixDPM_TABLE_267 0x3f5c0 568 + #define ixDPM_TABLE_268 0x3f5c4 569 + #define ixDPM_TABLE_269 0x3f5c8 570 + #define ixDPM_TABLE_270 0x3f5cc 571 + #define ixDPM_TABLE_271 0x3f5d0 572 + #define ixDPM_TABLE_272 0x3f5d4 573 + #define ixDPM_TABLE_273 0x3f5d8 574 + #define ixDPM_TABLE_274 0x3f5dc 575 + #define ixDPM_TABLE_275 0x3f5e0 576 + #define ixDPM_TABLE_276 0x3f5e4 577 + #define ixDPM_TABLE_277 0x3f5e8 578 + #define ixDPM_TABLE_278 0x3f5ec 579 + #define ixDPM_TABLE_279 0x3f5f0 580 + #define ixDPM_TABLE_280 0x3f5f4 581 + #define ixDPM_TABLE_281 0x3f5f8 582 + #define ixDPM_TABLE_282 0x3f5fc 583 + #define ixDPM_TABLE_283 0x3f600 584 + #define ixDPM_TABLE_284 0x3f604 585 + #define ixDPM_TABLE_285 0x3f608 586 + #define ixDPM_TABLE_286 0x3f60c 587 + #define ixDPM_TABLE_287 0x3f610 588 + #define ixDPM_TABLE_288 0x3f614 589 + #define ixDPM_TABLE_289 0x3f618 590 + #define ixDPM_TABLE_290 0x3f61c 591 + #define ixDPM_TABLE_291 0x3f620 592 + #define ixDPM_TABLE_292 0x3f624 593 + #define ixDPM_TABLE_293 0x3f628 594 + #define ixDPM_TABLE_294 0x3f62c 595 + #define ixDPM_TABLE_295 0x3f630 596 + #define ixDPM_TABLE_296 0x3f634 597 + #define ixDPM_TABLE_297 0x3f638 598 + #define ixDPM_TABLE_298 0x3f63c 599 + #define ixDPM_TABLE_299 0x3f640 600 + #define ixDPM_TABLE_300 0x3f644 601 + #define ixDPM_TABLE_301 0x3f648 602 + #define ixDPM_TABLE_302 0x3f64c 603 + #define ixDPM_TABLE_303 0x3f650 604 + #define ixDPM_TABLE_304 0x3f654 605 + #define ixDPM_TABLE_305 0x3f658 606 + #define ixDPM_TABLE_306 0x3f65c 607 + #define ixDPM_TABLE_307 0x3f660 608 + #define ixDPM_TABLE_308 0x3f664 609 + #define ixDPM_TABLE_309 0x3f668 610 + #define ixDPM_TABLE_310 0x3f66c 611 + #define ixDPM_TABLE_311 0x3f670 612 + #define ixDPM_TABLE_312 0x3f674 613 + #define ixDPM_TABLE_313 0x3f678 614 + #define ixDPM_TABLE_314 0x3f67c 615 + #define ixDPM_TABLE_315 0x3f680 616 + #define ixDPM_TABLE_316 0x3f684 617 + #define ixDPM_TABLE_317 0x3f688 618 + #define ixDPM_TABLE_318 0x3f68c 619 + #define ixDPM_TABLE_319 0x3f690 620 + #define ixDPM_TABLE_320 0x3f694 621 + #define ixDPM_TABLE_321 0x3f698 622 + #define ixDPM_TABLE_322 0x3f69c 623 + #define ixDPM_TABLE_323 0x3f6a0 624 + #define ixDPM_TABLE_324 0x3f6a4 625 + #define ixDPM_TABLE_325 0x3f6a8 626 + #define ixDPM_TABLE_326 0x3f6ac 627 + #define ixDPM_TABLE_327 0x3f6b0 628 + #define ixDPM_TABLE_328 0x3f6b4 629 + #define ixDPM_TABLE_329 0x3f6b8 630 + #define ixDPM_TABLE_330 0x3f6bc 631 + #define ixDPM_TABLE_331 0x3f6c0 632 + #define ixDPM_TABLE_332 0x3f6c4 633 + #define ixDPM_TABLE_333 0x3f6c8 634 + #define ixDPM_TABLE_334 0x3f6cc 635 + #define ixDPM_TABLE_335 0x3f6d0 636 + #define ixDPM_TABLE_336 0x3f6d4 637 + #define ixDPM_TABLE_337 0x3f6d8 638 + #define ixDPM_TABLE_338 0x3f6dc 639 + #define ixDPM_TABLE_339 0x3f6e0 640 + #define ixDPM_TABLE_340 0x3f6e4 641 + #define ixDPM_TABLE_341 0x3f6e8 642 + #define ixDPM_TABLE_342 0x3f6ec 643 + #define ixDPM_TABLE_343 0x3f6f0 644 + #define ixDPM_TABLE_344 0x3f6f4 645 + #define ixDPM_TABLE_345 0x3f6f8 646 + #define ixDPM_TABLE_346 0x3f6fc 647 + #define ixDPM_TABLE_347 0x3f700 648 + #define ixDPM_TABLE_348 0x3f704 649 + #define ixDPM_TABLE_349 0x3f708 650 + #define ixDPM_TABLE_350 0x3f70c 651 + #define ixDPM_TABLE_351 0x3f710 652 + #define ixDPM_TABLE_352 0x3f714 653 + #define ixDPM_TABLE_353 0x3f718 654 + #define ixDPM_TABLE_354 0x3f71c 655 + #define ixDPM_TABLE_355 0x3f720 656 + #define ixDPM_TABLE_356 0x3f724 657 + #define ixDPM_TABLE_357 0x3f728 658 + #define ixDPM_TABLE_358 0x3f72c 659 + #define ixDPM_TABLE_359 0x3f730 660 + #define ixDPM_TABLE_360 0x3f734 661 + #define ixDPM_TABLE_361 0x3f738 662 + #define ixDPM_TABLE_362 0x3f73c 663 + #define ixDPM_TABLE_363 0x3f740 664 + #define ixDPM_TABLE_364 0x3f744 665 + #define ixDPM_TABLE_365 0x3f748 666 + #define ixDPM_TABLE_366 0x3f74c 667 + #define ixDPM_TABLE_367 0x3f750 668 + #define ixDPM_TABLE_368 0x3f754 669 + #define ixDPM_TABLE_369 0x3f758 670 + #define ixDPM_TABLE_370 0x3f75c 671 + #define ixDPM_TABLE_371 0x3f760 672 + #define ixDPM_TABLE_372 0x3f764 673 + #define ixDPM_TABLE_373 0x3f768 674 + #define ixDPM_TABLE_374 0x3f76c 675 + #define ixDPM_TABLE_375 0x3f770 676 + #define ixDPM_TABLE_376 0x3f774 677 + #define ixDPM_TABLE_377 0x3f778 678 + #define ixDPM_TABLE_378 0x3f77c 679 + #define ixDPM_TABLE_379 0x3f780 680 + #define ixDPM_TABLE_380 0x3f784 681 + #define ixDPM_TABLE_381 0x3f788 682 + #define ixDPM_TABLE_382 0x3f78c 683 + #define ixDPM_TABLE_383 0x3f790 684 + #define ixDPM_TABLE_384 0x3f794 685 + #define ixDPM_TABLE_385 0x3f798 686 + #define ixDPM_TABLE_386 0x3f79c 687 + #define ixDPM_TABLE_387 0x3f7a0 688 + #define ixDPM_TABLE_388 0x3f7a4 689 + #define ixDPM_TABLE_389 0x3f7a8 690 + #define ixDPM_TABLE_390 0x3f7ac 691 + #define ixDPM_TABLE_391 0x3f7b0 692 + #define ixDPM_TABLE_392 0x3f7b4 693 + #define ixDPM_TABLE_393 0x3f7b8 694 + #define ixDPM_TABLE_394 0x3f7bc 695 + #define ixDPM_TABLE_395 0x3f7c0 696 + #define ixDPM_TABLE_396 0x3f7c4 697 + #define ixDPM_TABLE_397 0x3f7c8 698 + #define ixDPM_TABLE_398 0x3f7cc 699 + #define ixDPM_TABLE_399 0x3f7d0 700 + #define ixDPM_TABLE_400 0x3f7d4 701 + #define ixDPM_TABLE_401 0x3f7d8 702 + #define ixDPM_TABLE_402 0x3f7dc 703 + #define ixDPM_TABLE_403 0x3f7e0 704 + #define ixDPM_TABLE_404 0x3f7e4 705 + #define ixDPM_TABLE_405 0x3f7e8 706 + #define ixDPM_TABLE_406 0x3f7ec 707 + #define ixDPM_TABLE_407 0x3f7f0 708 + #define ixDPM_TABLE_408 0x3f7f4 709 + #define ixDPM_TABLE_409 0x3f7f8 710 + #define ixDPM_TABLE_410 0x3f7fc 711 + #define ixDPM_TABLE_411 0x3f800 712 + #define ixDPM_TABLE_412 0x3f804 713 + #define ixDPM_TABLE_413 0x3f808 714 + #define ixDPM_TABLE_414 0x3f80c 715 + #define ixDPM_TABLE_415 0x3f810 716 + #define ixDPM_TABLE_416 0x3f814 717 + #define ixDPM_TABLE_417 0x3f818 718 + #define ixDPM_TABLE_418 0x3f81c 719 + #define ixDPM_TABLE_419 0x3f820 720 + #define ixDPM_TABLE_420 0x3f824 721 + #define ixDPM_TABLE_421 0x3f828 722 + #define ixDPM_TABLE_422 0x3f82c 723 + #define ixDPM_TABLE_423 0x3f830 724 + #define ixDPM_TABLE_424 0x3f834 725 + #define ixDPM_TABLE_425 0x3f838 726 + #define ixDPM_TABLE_426 0x3f83c 727 + #define ixDPM_TABLE_427 0x3f840 728 + #define ixDPM_TABLE_428 0x3f844 729 + #define ixDPM_TABLE_429 0x3f848 730 + #define ixDPM_TABLE_430 0x3f84c 731 + #define ixDPM_TABLE_431 0x3f850 732 + #define ixDPM_TABLE_432 0x3f854 733 + #define ixDPM_TABLE_433 0x3f858 734 + #define ixDPM_TABLE_434 0x3f85c 735 + #define ixDPM_TABLE_435 0x3f860 736 + #define ixDPM_TABLE_436 0x3f864 737 + #define ixDPM_TABLE_437 0x3f868 738 + #define ixDPM_TABLE_438 0x3f86c 739 + #define ixDPM_TABLE_439 0x3f870 740 + #define ixDPM_TABLE_440 0x3f874 741 + #define ixSOFT_REGISTERS_TABLE_1 0x3f89c 742 + #define ixSOFT_REGISTERS_TABLE_2 0x3f8a0 743 + #define ixSOFT_REGISTERS_TABLE_3 0x3f8a4 744 + #define ixSOFT_REGISTERS_TABLE_4 0x3f8a8 745 + #define ixSOFT_REGISTERS_TABLE_5 0x3f8ac 746 + #define ixSOFT_REGISTERS_TABLE_6 0x3f8b0 747 + #define ixSOFT_REGISTERS_TABLE_7 0x3f8b4 748 + #define ixSOFT_REGISTERS_TABLE_8 0x3f8b8 749 + #define ixSOFT_REGISTERS_TABLE_9 0x3f8bc 750 + #define ixSOFT_REGISTERS_TABLE_10 0x3f8c0 751 + #define ixSOFT_REGISTERS_TABLE_11 0x3f8c4 752 + #define ixSOFT_REGISTERS_TABLE_12 0x3f8c8 753 + #define ixSOFT_REGISTERS_TABLE_13 0x3f8cc 754 + #define ixSOFT_REGISTERS_TABLE_14 0x3f8d0 755 + #define ixSOFT_REGISTERS_TABLE_15 0x3f8d4 756 + #define ixSOFT_REGISTERS_TABLE_16 0x3f8d8 757 + #define ixSOFT_REGISTERS_TABLE_17 0x3f8dc 758 + #define ixSOFT_REGISTERS_TABLE_18 0x3f8e0 759 + #define ixSOFT_REGISTERS_TABLE_19 0x3f8e4 760 + #define ixSOFT_REGISTERS_TABLE_20 0x3f8e8 761 + #define ixSOFT_REGISTERS_TABLE_21 0x3f8ec 762 + #define ixSOFT_REGISTERS_TABLE_22 0x3f8f0 763 + #define ixSOFT_REGISTERS_TABLE_23 0x3f8f4 764 + #define ixSOFT_REGISTERS_TABLE_24 0x3f8f8 765 + #define ixSOFT_REGISTERS_TABLE_25 0x3f8fc 766 + #define ixSOFT_REGISTERS_TABLE_26 0x3f900 767 + #define ixSOFT_REGISTERS_TABLE_27 0x3f904 768 + #define ixSOFT_REGISTERS_TABLE_28 0x3f888 769 + #define ixSOFT_REGISTERS_TABLE_29 0x3f90c 770 + #define ixSOFT_REGISTERS_TABLE_30 0x3f910 771 + #define ixPM_FUSES_1 0x3f914 772 + #define ixPM_FUSES_2 0x3f918 773 + #define ixPM_FUSES_3 0x3f91c 774 + #define ixPM_FUSES_4 0x3f920 775 + #define ixPM_FUSES_5 0x3f924 776 + #define ixPM_FUSES_6 0x3f928 777 + #define ixPM_FUSES_7 0x3f92c 778 + #define ixPM_FUSES_8 0x3f930 779 + #define ixPM_FUSES_9 0x3f934 780 + #define ixPM_FUSES_10 0x3f938 781 + #define ixPM_FUSES_11 0x3f93c 782 + #define ixPM_FUSES_12 0x3f940 783 + #define ixPM_FUSES_13 0x3f944 784 + #define ixPM_FUSES_14 0x3f948 785 + #define ixPM_FUSES_15 0x3f94c 786 + #define ixSMU_PM_STATUS_0 0x3fe00 787 + #define ixSMU_PM_STATUS_1 0x3fe04 788 + #define ixSMU_PM_STATUS_2 0x3fe08 789 + #define ixSMU_PM_STATUS_3 0x3fe0c 790 + #define ixSMU_PM_STATUS_4 0x3fe10 791 + #define ixSMU_PM_STATUS_5 0x3fe14 792 + #define ixSMU_PM_STATUS_6 0x3fe18 793 + #define ixSMU_PM_STATUS_7 0x3fe1c 794 + #define ixSMU_PM_STATUS_8 0x3fe20 795 + #define ixSMU_PM_STATUS_9 0x3fe24 796 + #define ixSMU_PM_STATUS_10 0x3fe28 797 + #define ixSMU_PM_STATUS_11 0x3fe2c 798 + #define ixSMU_PM_STATUS_12 0x3fe30 799 + #define ixSMU_PM_STATUS_13 0x3fe34 800 + #define ixSMU_PM_STATUS_14 0x3fe38 801 + #define ixSMU_PM_STATUS_15 0x3fe3c 802 + #define ixSMU_PM_STATUS_16 0x3fe40 803 + #define ixSMU_PM_STATUS_17 0x3fe44 804 + #define ixSMU_PM_STATUS_18 0x3fe48 805 + #define ixSMU_PM_STATUS_19 0x3fe4c 806 + #define ixSMU_PM_STATUS_20 0x3fe50 807 + #define ixSMU_PM_STATUS_21 0x3fe54 808 + #define ixSMU_PM_STATUS_22 0x3fe58 809 + #define ixSMU_PM_STATUS_23 0x3fe5c 810 + #define ixSMU_PM_STATUS_24 0x3fe60 811 + #define ixSMU_PM_STATUS_25 0x3fe64 812 + #define ixSMU_PM_STATUS_26 0x3fe68 813 + #define ixSMU_PM_STATUS_27 0x3fe6c 814 + #define ixSMU_PM_STATUS_28 0x3fe70 815 + #define ixSMU_PM_STATUS_29 0x3fe74 816 + #define ixSMU_PM_STATUS_30 0x3fe78 817 + #define ixSMU_PM_STATUS_31 0x3fe7c 818 + #define ixSMU_PM_STATUS_32 0x3fe80 819 + #define ixSMU_PM_STATUS_33 0x3fe84 820 + #define ixSMU_PM_STATUS_34 0x3fe88 821 + #define ixSMU_PM_STATUS_35 0x3fe8c 822 + #define ixSMU_PM_STATUS_36 0x3fe90 823 + #define ixSMU_PM_STATUS_37 0x3fe94 824 + #define ixSMU_PM_STATUS_38 0x3fe98 825 + #define ixSMU_PM_STATUS_39 0x3fe9c 826 + #define ixSMU_PM_STATUS_40 0x3fea0 827 + #define ixSMU_PM_STATUS_41 0x3fea4 828 + #define ixSMU_PM_STATUS_42 0x3fea8 829 + #define ixSMU_PM_STATUS_43 0x3feac 830 + #define ixSMU_PM_STATUS_44 0x3feb0 831 + #define ixSMU_PM_STATUS_45 0x3feb4 832 + #define ixSMU_PM_STATUS_46 0x3feb8 833 + #define ixSMU_PM_STATUS_47 0x3febc 834 + #define ixSMU_PM_STATUS_48 0x3fec0 835 + #define ixSMU_PM_STATUS_49 0x3fec4 836 + #define ixSMU_PM_STATUS_50 0x3fec8 837 + #define ixSMU_PM_STATUS_51 0x3fecc 838 + #define ixSMU_PM_STATUS_52 0x3fed0 839 + #define ixSMU_PM_STATUS_53 0x3fed4 840 + #define ixSMU_PM_STATUS_54 0x3fed8 841 + #define ixSMU_PM_STATUS_55 0x3fedc 842 + #define ixSMU_PM_STATUS_56 0x3fee0 843 + #define ixSMU_PM_STATUS_57 0x3fee4 844 + #define ixSMU_PM_STATUS_58 0x3fee8 845 + #define ixSMU_PM_STATUS_59 0x3feec 846 + #define ixSMU_PM_STATUS_60 0x3fef0 847 + #define ixSMU_PM_STATUS_61 0x3fef4 848 + #define ixSMU_PM_STATUS_62 0x3fef8 849 + #define ixSMU_PM_STATUS_63 0x3fefc 850 + #define ixSMU_PM_STATUS_64 0x3ff00 851 + #define ixSMU_PM_STATUS_65 0x3ff04 852 + #define ixSMU_PM_STATUS_66 0x3ff08 853 + #define ixSMU_PM_STATUS_67 0x3ff0c 854 + #define ixSMU_PM_STATUS_68 0x3ff10 855 + #define ixSMU_PM_STATUS_69 0x3ff14 856 + #define ixSMU_PM_STATUS_70 0x3ff18 857 + #define ixSMU_PM_STATUS_71 0x3ff1c 858 + #define ixSMU_PM_STATUS_72 0x3ff20 859 + #define ixSMU_PM_STATUS_73 0x3ff24 860 + #define ixSMU_PM_STATUS_74 0x3ff28 861 + #define ixSMU_PM_STATUS_75 0x3ff2c 862 + #define ixSMU_PM_STATUS_76 0x3ff30 863 + #define ixSMU_PM_STATUS_77 0x3ff34 864 + #define ixSMU_PM_STATUS_78 0x3ff38 865 + #define ixSMU_PM_STATUS_79 0x3ff3c 866 + #define ixSMU_PM_STATUS_80 0x3ff40 867 + #define ixSMU_PM_STATUS_81 0x3ff44 868 + #define ixSMU_PM_STATUS_82 0x3ff48 869 + #define ixSMU_PM_STATUS_83 0x3ff4c 870 + #define ixSMU_PM_STATUS_84 0x3ff50 871 + #define ixSMU_PM_STATUS_85 0x3ff54 872 + #define ixSMU_PM_STATUS_86 0x3ff58 873 + #define ixSMU_PM_STATUS_87 0x3ff5c 874 + #define ixSMU_PM_STATUS_88 0x3ff60 875 + #define ixSMU_PM_STATUS_89 0x3ff64 876 + #define ixSMU_PM_STATUS_90 0x3ff68 877 + #define ixSMU_PM_STATUS_91 0x3ff6c 878 + #define ixSMU_PM_STATUS_92 0x3ff70 879 + #define ixSMU_PM_STATUS_93 0x3ff74 880 + #define ixSMU_PM_STATUS_94 0x3ff78 881 + #define ixSMU_PM_STATUS_95 0x3ff7c 882 + #define ixSMU_PM_STATUS_96 0x3ff80 883 + #define ixSMU_PM_STATUS_97 0x3ff84 884 + #define ixSMU_PM_STATUS_98 0x3ff88 885 + #define ixSMU_PM_STATUS_99 0x3ff8c 886 + #define ixSMU_PM_STATUS_100 0x3ff90 887 + #define ixSMU_PM_STATUS_101 0x3ff94 888 + #define ixSMU_PM_STATUS_102 0x3ff98 889 + #define ixSMU_PM_STATUS_103 0x3ff9c 890 + #define ixSMU_PM_STATUS_104 0x3ffa0 891 + #define ixSMU_PM_STATUS_105 0x3ffa4 892 + #define ixSMU_PM_STATUS_106 0x3ffa8 893 + #define ixSMU_PM_STATUS_107 0x3ffac 894 + #define ixSMU_PM_STATUS_108 0x3ffb0 895 + #define ixSMU_PM_STATUS_109 0x3ffb4 896 + #define ixSMU_PM_STATUS_110 0x3ffb8 897 + #define ixSMU_PM_STATUS_111 0x3ffbc 898 + #define ixSMU_PM_STATUS_112 0x3ffc0 899 + #define ixSMU_PM_STATUS_113 0x3ffc4 900 + #define ixSMU_PM_STATUS_114 0x3ffc8 901 + #define ixSMU_PM_STATUS_115 0x3ffcc 902 + #define ixSMU_PM_STATUS_116 0x3ffd0 903 + #define ixSMU_PM_STATUS_117 0x3ffd4 904 + #define ixSMU_PM_STATUS_118 0x3ffd8 905 + #define ixSMU_PM_STATUS_119 0x3ffdc 906 + #define ixSMU_PM_STATUS_120 0x3ffe0 907 + #define ixSMU_PM_STATUS_121 0x3ffe4 908 + #define ixSMU_PM_STATUS_122 0x3ffe8 909 + #define ixSMU_PM_STATUS_123 0x3ffec 910 + #define ixSMU_PM_STATUS_124 0x3fff0 911 + #define ixSMU_PM_STATUS_125 0x3fff4 912 + #define ixSMU_PM_STATUS_126 0x3fff8 913 + #define ixSMU_PM_STATUS_127 0x3fffc 914 + #define ixCG_THERMAL_INT_ENA 0xc2100024 915 + #define ixCG_THERMAL_INT_CTRL 0xc2100028 916 + #define ixCG_THERMAL_INT_STATUS 0xc210002c 917 + #define ixCG_THERMAL_CTRL 0xc0300004 918 + #define ixCG_THERMAL_STATUS 0xc0300008 919 + #define ixCG_THERMAL_INT 0xc030000c 920 + #define ixCG_MULT_THERMAL_CTRL 0xc0300010 921 + #define ixCG_MULT_THERMAL_STATUS 0xc0300014 922 + #define ixTHM_TMON2_CTRL 0xc0300034 923 + #define ixTHM_TMON2_CTRL2 0xc0300038 924 + #define ixTHM_TMON2_CSR_WR 0xc0300054 925 + #define ixTHM_TMON2_CSR_RD 0xc0300058 926 + #define ixCG_FDO_CTRL0 0xc0300064 927 + #define ixCG_FDO_CTRL1 0xc0300068 928 + #define ixCG_FDO_CTRL2 0xc030006c 929 + #define ixCG_TACH_CTRL 0xc0300070 930 + #define ixCG_TACH_STATUS 0xc0300074 931 + #define ixCC_THM_STRAPS0 0xc0300080 932 + #define ixTHM_TMON0_RDIL0_DATA 0xc0300100 933 + #define ixTHM_TMON0_RDIL1_DATA 0xc0300104 934 + #define ixTHM_TMON0_RDIL2_DATA 0xc0300108 935 + #define ixTHM_TMON0_RDIL3_DATA 0xc030010c 936 + #define ixTHM_TMON0_RDIL4_DATA 0xc0300110 937 + #define ixTHM_TMON0_RDIL5_DATA 0xc0300114 938 + #define ixTHM_TMON0_RDIL6_DATA 0xc0300118 939 + #define ixTHM_TMON0_RDIL7_DATA 0xc030011c 940 + #define ixTHM_TMON0_RDIL8_DATA 0xc0300120 941 + #define ixTHM_TMON0_RDIL9_DATA 0xc0300124 942 + #define ixTHM_TMON0_RDIL10_DATA 0xc0300128 943 + #define ixTHM_TMON0_RDIL11_DATA 0xc030012c 944 + #define ixTHM_TMON0_RDIL12_DATA 0xc0300130 945 + #define ixTHM_TMON0_RDIL13_DATA 0xc0300134 946 + #define ixTHM_TMON0_RDIL14_DATA 0xc0300138 947 + #define ixTHM_TMON0_RDIL15_DATA 0xc030013c 948 + #define ixTHM_TMON0_RDIR0_DATA 0xc0300140 949 + #define ixTHM_TMON0_RDIR1_DATA 0xc0300144 950 + #define ixTHM_TMON0_RDIR2_DATA 0xc0300148 951 + #define ixTHM_TMON0_RDIR3_DATA 0xc030014c 952 + #define ixTHM_TMON0_RDIR4_DATA 0xc0300150 953 + #define ixTHM_TMON0_RDIR5_DATA 0xc0300154 954 + #define ixTHM_TMON0_RDIR6_DATA 0xc0300158 955 + #define ixTHM_TMON0_RDIR7_DATA 0xc030015c 956 + #define ixTHM_TMON0_RDIR8_DATA 0xc0300160 957 + #define ixTHM_TMON0_RDIR9_DATA 0xc0300164 958 + #define ixTHM_TMON0_RDIR10_DATA 0xc0300168 959 + #define ixTHM_TMON0_RDIR11_DATA 0xc030016c 960 + #define ixTHM_TMON0_RDIR12_DATA 0xc0300170 961 + #define ixTHM_TMON0_RDIR13_DATA 0xc0300174 962 + #define ixTHM_TMON0_RDIR14_DATA 0xc0300178 963 + #define ixTHM_TMON0_RDIR15_DATA 0xc030017c 964 + #define ixTHM_TMON1_RDIL0_DATA 0xc0300180 965 + #define ixTHM_TMON1_RDIL1_DATA 0xc0300184 966 + #define ixTHM_TMON1_RDIL2_DATA 0xc0300188 967 + #define ixTHM_TMON1_RDIL3_DATA 0xc030018c 968 + #define ixTHM_TMON1_RDIL4_DATA 0xc0300190 969 + #define ixTHM_TMON1_RDIL5_DATA 0xc0300194 970 + #define ixTHM_TMON1_RDIL6_DATA 0xc0300198 971 + #define ixTHM_TMON1_RDIL7_DATA 0xc030019c 972 + #define ixTHM_TMON1_RDIL8_DATA 0xc03001a0 973 + #define ixTHM_TMON1_RDIL9_DATA 0xc03001a4 974 + #define ixTHM_TMON1_RDIL10_DATA 0xc03001a8 975 + #define ixTHM_TMON1_RDIL11_DATA 0xc03001ac 976 + #define ixTHM_TMON1_RDIL12_DATA 0xc03001b0 977 + #define ixTHM_TMON1_RDIL13_DATA 0xc03001b4 978 + #define ixTHM_TMON1_RDIL14_DATA 0xc03001b8 979 + #define ixTHM_TMON1_RDIL15_DATA 0xc03001bc 980 + #define ixTHM_TMON1_RDIR0_DATA 0xc03001c0 981 + #define ixTHM_TMON1_RDIR1_DATA 0xc03001c4 982 + #define ixTHM_TMON1_RDIR2_DATA 0xc03001c8 983 + #define ixTHM_TMON1_RDIR3_DATA 0xc03001cc 984 + #define ixTHM_TMON1_RDIR4_DATA 0xc03001d0 985 + #define ixTHM_TMON1_RDIR5_DATA 0xc03001d4 986 + #define ixTHM_TMON1_RDIR6_DATA 0xc03001d8 987 + #define ixTHM_TMON1_RDIR7_DATA 0xc03001dc 988 + #define ixTHM_TMON1_RDIR8_DATA 0xc03001e0 989 + #define ixTHM_TMON1_RDIR9_DATA 0xc03001e4 990 + #define ixTHM_TMON1_RDIR10_DATA 0xc03001e8 991 + #define ixTHM_TMON1_RDIR11_DATA 0xc03001ec 992 + #define ixTHM_TMON1_RDIR12_DATA 0xc03001f0 993 + #define ixTHM_TMON1_RDIR13_DATA 0xc03001f4 994 + #define ixTHM_TMON1_RDIR14_DATA 0xc03001f8 995 + #define ixTHM_TMON1_RDIR15_DATA 0xc03001fc 996 + #define ixTHM_TMON2_RDIL0_DATA 0xc0300200 997 + #define ixTHM_TMON2_RDIL1_DATA 0xc0300204 998 + #define ixTHM_TMON2_RDIL2_DATA 0xc0300208 999 + #define ixTHM_TMON2_RDIL3_DATA 0xc030020c 1000 + #define ixTHM_TMON2_RDIL4_DATA 0xc0300210 1001 + #define ixTHM_TMON2_RDIL5_DATA 0xc0300214 1002 + #define ixTHM_TMON2_RDIL6_DATA 0xc0300218 1003 + #define ixTHM_TMON2_RDIL7_DATA 0xc030021c 1004 + #define ixTHM_TMON2_RDIL8_DATA 0xc0300220 1005 + #define ixTHM_TMON2_RDIL9_DATA 0xc0300224 1006 + #define ixTHM_TMON2_RDIL10_DATA 0xc0300228 1007 + #define ixTHM_TMON2_RDIL11_DATA 0xc030022c 1008 + #define ixTHM_TMON2_RDIL12_DATA 0xc0300230 1009 + #define ixTHM_TMON2_RDIL13_DATA 0xc0300234 1010 + #define ixTHM_TMON2_RDIL14_DATA 0xc0300238 1011 + #define ixTHM_TMON2_RDIL15_DATA 0xc030023c 1012 + #define ixTHM_TMON2_RDIR0_DATA 0xc0300240 1013 + #define ixTHM_TMON2_RDIR1_DATA 0xc0300244 1014 + #define ixTHM_TMON2_RDIR2_DATA 0xc0300248 1015 + #define ixTHM_TMON2_RDIR3_DATA 0xc030024c 1016 + #define ixTHM_TMON2_RDIR4_DATA 0xc0300250 1017 + #define ixTHM_TMON2_RDIR5_DATA 0xc0300254 1018 + #define ixTHM_TMON2_RDIR6_DATA 0xc0300258 1019 + #define ixTHM_TMON2_RDIR7_DATA 0xc030025c 1020 + #define ixTHM_TMON2_RDIR8_DATA 0xc0300260 1021 + #define ixTHM_TMON2_RDIR9_DATA 0xc0300264 1022 + #define ixTHM_TMON2_RDIR10_DATA 0xc0300268 1023 + #define ixTHM_TMON2_RDIR11_DATA 0xc030026c 1024 + #define ixTHM_TMON2_RDIR12_DATA 0xc0300270 1025 + #define ixTHM_TMON2_RDIR13_DATA 0xc0300274 1026 + #define ixTHM_TMON2_RDIR14_DATA 0xc0300278 1027 + #define ixTHM_TMON2_RDIR15_DATA 0xc030027c 1028 + #define ixTHM_TMON0_INT_DATA 0xc0300300 1029 + #define ixTHM_TMON1_INT_DATA 0xc0300304 1030 + #define ixTHM_TMON2_INT_DATA 0xc0300308 1031 + #define ixTHM_TMON0_DEBUG 0xc0300310 1032 + #define ixTHM_TMON1_DEBUG 0xc0300314 1033 + #define ixTHM_TMON2_DEBUG 0xc0300318 1034 + #define ixTHM_TMON0_STATUS 0xc0300320 1035 + #define ixTHM_TMON1_STATUS 0xc0300324 1036 + #define ixTHM_TMON2_STATUS 0xc0300328 1037 + #define ixGENERAL_PWRMGT 0xc0200000 1038 + #define ixCNB_PWRMGT_CNTL 0xc0200004 1039 + #define ixSCLK_PWRMGT_CNTL 0xc0200008 1040 + #define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xc0200014 1041 + #define ixPWR_PCC_CONTROL 0xc0200018 1042 + #define ixPWR_PCC_GPIO_SELECT 0xc020001c 1043 + #define ixCG_FREQ_TRAN_VOTING_0 0xc02001a8 1044 + #define ixCG_FREQ_TRAN_VOTING_1 0xc02001ac 1045 + #define ixCG_FREQ_TRAN_VOTING_2 0xc02001b0 1046 + #define ixCG_FREQ_TRAN_VOTING_3 0xc02001b4 1047 + #define ixCG_FREQ_TRAN_VOTING_4 0xc02001b8 1048 + #define ixCG_FREQ_TRAN_VOTING_5 0xc02001bc 1049 + #define ixCG_FREQ_TRAN_VOTING_6 0xc02001c0 1050 + #define ixCG_FREQ_TRAN_VOTING_7 0xc02001c4 1051 + #define ixPLL_TEST_CNTL 0xc020003c 1052 + #define ixCG_STATIC_SCREEN_PARAMETER 0xc0200044 1053 + #define ixCG_DISPLAY_GAP_CNTL 0xc0200060 1054 + #define ixCG_DISPLAY_GAP_CNTL2 0xc0200230 1055 + #define ixCG_ACPI_CNTL 0xc0200064 1056 + #define ixSCLK_DEEP_SLEEP_CNTL 0xc0200080 1057 + #define ixSCLK_DEEP_SLEEP_CNTL2 0xc0200084 1058 + #define ixSCLK_DEEP_SLEEP_CNTL3 0xc020009c 1059 + #define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xc0200088 1060 + #define ixLCLK_DEEP_SLEEP_CNTL 0xc020008c 1061 + #define ixLCLK_DEEP_SLEEP_CNTL2 0xc0200310 1062 + #define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xc02000f0 1063 + #define ixCG_ULV_PARAMETER 0xc020015c 1064 + #define ixSCLK_MIN_DIV 0xc02003ac 1065 + #define ixPWR_AVFS_SEL 0xc0200384 1066 + #define ixPWR_AVFS_CNTL 0xc0200388 1067 + #define ixPWR_AVFS0_CNTL_STATUS 0xc0200400 1068 + #define ixPWR_AVFS1_CNTL_STATUS 0xc0200404 1069 + #define ixPWR_AVFS2_CNTL_STATUS 0xc0200408 1070 + #define ixPWR_AVFS3_CNTL_STATUS 0xc020040c 1071 + #define ixPWR_AVFS4_CNTL_STATUS 0xc0200410 1072 + #define ixPWR_AVFS5_CNTL_STATUS 0xc0200414 1073 + #define ixPWR_AVFS6_CNTL_STATUS 0xc0200418 1074 + #define ixPWR_AVFS7_CNTL_STATUS 0xc020041c 1075 + #define ixPWR_AVFS8_CNTL_STATUS 0xc0200420 1076 + #define ixPWR_AVFS9_CNTL_STATUS 0xc0200424 1077 + #define ixPWR_AVFS10_CNTL_STATUS 0xc0200428 1078 + #define ixPWR_AVFS11_CNTL_STATUS 0xc020042c 1079 + #define ixPWR_AVFS12_CNTL_STATUS 0xc0200430 1080 + #define ixPWR_AVFS13_CNTL_STATUS 0xc0200434 1081 + #define ixPWR_AVFS14_CNTL_STATUS 0xc0200438 1082 + #define ixPWR_AVFS15_CNTL_STATUS 0xc020043c 1083 + #define ixPWR_AVFS16_CNTL_STATUS 0xc0200440 1084 + #define ixPWR_AVFS17_CNTL_STATUS 0xc0200444 1085 + #define ixPWR_AVFS18_CNTL_STATUS 0xc0200448 1086 + #define ixPWR_AVFS19_CNTL_STATUS 0xc020044c 1087 + #define ixPWR_AVFS20_CNTL_STATUS 0xc0200450 1088 + #define ixPWR_AVFS21_CNTL_STATUS 0xc0200454 1089 + #define ixPWR_AVFS22_CNTL_STATUS 0xc0200458 1090 + #define ixPWR_AVFS23_CNTL_STATUS 0xc020045c 1091 + #define ixPWR_AVFS24_CNTL_STATUS 0xc0200460 1092 + #define ixPWR_AVFS25_CNTL_STATUS 0xc0200464 1093 + #define ixPWR_AVFS26_CNTL_STATUS 0xc0200468 1094 + #define ixPWR_AVFS27_CNTL_STATUS 0xc020046c 1095 + #define ixPWR_CKS_ENABLE 0xc020034c 1096 + #define ixPWR_CKS_CNTL 0xc0200350 1097 + #define ixPWR_DISP_TIMER_CONTROL 0xc02003c0 1098 + #define ixPWR_DISP_TIMER_DEBUG 0xc02003c4 1099 + #define ixPWR_DISP_TIMER2_CONTROL 0xc02003c8 1100 + #define ixPWR_DISP_TIMER2_DEBUG 0xc02003cc 1101 + #define ixPWR_DISP_TIMER_CONTROL2 0xc0200378 1102 + #define ixVDDGFX_IDLE_PARAMETER 0xc020036c 1103 + #define ixVDDGFX_IDLE_CONTROL 0xc0200370 1104 + #define ixVDDGFX_IDLE_EXIT 0xc0200374 1105 + #define ixLCAC_MC0_CNTL 0xc0400130 1106 + #define ixLCAC_MC0_OVR_SEL 0xc0400134 1107 + #define ixLCAC_MC0_OVR_VAL 0xc0400138 1108 + #define ixLCAC_MC1_CNTL 0xc040013c 1109 + #define ixLCAC_MC1_OVR_SEL 0xc0400140 1110 + #define ixLCAC_MC1_OVR_VAL 0xc0400144 1111 + #define ixLCAC_MC2_CNTL 0xc0400148 1112 + #define ixLCAC_MC2_OVR_SEL 0xc040014c 1113 + #define ixLCAC_MC2_OVR_VAL 0xc0400150 1114 + #define ixLCAC_MC3_CNTL 0xc0400154 1115 + #define ixLCAC_MC3_OVR_SEL 0xc0400158 1116 + #define ixLCAC_MC3_OVR_VAL 0xc040015c 1117 + #define ixLCAC_MC4_CNTL 0xc0400d60 1118 + #define ixLCAC_MC4_OVR_SEL 0xc0400d64 1119 + #define ixLCAC_MC4_OVR_VAL 0xc0400d68 1120 + #define ixLCAC_MC5_CNTL 0xc0400d6c 1121 + #define ixLCAC_MC5_OVR_SEL 0xc0400d70 1122 + #define ixLCAC_MC5_OVR_VAL 0xc0400d74 1123 + #define ixLCAC_MC6_CNTL 0xc0400d78 1124 + #define ixLCAC_MC6_OVR_SEL 0xc0400d7c 1125 + #define ixLCAC_MC6_OVR_VAL 0xc0400d80 1126 + #define ixLCAC_MC7_CNTL 0xc0400d84 1127 + #define ixLCAC_MC7_OVR_SEL 0xc0400d88 1128 + #define ixLCAC_MC7_OVR_VAL 0xc0400d8c 1129 + #define ixLCAC_CPL_CNTL 0xc0400160 1130 + #define ixLCAC_CPL_OVR_SEL 0xc0400164 1131 + #define ixLCAC_CPL_OVR_VAL 0xc0400168 1132 + #define mmROM_SMC_IND_INDEX 0x80 1133 + #define mmROM0_ROM_SMC_IND_INDEX 0x80 1134 + #define mmROM1_ROM_SMC_IND_INDEX 0x82 1135 + #define mmROM2_ROM_SMC_IND_INDEX 0x84 1136 + #define mmROM3_ROM_SMC_IND_INDEX 0x86 1137 + #define mmROM_SMC_IND_DATA 0x81 1138 + #define mmROM0_ROM_SMC_IND_DATA 0x81 1139 + #define mmROM1_ROM_SMC_IND_DATA 0x83 1140 + #define mmROM2_ROM_SMC_IND_DATA 0x85 1141 + #define mmROM3_ROM_SMC_IND_DATA 0x87 1142 + #define ixROM_CNTL 0xc0600000 1143 + #define ixPAGE_MIRROR_CNTL 0xc0600004 1144 + #define ixROM_STATUS 0xc0600008 1145 + #define ixCGTT_ROM_CLK_CTRL0 0xc060000c 1146 + #define ixROM_INDEX 0xc0600010 1147 + #define ixROM_DATA 0xc0600014 1148 + #define ixROM_START 0xc0600018 1149 + #define ixROM_SW_CNTL 0xc060001c 1150 + #define ixROM_SW_STATUS 0xc0600020 1151 + #define ixROM_SW_COMMAND 0xc0600024 1152 + #define ixROM_SW_DATA_1 0xc0600028 1153 + #define ixROM_SW_DATA_2 0xc060002c 1154 + #define ixROM_SW_DATA_3 0xc0600030 1155 + #define ixROM_SW_DATA_4 0xc0600034 1156 + #define ixROM_SW_DATA_5 0xc0600038 1157 + #define ixROM_SW_DATA_6 0xc060003c 1158 + #define ixROM_SW_DATA_7 0xc0600040 1159 + #define ixROM_SW_DATA_8 0xc0600044 1160 + #define ixROM_SW_DATA_9 0xc0600048 1161 + #define ixROM_SW_DATA_10 0xc060004c 1162 + #define ixROM_SW_DATA_11 0xc0600050 1163 + #define ixROM_SW_DATA_12 0xc0600054 1164 + #define ixROM_SW_DATA_13 0xc0600058 1165 + #define ixROM_SW_DATA_14 0xc060005c 1166 + #define ixROM_SW_DATA_15 0xc0600060 1167 + #define ixROM_SW_DATA_16 0xc0600064 1168 + #define ixROM_SW_DATA_17 0xc0600068 1169 + #define ixROM_SW_DATA_18 0xc060006c 1170 + #define ixROM_SW_DATA_19 0xc0600070 1171 + #define ixROM_SW_DATA_20 0xc0600074 1172 + #define ixROM_SW_DATA_21 0xc0600078 1173 + #define ixROM_SW_DATA_22 0xc060007c 1174 + #define ixROM_SW_DATA_23 0xc0600080 1175 + #define ixROM_SW_DATA_24 0xc0600084 1176 + #define ixROM_SW_DATA_25 0xc0600088 1177 + #define ixROM_SW_DATA_26 0xc060008c 1178 + #define ixROM_SW_DATA_27 0xc0600090 1179 + #define ixROM_SW_DATA_28 0xc0600094 1180 + #define ixROM_SW_DATA_29 0xc0600098 1181 + #define ixROM_SW_DATA_30 0xc060009c 1182 + #define ixROM_SW_DATA_31 0xc06000a0 1183 + #define ixROM_SW_DATA_32 0xc06000a4 1184 + #define ixROM_SW_DATA_33 0xc06000a8 1185 + #define ixROM_SW_DATA_34 0xc06000ac 1186 + #define ixROM_SW_DATA_35 0xc06000b0 1187 + #define ixROM_SW_DATA_36 0xc06000b4 1188 + #define ixROM_SW_DATA_37 0xc06000b8 1189 + #define ixROM_SW_DATA_38 0xc06000bc 1190 + #define ixROM_SW_DATA_39 0xc06000c0 1191 + #define ixROM_SW_DATA_40 0xc06000c4 1192 + #define ixROM_SW_DATA_41 0xc06000c8 1193 + #define ixROM_SW_DATA_42 0xc06000cc 1194 + #define ixROM_SW_DATA_43 0xc06000d0 1195 + #define ixROM_SW_DATA_44 0xc06000d4 1196 + #define ixROM_SW_DATA_45 0xc06000d8 1197 + #define ixROM_SW_DATA_46 0xc06000dc 1198 + #define ixROM_SW_DATA_47 0xc06000e0 1199 + #define ixROM_SW_DATA_48 0xc06000e4 1200 + #define ixROM_SW_DATA_49 0xc06000e8 1201 + #define ixROM_SW_DATA_50 0xc06000ec 1202 + #define ixROM_SW_DATA_51 0xc06000f0 1203 + #define ixROM_SW_DATA_52 0xc06000f4 1204 + #define ixROM_SW_DATA_53 0xc06000f8 1205 + #define ixROM_SW_DATA_54 0xc06000fc 1206 + #define ixROM_SW_DATA_55 0xc0600100 1207 + #define ixROM_SW_DATA_56 0xc0600104 1208 + #define ixROM_SW_DATA_57 0xc0600108 1209 + #define ixROM_SW_DATA_58 0xc060010c 1210 + #define ixROM_SW_DATA_59 0xc0600110 1211 + #define ixROM_SW_DATA_60 0xc0600114 1212 + #define ixROM_SW_DATA_61 0xc0600118 1213 + #define ixROM_SW_DATA_62 0xc060011c 1214 + #define ixROM_SW_DATA_63 0xc0600120 1215 + #define ixROM_SW_DATA_64 0xc0600124 1216 + #define mmGC_CAC_CGTT_CLK_CTRL 0x3292 1217 + #define mmSE_CAC_CGTT_CLK_CTRL 0x3293 1218 + #define mmGC_CAC_LKG_AGGR_LOWER 0x3296 1219 + #define mmGC_CAC_LKG_AGGR_UPPER 0x3297 1220 + #define ixGC_CAC_WEIGHT_CU_0 0x32 1221 + #define ixGC_CAC_WEIGHT_CU_1 0x33 1222 + #define ixGC_CAC_WEIGHT_CU_2 0x34 1223 + #define ixGC_CAC_WEIGHT_CU_3 0x35 1224 + #define ixGC_CAC_WEIGHT_CU_4 0x36 1225 + #define ixGC_CAC_WEIGHT_CU_5 0x37 1226 + #define ixGC_CAC_WEIGHT_CU_6 0x38 1227 + #define ixGC_CAC_WEIGHT_CU_7 0x39 1228 + #define ixGC_CAC_ACC_CU0 0xba 1229 + #define ixGC_CAC_ACC_CU1 0xbb 1230 + #define ixGC_CAC_ACC_CU2 0xbc 1231 + #define ixGC_CAC_ACC_CU3 0xbd 1232 + #define ixGC_CAC_ACC_CU4 0xbe 1233 + #define ixGC_CAC_ACC_CU5 0xbf 1234 + #define ixGC_CAC_ACC_CU6 0xc0 1235 + #define ixGC_CAC_ACC_CU7 0xc1 1236 + #define ixGC_CAC_ACC_CU8 0xc2 1237 + #define ixGC_CAC_ACC_CU9 0xc3 1238 + #define ixGC_CAC_ACC_CU10 0xc4 1239 + #define ixGC_CAC_ACC_CU11 0xc5 1240 + #define ixGC_CAC_ACC_CU12 0xc6 1241 + #define ixGC_CAC_ACC_CU13 0xc7 1242 + #define ixGC_CAC_ACC_CU14 0xc8 1243 + #define ixGC_CAC_ACC_CU15 0xc9 1244 + #define ixGC_CAC_OVRD_CU 0xe7 1245 + 1246 + #endif /* SMU_7_1_3_D_H */
+1282
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_enum.h
··· 1 + /* 2 + * SMU_7_1_3 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef SMU_7_1_3_ENUM_H 25 + #define SMU_7_1_3_ENUM_H 26 + 27 + #define CG_SRBM_START_ADDR 0x600 28 + #define CG_SRBM_END_ADDR 0x8ff 29 + #define RCU_CCF_DWORDS0 0xa0 30 + #define RCU_CCF_BITS0 0x1400 31 + #define RCU_SAM_BYTES 0x2c 32 + #define RCU_SAM_RTL_BYTES 0x2c 33 + #define RCU_SMU_BYTES 0x14 34 + #define RCU_SMU_RTL_BYTES 0x14 35 + #define SFP_CHAIN_ADDR 0x1 36 + #define SFP_SADR 0x0 37 + #define SFP_EADR 0x37f 38 + #define SAMU_KEY_CHAIN_ADR 0x0 39 + #define SAMU_KEY_SADR 0x280 40 + #define SAMU_KEY_EADR 0x2ab 41 + #define SMU_KEY_CHAIN_ADR 0x0 42 + #define SMU_KEY_SADR 0x2ac 43 + #define SMU_KEY_EADR 0x2bf 44 + #define SMC_MSG_TEST 0x1 45 + #define SMC_MSG_PHY_LN_OFF 0x2 46 + #define SMC_MSG_PHY_LN_ON 0x3 47 + #define SMC_MSG_DDI_PHY_OFF 0x4 48 + #define SMC_MSG_DDI_PHY_ON 0x5 49 + #define SMC_MSG_CASCADE_PLL_OFF 0x6 50 + #define SMC_MSG_CASCADE_PLL_ON 0x7 51 + #define SMC_MSG_PWR_OFF_x16 0x8 52 + #define SMC_MSG_CONFIG_LCLK_DPM 0x9 53 + #define SMC_MSG_FLUSH_DATA_CACHE 0xa 54 + #define SMC_MSG_FLUSH_INSTRUCTION_CACHE 0xb 55 + #define SMC_MSG_CONFIG_VPC_ACCUMULATOR 0xc 56 + #define SMC_MSG_CONFIG_BAPM 0xd 57 + #define SMC_MSG_CONFIG_TDC_LIMIT 0xe 58 + #define SMC_MSG_CONFIG_LPMx 0xf 59 + #define SMC_MSG_CONFIG_HTC_LIMIT 0x10 60 + #define SMC_MSG_CONFIG_THERMAL_CNTL 0x11 61 + #define SMC_MSG_CONFIG_VOLTAGE_CNTL 0x12 62 + #define SMC_MSG_CONFIG_TDP_CNTL 0x13 63 + #define SMC_MSG_EN_PM_CNTL 0x14 64 + #define SMC_MSG_DIS_PM_CNTL 0x15 65 + #define SMC_MSG_CONFIG_NBDPM 0x16 66 + #define SMC_MSG_CONFIG_LOADLINE 0x17 67 + #define SMC_MSG_ADJUST_LOADLINE 0x18 68 + #define SMC_MSG_RESET 0x20 69 + #define SMC_MSG_VOLTAGE 0x25 70 + #define SMC_VERSION_MAJOR 0x7 71 + #define SMC_VERSION_MINOR 0x0 72 + #define SMC_HEADER_SIZE 0x40 73 + #define ROM_SIGNATURE 0xaa55 74 + typedef enum SurfaceEndian { 75 + ENDIAN_NONE = 0x0, 76 + ENDIAN_8IN16 = 0x1, 77 + ENDIAN_8IN32 = 0x2, 78 + ENDIAN_8IN64 = 0x3, 79 + } SurfaceEndian; 80 + typedef enum ArrayMode { 81 + ARRAY_LINEAR_GENERAL = 0x0, 82 + ARRAY_LINEAR_ALIGNED = 0x1, 83 + ARRAY_1D_TILED_THIN1 = 0x2, 84 + ARRAY_1D_TILED_THICK = 0x3, 85 + ARRAY_2D_TILED_THIN1 = 0x4, 86 + ARRAY_PRT_TILED_THIN1 = 0x5, 87 + ARRAY_PRT_2D_TILED_THIN1 = 0x6, 88 + ARRAY_2D_TILED_THICK = 0x7, 89 + ARRAY_2D_TILED_XTHICK = 0x8, 90 + ARRAY_PRT_TILED_THICK = 0x9, 91 + ARRAY_PRT_2D_TILED_THICK = 0xa, 92 + ARRAY_PRT_3D_TILED_THIN1 = 0xb, 93 + ARRAY_3D_TILED_THIN1 = 0xc, 94 + ARRAY_3D_TILED_THICK = 0xd, 95 + ARRAY_3D_TILED_XTHICK = 0xe, 96 + ARRAY_PRT_3D_TILED_THICK = 0xf, 97 + } ArrayMode; 98 + typedef enum PipeTiling { 99 + CONFIG_1_PIPE = 0x0, 100 + CONFIG_2_PIPE = 0x1, 101 + CONFIG_4_PIPE = 0x2, 102 + CONFIG_8_PIPE = 0x3, 103 + } PipeTiling; 104 + typedef enum BankTiling { 105 + CONFIG_4_BANK = 0x0, 106 + CONFIG_8_BANK = 0x1, 107 + } BankTiling; 108 + typedef enum GroupInterleave { 109 + CONFIG_256B_GROUP = 0x0, 110 + CONFIG_512B_GROUP = 0x1, 111 + } GroupInterleave; 112 + typedef enum RowTiling { 113 + CONFIG_1KB_ROW = 0x0, 114 + CONFIG_2KB_ROW = 0x1, 115 + CONFIG_4KB_ROW = 0x2, 116 + CONFIG_8KB_ROW = 0x3, 117 + CONFIG_1KB_ROW_OPT = 0x4, 118 + CONFIG_2KB_ROW_OPT = 0x5, 119 + CONFIG_4KB_ROW_OPT = 0x6, 120 + CONFIG_8KB_ROW_OPT = 0x7, 121 + } RowTiling; 122 + typedef enum BankSwapBytes { 123 + CONFIG_128B_SWAPS = 0x0, 124 + CONFIG_256B_SWAPS = 0x1, 125 + CONFIG_512B_SWAPS = 0x2, 126 + CONFIG_1KB_SWAPS = 0x3, 127 + } BankSwapBytes; 128 + typedef enum SampleSplitBytes { 129 + CONFIG_1KB_SPLIT = 0x0, 130 + CONFIG_2KB_SPLIT = 0x1, 131 + CONFIG_4KB_SPLIT = 0x2, 132 + CONFIG_8KB_SPLIT = 0x3, 133 + } SampleSplitBytes; 134 + typedef enum NumPipes { 135 + ADDR_CONFIG_1_PIPE = 0x0, 136 + ADDR_CONFIG_2_PIPE = 0x1, 137 + ADDR_CONFIG_4_PIPE = 0x2, 138 + ADDR_CONFIG_8_PIPE = 0x3, 139 + } NumPipes; 140 + typedef enum PipeInterleaveSize { 141 + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 142 + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 143 + } PipeInterleaveSize; 144 + typedef enum BankInterleaveSize { 145 + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 146 + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 147 + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 148 + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 149 + } BankInterleaveSize; 150 + typedef enum NumShaderEngines { 151 + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 152 + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 153 + } NumShaderEngines; 154 + typedef enum ShaderEngineTileSize { 155 + ADDR_CONFIG_SE_TILE_16 = 0x0, 156 + ADDR_CONFIG_SE_TILE_32 = 0x1, 157 + } ShaderEngineTileSize; 158 + typedef enum NumGPUs { 159 + ADDR_CONFIG_1_GPU = 0x0, 160 + ADDR_CONFIG_2_GPU = 0x1, 161 + ADDR_CONFIG_4_GPU = 0x2, 162 + } NumGPUs; 163 + typedef enum MultiGPUTileSize { 164 + ADDR_CONFIG_GPU_TILE_16 = 0x0, 165 + ADDR_CONFIG_GPU_TILE_32 = 0x1, 166 + ADDR_CONFIG_GPU_TILE_64 = 0x2, 167 + ADDR_CONFIG_GPU_TILE_128 = 0x3, 168 + } MultiGPUTileSize; 169 + typedef enum RowSize { 170 + ADDR_CONFIG_1KB_ROW = 0x0, 171 + ADDR_CONFIG_2KB_ROW = 0x1, 172 + ADDR_CONFIG_4KB_ROW = 0x2, 173 + } RowSize; 174 + typedef enum NumLowerPipes { 175 + ADDR_CONFIG_1_LOWER_PIPES = 0x0, 176 + ADDR_CONFIG_2_LOWER_PIPES = 0x1, 177 + } NumLowerPipes; 178 + typedef enum DebugBlockId { 179 + DBG_CLIENT_BLKID_RESERVED = 0x0, 180 + DBG_CLIENT_BLKID_dbg = 0x1, 181 + DBG_CLIENT_BLKID_scf2 = 0x2, 182 + DBG_CLIENT_BLKID_mcd5_0 = 0x3, 183 + DBG_CLIENT_BLKID_mcd5_1 = 0x4, 184 + DBG_CLIENT_BLKID_mcd6_0 = 0x5, 185 + DBG_CLIENT_BLKID_mcd6_1 = 0x6, 186 + DBG_CLIENT_BLKID_mcd7_0 = 0x7, 187 + DBG_CLIENT_BLKID_mcd7_1 = 0x8, 188 + DBG_CLIENT_BLKID_vmc = 0x9, 189 + DBG_CLIENT_BLKID_sx30 = 0xa, 190 + DBG_CLIENT_BLKID_mcd2_0 = 0xb, 191 + DBG_CLIENT_BLKID_mcd2_1 = 0xc, 192 + DBG_CLIENT_BLKID_bci1 = 0xd, 193 + DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0xe, 194 + DBG_CLIENT_BLKID_mcc0 = 0xf, 195 + DBG_CLIENT_BLKID_uvdf_0 = 0x10, 196 + DBG_CLIENT_BLKID_uvdf_1 = 0x11, 197 + DBG_CLIENT_BLKID_uvdf_2 = 0x12, 198 + DBG_CLIENT_BLKID_bci0 = 0x13, 199 + DBG_CLIENT_BLKID_vcec0_0 = 0x14, 200 + DBG_CLIENT_BLKID_cb100 = 0x15, 201 + DBG_CLIENT_BLKID_cb001 = 0x16, 202 + DBG_CLIENT_BLKID_cb002 = 0x17, 203 + DBG_CLIENT_BLKID_cb003 = 0x18, 204 + DBG_CLIENT_BLKID_mcd4_0 = 0x19, 205 + DBG_CLIENT_BLKID_mcd4_1 = 0x1a, 206 + DBG_CLIENT_BLKID_tmonw00 = 0x1b, 207 + DBG_CLIENT_BLKID_cb101 = 0x1c, 208 + DBG_CLIENT_BLKID_cb102 = 0x1d, 209 + DBG_CLIENT_BLKID_cb103 = 0x1e, 210 + DBG_CLIENT_BLKID_sx10 = 0x1f, 211 + DBG_CLIENT_BLKID_cb301 = 0x20, 212 + DBG_CLIENT_BLKID_cb302 = 0x21, 213 + DBG_CLIENT_BLKID_cb303 = 0x22, 214 + DBG_CLIENT_BLKID_tmonw01 = 0x23, 215 + DBG_CLIENT_BLKID_tmonw02 = 0x24, 216 + DBG_CLIENT_BLKID_vcea0_0 = 0x25, 217 + DBG_CLIENT_BLKID_vcea0_1 = 0x26, 218 + DBG_CLIENT_BLKID_vcea0_2 = 0x27, 219 + DBG_CLIENT_BLKID_vcea0_3 = 0x28, 220 + DBG_CLIENT_BLKID_scf1 = 0x29, 221 + DBG_CLIENT_BLKID_sx20 = 0x2a, 222 + DBG_CLIENT_BLKID_spim1 = 0x2b, 223 + DBG_CLIENT_BLKID_scb1 = 0x2c, 224 + DBG_CLIENT_BLKID_pa10 = 0x2d, 225 + DBG_CLIENT_BLKID_pa00 = 0x2e, 226 + DBG_CLIENT_BLKID_gmcon = 0x2f, 227 + DBG_CLIENT_BLKID_mcb = 0x30, 228 + DBG_CLIENT_BLKID_vgt0 = 0x31, 229 + DBG_CLIENT_BLKID_pc0 = 0x32, 230 + DBG_CLIENT_BLKID_bci2 = 0x33, 231 + DBG_CLIENT_BLKID_uvdb_0 = 0x34, 232 + DBG_CLIENT_BLKID_spim3 = 0x35, 233 + DBG_CLIENT_BLKID_scb3 = 0x36, 234 + DBG_CLIENT_BLKID_cpc_0 = 0x37, 235 + DBG_CLIENT_BLKID_cpc_1 = 0x38, 236 + DBG_CLIENT_BLKID_uvdm_0 = 0x39, 237 + DBG_CLIENT_BLKID_uvdm_1 = 0x3a, 238 + DBG_CLIENT_BLKID_uvdm_2 = 0x3b, 239 + DBG_CLIENT_BLKID_uvdm_3 = 0x3c, 240 + DBG_CLIENT_BLKID_cb000 = 0x3d, 241 + DBG_CLIENT_BLKID_spim0 = 0x3e, 242 + DBG_CLIENT_BLKID_scb0 = 0x3f, 243 + DBG_CLIENT_BLKID_mcc2 = 0x40, 244 + DBG_CLIENT_BLKID_ds0 = 0x41, 245 + DBG_CLIENT_BLKID_srbm = 0x42, 246 + DBG_CLIENT_BLKID_ih = 0x43, 247 + DBG_CLIENT_BLKID_sem = 0x44, 248 + DBG_CLIENT_BLKID_sdma_0 = 0x45, 249 + DBG_CLIENT_BLKID_sdma_1 = 0x46, 250 + DBG_CLIENT_BLKID_hdp = 0x47, 251 + DBG_CLIENT_BLKID_acp_0 = 0x48, 252 + DBG_CLIENT_BLKID_acp_1 = 0x49, 253 + DBG_CLIENT_BLKID_cb200 = 0x4a, 254 + DBG_CLIENT_BLKID_scf3 = 0x4b, 255 + DBG_CLIENT_BLKID_bci3 = 0x4c, 256 + DBG_CLIENT_BLKID_mcd0_0 = 0x4d, 257 + DBG_CLIENT_BLKID_mcd0_1 = 0x4e, 258 + DBG_CLIENT_BLKID_pa11 = 0x4f, 259 + DBG_CLIENT_BLKID_pa01 = 0x50, 260 + DBG_CLIENT_BLKID_cb201 = 0x51, 261 + DBG_CLIENT_BLKID_cb202 = 0x52, 262 + DBG_CLIENT_BLKID_cb203 = 0x53, 263 + DBG_CLIENT_BLKID_spim2 = 0x54, 264 + DBG_CLIENT_BLKID_scb2 = 0x55, 265 + DBG_CLIENT_BLKID_vgt2 = 0x56, 266 + DBG_CLIENT_BLKID_pc2 = 0x57, 267 + DBG_CLIENT_BLKID_smu_0 = 0x58, 268 + DBG_CLIENT_BLKID_smu_1 = 0x59, 269 + DBG_CLIENT_BLKID_smu_2 = 0x5a, 270 + DBG_CLIENT_BLKID_cb1 = 0x5b, 271 + DBG_CLIENT_BLKID_ia0 = 0x5c, 272 + DBG_CLIENT_BLKID_wd = 0x5d, 273 + DBG_CLIENT_BLKID_ia1 = 0x5e, 274 + DBG_CLIENT_BLKID_scf0 = 0x5f, 275 + DBG_CLIENT_BLKID_vgt1 = 0x60, 276 + DBG_CLIENT_BLKID_pc1 = 0x61, 277 + DBG_CLIENT_BLKID_cb0 = 0x62, 278 + DBG_CLIENT_BLKID_gdc_one_0 = 0x63, 279 + DBG_CLIENT_BLKID_gdc_one_1 = 0x64, 280 + DBG_CLIENT_BLKID_gdc_one_2 = 0x65, 281 + DBG_CLIENT_BLKID_gdc_one_3 = 0x66, 282 + DBG_CLIENT_BLKID_gdc_one_4 = 0x67, 283 + DBG_CLIENT_BLKID_gdc_one_5 = 0x68, 284 + DBG_CLIENT_BLKID_gdc_one_6 = 0x69, 285 + DBG_CLIENT_BLKID_gdc_one_7 = 0x6a, 286 + DBG_CLIENT_BLKID_gdc_one_8 = 0x6b, 287 + DBG_CLIENT_BLKID_gdc_one_9 = 0x6c, 288 + DBG_CLIENT_BLKID_gdc_one_10 = 0x6d, 289 + DBG_CLIENT_BLKID_gdc_one_11 = 0x6e, 290 + DBG_CLIENT_BLKID_gdc_one_12 = 0x6f, 291 + DBG_CLIENT_BLKID_gdc_one_13 = 0x70, 292 + DBG_CLIENT_BLKID_gdc_one_14 = 0x71, 293 + DBG_CLIENT_BLKID_gdc_one_15 = 0x72, 294 + DBG_CLIENT_BLKID_gdc_one_16 = 0x73, 295 + DBG_CLIENT_BLKID_gdc_one_17 = 0x74, 296 + DBG_CLIENT_BLKID_gdc_one_18 = 0x75, 297 + DBG_CLIENT_BLKID_gdc_one_19 = 0x76, 298 + DBG_CLIENT_BLKID_gdc_one_20 = 0x77, 299 + DBG_CLIENT_BLKID_gdc_one_21 = 0x78, 300 + DBG_CLIENT_BLKID_gdc_one_22 = 0x79, 301 + DBG_CLIENT_BLKID_gdc_one_23 = 0x7a, 302 + DBG_CLIENT_BLKID_gdc_one_24 = 0x7b, 303 + DBG_CLIENT_BLKID_gdc_one_25 = 0x7c, 304 + DBG_CLIENT_BLKID_gdc_one_26 = 0x7d, 305 + DBG_CLIENT_BLKID_gdc_one_27 = 0x7e, 306 + DBG_CLIENT_BLKID_gdc_one_28 = 0x7f, 307 + DBG_CLIENT_BLKID_gdc_one_29 = 0x80, 308 + DBG_CLIENT_BLKID_gdc_one_30 = 0x81, 309 + DBG_CLIENT_BLKID_gdc_one_31 = 0x82, 310 + DBG_CLIENT_BLKID_gdc_one_32 = 0x83, 311 + DBG_CLIENT_BLKID_gdc_one_33 = 0x84, 312 + DBG_CLIENT_BLKID_gdc_one_34 = 0x85, 313 + DBG_CLIENT_BLKID_gdc_one_35 = 0x86, 314 + DBG_CLIENT_BLKID_vceb0_0 = 0x87, 315 + DBG_CLIENT_BLKID_vgt3 = 0x88, 316 + DBG_CLIENT_BLKID_pc3 = 0x89, 317 + DBG_CLIENT_BLKID_mcd3_0 = 0x8a, 318 + DBG_CLIENT_BLKID_mcd3_1 = 0x8b, 319 + DBG_CLIENT_BLKID_uvdu_0 = 0x8c, 320 + DBG_CLIENT_BLKID_uvdu_1 = 0x8d, 321 + DBG_CLIENT_BLKID_uvdu_2 = 0x8e, 322 + DBG_CLIENT_BLKID_uvdu_3 = 0x8f, 323 + DBG_CLIENT_BLKID_uvdu_4 = 0x90, 324 + DBG_CLIENT_BLKID_uvdu_5 = 0x91, 325 + DBG_CLIENT_BLKID_uvdu_6 = 0x92, 326 + DBG_CLIENT_BLKID_cb300 = 0x93, 327 + DBG_CLIENT_BLKID_mcd1_0 = 0x94, 328 + DBG_CLIENT_BLKID_mcd1_1 = 0x95, 329 + DBG_CLIENT_BLKID_sx00 = 0x96, 330 + DBG_CLIENT_BLKID_uvdc_0 = 0x97, 331 + DBG_CLIENT_BLKID_uvdc_1 = 0x98, 332 + DBG_CLIENT_BLKID_mcc3 = 0x99, 333 + DBG_CLIENT_BLKID_mcc4 = 0x9a, 334 + DBG_CLIENT_BLKID_mcc5 = 0x9b, 335 + DBG_CLIENT_BLKID_mcc6 = 0x9c, 336 + DBG_CLIENT_BLKID_mcc7 = 0x9d, 337 + DBG_CLIENT_BLKID_cpg_0 = 0x9e, 338 + DBG_CLIENT_BLKID_cpg_1 = 0x9f, 339 + DBG_CLIENT_BLKID_gck = 0xa0, 340 + DBG_CLIENT_BLKID_mcc1 = 0xa1, 341 + DBG_CLIENT_BLKID_cpf_0 = 0xa2, 342 + DBG_CLIENT_BLKID_cpf_1 = 0xa3, 343 + DBG_CLIENT_BLKID_rlc = 0xa4, 344 + DBG_CLIENT_BLKID_grbm = 0xa5, 345 + DBG_CLIENT_BLKID_sammsp = 0xa6, 346 + DBG_CLIENT_BLKID_dci_pg = 0xa7, 347 + DBG_CLIENT_BLKID_dci_0 = 0xa8, 348 + DBG_CLIENT_BLKID_dccg0_0 = 0xa9, 349 + DBG_CLIENT_BLKID_dccg0_1 = 0xaa, 350 + DBG_CLIENT_BLKID_dcfe01_0 = 0xab, 351 + DBG_CLIENT_BLKID_dcfe02_0 = 0xac, 352 + DBG_CLIENT_BLKID_dcfe03_0 = 0xad, 353 + DBG_CLIENT_BLKID_dcfe04_0 = 0xae, 354 + DBG_CLIENT_BLKID_dcfe05_0 = 0xaf, 355 + DBG_CLIENT_BLKID_dcfe06_0 = 0xb0, 356 + DBG_CLIENT_BLKID_mcq0_0 = 0xb1, 357 + DBG_CLIENT_BLKID_mcq0_1 = 0xb2, 358 + DBG_CLIENT_BLKID_mcq1_0 = 0xb3, 359 + DBG_CLIENT_BLKID_mcq1_1 = 0xb4, 360 + DBG_CLIENT_BLKID_mcq2_0 = 0xb5, 361 + DBG_CLIENT_BLKID_mcq2_1 = 0xb6, 362 + DBG_CLIENT_BLKID_mcq3_0 = 0xb7, 363 + DBG_CLIENT_BLKID_mcq3_1 = 0xb8, 364 + DBG_CLIENT_BLKID_mcq4_0 = 0xb9, 365 + DBG_CLIENT_BLKID_mcq4_1 = 0xba, 366 + DBG_CLIENT_BLKID_mcq5_0 = 0xbb, 367 + DBG_CLIENT_BLKID_mcq5_1 = 0xbc, 368 + DBG_CLIENT_BLKID_mcq6_0 = 0xbd, 369 + DBG_CLIENT_BLKID_mcq6_1 = 0xbe, 370 + DBG_CLIENT_BLKID_mcq7_0 = 0xbf, 371 + DBG_CLIENT_BLKID_mcq7_1 = 0xc0, 372 + DBG_CLIENT_BLKID_uvdi_0 = 0xc1, 373 + DBG_CLIENT_BLKID_RESERVED_LAST = 0xc2, 374 + } DebugBlockId; 375 + typedef enum DebugBlockId_OLD { 376 + DBG_BLOCK_ID_RESERVED = 0x0, 377 + DBG_BLOCK_ID_DBG = 0x1, 378 + DBG_BLOCK_ID_VMC = 0x2, 379 + DBG_BLOCK_ID_PDMA = 0x3, 380 + DBG_BLOCK_ID_CG = 0x4, 381 + DBG_BLOCK_ID_SRBM = 0x5, 382 + DBG_BLOCK_ID_GRBM = 0x6, 383 + DBG_BLOCK_ID_RLC = 0x7, 384 + DBG_BLOCK_ID_CSC = 0x8, 385 + DBG_BLOCK_ID_SEM = 0x9, 386 + DBG_BLOCK_ID_IH = 0xa, 387 + DBG_BLOCK_ID_SC = 0xb, 388 + DBG_BLOCK_ID_SQ = 0xc, 389 + DBG_BLOCK_ID_AVP = 0xd, 390 + DBG_BLOCK_ID_GMCON = 0xe, 391 + DBG_BLOCK_ID_SMU = 0xf, 392 + DBG_BLOCK_ID_DMA0 = 0x10, 393 + DBG_BLOCK_ID_DMA1 = 0x11, 394 + DBG_BLOCK_ID_SPIM = 0x12, 395 + DBG_BLOCK_ID_GDS = 0x13, 396 + DBG_BLOCK_ID_SPIS = 0x14, 397 + DBG_BLOCK_ID_UNUSED0 = 0x15, 398 + DBG_BLOCK_ID_PA0 = 0x16, 399 + DBG_BLOCK_ID_PA1 = 0x17, 400 + DBG_BLOCK_ID_CP0 = 0x18, 401 + DBG_BLOCK_ID_CP1 = 0x19, 402 + DBG_BLOCK_ID_CP2 = 0x1a, 403 + DBG_BLOCK_ID_UNUSED1 = 0x1b, 404 + DBG_BLOCK_ID_UVDU = 0x1c, 405 + DBG_BLOCK_ID_UVDM = 0x1d, 406 + DBG_BLOCK_ID_VCE = 0x1e, 407 + DBG_BLOCK_ID_UNUSED2 = 0x1f, 408 + DBG_BLOCK_ID_VGT0 = 0x20, 409 + DBG_BLOCK_ID_VGT1 = 0x21, 410 + DBG_BLOCK_ID_IA = 0x22, 411 + DBG_BLOCK_ID_UNUSED3 = 0x23, 412 + DBG_BLOCK_ID_SCT0 = 0x24, 413 + DBG_BLOCK_ID_SCT1 = 0x25, 414 + DBG_BLOCK_ID_SPM0 = 0x26, 415 + DBG_BLOCK_ID_SPM1 = 0x27, 416 + DBG_BLOCK_ID_TCAA = 0x28, 417 + DBG_BLOCK_ID_TCAB = 0x29, 418 + DBG_BLOCK_ID_TCCA = 0x2a, 419 + DBG_BLOCK_ID_TCCB = 0x2b, 420 + DBG_BLOCK_ID_MCC0 = 0x2c, 421 + DBG_BLOCK_ID_MCC1 = 0x2d, 422 + DBG_BLOCK_ID_MCC2 = 0x2e, 423 + DBG_BLOCK_ID_MCC3 = 0x2f, 424 + DBG_BLOCK_ID_SX0 = 0x30, 425 + DBG_BLOCK_ID_SX1 = 0x31, 426 + DBG_BLOCK_ID_SX2 = 0x32, 427 + DBG_BLOCK_ID_SX3 = 0x33, 428 + DBG_BLOCK_ID_UNUSED4 = 0x34, 429 + DBG_BLOCK_ID_UNUSED5 = 0x35, 430 + DBG_BLOCK_ID_UNUSED6 = 0x36, 431 + DBG_BLOCK_ID_UNUSED7 = 0x37, 432 + DBG_BLOCK_ID_PC0 = 0x38, 433 + DBG_BLOCK_ID_PC1 = 0x39, 434 + DBG_BLOCK_ID_UNUSED8 = 0x3a, 435 + DBG_BLOCK_ID_UNUSED9 = 0x3b, 436 + DBG_BLOCK_ID_UNUSED10 = 0x3c, 437 + DBG_BLOCK_ID_UNUSED11 = 0x3d, 438 + DBG_BLOCK_ID_MCB = 0x3e, 439 + DBG_BLOCK_ID_UNUSED12 = 0x3f, 440 + DBG_BLOCK_ID_SCB0 = 0x40, 441 + DBG_BLOCK_ID_SCB1 = 0x41, 442 + DBG_BLOCK_ID_UNUSED13 = 0x42, 443 + DBG_BLOCK_ID_UNUSED14 = 0x43, 444 + DBG_BLOCK_ID_SCF0 = 0x44, 445 + DBG_BLOCK_ID_SCF1 = 0x45, 446 + DBG_BLOCK_ID_UNUSED15 = 0x46, 447 + DBG_BLOCK_ID_UNUSED16 = 0x47, 448 + DBG_BLOCK_ID_BCI0 = 0x48, 449 + DBG_BLOCK_ID_BCI1 = 0x49, 450 + DBG_BLOCK_ID_BCI2 = 0x4a, 451 + DBG_BLOCK_ID_BCI3 = 0x4b, 452 + DBG_BLOCK_ID_UNUSED17 = 0x4c, 453 + DBG_BLOCK_ID_UNUSED18 = 0x4d, 454 + DBG_BLOCK_ID_UNUSED19 = 0x4e, 455 + DBG_BLOCK_ID_UNUSED20 = 0x4f, 456 + DBG_BLOCK_ID_CB00 = 0x50, 457 + DBG_BLOCK_ID_CB01 = 0x51, 458 + DBG_BLOCK_ID_CB02 = 0x52, 459 + DBG_BLOCK_ID_CB03 = 0x53, 460 + DBG_BLOCK_ID_CB04 = 0x54, 461 + DBG_BLOCK_ID_UNUSED21 = 0x55, 462 + DBG_BLOCK_ID_UNUSED22 = 0x56, 463 + DBG_BLOCK_ID_UNUSED23 = 0x57, 464 + DBG_BLOCK_ID_CB10 = 0x58, 465 + DBG_BLOCK_ID_CB11 = 0x59, 466 + DBG_BLOCK_ID_CB12 = 0x5a, 467 + DBG_BLOCK_ID_CB13 = 0x5b, 468 + DBG_BLOCK_ID_CB14 = 0x5c, 469 + DBG_BLOCK_ID_UNUSED24 = 0x5d, 470 + DBG_BLOCK_ID_UNUSED25 = 0x5e, 471 + DBG_BLOCK_ID_UNUSED26 = 0x5f, 472 + DBG_BLOCK_ID_TCP0 = 0x60, 473 + DBG_BLOCK_ID_TCP1 = 0x61, 474 + DBG_BLOCK_ID_TCP2 = 0x62, 475 + DBG_BLOCK_ID_TCP3 = 0x63, 476 + DBG_BLOCK_ID_TCP4 = 0x64, 477 + DBG_BLOCK_ID_TCP5 = 0x65, 478 + DBG_BLOCK_ID_TCP6 = 0x66, 479 + DBG_BLOCK_ID_TCP7 = 0x67, 480 + DBG_BLOCK_ID_TCP8 = 0x68, 481 + DBG_BLOCK_ID_TCP9 = 0x69, 482 + DBG_BLOCK_ID_TCP10 = 0x6a, 483 + DBG_BLOCK_ID_TCP11 = 0x6b, 484 + DBG_BLOCK_ID_TCP12 = 0x6c, 485 + DBG_BLOCK_ID_TCP13 = 0x6d, 486 + DBG_BLOCK_ID_TCP14 = 0x6e, 487 + DBG_BLOCK_ID_TCP15 = 0x6f, 488 + DBG_BLOCK_ID_TCP16 = 0x70, 489 + DBG_BLOCK_ID_TCP17 = 0x71, 490 + DBG_BLOCK_ID_TCP18 = 0x72, 491 + DBG_BLOCK_ID_TCP19 = 0x73, 492 + DBG_BLOCK_ID_TCP20 = 0x74, 493 + DBG_BLOCK_ID_TCP21 = 0x75, 494 + DBG_BLOCK_ID_TCP22 = 0x76, 495 + DBG_BLOCK_ID_TCP23 = 0x77, 496 + DBG_BLOCK_ID_TCP_RESERVED0 = 0x78, 497 + DBG_BLOCK_ID_TCP_RESERVED1 = 0x79, 498 + DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a, 499 + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b, 500 + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c, 501 + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d, 502 + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e, 503 + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f, 504 + DBG_BLOCK_ID_DB00 = 0x80, 505 + DBG_BLOCK_ID_DB01 = 0x81, 506 + DBG_BLOCK_ID_DB02 = 0x82, 507 + DBG_BLOCK_ID_DB03 = 0x83, 508 + DBG_BLOCK_ID_DB04 = 0x84, 509 + DBG_BLOCK_ID_UNUSED27 = 0x85, 510 + DBG_BLOCK_ID_UNUSED28 = 0x86, 511 + DBG_BLOCK_ID_UNUSED29 = 0x87, 512 + DBG_BLOCK_ID_DB10 = 0x88, 513 + DBG_BLOCK_ID_DB11 = 0x89, 514 + DBG_BLOCK_ID_DB12 = 0x8a, 515 + DBG_BLOCK_ID_DB13 = 0x8b, 516 + DBG_BLOCK_ID_DB14 = 0x8c, 517 + DBG_BLOCK_ID_UNUSED30 = 0x8d, 518 + DBG_BLOCK_ID_UNUSED31 = 0x8e, 519 + DBG_BLOCK_ID_UNUSED32 = 0x8f, 520 + DBG_BLOCK_ID_TCC0 = 0x90, 521 + DBG_BLOCK_ID_TCC1 = 0x91, 522 + DBG_BLOCK_ID_TCC2 = 0x92, 523 + DBG_BLOCK_ID_TCC3 = 0x93, 524 + DBG_BLOCK_ID_TCC4 = 0x94, 525 + DBG_BLOCK_ID_TCC5 = 0x95, 526 + DBG_BLOCK_ID_TCC6 = 0x96, 527 + DBG_BLOCK_ID_TCC7 = 0x97, 528 + DBG_BLOCK_ID_SPS00 = 0x98, 529 + DBG_BLOCK_ID_SPS01 = 0x99, 530 + DBG_BLOCK_ID_SPS02 = 0x9a, 531 + DBG_BLOCK_ID_SPS10 = 0x9b, 532 + DBG_BLOCK_ID_SPS11 = 0x9c, 533 + DBG_BLOCK_ID_SPS12 = 0x9d, 534 + DBG_BLOCK_ID_UNUSED33 = 0x9e, 535 + DBG_BLOCK_ID_UNUSED34 = 0x9f, 536 + DBG_BLOCK_ID_TA00 = 0xa0, 537 + DBG_BLOCK_ID_TA01 = 0xa1, 538 + DBG_BLOCK_ID_TA02 = 0xa2, 539 + DBG_BLOCK_ID_TA03 = 0xa3, 540 + DBG_BLOCK_ID_TA04 = 0xa4, 541 + DBG_BLOCK_ID_TA05 = 0xa5, 542 + DBG_BLOCK_ID_TA06 = 0xa6, 543 + DBG_BLOCK_ID_TA07 = 0xa7, 544 + DBG_BLOCK_ID_TA08 = 0xa8, 545 + DBG_BLOCK_ID_TA09 = 0xa9, 546 + DBG_BLOCK_ID_TA0A = 0xaa, 547 + DBG_BLOCK_ID_TA0B = 0xab, 548 + DBG_BLOCK_ID_UNUSED35 = 0xac, 549 + DBG_BLOCK_ID_UNUSED36 = 0xad, 550 + DBG_BLOCK_ID_UNUSED37 = 0xae, 551 + DBG_BLOCK_ID_UNUSED38 = 0xaf, 552 + DBG_BLOCK_ID_TA10 = 0xb0, 553 + DBG_BLOCK_ID_TA11 = 0xb1, 554 + DBG_BLOCK_ID_TA12 = 0xb2, 555 + DBG_BLOCK_ID_TA13 = 0xb3, 556 + DBG_BLOCK_ID_TA14 = 0xb4, 557 + DBG_BLOCK_ID_TA15 = 0xb5, 558 + DBG_BLOCK_ID_TA16 = 0xb6, 559 + DBG_BLOCK_ID_TA17 = 0xb7, 560 + DBG_BLOCK_ID_TA18 = 0xb8, 561 + DBG_BLOCK_ID_TA19 = 0xb9, 562 + DBG_BLOCK_ID_TA1A = 0xba, 563 + DBG_BLOCK_ID_TA1B = 0xbb, 564 + DBG_BLOCK_ID_UNUSED39 = 0xbc, 565 + DBG_BLOCK_ID_UNUSED40 = 0xbd, 566 + DBG_BLOCK_ID_UNUSED41 = 0xbe, 567 + DBG_BLOCK_ID_UNUSED42 = 0xbf, 568 + DBG_BLOCK_ID_TD00 = 0xc0, 569 + DBG_BLOCK_ID_TD01 = 0xc1, 570 + DBG_BLOCK_ID_TD02 = 0xc2, 571 + DBG_BLOCK_ID_TD03 = 0xc3, 572 + DBG_BLOCK_ID_TD04 = 0xc4, 573 + DBG_BLOCK_ID_TD05 = 0xc5, 574 + DBG_BLOCK_ID_TD06 = 0xc6, 575 + DBG_BLOCK_ID_TD07 = 0xc7, 576 + DBG_BLOCK_ID_TD08 = 0xc8, 577 + DBG_BLOCK_ID_TD09 = 0xc9, 578 + DBG_BLOCK_ID_TD0A = 0xca, 579 + DBG_BLOCK_ID_TD0B = 0xcb, 580 + DBG_BLOCK_ID_UNUSED43 = 0xcc, 581 + DBG_BLOCK_ID_UNUSED44 = 0xcd, 582 + DBG_BLOCK_ID_UNUSED45 = 0xce, 583 + DBG_BLOCK_ID_UNUSED46 = 0xcf, 584 + DBG_BLOCK_ID_TD10 = 0xd0, 585 + DBG_BLOCK_ID_TD11 = 0xd1, 586 + DBG_BLOCK_ID_TD12 = 0xd2, 587 + DBG_BLOCK_ID_TD13 = 0xd3, 588 + DBG_BLOCK_ID_TD14 = 0xd4, 589 + DBG_BLOCK_ID_TD15 = 0xd5, 590 + DBG_BLOCK_ID_TD16 = 0xd6, 591 + DBG_BLOCK_ID_TD17 = 0xd7, 592 + DBG_BLOCK_ID_TD18 = 0xd8, 593 + DBG_BLOCK_ID_TD19 = 0xd9, 594 + DBG_BLOCK_ID_TD1A = 0xda, 595 + DBG_BLOCK_ID_TD1B = 0xdb, 596 + DBG_BLOCK_ID_UNUSED47 = 0xdc, 597 + DBG_BLOCK_ID_UNUSED48 = 0xdd, 598 + DBG_BLOCK_ID_UNUSED49 = 0xde, 599 + DBG_BLOCK_ID_UNUSED50 = 0xdf, 600 + DBG_BLOCK_ID_MCD0 = 0xe0, 601 + DBG_BLOCK_ID_MCD1 = 0xe1, 602 + DBG_BLOCK_ID_MCD2 = 0xe2, 603 + DBG_BLOCK_ID_MCD3 = 0xe3, 604 + DBG_BLOCK_ID_MCD4 = 0xe4, 605 + DBG_BLOCK_ID_MCD5 = 0xe5, 606 + DBG_BLOCK_ID_UNUSED51 = 0xe6, 607 + DBG_BLOCK_ID_UNUSED52 = 0xe7, 608 + } DebugBlockId_OLD; 609 + typedef enum DebugBlockId_BY2 { 610 + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 611 + DBG_BLOCK_ID_VMC_BY2 = 0x1, 612 + DBG_BLOCK_ID_CG_BY2 = 0x2, 613 + DBG_BLOCK_ID_GRBM_BY2 = 0x3, 614 + DBG_BLOCK_ID_CSC_BY2 = 0x4, 615 + DBG_BLOCK_ID_IH_BY2 = 0x5, 616 + DBG_BLOCK_ID_SQ_BY2 = 0x6, 617 + DBG_BLOCK_ID_GMCON_BY2 = 0x7, 618 + DBG_BLOCK_ID_DMA0_BY2 = 0x8, 619 + DBG_BLOCK_ID_SPIM_BY2 = 0x9, 620 + DBG_BLOCK_ID_SPIS_BY2 = 0xa, 621 + DBG_BLOCK_ID_PA0_BY2 = 0xb, 622 + DBG_BLOCK_ID_CP0_BY2 = 0xc, 623 + DBG_BLOCK_ID_CP2_BY2 = 0xd, 624 + DBG_BLOCK_ID_UVDU_BY2 = 0xe, 625 + DBG_BLOCK_ID_VCE_BY2 = 0xf, 626 + DBG_BLOCK_ID_VGT0_BY2 = 0x10, 627 + DBG_BLOCK_ID_IA_BY2 = 0x11, 628 + DBG_BLOCK_ID_SCT0_BY2 = 0x12, 629 + DBG_BLOCK_ID_SPM0_BY2 = 0x13, 630 + DBG_BLOCK_ID_TCAA_BY2 = 0x14, 631 + DBG_BLOCK_ID_TCCA_BY2 = 0x15, 632 + DBG_BLOCK_ID_MCC0_BY2 = 0x16, 633 + DBG_BLOCK_ID_MCC2_BY2 = 0x17, 634 + DBG_BLOCK_ID_SX0_BY2 = 0x18, 635 + DBG_BLOCK_ID_SX2_BY2 = 0x19, 636 + DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a, 637 + DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b, 638 + DBG_BLOCK_ID_PC0_BY2 = 0x1c, 639 + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d, 640 + DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e, 641 + DBG_BLOCK_ID_MCB_BY2 = 0x1f, 642 + DBG_BLOCK_ID_SCB0_BY2 = 0x20, 643 + DBG_BLOCK_ID_UNUSED13_BY2 = 0x21, 644 + DBG_BLOCK_ID_SCF0_BY2 = 0x22, 645 + DBG_BLOCK_ID_UNUSED15_BY2 = 0x23, 646 + DBG_BLOCK_ID_BCI0_BY2 = 0x24, 647 + DBG_BLOCK_ID_BCI2_BY2 = 0x25, 648 + DBG_BLOCK_ID_UNUSED17_BY2 = 0x26, 649 + DBG_BLOCK_ID_UNUSED19_BY2 = 0x27, 650 + DBG_BLOCK_ID_CB00_BY2 = 0x28, 651 + DBG_BLOCK_ID_CB02_BY2 = 0x29, 652 + DBG_BLOCK_ID_CB04_BY2 = 0x2a, 653 + DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b, 654 + DBG_BLOCK_ID_CB10_BY2 = 0x2c, 655 + DBG_BLOCK_ID_CB12_BY2 = 0x2d, 656 + DBG_BLOCK_ID_CB14_BY2 = 0x2e, 657 + DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f, 658 + DBG_BLOCK_ID_TCP0_BY2 = 0x30, 659 + DBG_BLOCK_ID_TCP2_BY2 = 0x31, 660 + DBG_BLOCK_ID_TCP4_BY2 = 0x32, 661 + DBG_BLOCK_ID_TCP6_BY2 = 0x33, 662 + DBG_BLOCK_ID_TCP8_BY2 = 0x34, 663 + DBG_BLOCK_ID_TCP10_BY2 = 0x35, 664 + DBG_BLOCK_ID_TCP12_BY2 = 0x36, 665 + DBG_BLOCK_ID_TCP14_BY2 = 0x37, 666 + DBG_BLOCK_ID_TCP16_BY2 = 0x38, 667 + DBG_BLOCK_ID_TCP18_BY2 = 0x39, 668 + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 669 + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 670 + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 671 + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 672 + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 673 + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 674 + DBG_BLOCK_ID_DB00_BY2 = 0x40, 675 + DBG_BLOCK_ID_DB02_BY2 = 0x41, 676 + DBG_BLOCK_ID_DB04_BY2 = 0x42, 677 + DBG_BLOCK_ID_UNUSED28_BY2 = 0x43, 678 + DBG_BLOCK_ID_DB10_BY2 = 0x44, 679 + DBG_BLOCK_ID_DB12_BY2 = 0x45, 680 + DBG_BLOCK_ID_DB14_BY2 = 0x46, 681 + DBG_BLOCK_ID_UNUSED31_BY2 = 0x47, 682 + DBG_BLOCK_ID_TCC0_BY2 = 0x48, 683 + DBG_BLOCK_ID_TCC2_BY2 = 0x49, 684 + DBG_BLOCK_ID_TCC4_BY2 = 0x4a, 685 + DBG_BLOCK_ID_TCC6_BY2 = 0x4b, 686 + DBG_BLOCK_ID_SPS00_BY2 = 0x4c, 687 + DBG_BLOCK_ID_SPS02_BY2 = 0x4d, 688 + DBG_BLOCK_ID_SPS11_BY2 = 0x4e, 689 + DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f, 690 + DBG_BLOCK_ID_TA00_BY2 = 0x50, 691 + DBG_BLOCK_ID_TA02_BY2 = 0x51, 692 + DBG_BLOCK_ID_TA04_BY2 = 0x52, 693 + DBG_BLOCK_ID_TA06_BY2 = 0x53, 694 + DBG_BLOCK_ID_TA08_BY2 = 0x54, 695 + DBG_BLOCK_ID_TA0A_BY2 = 0x55, 696 + DBG_BLOCK_ID_UNUSED35_BY2 = 0x56, 697 + DBG_BLOCK_ID_UNUSED37_BY2 = 0x57, 698 + DBG_BLOCK_ID_TA10_BY2 = 0x58, 699 + DBG_BLOCK_ID_TA12_BY2 = 0x59, 700 + DBG_BLOCK_ID_TA14_BY2 = 0x5a, 701 + DBG_BLOCK_ID_TA16_BY2 = 0x5b, 702 + DBG_BLOCK_ID_TA18_BY2 = 0x5c, 703 + DBG_BLOCK_ID_TA1A_BY2 = 0x5d, 704 + DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e, 705 + DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f, 706 + DBG_BLOCK_ID_TD00_BY2 = 0x60, 707 + DBG_BLOCK_ID_TD02_BY2 = 0x61, 708 + DBG_BLOCK_ID_TD04_BY2 = 0x62, 709 + DBG_BLOCK_ID_TD06_BY2 = 0x63, 710 + DBG_BLOCK_ID_TD08_BY2 = 0x64, 711 + DBG_BLOCK_ID_TD0A_BY2 = 0x65, 712 + DBG_BLOCK_ID_UNUSED43_BY2 = 0x66, 713 + DBG_BLOCK_ID_UNUSED45_BY2 = 0x67, 714 + DBG_BLOCK_ID_TD10_BY2 = 0x68, 715 + DBG_BLOCK_ID_TD12_BY2 = 0x69, 716 + DBG_BLOCK_ID_TD14_BY2 = 0x6a, 717 + DBG_BLOCK_ID_TD16_BY2 = 0x6b, 718 + DBG_BLOCK_ID_TD18_BY2 = 0x6c, 719 + DBG_BLOCK_ID_TD1A_BY2 = 0x6d, 720 + DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e, 721 + DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f, 722 + DBG_BLOCK_ID_MCD0_BY2 = 0x70, 723 + DBG_BLOCK_ID_MCD2_BY2 = 0x71, 724 + DBG_BLOCK_ID_MCD4_BY2 = 0x72, 725 + DBG_BLOCK_ID_UNUSED51_BY2 = 0x73, 726 + } DebugBlockId_BY2; 727 + typedef enum DebugBlockId_BY4 { 728 + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 729 + DBG_BLOCK_ID_CG_BY4 = 0x1, 730 + DBG_BLOCK_ID_CSC_BY4 = 0x2, 731 + DBG_BLOCK_ID_SQ_BY4 = 0x3, 732 + DBG_BLOCK_ID_DMA0_BY4 = 0x4, 733 + DBG_BLOCK_ID_SPIS_BY4 = 0x5, 734 + DBG_BLOCK_ID_CP0_BY4 = 0x6, 735 + DBG_BLOCK_ID_UVDU_BY4 = 0x7, 736 + DBG_BLOCK_ID_VGT0_BY4 = 0x8, 737 + DBG_BLOCK_ID_SCT0_BY4 = 0x9, 738 + DBG_BLOCK_ID_TCAA_BY4 = 0xa, 739 + DBG_BLOCK_ID_MCC0_BY4 = 0xb, 740 + DBG_BLOCK_ID_SX0_BY4 = 0xc, 741 + DBG_BLOCK_ID_UNUSED4_BY4 = 0xd, 742 + DBG_BLOCK_ID_PC0_BY4 = 0xe, 743 + DBG_BLOCK_ID_UNUSED10_BY4 = 0xf, 744 + DBG_BLOCK_ID_SCB0_BY4 = 0x10, 745 + DBG_BLOCK_ID_SCF0_BY4 = 0x11, 746 + DBG_BLOCK_ID_BCI0_BY4 = 0x12, 747 + DBG_BLOCK_ID_UNUSED17_BY4 = 0x13, 748 + DBG_BLOCK_ID_CB00_BY4 = 0x14, 749 + DBG_BLOCK_ID_CB04_BY4 = 0x15, 750 + DBG_BLOCK_ID_CB10_BY4 = 0x16, 751 + DBG_BLOCK_ID_CB14_BY4 = 0x17, 752 + DBG_BLOCK_ID_TCP0_BY4 = 0x18, 753 + DBG_BLOCK_ID_TCP4_BY4 = 0x19, 754 + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 755 + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 756 + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 757 + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 758 + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 759 + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 760 + DBG_BLOCK_ID_DB_BY4 = 0x20, 761 + DBG_BLOCK_ID_DB04_BY4 = 0x21, 762 + DBG_BLOCK_ID_DB10_BY4 = 0x22, 763 + DBG_BLOCK_ID_DB14_BY4 = 0x23, 764 + DBG_BLOCK_ID_TCC0_BY4 = 0x24, 765 + DBG_BLOCK_ID_TCC4_BY4 = 0x25, 766 + DBG_BLOCK_ID_SPS00_BY4 = 0x26, 767 + DBG_BLOCK_ID_SPS11_BY4 = 0x27, 768 + DBG_BLOCK_ID_TA00_BY4 = 0x28, 769 + DBG_BLOCK_ID_TA04_BY4 = 0x29, 770 + DBG_BLOCK_ID_TA08_BY4 = 0x2a, 771 + DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b, 772 + DBG_BLOCK_ID_TA10_BY4 = 0x2c, 773 + DBG_BLOCK_ID_TA14_BY4 = 0x2d, 774 + DBG_BLOCK_ID_TA18_BY4 = 0x2e, 775 + DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f, 776 + DBG_BLOCK_ID_TD00_BY4 = 0x30, 777 + DBG_BLOCK_ID_TD04_BY4 = 0x31, 778 + DBG_BLOCK_ID_TD08_BY4 = 0x32, 779 + DBG_BLOCK_ID_UNUSED43_BY4 = 0x33, 780 + DBG_BLOCK_ID_TD10_BY4 = 0x34, 781 + DBG_BLOCK_ID_TD14_BY4 = 0x35, 782 + DBG_BLOCK_ID_TD18_BY4 = 0x36, 783 + DBG_BLOCK_ID_UNUSED47_BY4 = 0x37, 784 + DBG_BLOCK_ID_MCD0_BY4 = 0x38, 785 + DBG_BLOCK_ID_MCD4_BY4 = 0x39, 786 + } DebugBlockId_BY4; 787 + typedef enum DebugBlockId_BY8 { 788 + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 789 + DBG_BLOCK_ID_CSC_BY8 = 0x1, 790 + DBG_BLOCK_ID_DMA0_BY8 = 0x2, 791 + DBG_BLOCK_ID_CP0_BY8 = 0x3, 792 + DBG_BLOCK_ID_VGT0_BY8 = 0x4, 793 + DBG_BLOCK_ID_TCAA_BY8 = 0x5, 794 + DBG_BLOCK_ID_SX0_BY8 = 0x6, 795 + DBG_BLOCK_ID_PC0_BY8 = 0x7, 796 + DBG_BLOCK_ID_SCB0_BY8 = 0x8, 797 + DBG_BLOCK_ID_BCI0_BY8 = 0x9, 798 + DBG_BLOCK_ID_CB00_BY8 = 0xa, 799 + DBG_BLOCK_ID_CB10_BY8 = 0xb, 800 + DBG_BLOCK_ID_TCP0_BY8 = 0xc, 801 + DBG_BLOCK_ID_TCP8_BY8 = 0xd, 802 + DBG_BLOCK_ID_TCP16_BY8 = 0xe, 803 + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 804 + DBG_BLOCK_ID_DB00_BY8 = 0x10, 805 + DBG_BLOCK_ID_DB10_BY8 = 0x11, 806 + DBG_BLOCK_ID_TCC0_BY8 = 0x12, 807 + DBG_BLOCK_ID_SPS00_BY8 = 0x13, 808 + DBG_BLOCK_ID_TA00_BY8 = 0x14, 809 + DBG_BLOCK_ID_TA08_BY8 = 0x15, 810 + DBG_BLOCK_ID_TA10_BY8 = 0x16, 811 + DBG_BLOCK_ID_TA18_BY8 = 0x17, 812 + DBG_BLOCK_ID_TD00_BY8 = 0x18, 813 + DBG_BLOCK_ID_TD08_BY8 = 0x19, 814 + DBG_BLOCK_ID_TD10_BY8 = 0x1a, 815 + DBG_BLOCK_ID_TD18_BY8 = 0x1b, 816 + DBG_BLOCK_ID_MCD0_BY8 = 0x1c, 817 + } DebugBlockId_BY8; 818 + typedef enum DebugBlockId_BY16 { 819 + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 820 + DBG_BLOCK_ID_DMA0_BY16 = 0x1, 821 + DBG_BLOCK_ID_VGT0_BY16 = 0x2, 822 + DBG_BLOCK_ID_SX0_BY16 = 0x3, 823 + DBG_BLOCK_ID_SCB0_BY16 = 0x4, 824 + DBG_BLOCK_ID_CB00_BY16 = 0x5, 825 + DBG_BLOCK_ID_TCP0_BY16 = 0x6, 826 + DBG_BLOCK_ID_TCP16_BY16 = 0x7, 827 + DBG_BLOCK_ID_DB00_BY16 = 0x8, 828 + DBG_BLOCK_ID_TCC0_BY16 = 0x9, 829 + DBG_BLOCK_ID_TA00_BY16 = 0xa, 830 + DBG_BLOCK_ID_TA10_BY16 = 0xb, 831 + DBG_BLOCK_ID_TD00_BY16 = 0xc, 832 + DBG_BLOCK_ID_TD10_BY16 = 0xd, 833 + DBG_BLOCK_ID_MCD0_BY16 = 0xe, 834 + } DebugBlockId_BY16; 835 + typedef enum ColorTransform { 836 + DCC_CT_AUTO = 0x0, 837 + DCC_CT_NONE = 0x1, 838 + ABGR_TO_A_BG_G_RB = 0x2, 839 + BGRA_TO_BG_G_RB_A = 0x3, 840 + } ColorTransform; 841 + typedef enum CompareRef { 842 + REF_NEVER = 0x0, 843 + REF_LESS = 0x1, 844 + REF_EQUAL = 0x2, 845 + REF_LEQUAL = 0x3, 846 + REF_GREATER = 0x4, 847 + REF_NOTEQUAL = 0x5, 848 + REF_GEQUAL = 0x6, 849 + REF_ALWAYS = 0x7, 850 + } CompareRef; 851 + typedef enum ReadSize { 852 + READ_256_BITS = 0x0, 853 + READ_512_BITS = 0x1, 854 + } ReadSize; 855 + typedef enum DepthFormat { 856 + DEPTH_INVALID = 0x0, 857 + DEPTH_16 = 0x1, 858 + DEPTH_X8_24 = 0x2, 859 + DEPTH_8_24 = 0x3, 860 + DEPTH_X8_24_FLOAT = 0x4, 861 + DEPTH_8_24_FLOAT = 0x5, 862 + DEPTH_32_FLOAT = 0x6, 863 + DEPTH_X24_8_32_FLOAT = 0x7, 864 + } DepthFormat; 865 + typedef enum ZFormat { 866 + Z_INVALID = 0x0, 867 + Z_16 = 0x1, 868 + Z_24 = 0x2, 869 + Z_32_FLOAT = 0x3, 870 + } ZFormat; 871 + typedef enum StencilFormat { 872 + STENCIL_INVALID = 0x0, 873 + STENCIL_8 = 0x1, 874 + } StencilFormat; 875 + typedef enum CmaskMode { 876 + CMASK_CLEAR_NONE = 0x0, 877 + CMASK_CLEAR_ONE = 0x1, 878 + CMASK_CLEAR_ALL = 0x2, 879 + CMASK_ANY_EXPANDED = 0x3, 880 + CMASK_ALPHA0_FRAG1 = 0x4, 881 + CMASK_ALPHA0_FRAG2 = 0x5, 882 + CMASK_ALPHA0_FRAG4 = 0x6, 883 + CMASK_ALPHA0_FRAGS = 0x7, 884 + CMASK_ALPHA1_FRAG1 = 0x8, 885 + CMASK_ALPHA1_FRAG2 = 0x9, 886 + CMASK_ALPHA1_FRAG4 = 0xa, 887 + CMASK_ALPHA1_FRAGS = 0xb, 888 + CMASK_ALPHAX_FRAG1 = 0xc, 889 + CMASK_ALPHAX_FRAG2 = 0xd, 890 + CMASK_ALPHAX_FRAG4 = 0xe, 891 + CMASK_ALPHAX_FRAGS = 0xf, 892 + } CmaskMode; 893 + typedef enum QuadExportFormat { 894 + EXPORT_UNUSED = 0x0, 895 + EXPORT_32_R = 0x1, 896 + EXPORT_32_GR = 0x2, 897 + EXPORT_32_AR = 0x3, 898 + EXPORT_FP16_ABGR = 0x4, 899 + EXPORT_UNSIGNED16_ABGR = 0x5, 900 + EXPORT_SIGNED16_ABGR = 0x6, 901 + EXPORT_32_ABGR = 0x7, 902 + } QuadExportFormat; 903 + typedef enum QuadExportFormatOld { 904 + EXPORT_4P_32BPC_ABGR = 0x0, 905 + EXPORT_4P_16BPC_ABGR = 0x1, 906 + EXPORT_4P_32BPC_GR = 0x2, 907 + EXPORT_4P_32BPC_AR = 0x3, 908 + EXPORT_2P_32BPC_ABGR = 0x4, 909 + EXPORT_8P_32BPC_R = 0x5, 910 + } QuadExportFormatOld; 911 + typedef enum ColorFormat { 912 + COLOR_INVALID = 0x0, 913 + COLOR_8 = 0x1, 914 + COLOR_16 = 0x2, 915 + COLOR_8_8 = 0x3, 916 + COLOR_32 = 0x4, 917 + COLOR_16_16 = 0x5, 918 + COLOR_10_11_11 = 0x6, 919 + COLOR_11_11_10 = 0x7, 920 + COLOR_10_10_10_2 = 0x8, 921 + COLOR_2_10_10_10 = 0x9, 922 + COLOR_8_8_8_8 = 0xa, 923 + COLOR_32_32 = 0xb, 924 + COLOR_16_16_16_16 = 0xc, 925 + COLOR_RESERVED_13 = 0xd, 926 + COLOR_32_32_32_32 = 0xe, 927 + COLOR_RESERVED_15 = 0xf, 928 + COLOR_5_6_5 = 0x10, 929 + COLOR_1_5_5_5 = 0x11, 930 + COLOR_5_5_5_1 = 0x12, 931 + COLOR_4_4_4_4 = 0x13, 932 + COLOR_8_24 = 0x14, 933 + COLOR_24_8 = 0x15, 934 + COLOR_X24_8_32_FLOAT = 0x16, 935 + COLOR_RESERVED_23 = 0x17, 936 + } ColorFormat; 937 + typedef enum SurfaceFormat { 938 + FMT_INVALID = 0x0, 939 + FMT_8 = 0x1, 940 + FMT_16 = 0x2, 941 + FMT_8_8 = 0x3, 942 + FMT_32 = 0x4, 943 + FMT_16_16 = 0x5, 944 + FMT_10_11_11 = 0x6, 945 + FMT_11_11_10 = 0x7, 946 + FMT_10_10_10_2 = 0x8, 947 + FMT_2_10_10_10 = 0x9, 948 + FMT_8_8_8_8 = 0xa, 949 + FMT_32_32 = 0xb, 950 + FMT_16_16_16_16 = 0xc, 951 + FMT_32_32_32 = 0xd, 952 + FMT_32_32_32_32 = 0xe, 953 + FMT_RESERVED_4 = 0xf, 954 + FMT_5_6_5 = 0x10, 955 + FMT_1_5_5_5 = 0x11, 956 + FMT_5_5_5_1 = 0x12, 957 + FMT_4_4_4_4 = 0x13, 958 + FMT_8_24 = 0x14, 959 + FMT_24_8 = 0x15, 960 + FMT_X24_8_32_FLOAT = 0x16, 961 + FMT_RESERVED_33 = 0x17, 962 + FMT_11_11_10_FLOAT = 0x18, 963 + FMT_16_FLOAT = 0x19, 964 + FMT_32_FLOAT = 0x1a, 965 + FMT_16_16_FLOAT = 0x1b, 966 + FMT_8_24_FLOAT = 0x1c, 967 + FMT_24_8_FLOAT = 0x1d, 968 + FMT_32_32_FLOAT = 0x1e, 969 + FMT_10_11_11_FLOAT = 0x1f, 970 + FMT_16_16_16_16_FLOAT = 0x20, 971 + FMT_3_3_2 = 0x21, 972 + FMT_6_5_5 = 0x22, 973 + FMT_32_32_32_32_FLOAT = 0x23, 974 + FMT_RESERVED_36 = 0x24, 975 + FMT_1 = 0x25, 976 + FMT_1_REVERSED = 0x26, 977 + FMT_GB_GR = 0x27, 978 + FMT_BG_RG = 0x28, 979 + FMT_32_AS_8 = 0x29, 980 + FMT_32_AS_8_8 = 0x2a, 981 + FMT_5_9_9_9_SHAREDEXP = 0x2b, 982 + FMT_8_8_8 = 0x2c, 983 + FMT_16_16_16 = 0x2d, 984 + FMT_16_16_16_FLOAT = 0x2e, 985 + FMT_4_4 = 0x2f, 986 + FMT_32_32_32_FLOAT = 0x30, 987 + FMT_BC1 = 0x31, 988 + FMT_BC2 = 0x32, 989 + FMT_BC3 = 0x33, 990 + FMT_BC4 = 0x34, 991 + FMT_BC5 = 0x35, 992 + FMT_BC6 = 0x36, 993 + FMT_BC7 = 0x37, 994 + FMT_32_AS_32_32_32_32 = 0x38, 995 + FMT_APC3 = 0x39, 996 + FMT_APC4 = 0x3a, 997 + FMT_APC5 = 0x3b, 998 + FMT_APC6 = 0x3c, 999 + FMT_APC7 = 0x3d, 1000 + FMT_CTX1 = 0x3e, 1001 + FMT_RESERVED_63 = 0x3f, 1002 + } SurfaceFormat; 1003 + typedef enum BUF_DATA_FORMAT { 1004 + BUF_DATA_FORMAT_INVALID = 0x0, 1005 + BUF_DATA_FORMAT_8 = 0x1, 1006 + BUF_DATA_FORMAT_16 = 0x2, 1007 + BUF_DATA_FORMAT_8_8 = 0x3, 1008 + BUF_DATA_FORMAT_32 = 0x4, 1009 + BUF_DATA_FORMAT_16_16 = 0x5, 1010 + BUF_DATA_FORMAT_10_11_11 = 0x6, 1011 + BUF_DATA_FORMAT_11_11_10 = 0x7, 1012 + BUF_DATA_FORMAT_10_10_10_2 = 0x8, 1013 + BUF_DATA_FORMAT_2_10_10_10 = 0x9, 1014 + BUF_DATA_FORMAT_8_8_8_8 = 0xa, 1015 + BUF_DATA_FORMAT_32_32 = 0xb, 1016 + BUF_DATA_FORMAT_16_16_16_16 = 0xc, 1017 + BUF_DATA_FORMAT_32_32_32 = 0xd, 1018 + BUF_DATA_FORMAT_32_32_32_32 = 0xe, 1019 + BUF_DATA_FORMAT_RESERVED_15 = 0xf, 1020 + } BUF_DATA_FORMAT; 1021 + typedef enum IMG_DATA_FORMAT { 1022 + IMG_DATA_FORMAT_INVALID = 0x0, 1023 + IMG_DATA_FORMAT_8 = 0x1, 1024 + IMG_DATA_FORMAT_16 = 0x2, 1025 + IMG_DATA_FORMAT_8_8 = 0x3, 1026 + IMG_DATA_FORMAT_32 = 0x4, 1027 + IMG_DATA_FORMAT_16_16 = 0x5, 1028 + IMG_DATA_FORMAT_10_11_11 = 0x6, 1029 + IMG_DATA_FORMAT_11_11_10 = 0x7, 1030 + IMG_DATA_FORMAT_10_10_10_2 = 0x8, 1031 + IMG_DATA_FORMAT_2_10_10_10 = 0x9, 1032 + IMG_DATA_FORMAT_8_8_8_8 = 0xa, 1033 + IMG_DATA_FORMAT_32_32 = 0xb, 1034 + IMG_DATA_FORMAT_16_16_16_16 = 0xc, 1035 + IMG_DATA_FORMAT_32_32_32 = 0xd, 1036 + IMG_DATA_FORMAT_32_32_32_32 = 0xe, 1037 + IMG_DATA_FORMAT_RESERVED_15 = 0xf, 1038 + IMG_DATA_FORMAT_5_6_5 = 0x10, 1039 + IMG_DATA_FORMAT_1_5_5_5 = 0x11, 1040 + IMG_DATA_FORMAT_5_5_5_1 = 0x12, 1041 + IMG_DATA_FORMAT_4_4_4_4 = 0x13, 1042 + IMG_DATA_FORMAT_8_24 = 0x14, 1043 + IMG_DATA_FORMAT_24_8 = 0x15, 1044 + IMG_DATA_FORMAT_X24_8_32 = 0x16, 1045 + IMG_DATA_FORMAT_RESERVED_23 = 0x17, 1046 + IMG_DATA_FORMAT_RESERVED_24 = 0x18, 1047 + IMG_DATA_FORMAT_RESERVED_25 = 0x19, 1048 + IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 1049 + IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 1050 + IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 1051 + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1052 + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1053 + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1054 + IMG_DATA_FORMAT_GB_GR = 0x20, 1055 + IMG_DATA_FORMAT_BG_RG = 0x21, 1056 + IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1057 + IMG_DATA_FORMAT_BC1 = 0x23, 1058 + IMG_DATA_FORMAT_BC2 = 0x24, 1059 + IMG_DATA_FORMAT_BC3 = 0x25, 1060 + IMG_DATA_FORMAT_BC4 = 0x26, 1061 + IMG_DATA_FORMAT_BC5 = 0x27, 1062 + IMG_DATA_FORMAT_BC6 = 0x28, 1063 + IMG_DATA_FORMAT_BC7 = 0x29, 1064 + IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1065 + IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1066 + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1067 + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1068 + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1069 + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1070 + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1071 + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1072 + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1073 + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1074 + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1075 + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1076 + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1077 + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1078 + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1079 + IMG_DATA_FORMAT_4_4 = 0x39, 1080 + IMG_DATA_FORMAT_6_5_5 = 0x3a, 1081 + IMG_DATA_FORMAT_1 = 0x3b, 1082 + IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1083 + IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1084 + IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1085 + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1086 + } IMG_DATA_FORMAT; 1087 + typedef enum BUF_NUM_FORMAT { 1088 + BUF_NUM_FORMAT_UNORM = 0x0, 1089 + BUF_NUM_FORMAT_SNORM = 0x1, 1090 + BUF_NUM_FORMAT_USCALED = 0x2, 1091 + BUF_NUM_FORMAT_SSCALED = 0x3, 1092 + BUF_NUM_FORMAT_UINT = 0x4, 1093 + BUF_NUM_FORMAT_SINT = 0x5, 1094 + BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1095 + BUF_NUM_FORMAT_FLOAT = 0x7, 1096 + } BUF_NUM_FORMAT; 1097 + typedef enum IMG_NUM_FORMAT { 1098 + IMG_NUM_FORMAT_UNORM = 0x0, 1099 + IMG_NUM_FORMAT_SNORM = 0x1, 1100 + IMG_NUM_FORMAT_USCALED = 0x2, 1101 + IMG_NUM_FORMAT_SSCALED = 0x3, 1102 + IMG_NUM_FORMAT_UINT = 0x4, 1103 + IMG_NUM_FORMAT_SINT = 0x5, 1104 + IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1105 + IMG_NUM_FORMAT_FLOAT = 0x7, 1106 + IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1107 + IMG_NUM_FORMAT_SRGB = 0x9, 1108 + IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1109 + IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1110 + IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1111 + IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1112 + IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1113 + IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1114 + } IMG_NUM_FORMAT; 1115 + typedef enum TileType { 1116 + ARRAY_COLOR_TILE = 0x0, 1117 + ARRAY_DEPTH_TILE = 0x1, 1118 + } TileType; 1119 + typedef enum NonDispTilingOrder { 1120 + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1121 + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1122 + } NonDispTilingOrder; 1123 + typedef enum MicroTileMode { 1124 + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1125 + ADDR_SURF_THIN_MICRO_TILING = 0x1, 1126 + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1127 + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1128 + ADDR_SURF_THICK_MICRO_TILING = 0x4, 1129 + } MicroTileMode; 1130 + typedef enum TileSplit { 1131 + ADDR_SURF_TILE_SPLIT_64B = 0x0, 1132 + ADDR_SURF_TILE_SPLIT_128B = 0x1, 1133 + ADDR_SURF_TILE_SPLIT_256B = 0x2, 1134 + ADDR_SURF_TILE_SPLIT_512B = 0x3, 1135 + ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1136 + ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1137 + ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1138 + } TileSplit; 1139 + typedef enum SampleSplit { 1140 + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1141 + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1142 + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1143 + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1144 + } SampleSplit; 1145 + typedef enum PipeConfig { 1146 + ADDR_SURF_P2 = 0x0, 1147 + ADDR_SURF_P2_RESERVED0 = 0x1, 1148 + ADDR_SURF_P2_RESERVED1 = 0x2, 1149 + ADDR_SURF_P2_RESERVED2 = 0x3, 1150 + ADDR_SURF_P4_8x16 = 0x4, 1151 + ADDR_SURF_P4_16x16 = 0x5, 1152 + ADDR_SURF_P4_16x32 = 0x6, 1153 + ADDR_SURF_P4_32x32 = 0x7, 1154 + ADDR_SURF_P8_16x16_8x16 = 0x8, 1155 + ADDR_SURF_P8_16x32_8x16 = 0x9, 1156 + ADDR_SURF_P8_32x32_8x16 = 0xa, 1157 + ADDR_SURF_P8_16x32_16x16 = 0xb, 1158 + ADDR_SURF_P8_32x32_16x16 = 0xc, 1159 + ADDR_SURF_P8_32x32_16x32 = 0xd, 1160 + ADDR_SURF_P8_32x64_32x32 = 0xe, 1161 + ADDR_SURF_P8_RESERVED0 = 0xf, 1162 + ADDR_SURF_P16_32x32_8x16 = 0x10, 1163 + ADDR_SURF_P16_32x32_16x16 = 0x11, 1164 + } PipeConfig; 1165 + typedef enum NumBanks { 1166 + ADDR_SURF_2_BANK = 0x0, 1167 + ADDR_SURF_4_BANK = 0x1, 1168 + ADDR_SURF_8_BANK = 0x2, 1169 + ADDR_SURF_16_BANK = 0x3, 1170 + } NumBanks; 1171 + typedef enum BankWidth { 1172 + ADDR_SURF_BANK_WIDTH_1 = 0x0, 1173 + ADDR_SURF_BANK_WIDTH_2 = 0x1, 1174 + ADDR_SURF_BANK_WIDTH_4 = 0x2, 1175 + ADDR_SURF_BANK_WIDTH_8 = 0x3, 1176 + } BankWidth; 1177 + typedef enum BankHeight { 1178 + ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1179 + ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1180 + ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1181 + ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1182 + } BankHeight; 1183 + typedef enum BankWidthHeight { 1184 + ADDR_SURF_BANK_WH_1 = 0x0, 1185 + ADDR_SURF_BANK_WH_2 = 0x1, 1186 + ADDR_SURF_BANK_WH_4 = 0x2, 1187 + ADDR_SURF_BANK_WH_8 = 0x3, 1188 + } BankWidthHeight; 1189 + typedef enum MacroTileAspect { 1190 + ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1191 + ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1192 + ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1193 + ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1194 + } MacroTileAspect; 1195 + typedef enum GATCL1RequestType { 1196 + GATCL1_TYPE_NORMAL = 0x0, 1197 + GATCL1_TYPE_SHOOTDOWN = 0x1, 1198 + GATCL1_TYPE_BYPASS = 0x2, 1199 + } GATCL1RequestType; 1200 + typedef enum TCC_CACHE_POLICIES { 1201 + TCC_CACHE_POLICY_LRU = 0x0, 1202 + TCC_CACHE_POLICY_STREAM = 0x1, 1203 + } TCC_CACHE_POLICIES; 1204 + typedef enum MTYPE { 1205 + MTYPE_NC_NV = 0x0, 1206 + MTYPE_NC = 0x1, 1207 + MTYPE_CC = 0x2, 1208 + MTYPE_UC = 0x3, 1209 + } MTYPE; 1210 + typedef enum PERFMON_COUNTER_MODE { 1211 + PERFMON_COUNTER_MODE_ACCUM = 0x0, 1212 + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1213 + PERFMON_COUNTER_MODE_MAX = 0x2, 1214 + PERFMON_COUNTER_MODE_DIRTY = 0x3, 1215 + PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1216 + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1217 + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1218 + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1219 + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1220 + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1221 + PERFMON_COUNTER_MODE_RESERVED = 0xf, 1222 + } PERFMON_COUNTER_MODE; 1223 + typedef enum PERFMON_SPM_MODE { 1224 + PERFMON_SPM_MODE_OFF = 0x0, 1225 + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1226 + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1227 + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1228 + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1229 + PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1230 + PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1231 + PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1232 + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1233 + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1234 + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1235 + } PERFMON_SPM_MODE; 1236 + typedef enum SurfaceTiling { 1237 + ARRAY_LINEAR = 0x0, 1238 + ARRAY_TILED = 0x1, 1239 + } SurfaceTiling; 1240 + typedef enum SurfaceArray { 1241 + ARRAY_1D = 0x0, 1242 + ARRAY_2D = 0x1, 1243 + ARRAY_3D = 0x2, 1244 + ARRAY_3D_SLICE = 0x3, 1245 + } SurfaceArray; 1246 + typedef enum ColorArray { 1247 + ARRAY_2D_ALT_COLOR = 0x0, 1248 + ARRAY_2D_COLOR = 0x1, 1249 + ARRAY_3D_SLICE_COLOR = 0x3, 1250 + } ColorArray; 1251 + typedef enum DepthArray { 1252 + ARRAY_2D_ALT_DEPTH = 0x0, 1253 + ARRAY_2D_DEPTH = 0x1, 1254 + } DepthArray; 1255 + typedef enum ENUM_NUM_SIMD_PER_CU { 1256 + NUM_SIMD_PER_CU = 0x4, 1257 + } ENUM_NUM_SIMD_PER_CU; 1258 + typedef enum MEM_PWR_FORCE_CTRL { 1259 + NO_FORCE_REQUEST = 0x0, 1260 + FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1261 + FORCE_DEEP_SLEEP_REQUEST = 0x2, 1262 + FORCE_SHUT_DOWN_REQUEST = 0x3, 1263 + } MEM_PWR_FORCE_CTRL; 1264 + typedef enum MEM_PWR_FORCE_CTRL2 { 1265 + NO_FORCE_REQ = 0x0, 1266 + FORCE_LIGHT_SLEEP_REQ = 0x1, 1267 + } MEM_PWR_FORCE_CTRL2; 1268 + typedef enum MEM_PWR_DIS_CTRL { 1269 + ENABLE_MEM_PWR_CTRL = 0x0, 1270 + DISABLE_MEM_PWR_CTRL = 0x1, 1271 + } MEM_PWR_DIS_CTRL; 1272 + typedef enum MEM_PWR_SEL_CTRL { 1273 + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1274 + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1275 + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1276 + } MEM_PWR_SEL_CTRL; 1277 + typedef enum MEM_PWR_SEL_CTRL2 { 1278 + DYNAMIC_DEEP_SLEEP_EN = 0x0, 1279 + DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1280 + } MEM_PWR_SEL_CTRL2; 1281 + 1282 + #endif /* SMU_7_1_3_ENUM_H */
+6080
drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h
··· 1 + /* 2 + * SMU_7_1_3 Register documentation 3 + * 4 + * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 + * 6 + * Permission is hereby granted, free of charge, to any person obtaining a 7 + * copy of this software and associated documentation files (the "Software"), 8 + * to deal in the Software without restriction, including without limitation 9 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 + * and/or sell copies of the Software, and to permit persons to whom the 11 + * Software is furnished to do so, subject to the following conditions: 12 + * 13 + * The above copyright notice and this permission notice shall be included 14 + * in all copies or substantial portions of the Software. 15 + * 16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 + */ 23 + 24 + #ifndef SMU_7_1_3_SH_MASK_H 25 + #define SMU_7_1_3_SH_MASK_H 26 + 27 + #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 + #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 + #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 + #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 + #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f 32 + #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0 33 + #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780 34 + #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7 35 + #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800 36 + #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb 37 + #define GCK_MCLK_FUSES__MClkDiDtWait_MASK 0xe000 38 + #define GCK_MCLK_FUSES__MClkDiDtWait__SHIFT 0xd 39 + #define GCK_MCLK_FUSES__MClkDiDtFloor_MASK 0x30000 40 + #define GCK_MCLK_FUSES__MClkDiDtFloor__SHIFT 0x10 41 + #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 42 + #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 43 + #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 44 + #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 45 + #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 46 + #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 47 + #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 48 + #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 49 + #define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1 50 + #define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0 51 + #define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2 52 + #define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1 53 + #define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f 54 + #define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0 55 + #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100 56 + #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8 57 + #define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200 58 + #define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9 59 + #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 60 + #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 61 + #define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1 62 + #define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0 63 + #define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2 64 + #define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1 65 + #define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f 66 + #define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0 67 + #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100 68 + #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8 69 + #define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200 70 + #define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9 71 + #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 72 + #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa 73 + #define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1 74 + #define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0 75 + #define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2 76 + #define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1 77 + #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f 78 + #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0 79 + #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100 80 + #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8 81 + #define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200 82 + #define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9 83 + #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 84 + #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa 85 + #define CG_MCLK_CNTL__MCLK_DIVIDER_MASK 0x7f 86 + #define CG_MCLK_CNTL__MCLK_DIVIDER__SHIFT 0x0 87 + #define CG_MCLK_CNTL__MCLK_DIR_CNTL_EN_MASK 0x100 88 + #define CG_MCLK_CNTL__MCLK_DIR_CNTL_EN__SHIFT 0x8 89 + #define CG_MCLK_CNTL__MCLK_DIR_CNTL_TOG_MASK 0x200 90 + #define CG_MCLK_CNTL__MCLK_DIR_CNTL_TOG__SHIFT 0x9 91 + #define CG_MCLK_CNTL__MCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00 92 + #define CG_MCLK_CNTL__MCLK_DIR_CNTL_DIVIDER__SHIFT 0xa 93 + #define CG_MCLK_STATUS__MCLK_STATUS_MASK 0x1 94 + #define CG_MCLK_STATUS__MCLK_STATUS__SHIFT 0x0 95 + #define CG_MCLK_STATUS__MCLK_DIR_CNTL_DONETOG_MASK 0x2 96 + #define CG_MCLK_STATUS__MCLK_DIR_CNTL_DONETOG__SHIFT 0x1 97 + #define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1 98 + #define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0 99 + #define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2 100 + #define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1 101 + #define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4 102 + #define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2 103 + #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8 104 + #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3 105 + #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10 106 + #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4 107 + #define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20 108 + #define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5 109 + #define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40 110 + #define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6 111 + #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80 112 + #define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7 113 + #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100 114 + #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8 115 + #define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200 116 + #define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9 117 + #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400 118 + #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa 119 + #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800 120 + #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb 121 + #define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000 122 + #define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc 123 + #define GCK_DFS_BYPASS_CNTL__BYPASSMCLK_MASK 0x2000 124 + #define GCK_DFS_BYPASS_CNTL__BYPASSMCLK__SHIFT 0xd 125 + #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1 126 + #define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0 127 + #define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2 128 + #define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1 129 + #define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4 130 + #define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2 131 + #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8 132 + #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3 133 + #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10 134 + #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4 135 + #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0 136 + #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5 137 + #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800 138 + #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb 139 + #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000 140 + #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc 141 + #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x7f00000 142 + #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x14 143 + #define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK_MASK 0x8000000 144 + #define CG_SPLL_FUNC_CNTL__SPLL_DIVA_ACK__SHIFT 0x1b 145 + #define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000 146 + #define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c 147 + #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff 148 + #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0 149 + #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800 150 + #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb 151 + #define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000 152 + #define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16 153 + #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000 154 + #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17 155 + #define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000 156 + #define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18 157 + #define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000 158 + #define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19 159 + #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000 160 + #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a 161 + #define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000 162 + #define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b 163 + #define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000 164 + #define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c 165 + #define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000 166 + #define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e 167 + #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff 168 + #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0 169 + #define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000 170 + #define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c 171 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf 172 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0 173 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60 174 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5 175 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180 176 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7 177 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0xe00 178 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0x9 179 + #define CG_SPLL_FUNC_CNTL_4__PCC_INC_DIV_MASK 0x7f000 180 + #define CG_SPLL_FUNC_CNTL_4__PCC_INC_DIV__SHIFT 0xc 181 + #define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000 182 + #define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15 183 + #define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000 184 + #define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17 185 + #define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000 186 + #define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18 187 + #define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000 188 + #define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19 189 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000 190 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a 191 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000 192 + #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c 193 + #define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000 194 + #define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f 195 + #define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1 196 + #define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0 197 + #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2 198 + #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1 199 + #define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc 200 + #define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2 201 + #define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30 202 + #define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4 203 + #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0 204 + #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6 205 + #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100 206 + #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8 207 + #define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200 208 + #define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9 209 + #define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff 210 + #define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0 211 + #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00 212 + #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8 213 + #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000 214 + #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10 215 + #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000 216 + #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11 217 + #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000 218 + #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15 219 + #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000 220 + #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19 221 + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff 222 + #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0 223 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1 224 + #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0 225 + #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2 226 + #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1 227 + #define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4 228 + #define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2 229 + #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8 230 + #define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3 231 + #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10 232 + #define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4 233 + #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00 234 + #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa 235 + #define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000 236 + #define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc 237 + #define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000 238 + #define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c 239 + #define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000 240 + #define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d 241 + #define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1 242 + #define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0 243 + #define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0 244 + #define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4 245 + #define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff 246 + #define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0 247 + #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00 248 + #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8 249 + #define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2 250 + #define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1 251 + #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4 252 + #define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2 253 + #define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1 254 + #define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0 255 + #define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8 256 + #define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3 257 + #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100 258 + #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8 259 + #define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000 260 + #define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe 261 + #define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000 262 + #define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf 263 + #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000 264 + #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10 265 + #define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000 266 + #define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11 267 + #define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000 268 + #define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12 269 + #define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000 270 + #define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13 271 + #define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000 272 + #define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14 273 + #define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000 274 + #define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15 275 + #define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000 276 + #define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16 277 + #define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000 278 + #define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18 279 + #define CG_CLKPIN_CNTL_DC__OSC_EN_MASK 0x1 280 + #define CG_CLKPIN_CNTL_DC__OSC_EN__SHIFT 0x0 281 + #define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN_MASK 0x6 282 + #define CG_CLKPIN_CNTL_DC__XTL_LOW_GAIN__SHIFT 0x1 283 + #define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN_MASK 0x200 284 + #define CG_CLKPIN_CNTL_DC__XTL_XOCLK_DRV_R_EN__SHIFT 0x9 285 + #define CG_CLKPIN_CNTL_DC__XTALIN_SEL_MASK 0x1c00 286 + #define CG_CLKPIN_CNTL_DC__XTALIN_SEL__SHIFT 0xa 287 + #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff 288 + #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0 289 + #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00 290 + #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8 291 + #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000 292 + #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10 293 + #define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff 294 + #define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0 295 + #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 296 + #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8 297 + #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000 298 + #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10 299 + #define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f 300 + #define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 301 + #define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0 302 + #define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5 303 + #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00 304 + #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa 305 + #define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000 306 + #define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11 307 + #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000 308 + #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12 309 + #define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000 310 + #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11 311 + #define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7 312 + #define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0 313 + #define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38 314 + #define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3 315 + #define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0 316 + #define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6 317 + #define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00 318 + #define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9 319 + #define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000 320 + #define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc 321 + #define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000 322 + #define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf 323 + #define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000 324 + #define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12 325 + #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000 326 + #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15 327 + #define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000 328 + #define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18 329 + #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000 330 + #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b 331 + #define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 332 + #define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 333 + #define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 334 + #define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 335 + #define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff 336 + #define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 337 + #define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff 338 + #define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 339 + #define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff 340 + #define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 341 + #define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff 342 + #define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 343 + #define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff 344 + #define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 345 + #define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff 346 + #define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 347 + #define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff 348 + #define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 349 + #define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff 350 + #define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 351 + #define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff 352 + #define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 353 + #define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff 354 + #define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 355 + #define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff 356 + #define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 357 + #define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff 358 + #define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 359 + #define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff 360 + #define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 361 + #define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff 362 + #define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 363 + #define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff 364 + #define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 365 + #define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff 366 + #define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 367 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1 368 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0 369 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2 370 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1 371 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4 372 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2 373 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8 374 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3 375 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10 376 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4 377 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20 378 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5 379 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40 380 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6 381 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80 382 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7 383 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8_MASK 0x100 384 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_8__SHIFT 0x8 385 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9_MASK 0x200 386 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_9__SHIFT 0x9 387 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10_MASK 0x400 388 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_10__SHIFT 0xa 389 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11_MASK 0x800 390 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_11__SHIFT 0xb 391 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12_MASK 0x1000 392 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_12__SHIFT 0xc 393 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13_MASK 0x2000 394 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_13__SHIFT 0xd 395 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14_MASK 0x4000 396 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_14__SHIFT 0xe 397 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15_MASK 0x8000 398 + #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_15__SHIFT 0xf 399 + #define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff 400 + #define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0 401 + #define SMC_RESP_0__SMC_RESP_MASK 0xffff 402 + #define SMC_RESP_0__SMC_RESP__SHIFT 0x0 403 + #define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff 404 + #define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0 405 + #define SMC_RESP_1__SMC_RESP_MASK 0xffff 406 + #define SMC_RESP_1__SMC_RESP__SHIFT 0x0 407 + #define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff 408 + #define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0 409 + #define SMC_RESP_2__SMC_RESP_MASK 0xffff 410 + #define SMC_RESP_2__SMC_RESP__SHIFT 0x0 411 + #define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff 412 + #define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0 413 + #define SMC_RESP_3__SMC_RESP_MASK 0xffff 414 + #define SMC_RESP_3__SMC_RESP__SHIFT 0x0 415 + #define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff 416 + #define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0 417 + #define SMC_RESP_4__SMC_RESP_MASK 0xffff 418 + #define SMC_RESP_4__SMC_RESP__SHIFT 0x0 419 + #define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff 420 + #define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0 421 + #define SMC_RESP_5__SMC_RESP_MASK 0xffff 422 + #define SMC_RESP_5__SMC_RESP__SHIFT 0x0 423 + #define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff 424 + #define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0 425 + #define SMC_RESP_6__SMC_RESP_MASK 0xffff 426 + #define SMC_RESP_6__SMC_RESP__SHIFT 0x0 427 + #define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff 428 + #define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0 429 + #define SMC_RESP_7__SMC_RESP_MASK 0xffff 430 + #define SMC_RESP_7__SMC_RESP__SHIFT 0x0 431 + #define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff 432 + #define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0 433 + #define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff 434 + #define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0 435 + #define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff 436 + #define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0 437 + #define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff 438 + #define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0 439 + #define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff 440 + #define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0 441 + #define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff 442 + #define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0 443 + #define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff 444 + #define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0 445 + #define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff 446 + #define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0 447 + #define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff 448 + #define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0 449 + #define SMC_RESP_8__SMC_RESP_MASK 0xffff 450 + #define SMC_RESP_8__SMC_RESP__SHIFT 0x0 451 + #define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff 452 + #define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0 453 + #define SMC_RESP_9__SMC_RESP_MASK 0xffff 454 + #define SMC_RESP_9__SMC_RESP__SHIFT 0x0 455 + #define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff 456 + #define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0 457 + #define SMC_RESP_10__SMC_RESP_MASK 0xffff 458 + #define SMC_RESP_10__SMC_RESP__SHIFT 0x0 459 + #define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff 460 + #define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0 461 + #define SMC_RESP_11__SMC_RESP_MASK 0xffff 462 + #define SMC_RESP_11__SMC_RESP__SHIFT 0x0 463 + #define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff 464 + #define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0 465 + #define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff 466 + #define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0 467 + #define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff 468 + #define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0 469 + #define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff 470 + #define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0 471 + #define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1 472 + #define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0 473 + #define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2 474 + #define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1 475 + #define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000 476 + #define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e 477 + #define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1 478 + #define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0 479 + #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2 480 + #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1 481 + #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00 482 + #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8 483 + #define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000 484 + #define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18 485 + #define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1 486 + #define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0 487 + #define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff 488 + #define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0 489 + #define SMC_SYSCON_MISC_CNTL__dma_no_outstanding_MASK 0x2 490 + #define SMC_SYSCON_MISC_CNTL__dma_no_outstanding__SHIFT 0x1 491 + #define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff 492 + #define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0 493 + #define SMC_PC_C__smc_pc_c_MASK 0xffffffff 494 + #define SMC_PC_C__smc_pc_c__SHIFT 0x0 495 + #define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff 496 + #define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0 497 + #define GPIOPAD_SW_INT_STAT__SW_INT_STAT_MASK 0x1 498 + #define GPIOPAD_SW_INT_STAT__SW_INT_STAT__SHIFT 0x0 499 + #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN_MASK 0xf 500 + #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SN__SHIFT 0x0 501 + #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP_MASK 0xf0 502 + #define GPIOPAD_STRENGTH__GPIO_STRENGTH_SP__SHIFT 0x4 503 + #define GPIOPAD_MASK__GPIO_MASK_MASK 0x7fffffff 504 + #define GPIOPAD_MASK__GPIO_MASK__SHIFT 0x0 505 + #define GPIOPAD_A__GPIO_A_MASK 0x7fffffff 506 + #define GPIOPAD_A__GPIO_A__SHIFT 0x0 507 + #define GPIOPAD_EN__GPIO_EN_MASK 0x7fffffff 508 + #define GPIOPAD_EN__GPIO_EN__SHIFT 0x0 509 + #define GPIOPAD_Y__GPIO_Y_MASK 0x7fffffff 510 + #define GPIOPAD_Y__GPIO_Y__SHIFT 0x0 511 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0_MASK 0x1 512 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_0__SHIFT 0x0 513 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1_MASK 0x2 514 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_1__SHIFT 0x1 515 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2_MASK 0x4 516 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_2__SHIFT 0x2 517 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3_MASK 0x8 518 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_3__SHIFT 0x3 519 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4_MASK 0x10 520 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_4__SHIFT 0x4 521 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5_MASK 0x20 522 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_5__SHIFT 0x5 523 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6_MASK 0x40 524 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_6__SHIFT 0x6 525 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7_MASK 0x80 526 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_7__SHIFT 0x7 527 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8_MASK 0x100 528 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_8__SHIFT 0x8 529 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9_MASK 0x200 530 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_9__SHIFT 0x9 531 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10_MASK 0x400 532 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_10__SHIFT 0xa 533 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11_MASK 0x800 534 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_11__SHIFT 0xb 535 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12_MASK 0x1000 536 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_12__SHIFT 0xc 537 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13_MASK 0x2000 538 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_13__SHIFT 0xd 539 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14_MASK 0x4000 540 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_14__SHIFT 0xe 541 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15_MASK 0x8000 542 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_15__SHIFT 0xf 543 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16_MASK 0x10000 544 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_16__SHIFT 0x10 545 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17_MASK 0x20000 546 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_17__SHIFT 0x11 547 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18_MASK 0x40000 548 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_18__SHIFT 0x12 549 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19_MASK 0x80000 550 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_19__SHIFT 0x13 551 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20_MASK 0x100000 552 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_20__SHIFT 0x14 553 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21_MASK 0x200000 554 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_21__SHIFT 0x15 555 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22_MASK 0x400000 556 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_22__SHIFT 0x16 557 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23_MASK 0x800000 558 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_23__SHIFT 0x17 559 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24_MASK 0x1000000 560 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_24__SHIFT 0x18 561 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25_MASK 0x2000000 562 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_25__SHIFT 0x19 563 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26_MASK 0x4000000 564 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_26__SHIFT 0x1a 565 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27_MASK 0x8000000 566 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_27__SHIFT 0x1b 567 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28_MASK 0x10000000 568 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_28__SHIFT 0x1c 569 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29_MASK 0x20000000 570 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_29__SHIFT 0x1d 571 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30_MASK 0x40000000 572 + #define GPIOPAD_PINSTRAPS__GPIO_PINSTRAP_30__SHIFT 0x1e 573 + #define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN_MASK 0x1fffffff 574 + #define GPIOPAD_INT_STAT_EN__GPIO_INT_STAT_EN__SHIFT 0x0 575 + #define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN_MASK 0x80000000 576 + #define GPIOPAD_INT_STAT_EN__SW_INITIATED_INT_STAT_EN__SHIFT 0x1f 577 + #define GPIOPAD_INT_STAT__GPIO_INT_STAT_MASK 0x1fffffff 578 + #define GPIOPAD_INT_STAT__GPIO_INT_STAT__SHIFT 0x0 579 + #define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT_MASK 0x80000000 580 + #define GPIOPAD_INT_STAT__SW_INITIATED_INT_STAT__SHIFT 0x1f 581 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0_MASK 0x1 582 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_0__SHIFT 0x0 583 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1_MASK 0x2 584 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_1__SHIFT 0x1 585 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2_MASK 0x4 586 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_2__SHIFT 0x2 587 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3_MASK 0x8 588 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_3__SHIFT 0x3 589 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4_MASK 0x10 590 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_4__SHIFT 0x4 591 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5_MASK 0x20 592 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_5__SHIFT 0x5 593 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6_MASK 0x40 594 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_6__SHIFT 0x6 595 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7_MASK 0x80 596 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_7__SHIFT 0x7 597 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8_MASK 0x100 598 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_8__SHIFT 0x8 599 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9_MASK 0x200 600 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_9__SHIFT 0x9 601 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10_MASK 0x400 602 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_10__SHIFT 0xa 603 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11_MASK 0x800 604 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_11__SHIFT 0xb 605 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12_MASK 0x1000 606 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_12__SHIFT 0xc 607 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13_MASK 0x2000 608 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_13__SHIFT 0xd 609 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14_MASK 0x4000 610 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_14__SHIFT 0xe 611 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15_MASK 0x8000 612 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_15__SHIFT 0xf 613 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16_MASK 0x10000 614 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_16__SHIFT 0x10 615 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17_MASK 0x20000 616 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_17__SHIFT 0x11 617 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18_MASK 0x40000 618 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_18__SHIFT 0x12 619 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19_MASK 0x80000 620 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_19__SHIFT 0x13 621 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20_MASK 0x100000 622 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_20__SHIFT 0x14 623 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21_MASK 0x200000 624 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_21__SHIFT 0x15 625 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22_MASK 0x400000 626 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_22__SHIFT 0x16 627 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23_MASK 0x800000 628 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_23__SHIFT 0x17 629 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24_MASK 0x1000000 630 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_24__SHIFT 0x18 631 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25_MASK 0x2000000 632 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_25__SHIFT 0x19 633 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26_MASK 0x4000000 634 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_26__SHIFT 0x1a 635 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27_MASK 0x8000000 636 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_27__SHIFT 0x1b 637 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28_MASK 0x10000000 638 + #define GPIOPAD_INT_STAT_AK__GPIO_INT_STAT_AK_28__SHIFT 0x1c 639 + #define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK_MASK 0x80000000 640 + #define GPIOPAD_INT_STAT_AK__SW_INITIATED_INT_STAT_AK__SHIFT 0x1f 641 + #define GPIOPAD_INT_EN__GPIO_INT_EN_MASK 0x1fffffff 642 + #define GPIOPAD_INT_EN__GPIO_INT_EN__SHIFT 0x0 643 + #define GPIOPAD_INT_EN__SW_INITIATED_INT_EN_MASK 0x80000000 644 + #define GPIOPAD_INT_EN__SW_INITIATED_INT_EN__SHIFT 0x1f 645 + #define GPIOPAD_INT_TYPE__GPIO_INT_TYPE_MASK 0x1fffffff 646 + #define GPIOPAD_INT_TYPE__GPIO_INT_TYPE__SHIFT 0x0 647 + #define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE_MASK 0x80000000 648 + #define GPIOPAD_INT_TYPE__SW_INITIATED_INT_TYPE__SHIFT 0x1f 649 + #define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY_MASK 0x1fffffff 650 + #define GPIOPAD_INT_POLARITY__GPIO_INT_POLARITY__SHIFT 0x0 651 + #define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY_MASK 0x80000000 652 + #define GPIOPAD_INT_POLARITY__SW_INITIATED_INT_POLARITY__SHIFT 0x1f 653 + #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL_MASK 0x1f 654 + #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_SEL__SHIFT 0x0 655 + #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR_MASK 0x20 656 + #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_CLR__SHIFT 0x5 657 + #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ_MASK 0x40 658 + #define GPIOPAD_EXTERN_TRIG_CNTL__EXTERN_TRIG_READ__SHIFT 0x6 659 + #define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL_MASK 0x7fffffff 660 + #define GPIOPAD_RCVR_SEL__GPIO_RCVR_SEL__SHIFT 0x0 661 + #define GPIOPAD_PU_EN__GPIO_PU_EN_MASK 0x7fffffff 662 + #define GPIOPAD_PU_EN__GPIO_PU_EN__SHIFT 0x0 663 + #define GPIOPAD_PD_EN__GPIO_PD_EN_MASK 0x7fffffff 664 + #define GPIOPAD_PD_EN__GPIO_PD_EN__SHIFT 0x0 665 + #define CG_FPS_CNT__FPS_CNT_MASK 0xffffffff 666 + #define CG_FPS_CNT__FPS_CNT__SHIFT 0x0 667 + #define SMU_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff 668 + #define SMU_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0 669 + #define SMU_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff 670 + #define SMU_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0 671 + #define SMU_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff 672 + #define SMU_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0 673 + #define SMU_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff 674 + #define SMU_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0 675 + #define SMU_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff 676 + #define SMU_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0 677 + #define SMU_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff 678 + #define SMU_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0 679 + #define SMU_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff 680 + #define SMU_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0 681 + #define SMU_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff 682 + #define SMU_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0 683 + #define SMU_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff 684 + #define SMU_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0 685 + #define SMU_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff 686 + #define SMU_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0 687 + #define SMU_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff 688 + #define SMU_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0 689 + #define SMU_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff 690 + #define SMU_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0 691 + #define SMU_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff 692 + #define SMU_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0 693 + #define SMU_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff 694 + #define SMU_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0 695 + #define SMU_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff 696 + #define SMU_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0 697 + #define SMU_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff 698 + #define SMU_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0 699 + #define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 700 + #define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 701 + #define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 702 + #define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 703 + #define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1 704 + #define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0 705 + #define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2 706 + #define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1 707 + #define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4 708 + #define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2 709 + #define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK 0x8 710 + #define RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT 0x3 711 + #define RCU_UC_EVENTS__TP_Tester_MASK 0x40 712 + #define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6 713 + #define RCU_UC_EVENTS__boot_seq_done_MASK 0x80 714 + #define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7 715 + #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100 716 + #define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8 717 + #define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200 718 + #define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9 719 + #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400 720 + #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa 721 + #define RCU_UC_EVENTS__FCH_HALT_MASK 0x800 722 + #define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb 723 + #define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000 724 + #define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd 725 + #define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000 726 + #define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10 727 + #define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000 728 + #define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11 729 + #define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000 730 + #define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12 731 + #define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000 732 + #define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13 733 + #define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000 734 + #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18 735 + #define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2 736 + #define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1 737 + #define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8 738 + #define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3 739 + #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10 740 + #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4 741 + #define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20 742 + #define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5 743 + #define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100 744 + #define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8 745 + #define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000 746 + #define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10 747 + #define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000 748 + #define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11 749 + #define RCU_MISC_CTRL__SAMU_START_MASK 0x400000 750 + #define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16 751 + #define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000 752 + #define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17 753 + #define RCU_VIRT_RESET_REQ__VF_MASK 0xffff 754 + #define RCU_VIRT_RESET_REQ__VF__SHIFT 0x0 755 + #define RCU_VIRT_RESET_REQ__PF_MASK 0x80000000 756 + #define RCU_VIRT_RESET_REQ__PF__SHIFT 0x1f 757 + #define CC_RCU_FUSES__GPU_DIS_MASK 0x2 758 + #define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1 759 + #define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4 760 + #define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2 761 + #define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10 762 + #define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4 763 + #define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20 764 + #define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5 765 + #define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40 766 + #define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6 767 + #define CC_RCU_FUSES__ROM_DIS_MASK 0x80 768 + #define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7 769 + #define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100 770 + #define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8 771 + #define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200 772 + #define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9 773 + #define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400 774 + #define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa 775 + #define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x4000 776 + #define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xe 777 + #define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x8000 778 + #define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0xf 779 + #define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x10000 780 + #define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x10 781 + #define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x20000 782 + #define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x11 783 + #define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x40000 784 + #define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x12 785 + #define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x80000 786 + #define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x13 787 + #define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x200000 788 + #define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x15 789 + #define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x400000 790 + #define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x16 791 + #define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x800000 792 + #define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x17 793 + #define CC_RCU_FUSES__WRP_FUSE_VALID_MASK 0x1000000 794 + #define CC_RCU_FUSES__WRP_FUSE_VALID__SHIFT 0x18 795 + #define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x2000000 796 + #define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0x19 797 + #define CC_RCU_FUSES__RCU_SPARE_MASK 0xfc000000 798 + #define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x1a 799 + #define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2 800 + #define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1 801 + #define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc 802 + #define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2 803 + #define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600 804 + #define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9 805 + #define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800 806 + #define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb 807 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000 808 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12 809 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000 810 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13 811 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000 812 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14 813 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000 814 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15 815 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000 816 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16 817 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000 818 + #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17 819 + #define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000 820 + #define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b 821 + #define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000 822 + #define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c 823 + #define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000 824 + #define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d 825 + #define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff 826 + #define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0 827 + #define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00 828 + #define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8 829 + #define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000 830 + #define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10 831 + #define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000 832 + #define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18 833 + #define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe 834 + #define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1 835 + #define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3e 836 + #define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1 837 + #define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e 838 + #define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1 839 + #define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40 840 + #define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6 841 + #define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80 842 + #define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7 843 + #define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100 844 + #define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8 845 + #define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200 846 + #define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9 847 + #define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400 848 + #define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa 849 + #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800 850 + #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb 851 + #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000 852 + #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc 853 + #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000 854 + #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd 855 + #define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000 856 + #define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe 857 + #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000 858 + #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16 859 + #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000 860 + #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17 861 + #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000 862 + #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18 863 + #define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000 864 + #define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19 865 + #define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000 866 + #define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a 867 + #define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0 868 + #define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4 869 + #define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000 870 + #define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14 871 + #define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000 872 + #define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18 873 + #define CC_TST_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 874 + #define CC_TST_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c 875 + #define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2 876 + #define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1 877 + #define CC_HARVEST_FUSES__VCE_DISABLE_MASK 0x6 878 + #define CC_HARVEST_FUSES__VCE_DISABLE__SHIFT 0x1 879 + #define CC_HARVEST_FUSES__UVD_DISABLE_MASK 0x10 880 + #define CC_HARVEST_FUSES__UVD_DISABLE__SHIFT 0x4 881 + #define CC_HARVEST_FUSES__ACP_DISABLE_MASK 0x40 882 + #define CC_HARVEST_FUSES__ACP_DISABLE__SHIFT 0x6 883 + #define CC_HARVEST_FUSES__DC_DISABLE_MASK 0x3f00 884 + #define CC_HARVEST_FUSES__DC_DISABLE__SHIFT 0x8 885 + #define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff 886 + #define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0 887 + #define SMU_STATUS__SMU_DONE_MASK 0x1 888 + #define SMU_STATUS__SMU_DONE__SHIFT 0x0 889 + #define SMU_STATUS__SMU_PASS_MASK 0x2 890 + #define SMU_STATUS__SMU_PASS__SHIFT 0x1 891 + #define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1 892 + #define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0 893 + #define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6 894 + #define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1 895 + #define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8 896 + #define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3 897 + #define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10 898 + #define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4 899 + #define SMU_FIRMWARE__SMU_counter_MASK 0xf00 900 + #define SMU_FIRMWARE__SMU_counter__SHIFT 0x8 901 + #define SMU_FIRMWARE__SMU_MODE_MASK 0x10000 902 + #define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10 903 + #define SMU_FIRMWARE__SMU_SEL_MASK 0x20000 904 + #define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11 905 + #define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff 906 + #define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0 907 + #define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000 908 + #define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f 909 + #define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff 910 + #define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0 911 + #define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1 912 + #define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 913 + #define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe 914 + #define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 915 + #define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000 916 + #define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18 917 + #define TDC_STATUS__VDD_Boost_MASK 0xff 918 + #define TDC_STATUS__VDD_Boost__SHIFT 0x0 919 + #define TDC_STATUS__VDD_Throttle_MASK 0xff00 920 + #define TDC_STATUS__VDD_Throttle__SHIFT 0x8 921 + #define TDC_STATUS__VDDC_Boost_MASK 0xff0000 922 + #define TDC_STATUS__VDDC_Boost__SHIFT 0x10 923 + #define TDC_STATUS__VDDC_Throttle_MASK 0xff000000 924 + #define TDC_STATUS__VDDC_Throttle__SHIFT 0x18 925 + #define TDC_MV_AVERAGE__IDD_MASK 0xffff 926 + #define TDC_MV_AVERAGE__IDD__SHIFT 0x0 927 + #define TDC_MV_AVERAGE__IDDC_MASK 0xffff0000 928 + #define TDC_MV_AVERAGE__IDDC__SHIFT 0x10 929 + #define TDC_VRM_LIMIT__IDD_MASK 0xffff 930 + #define TDC_VRM_LIMIT__IDD__SHIFT 0x0 931 + #define TDC_VRM_LIMIT__IDDC_MASK 0xffff0000 932 + #define TDC_VRM_LIMIT__IDDC__SHIFT 0x10 933 + #define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1 934 + #define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0 935 + #define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2 936 + #define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1 937 + #define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4 938 + #define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2 939 + #define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8 940 + #define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3 941 + #define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10 942 + #define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4 943 + #define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x20 944 + #define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x5 945 + #define FEATURE_STATUS__ACP_DPM_ON_MASK 0x40 946 + #define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x6 947 + #define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80 948 + #define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7 949 + #define FEATURE_STATUS__BAPM_ON_MASK 0x100 950 + #define FEATURE_STATUS__BAPM_ON__SHIFT 0x8 951 + #define FEATURE_STATUS__LPMX_ON_MASK 0x200 952 + #define FEATURE_STATUS__LPMX_ON__SHIFT 0x9 953 + #define FEATURE_STATUS__NBDPM_ON_MASK 0x400 954 + #define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa 955 + #define FEATURE_STATUS__LHTC_ON_MASK 0x800 956 + #define FEATURE_STATUS__LHTC_ON__SHIFT 0xb 957 + #define FEATURE_STATUS__VPC_ON_MASK 0x1000 958 + #define FEATURE_STATUS__VPC_ON__SHIFT 0xc 959 + #define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000 960 + #define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd 961 + #define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000 962 + #define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe 963 + #define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000 964 + #define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf 965 + #define FEATURE_STATUS__AVS_ON_MASK 0x10000 966 + #define FEATURE_STATUS__AVS_ON__SHIFT 0x10 967 + #define FEATURE_STATUS__SPMI_ON_MASK 0x20000 968 + #define FEATURE_STATUS__SPMI_ON__SHIFT 0x11 969 + #define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000 970 + #define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12 971 + #define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000 972 + #define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13 973 + #define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000 974 + #define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14 975 + #define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000 976 + #define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15 977 + #define FEATURE_STATUS__RESERVED_MASK 0xffc00000 978 + #define FEATURE_STATUS__RESERVED__SHIFT 0x16 979 + #define ENTITY_TEMPERATURES_1__GPU_MASK 0xffffffff 980 + #define ENTITY_TEMPERATURES_1__GPU__SHIFT 0x0 981 + #define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming_MASK 0xffffffff 982 + #define MCARB_DRAM_TIMING_TABLE_1__entries_0_0_McArbDramTiming__SHIFT 0x0 983 + #define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2_MASK 0xffffffff 984 + #define MCARB_DRAM_TIMING_TABLE_2__entries_0_0_McArbDramTiming2__SHIFT 0x0 985 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2_MASK 0xff 986 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_2__SHIFT 0x0 987 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1_MASK 0xff00 988 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_1__SHIFT 0x8 989 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0_MASK 0xff0000 990 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_padding_0__SHIFT 0x10 991 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime_MASK 0xff000000 992 + #define MCARB_DRAM_TIMING_TABLE_3__entries_0_0_McArbBurstTime__SHIFT 0x18 993 + #define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming_MASK 0xffffffff 994 + #define MCARB_DRAM_TIMING_TABLE_4__entries_0_1_McArbDramTiming__SHIFT 0x0 995 + #define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2_MASK 0xffffffff 996 + #define MCARB_DRAM_TIMING_TABLE_5__entries_0_1_McArbDramTiming2__SHIFT 0x0 997 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2_MASK 0xff 998 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_2__SHIFT 0x0 999 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1_MASK 0xff00 1000 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_1__SHIFT 0x8 1001 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0_MASK 0xff0000 1002 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_padding_0__SHIFT 0x10 1003 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime_MASK 0xff000000 1004 + #define MCARB_DRAM_TIMING_TABLE_6__entries_0_1_McArbBurstTime__SHIFT 0x18 1005 + #define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming_MASK 0xffffffff 1006 + #define MCARB_DRAM_TIMING_TABLE_7__entries_0_2_McArbDramTiming__SHIFT 0x0 1007 + #define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2_MASK 0xffffffff 1008 + #define MCARB_DRAM_TIMING_TABLE_8__entries_0_2_McArbDramTiming2__SHIFT 0x0 1009 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2_MASK 0xff 1010 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_2__SHIFT 0x0 1011 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1_MASK 0xff00 1012 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_1__SHIFT 0x8 1013 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0_MASK 0xff0000 1014 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_padding_0__SHIFT 0x10 1015 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime_MASK 0xff000000 1016 + #define MCARB_DRAM_TIMING_TABLE_9__entries_0_2_McArbBurstTime__SHIFT 0x18 1017 + #define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming_MASK 0xffffffff 1018 + #define MCARB_DRAM_TIMING_TABLE_10__entries_0_3_McArbDramTiming__SHIFT 0x0 1019 + #define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2_MASK 0xffffffff 1020 + #define MCARB_DRAM_TIMING_TABLE_11__entries_0_3_McArbDramTiming2__SHIFT 0x0 1021 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2_MASK 0xff 1022 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_2__SHIFT 0x0 1023 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1_MASK 0xff00 1024 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_1__SHIFT 0x8 1025 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0_MASK 0xff0000 1026 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_padding_0__SHIFT 0x10 1027 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime_MASK 0xff000000 1028 + #define MCARB_DRAM_TIMING_TABLE_12__entries_0_3_McArbBurstTime__SHIFT 0x18 1029 + #define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming_MASK 0xffffffff 1030 + #define MCARB_DRAM_TIMING_TABLE_13__entries_1_0_McArbDramTiming__SHIFT 0x0 1031 + #define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2_MASK 0xffffffff 1032 + #define MCARB_DRAM_TIMING_TABLE_14__entries_1_0_McArbDramTiming2__SHIFT 0x0 1033 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2_MASK 0xff 1034 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_2__SHIFT 0x0 1035 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1_MASK 0xff00 1036 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_1__SHIFT 0x8 1037 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0_MASK 0xff0000 1038 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_padding_0__SHIFT 0x10 1039 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime_MASK 0xff000000 1040 + #define MCARB_DRAM_TIMING_TABLE_15__entries_1_0_McArbBurstTime__SHIFT 0x18 1041 + #define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming_MASK 0xffffffff 1042 + #define MCARB_DRAM_TIMING_TABLE_16__entries_1_1_McArbDramTiming__SHIFT 0x0 1043 + #define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2_MASK 0xffffffff 1044 + #define MCARB_DRAM_TIMING_TABLE_17__entries_1_1_McArbDramTiming2__SHIFT 0x0 1045 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2_MASK 0xff 1046 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_2__SHIFT 0x0 1047 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1_MASK 0xff00 1048 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_1__SHIFT 0x8 1049 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0_MASK 0xff0000 1050 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_padding_0__SHIFT 0x10 1051 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime_MASK 0xff000000 1052 + #define MCARB_DRAM_TIMING_TABLE_18__entries_1_1_McArbBurstTime__SHIFT 0x18 1053 + #define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming_MASK 0xffffffff 1054 + #define MCARB_DRAM_TIMING_TABLE_19__entries_1_2_McArbDramTiming__SHIFT 0x0 1055 + #define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2_MASK 0xffffffff 1056 + #define MCARB_DRAM_TIMING_TABLE_20__entries_1_2_McArbDramTiming2__SHIFT 0x0 1057 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2_MASK 0xff 1058 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_2__SHIFT 0x0 1059 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1_MASK 0xff00 1060 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_1__SHIFT 0x8 1061 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0_MASK 0xff0000 1062 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_padding_0__SHIFT 0x10 1063 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime_MASK 0xff000000 1064 + #define MCARB_DRAM_TIMING_TABLE_21__entries_1_2_McArbBurstTime__SHIFT 0x18 1065 + #define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming_MASK 0xffffffff 1066 + #define MCARB_DRAM_TIMING_TABLE_22__entries_1_3_McArbDramTiming__SHIFT 0x0 1067 + #define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2_MASK 0xffffffff 1068 + #define MCARB_DRAM_TIMING_TABLE_23__entries_1_3_McArbDramTiming2__SHIFT 0x0 1069 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2_MASK 0xff 1070 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_2__SHIFT 0x0 1071 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1_MASK 0xff00 1072 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_1__SHIFT 0x8 1073 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0_MASK 0xff0000 1074 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_padding_0__SHIFT 0x10 1075 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime_MASK 0xff000000 1076 + #define MCARB_DRAM_TIMING_TABLE_24__entries_1_3_McArbBurstTime__SHIFT 0x18 1077 + #define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming_MASK 0xffffffff 1078 + #define MCARB_DRAM_TIMING_TABLE_25__entries_2_0_McArbDramTiming__SHIFT 0x0 1079 + #define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2_MASK 0xffffffff 1080 + #define MCARB_DRAM_TIMING_TABLE_26__entries_2_0_McArbDramTiming2__SHIFT 0x0 1081 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2_MASK 0xff 1082 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_2__SHIFT 0x0 1083 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1_MASK 0xff00 1084 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_1__SHIFT 0x8 1085 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0_MASK 0xff0000 1086 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_padding_0__SHIFT 0x10 1087 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime_MASK 0xff000000 1088 + #define MCARB_DRAM_TIMING_TABLE_27__entries_2_0_McArbBurstTime__SHIFT 0x18 1089 + #define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming_MASK 0xffffffff 1090 + #define MCARB_DRAM_TIMING_TABLE_28__entries_2_1_McArbDramTiming__SHIFT 0x0 1091 + #define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2_MASK 0xffffffff 1092 + #define MCARB_DRAM_TIMING_TABLE_29__entries_2_1_McArbDramTiming2__SHIFT 0x0 1093 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2_MASK 0xff 1094 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_2__SHIFT 0x0 1095 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1_MASK 0xff00 1096 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_1__SHIFT 0x8 1097 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0_MASK 0xff0000 1098 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_padding_0__SHIFT 0x10 1099 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime_MASK 0xff000000 1100 + #define MCARB_DRAM_TIMING_TABLE_30__entries_2_1_McArbBurstTime__SHIFT 0x18 1101 + #define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming_MASK 0xffffffff 1102 + #define MCARB_DRAM_TIMING_TABLE_31__entries_2_2_McArbDramTiming__SHIFT 0x0 1103 + #define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2_MASK 0xffffffff 1104 + #define MCARB_DRAM_TIMING_TABLE_32__entries_2_2_McArbDramTiming2__SHIFT 0x0 1105 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2_MASK 0xff 1106 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_2__SHIFT 0x0 1107 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1_MASK 0xff00 1108 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_1__SHIFT 0x8 1109 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0_MASK 0xff0000 1110 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_padding_0__SHIFT 0x10 1111 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime_MASK 0xff000000 1112 + #define MCARB_DRAM_TIMING_TABLE_33__entries_2_2_McArbBurstTime__SHIFT 0x18 1113 + #define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming_MASK 0xffffffff 1114 + #define MCARB_DRAM_TIMING_TABLE_34__entries_2_3_McArbDramTiming__SHIFT 0x0 1115 + #define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2_MASK 0xffffffff 1116 + #define MCARB_DRAM_TIMING_TABLE_35__entries_2_3_McArbDramTiming2__SHIFT 0x0 1117 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2_MASK 0xff 1118 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_2__SHIFT 0x0 1119 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1_MASK 0xff00 1120 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_1__SHIFT 0x8 1121 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0_MASK 0xff0000 1122 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_padding_0__SHIFT 0x10 1123 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime_MASK 0xff000000 1124 + #define MCARB_DRAM_TIMING_TABLE_36__entries_2_3_McArbBurstTime__SHIFT 0x18 1125 + #define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming_MASK 0xffffffff 1126 + #define MCARB_DRAM_TIMING_TABLE_37__entries_3_0_McArbDramTiming__SHIFT 0x0 1127 + #define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2_MASK 0xffffffff 1128 + #define MCARB_DRAM_TIMING_TABLE_38__entries_3_0_McArbDramTiming2__SHIFT 0x0 1129 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2_MASK 0xff 1130 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_2__SHIFT 0x0 1131 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1_MASK 0xff00 1132 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_1__SHIFT 0x8 1133 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0_MASK 0xff0000 1134 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_padding_0__SHIFT 0x10 1135 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime_MASK 0xff000000 1136 + #define MCARB_DRAM_TIMING_TABLE_39__entries_3_0_McArbBurstTime__SHIFT 0x18 1137 + #define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming_MASK 0xffffffff 1138 + #define MCARB_DRAM_TIMING_TABLE_40__entries_3_1_McArbDramTiming__SHIFT 0x0 1139 + #define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2_MASK 0xffffffff 1140 + #define MCARB_DRAM_TIMING_TABLE_41__entries_3_1_McArbDramTiming2__SHIFT 0x0 1141 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2_MASK 0xff 1142 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_2__SHIFT 0x0 1143 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1_MASK 0xff00 1144 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_1__SHIFT 0x8 1145 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0_MASK 0xff0000 1146 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_padding_0__SHIFT 0x10 1147 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime_MASK 0xff000000 1148 + #define MCARB_DRAM_TIMING_TABLE_42__entries_3_1_McArbBurstTime__SHIFT 0x18 1149 + #define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming_MASK 0xffffffff 1150 + #define MCARB_DRAM_TIMING_TABLE_43__entries_3_2_McArbDramTiming__SHIFT 0x0 1151 + #define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2_MASK 0xffffffff 1152 + #define MCARB_DRAM_TIMING_TABLE_44__entries_3_2_McArbDramTiming2__SHIFT 0x0 1153 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2_MASK 0xff 1154 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_2__SHIFT 0x0 1155 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1_MASK 0xff00 1156 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_1__SHIFT 0x8 1157 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0_MASK 0xff0000 1158 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_padding_0__SHIFT 0x10 1159 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime_MASK 0xff000000 1160 + #define MCARB_DRAM_TIMING_TABLE_45__entries_3_2_McArbBurstTime__SHIFT 0x18 1161 + #define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming_MASK 0xffffffff 1162 + #define MCARB_DRAM_TIMING_TABLE_46__entries_3_3_McArbDramTiming__SHIFT 0x0 1163 + #define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2_MASK 0xffffffff 1164 + #define MCARB_DRAM_TIMING_TABLE_47__entries_3_3_McArbDramTiming2__SHIFT 0x0 1165 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2_MASK 0xff 1166 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_2__SHIFT 0x0 1167 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1_MASK 0xff00 1168 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_1__SHIFT 0x8 1169 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0_MASK 0xff0000 1170 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_padding_0__SHIFT 0x10 1171 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime_MASK 0xff000000 1172 + #define MCARB_DRAM_TIMING_TABLE_48__entries_3_3_McArbBurstTime__SHIFT 0x18 1173 + #define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming_MASK 0xffffffff 1174 + #define MCARB_DRAM_TIMING_TABLE_49__entries_4_0_McArbDramTiming__SHIFT 0x0 1175 + #define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2_MASK 0xffffffff 1176 + #define MCARB_DRAM_TIMING_TABLE_50__entries_4_0_McArbDramTiming2__SHIFT 0x0 1177 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2_MASK 0xff 1178 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_2__SHIFT 0x0 1179 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1_MASK 0xff00 1180 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_1__SHIFT 0x8 1181 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0_MASK 0xff0000 1182 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_padding_0__SHIFT 0x10 1183 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime_MASK 0xff000000 1184 + #define MCARB_DRAM_TIMING_TABLE_51__entries_4_0_McArbBurstTime__SHIFT 0x18 1185 + #define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming_MASK 0xffffffff 1186 + #define MCARB_DRAM_TIMING_TABLE_52__entries_4_1_McArbDramTiming__SHIFT 0x0 1187 + #define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2_MASK 0xffffffff 1188 + #define MCARB_DRAM_TIMING_TABLE_53__entries_4_1_McArbDramTiming2__SHIFT 0x0 1189 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2_MASK 0xff 1190 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_2__SHIFT 0x0 1191 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1_MASK 0xff00 1192 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_1__SHIFT 0x8 1193 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0_MASK 0xff0000 1194 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_padding_0__SHIFT 0x10 1195 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime_MASK 0xff000000 1196 + #define MCARB_DRAM_TIMING_TABLE_54__entries_4_1_McArbBurstTime__SHIFT 0x18 1197 + #define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming_MASK 0xffffffff 1198 + #define MCARB_DRAM_TIMING_TABLE_55__entries_4_2_McArbDramTiming__SHIFT 0x0 1199 + #define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2_MASK 0xffffffff 1200 + #define MCARB_DRAM_TIMING_TABLE_56__entries_4_2_McArbDramTiming2__SHIFT 0x0 1201 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2_MASK 0xff 1202 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_2__SHIFT 0x0 1203 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1_MASK 0xff00 1204 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_1__SHIFT 0x8 1205 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0_MASK 0xff0000 1206 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_padding_0__SHIFT 0x10 1207 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime_MASK 0xff000000 1208 + #define MCARB_DRAM_TIMING_TABLE_57__entries_4_2_McArbBurstTime__SHIFT 0x18 1209 + #define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming_MASK 0xffffffff 1210 + #define MCARB_DRAM_TIMING_TABLE_58__entries_4_3_McArbDramTiming__SHIFT 0x0 1211 + #define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2_MASK 0xffffffff 1212 + #define MCARB_DRAM_TIMING_TABLE_59__entries_4_3_McArbDramTiming2__SHIFT 0x0 1213 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2_MASK 0xff 1214 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_2__SHIFT 0x0 1215 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1_MASK 0xff00 1216 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_1__SHIFT 0x8 1217 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0_MASK 0xff0000 1218 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_padding_0__SHIFT 0x10 1219 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime_MASK 0xff000000 1220 + #define MCARB_DRAM_TIMING_TABLE_60__entries_4_3_McArbBurstTime__SHIFT 0x18 1221 + #define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming_MASK 0xffffffff 1222 + #define MCARB_DRAM_TIMING_TABLE_61__entries_5_0_McArbDramTiming__SHIFT 0x0 1223 + #define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2_MASK 0xffffffff 1224 + #define MCARB_DRAM_TIMING_TABLE_62__entries_5_0_McArbDramTiming2__SHIFT 0x0 1225 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2_MASK 0xff 1226 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_2__SHIFT 0x0 1227 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1_MASK 0xff00 1228 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_1__SHIFT 0x8 1229 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0_MASK 0xff0000 1230 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_padding_0__SHIFT 0x10 1231 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime_MASK 0xff000000 1232 + #define MCARB_DRAM_TIMING_TABLE_63__entries_5_0_McArbBurstTime__SHIFT 0x18 1233 + #define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming_MASK 0xffffffff 1234 + #define MCARB_DRAM_TIMING_TABLE_64__entries_5_1_McArbDramTiming__SHIFT 0x0 1235 + #define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2_MASK 0xffffffff 1236 + #define MCARB_DRAM_TIMING_TABLE_65__entries_5_1_McArbDramTiming2__SHIFT 0x0 1237 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2_MASK 0xff 1238 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_2__SHIFT 0x0 1239 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1_MASK 0xff00 1240 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_1__SHIFT 0x8 1241 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0_MASK 0xff0000 1242 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_padding_0__SHIFT 0x10 1243 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime_MASK 0xff000000 1244 + #define MCARB_DRAM_TIMING_TABLE_66__entries_5_1_McArbBurstTime__SHIFT 0x18 1245 + #define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming_MASK 0xffffffff 1246 + #define MCARB_DRAM_TIMING_TABLE_67__entries_5_2_McArbDramTiming__SHIFT 0x0 1247 + #define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2_MASK 0xffffffff 1248 + #define MCARB_DRAM_TIMING_TABLE_68__entries_5_2_McArbDramTiming2__SHIFT 0x0 1249 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2_MASK 0xff 1250 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_2__SHIFT 0x0 1251 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1_MASK 0xff00 1252 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_1__SHIFT 0x8 1253 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0_MASK 0xff0000 1254 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_padding_0__SHIFT 0x10 1255 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime_MASK 0xff000000 1256 + #define MCARB_DRAM_TIMING_TABLE_69__entries_5_2_McArbBurstTime__SHIFT 0x18 1257 + #define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming_MASK 0xffffffff 1258 + #define MCARB_DRAM_TIMING_TABLE_70__entries_5_3_McArbDramTiming__SHIFT 0x0 1259 + #define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2_MASK 0xffffffff 1260 + #define MCARB_DRAM_TIMING_TABLE_71__entries_5_3_McArbDramTiming2__SHIFT 0x0 1261 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2_MASK 0xff 1262 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_2__SHIFT 0x0 1263 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1_MASK 0xff00 1264 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_1__SHIFT 0x8 1265 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0_MASK 0xff0000 1266 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_padding_0__SHIFT 0x10 1267 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime_MASK 0xff000000 1268 + #define MCARB_DRAM_TIMING_TABLE_72__entries_5_3_McArbBurstTime__SHIFT 0x18 1269 + #define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming_MASK 0xffffffff 1270 + #define MCARB_DRAM_TIMING_TABLE_73__entries_6_0_McArbDramTiming__SHIFT 0x0 1271 + #define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2_MASK 0xffffffff 1272 + #define MCARB_DRAM_TIMING_TABLE_74__entries_6_0_McArbDramTiming2__SHIFT 0x0 1273 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2_MASK 0xff 1274 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_2__SHIFT 0x0 1275 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1_MASK 0xff00 1276 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_1__SHIFT 0x8 1277 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0_MASK 0xff0000 1278 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_padding_0__SHIFT 0x10 1279 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime_MASK 0xff000000 1280 + #define MCARB_DRAM_TIMING_TABLE_75__entries_6_0_McArbBurstTime__SHIFT 0x18 1281 + #define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming_MASK 0xffffffff 1282 + #define MCARB_DRAM_TIMING_TABLE_76__entries_6_1_McArbDramTiming__SHIFT 0x0 1283 + #define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2_MASK 0xffffffff 1284 + #define MCARB_DRAM_TIMING_TABLE_77__entries_6_1_McArbDramTiming2__SHIFT 0x0 1285 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2_MASK 0xff 1286 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_2__SHIFT 0x0 1287 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1_MASK 0xff00 1288 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_1__SHIFT 0x8 1289 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0_MASK 0xff0000 1290 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_padding_0__SHIFT 0x10 1291 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime_MASK 0xff000000 1292 + #define MCARB_DRAM_TIMING_TABLE_78__entries_6_1_McArbBurstTime__SHIFT 0x18 1293 + #define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming_MASK 0xffffffff 1294 + #define MCARB_DRAM_TIMING_TABLE_79__entries_6_2_McArbDramTiming__SHIFT 0x0 1295 + #define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2_MASK 0xffffffff 1296 + #define MCARB_DRAM_TIMING_TABLE_80__entries_6_2_McArbDramTiming2__SHIFT 0x0 1297 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2_MASK 0xff 1298 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_2__SHIFT 0x0 1299 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1_MASK 0xff00 1300 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_1__SHIFT 0x8 1301 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0_MASK 0xff0000 1302 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_padding_0__SHIFT 0x10 1303 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime_MASK 0xff000000 1304 + #define MCARB_DRAM_TIMING_TABLE_81__entries_6_2_McArbBurstTime__SHIFT 0x18 1305 + #define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming_MASK 0xffffffff 1306 + #define MCARB_DRAM_TIMING_TABLE_82__entries_6_3_McArbDramTiming__SHIFT 0x0 1307 + #define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2_MASK 0xffffffff 1308 + #define MCARB_DRAM_TIMING_TABLE_83__entries_6_3_McArbDramTiming2__SHIFT 0x0 1309 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2_MASK 0xff 1310 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_2__SHIFT 0x0 1311 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1_MASK 0xff00 1312 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_1__SHIFT 0x8 1313 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0_MASK 0xff0000 1314 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_padding_0__SHIFT 0x10 1315 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime_MASK 0xff000000 1316 + #define MCARB_DRAM_TIMING_TABLE_84__entries_6_3_McArbBurstTime__SHIFT 0x18 1317 + #define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming_MASK 0xffffffff 1318 + #define MCARB_DRAM_TIMING_TABLE_85__entries_7_0_McArbDramTiming__SHIFT 0x0 1319 + #define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2_MASK 0xffffffff 1320 + #define MCARB_DRAM_TIMING_TABLE_86__entries_7_0_McArbDramTiming2__SHIFT 0x0 1321 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2_MASK 0xff 1322 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_2__SHIFT 0x0 1323 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1_MASK 0xff00 1324 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_1__SHIFT 0x8 1325 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0_MASK 0xff0000 1326 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_padding_0__SHIFT 0x10 1327 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime_MASK 0xff000000 1328 + #define MCARB_DRAM_TIMING_TABLE_87__entries_7_0_McArbBurstTime__SHIFT 0x18 1329 + #define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming_MASK 0xffffffff 1330 + #define MCARB_DRAM_TIMING_TABLE_88__entries_7_1_McArbDramTiming__SHIFT 0x0 1331 + #define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2_MASK 0xffffffff 1332 + #define MCARB_DRAM_TIMING_TABLE_89__entries_7_1_McArbDramTiming2__SHIFT 0x0 1333 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2_MASK 0xff 1334 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_2__SHIFT 0x0 1335 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1_MASK 0xff00 1336 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_1__SHIFT 0x8 1337 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0_MASK 0xff0000 1338 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_padding_0__SHIFT 0x10 1339 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime_MASK 0xff000000 1340 + #define MCARB_DRAM_TIMING_TABLE_90__entries_7_1_McArbBurstTime__SHIFT 0x18 1341 + #define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming_MASK 0xffffffff 1342 + #define MCARB_DRAM_TIMING_TABLE_91__entries_7_2_McArbDramTiming__SHIFT 0x0 1343 + #define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2_MASK 0xffffffff 1344 + #define MCARB_DRAM_TIMING_TABLE_92__entries_7_2_McArbDramTiming2__SHIFT 0x0 1345 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2_MASK 0xff 1346 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_2__SHIFT 0x0 1347 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1_MASK 0xff00 1348 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_1__SHIFT 0x8 1349 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0_MASK 0xff0000 1350 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_padding_0__SHIFT 0x10 1351 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime_MASK 0xff000000 1352 + #define MCARB_DRAM_TIMING_TABLE_93__entries_7_2_McArbBurstTime__SHIFT 0x18 1353 + #define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming_MASK 0xffffffff 1354 + #define MCARB_DRAM_TIMING_TABLE_94__entries_7_3_McArbDramTiming__SHIFT 0x0 1355 + #define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2_MASK 0xffffffff 1356 + #define MCARB_DRAM_TIMING_TABLE_95__entries_7_3_McArbDramTiming2__SHIFT 0x0 1357 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2_MASK 0xff 1358 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_2__SHIFT 0x0 1359 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1_MASK 0xff00 1360 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_1__SHIFT 0x8 1361 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0_MASK 0xff0000 1362 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_padding_0__SHIFT 0x10 1363 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime_MASK 0xff000000 1364 + #define MCARB_DRAM_TIMING_TABLE_96__entries_7_3_McArbBurstTime__SHIFT 0x18 1365 + #define DPM_TABLE_1__GraphicsPIDController_Ki_MASK 0xffffffff 1366 + #define DPM_TABLE_1__GraphicsPIDController_Ki__SHIFT 0x0 1367 + #define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff 1368 + #define DPM_TABLE_2__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0 1369 + #define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff 1370 + #define DPM_TABLE_3__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0 1371 + #define DPM_TABLE_4__GraphicsPIDController_StatePrecision_MASK 0xffffffff 1372 + #define DPM_TABLE_4__GraphicsPIDController_StatePrecision__SHIFT 0x0 1373 + #define DPM_TABLE_5__GraphicsPIDController_LfPrecision_MASK 0xffffffff 1374 + #define DPM_TABLE_5__GraphicsPIDController_LfPrecision__SHIFT 0x0 1375 + #define DPM_TABLE_6__GraphicsPIDController_LfOffset_MASK 0xffffffff 1376 + #define DPM_TABLE_6__GraphicsPIDController_LfOffset__SHIFT 0x0 1377 + #define DPM_TABLE_7__GraphicsPIDController_MaxState_MASK 0xffffffff 1378 + #define DPM_TABLE_7__GraphicsPIDController_MaxState__SHIFT 0x0 1379 + #define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff 1380 + #define DPM_TABLE_8__GraphicsPIDController_MaxLfFraction__SHIFT 0x0 1381 + #define DPM_TABLE_9__GraphicsPIDController_StateShift_MASK 0xffffffff 1382 + #define DPM_TABLE_9__GraphicsPIDController_StateShift__SHIFT 0x0 1383 + #define DPM_TABLE_10__MemoryPIDController_Ki_MASK 0xffffffff 1384 + #define DPM_TABLE_10__MemoryPIDController_Ki__SHIFT 0x0 1385 + #define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim_MASK 0xffffffff 1386 + #define DPM_TABLE_11__MemoryPIDController_LFWindupUpperLim__SHIFT 0x0 1387 + #define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim_MASK 0xffffffff 1388 + #define DPM_TABLE_12__MemoryPIDController_LFWindupLowerLim__SHIFT 0x0 1389 + #define DPM_TABLE_13__MemoryPIDController_StatePrecision_MASK 0xffffffff 1390 + #define DPM_TABLE_13__MemoryPIDController_StatePrecision__SHIFT 0x0 1391 + #define DPM_TABLE_14__MemoryPIDController_LfPrecision_MASK 0xffffffff 1392 + #define DPM_TABLE_14__MemoryPIDController_LfPrecision__SHIFT 0x0 1393 + #define DPM_TABLE_15__MemoryPIDController_LfOffset_MASK 0xffffffff 1394 + #define DPM_TABLE_15__MemoryPIDController_LfOffset__SHIFT 0x0 1395 + #define DPM_TABLE_16__MemoryPIDController_MaxState_MASK 0xffffffff 1396 + #define DPM_TABLE_16__MemoryPIDController_MaxState__SHIFT 0x0 1397 + #define DPM_TABLE_17__MemoryPIDController_MaxLfFraction_MASK 0xffffffff 1398 + #define DPM_TABLE_17__MemoryPIDController_MaxLfFraction__SHIFT 0x0 1399 + #define DPM_TABLE_18__MemoryPIDController_StateShift_MASK 0xffffffff 1400 + #define DPM_TABLE_18__MemoryPIDController_StateShift__SHIFT 0x0 1401 + #define DPM_TABLE_19__LinkPIDController_Ki_MASK 0xffffffff 1402 + #define DPM_TABLE_19__LinkPIDController_Ki__SHIFT 0x0 1403 + #define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim_MASK 0xffffffff 1404 + #define DPM_TABLE_20__LinkPIDController_LFWindupUpperLim__SHIFT 0x0 1405 + #define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim_MASK 0xffffffff 1406 + #define DPM_TABLE_21__LinkPIDController_LFWindupLowerLim__SHIFT 0x0 1407 + #define DPM_TABLE_22__LinkPIDController_StatePrecision_MASK 0xffffffff 1408 + #define DPM_TABLE_22__LinkPIDController_StatePrecision__SHIFT 0x0 1409 + #define DPM_TABLE_23__LinkPIDController_LfPrecision_MASK 0xffffffff 1410 + #define DPM_TABLE_23__LinkPIDController_LfPrecision__SHIFT 0x0 1411 + #define DPM_TABLE_24__LinkPIDController_LfOffset_MASK 0xffffffff 1412 + #define DPM_TABLE_24__LinkPIDController_LfOffset__SHIFT 0x0 1413 + #define DPM_TABLE_25__LinkPIDController_MaxState_MASK 0xffffffff 1414 + #define DPM_TABLE_25__LinkPIDController_MaxState__SHIFT 0x0 1415 + #define DPM_TABLE_26__LinkPIDController_MaxLfFraction_MASK 0xffffffff 1416 + #define DPM_TABLE_26__LinkPIDController_MaxLfFraction__SHIFT 0x0 1417 + #define DPM_TABLE_27__LinkPIDController_StateShift_MASK 0xffffffff 1418 + #define DPM_TABLE_27__LinkPIDController_StateShift__SHIFT 0x0 1419 + #define DPM_TABLE_28__SystemFlags_MASK 0xffffffff 1420 + #define DPM_TABLE_28__SystemFlags__SHIFT 0x0 1421 + #define DPM_TABLE_29__VRConfig_MASK 0xffffffff 1422 + #define DPM_TABLE_29__VRConfig__SHIFT 0x0 1423 + #define DPM_TABLE_30__SmioMask1_MASK 0xffffffff 1424 + #define DPM_TABLE_30__SmioMask1__SHIFT 0x0 1425 + #define DPM_TABLE_31__SmioMask2_MASK 0xffffffff 1426 + #define DPM_TABLE_31__SmioMask2__SHIFT 0x0 1427 + #define DPM_TABLE_32__SmioTable1_Pattern_0_padding_MASK 0xff 1428 + #define DPM_TABLE_32__SmioTable1_Pattern_0_padding__SHIFT 0x0 1429 + #define DPM_TABLE_32__SmioTable1_Pattern_0_Smio_MASK 0xff00 1430 + #define DPM_TABLE_32__SmioTable1_Pattern_0_Smio__SHIFT 0x8 1431 + #define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage_MASK 0xffff0000 1432 + #define DPM_TABLE_32__SmioTable1_Pattern_0_Voltage__SHIFT 0x10 1433 + #define DPM_TABLE_33__SmioTable1_Pattern_1_padding_MASK 0xff 1434 + #define DPM_TABLE_33__SmioTable1_Pattern_1_padding__SHIFT 0x0 1435 + #define DPM_TABLE_33__SmioTable1_Pattern_1_Smio_MASK 0xff00 1436 + #define DPM_TABLE_33__SmioTable1_Pattern_1_Smio__SHIFT 0x8 1437 + #define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage_MASK 0xffff0000 1438 + #define DPM_TABLE_33__SmioTable1_Pattern_1_Voltage__SHIFT 0x10 1439 + #define DPM_TABLE_34__SmioTable1_Pattern_2_padding_MASK 0xff 1440 + #define DPM_TABLE_34__SmioTable1_Pattern_2_padding__SHIFT 0x0 1441 + #define DPM_TABLE_34__SmioTable1_Pattern_2_Smio_MASK 0xff00 1442 + #define DPM_TABLE_34__SmioTable1_Pattern_2_Smio__SHIFT 0x8 1443 + #define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage_MASK 0xffff0000 1444 + #define DPM_TABLE_34__SmioTable1_Pattern_2_Voltage__SHIFT 0x10 1445 + #define DPM_TABLE_35__SmioTable1_Pattern_3_padding_MASK 0xff 1446 + #define DPM_TABLE_35__SmioTable1_Pattern_3_padding__SHIFT 0x0 1447 + #define DPM_TABLE_35__SmioTable1_Pattern_3_Smio_MASK 0xff00 1448 + #define DPM_TABLE_35__SmioTable1_Pattern_3_Smio__SHIFT 0x8 1449 + #define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage_MASK 0xffff0000 1450 + #define DPM_TABLE_35__SmioTable1_Pattern_3_Voltage__SHIFT 0x10 1451 + #define DPM_TABLE_36__SmioTable2_Pattern_0_padding_MASK 0xff 1452 + #define DPM_TABLE_36__SmioTable2_Pattern_0_padding__SHIFT 0x0 1453 + #define DPM_TABLE_36__SmioTable2_Pattern_0_Smio_MASK 0xff00 1454 + #define DPM_TABLE_36__SmioTable2_Pattern_0_Smio__SHIFT 0x8 1455 + #define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage_MASK 0xffff0000 1456 + #define DPM_TABLE_36__SmioTable2_Pattern_0_Voltage__SHIFT 0x10 1457 + #define DPM_TABLE_37__SmioTable2_Pattern_1_padding_MASK 0xff 1458 + #define DPM_TABLE_37__SmioTable2_Pattern_1_padding__SHIFT 0x0 1459 + #define DPM_TABLE_37__SmioTable2_Pattern_1_Smio_MASK 0xff00 1460 + #define DPM_TABLE_37__SmioTable2_Pattern_1_Smio__SHIFT 0x8 1461 + #define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage_MASK 0xffff0000 1462 + #define DPM_TABLE_37__SmioTable2_Pattern_1_Voltage__SHIFT 0x10 1463 + #define DPM_TABLE_38__SmioTable2_Pattern_2_padding_MASK 0xff 1464 + #define DPM_TABLE_38__SmioTable2_Pattern_2_padding__SHIFT 0x0 1465 + #define DPM_TABLE_38__SmioTable2_Pattern_2_Smio_MASK 0xff00 1466 + #define DPM_TABLE_38__SmioTable2_Pattern_2_Smio__SHIFT 0x8 1467 + #define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage_MASK 0xffff0000 1468 + #define DPM_TABLE_38__SmioTable2_Pattern_2_Voltage__SHIFT 0x10 1469 + #define DPM_TABLE_39__SmioTable2_Pattern_3_padding_MASK 0xff 1470 + #define DPM_TABLE_39__SmioTable2_Pattern_3_padding__SHIFT 0x0 1471 + #define DPM_TABLE_39__SmioTable2_Pattern_3_Smio_MASK 0xff00 1472 + #define DPM_TABLE_39__SmioTable2_Pattern_3_Smio__SHIFT 0x8 1473 + #define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage_MASK 0xffff0000 1474 + #define DPM_TABLE_39__SmioTable2_Pattern_3_Voltage__SHIFT 0x10 1475 + #define DPM_TABLE_40__VddcLevelCount_MASK 0xffffffff 1476 + #define DPM_TABLE_40__VddcLevelCount__SHIFT 0x0 1477 + #define DPM_TABLE_41__VddciLevelCount_MASK 0xffffffff 1478 + #define DPM_TABLE_41__VddciLevelCount__SHIFT 0x0 1479 + #define DPM_TABLE_42__VddGfxLevelCount_MASK 0xffffffff 1480 + #define DPM_TABLE_42__VddGfxLevelCount__SHIFT 0x0 1481 + #define DPM_TABLE_43__MvddLevelCount_MASK 0xffffffff 1482 + #define DPM_TABLE_43__MvddLevelCount__SHIFT 0x0 1483 + #define DPM_TABLE_44__VddcTable_1_MASK 0xffff 1484 + #define DPM_TABLE_44__VddcTable_1__SHIFT 0x0 1485 + #define DPM_TABLE_44__VddcTable_0_MASK 0xffff0000 1486 + #define DPM_TABLE_44__VddcTable_0__SHIFT 0x10 1487 + #define DPM_TABLE_45__VddcTable_3_MASK 0xffff 1488 + #define DPM_TABLE_45__VddcTable_3__SHIFT 0x0 1489 + #define DPM_TABLE_45__VddcTable_2_MASK 0xffff0000 1490 + #define DPM_TABLE_45__VddcTable_2__SHIFT 0x10 1491 + #define DPM_TABLE_46__VddcTable_5_MASK 0xffff 1492 + #define DPM_TABLE_46__VddcTable_5__SHIFT 0x0 1493 + #define DPM_TABLE_46__VddcTable_4_MASK 0xffff0000 1494 + #define DPM_TABLE_46__VddcTable_4__SHIFT 0x10 1495 + #define DPM_TABLE_47__VddcTable_7_MASK 0xffff 1496 + #define DPM_TABLE_47__VddcTable_7__SHIFT 0x0 1497 + #define DPM_TABLE_47__VddcTable_6_MASK 0xffff0000 1498 + #define DPM_TABLE_47__VddcTable_6__SHIFT 0x10 1499 + #define DPM_TABLE_48__VddcTable_9_MASK 0xffff 1500 + #define DPM_TABLE_48__VddcTable_9__SHIFT 0x0 1501 + #define DPM_TABLE_48__VddcTable_8_MASK 0xffff0000 1502 + #define DPM_TABLE_48__VddcTable_8__SHIFT 0x10 1503 + #define DPM_TABLE_49__VddcTable_11_MASK 0xffff 1504 + #define DPM_TABLE_49__VddcTable_11__SHIFT 0x0 1505 + #define DPM_TABLE_49__VddcTable_10_MASK 0xffff0000 1506 + #define DPM_TABLE_49__VddcTable_10__SHIFT 0x10 1507 + #define DPM_TABLE_50__VddcTable_13_MASK 0xffff 1508 + #define DPM_TABLE_50__VddcTable_13__SHIFT 0x0 1509 + #define DPM_TABLE_50__VddcTable_12_MASK 0xffff0000 1510 + #define DPM_TABLE_50__VddcTable_12__SHIFT 0x10 1511 + #define DPM_TABLE_51__VddcTable_15_MASK 0xffff 1512 + #define DPM_TABLE_51__VddcTable_15__SHIFT 0x0 1513 + #define DPM_TABLE_51__VddcTable_14_MASK 0xffff0000 1514 + #define DPM_TABLE_51__VddcTable_14__SHIFT 0x10 1515 + #define DPM_TABLE_52__VddGfxTable_1_MASK 0xffff 1516 + #define DPM_TABLE_52__VddGfxTable_1__SHIFT 0x0 1517 + #define DPM_TABLE_52__VddGfxTable_0_MASK 0xffff0000 1518 + #define DPM_TABLE_52__VddGfxTable_0__SHIFT 0x10 1519 + #define DPM_TABLE_53__VddGfxTable_3_MASK 0xffff 1520 + #define DPM_TABLE_53__VddGfxTable_3__SHIFT 0x0 1521 + #define DPM_TABLE_53__VddGfxTable_2_MASK 0xffff0000 1522 + #define DPM_TABLE_53__VddGfxTable_2__SHIFT 0x10 1523 + #define DPM_TABLE_54__VddGfxTable_5_MASK 0xffff 1524 + #define DPM_TABLE_54__VddGfxTable_5__SHIFT 0x0 1525 + #define DPM_TABLE_54__VddGfxTable_4_MASK 0xffff0000 1526 + #define DPM_TABLE_54__VddGfxTable_4__SHIFT 0x10 1527 + #define DPM_TABLE_55__VddGfxTable_7_MASK 0xffff 1528 + #define DPM_TABLE_55__VddGfxTable_7__SHIFT 0x0 1529 + #define DPM_TABLE_55__VddGfxTable_6_MASK 0xffff0000 1530 + #define DPM_TABLE_55__VddGfxTable_6__SHIFT 0x10 1531 + #define DPM_TABLE_56__VddGfxTable_9_MASK 0xffff 1532 + #define DPM_TABLE_56__VddGfxTable_9__SHIFT 0x0 1533 + #define DPM_TABLE_56__VddGfxTable_8_MASK 0xffff0000 1534 + #define DPM_TABLE_56__VddGfxTable_8__SHIFT 0x10 1535 + #define DPM_TABLE_57__VddGfxTable_11_MASK 0xffff 1536 + #define DPM_TABLE_57__VddGfxTable_11__SHIFT 0x0 1537 + #define DPM_TABLE_57__VddGfxTable_10_MASK 0xffff0000 1538 + #define DPM_TABLE_57__VddGfxTable_10__SHIFT 0x10 1539 + #define DPM_TABLE_58__VddGfxTable_13_MASK 0xffff 1540 + #define DPM_TABLE_58__VddGfxTable_13__SHIFT 0x0 1541 + #define DPM_TABLE_58__VddGfxTable_12_MASK 0xffff0000 1542 + #define DPM_TABLE_58__VddGfxTable_12__SHIFT 0x10 1543 + #define DPM_TABLE_59__VddGfxTable_15_MASK 0xffff 1544 + #define DPM_TABLE_59__VddGfxTable_15__SHIFT 0x0 1545 + #define DPM_TABLE_59__VddGfxTable_14_MASK 0xffff0000 1546 + #define DPM_TABLE_59__VddGfxTable_14__SHIFT 0x10 1547 + #define DPM_TABLE_60__VddciTable_1_MASK 0xffff 1548 + #define DPM_TABLE_60__VddciTable_1__SHIFT 0x0 1549 + #define DPM_TABLE_60__VddciTable_0_MASK 0xffff0000 1550 + #define DPM_TABLE_60__VddciTable_0__SHIFT 0x10 1551 + #define DPM_TABLE_61__VddciTable_3_MASK 0xffff 1552 + #define DPM_TABLE_61__VddciTable_3__SHIFT 0x0 1553 + #define DPM_TABLE_61__VddciTable_2_MASK 0xffff0000 1554 + #define DPM_TABLE_61__VddciTable_2__SHIFT 0x10 1555 + #define DPM_TABLE_62__VddciTable_5_MASK 0xffff 1556 + #define DPM_TABLE_62__VddciTable_5__SHIFT 0x0 1557 + #define DPM_TABLE_62__VddciTable_4_MASK 0xffff0000 1558 + #define DPM_TABLE_62__VddciTable_4__SHIFT 0x10 1559 + #define DPM_TABLE_63__VddciTable_7_MASK 0xffff 1560 + #define DPM_TABLE_63__VddciTable_7__SHIFT 0x0 1561 + #define DPM_TABLE_63__VddciTable_6_MASK 0xffff0000 1562 + #define DPM_TABLE_63__VddciTable_6__SHIFT 0x10 1563 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_3_MASK 0xff 1564 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_3__SHIFT 0x0 1565 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_2_MASK 0xff00 1566 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_2__SHIFT 0x8 1567 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_1_MASK 0xff0000 1568 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_1__SHIFT 0x10 1569 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_0_MASK 0xff000000 1570 + #define DPM_TABLE_64__BapmVddGfxVidHiSidd_0__SHIFT 0x18 1571 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_7_MASK 0xff 1572 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_7__SHIFT 0x0 1573 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_6_MASK 0xff00 1574 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_6__SHIFT 0x8 1575 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_5_MASK 0xff0000 1576 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_5__SHIFT 0x10 1577 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_4_MASK 0xff000000 1578 + #define DPM_TABLE_65__BapmVddGfxVidHiSidd_4__SHIFT 0x18 1579 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_11_MASK 0xff 1580 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_11__SHIFT 0x0 1581 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_10_MASK 0xff00 1582 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_10__SHIFT 0x8 1583 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_9_MASK 0xff0000 1584 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_9__SHIFT 0x10 1585 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_8_MASK 0xff000000 1586 + #define DPM_TABLE_66__BapmVddGfxVidHiSidd_8__SHIFT 0x18 1587 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_15_MASK 0xff 1588 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_15__SHIFT 0x0 1589 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_14_MASK 0xff00 1590 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_14__SHIFT 0x8 1591 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_13_MASK 0xff0000 1592 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_13__SHIFT 0x10 1593 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_12_MASK 0xff000000 1594 + #define DPM_TABLE_67__BapmVddGfxVidHiSidd_12__SHIFT 0x18 1595 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_3_MASK 0xff 1596 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_3__SHIFT 0x0 1597 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_2_MASK 0xff00 1598 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_2__SHIFT 0x8 1599 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_1_MASK 0xff0000 1600 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_1__SHIFT 0x10 1601 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_0_MASK 0xff000000 1602 + #define DPM_TABLE_68__BapmVddGfxVidLoSidd_0__SHIFT 0x18 1603 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_7_MASK 0xff 1604 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_7__SHIFT 0x0 1605 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_6_MASK 0xff00 1606 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_6__SHIFT 0x8 1607 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_5_MASK 0xff0000 1608 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_5__SHIFT 0x10 1609 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_4_MASK 0xff000000 1610 + #define DPM_TABLE_69__BapmVddGfxVidLoSidd_4__SHIFT 0x18 1611 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_11_MASK 0xff 1612 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_11__SHIFT 0x0 1613 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_10_MASK 0xff00 1614 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_10__SHIFT 0x8 1615 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_9_MASK 0xff0000 1616 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_9__SHIFT 0x10 1617 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_8_MASK 0xff000000 1618 + #define DPM_TABLE_70__BapmVddGfxVidLoSidd_8__SHIFT 0x18 1619 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_15_MASK 0xff 1620 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_15__SHIFT 0x0 1621 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_14_MASK 0xff00 1622 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_14__SHIFT 0x8 1623 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_13_MASK 0xff0000 1624 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_13__SHIFT 0x10 1625 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_12_MASK 0xff000000 1626 + #define DPM_TABLE_71__BapmVddGfxVidLoSidd_12__SHIFT 0x18 1627 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3_MASK 0xff 1628 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_3__SHIFT 0x0 1629 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2_MASK 0xff00 1630 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_2__SHIFT 0x8 1631 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1_MASK 0xff0000 1632 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_1__SHIFT 0x10 1633 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0_MASK 0xff000000 1634 + #define DPM_TABLE_72__BapmVddGfxVidHiSidd2_0__SHIFT 0x18 1635 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7_MASK 0xff 1636 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_7__SHIFT 0x0 1637 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6_MASK 0xff00 1638 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_6__SHIFT 0x8 1639 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5_MASK 0xff0000 1640 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_5__SHIFT 0x10 1641 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4_MASK 0xff000000 1642 + #define DPM_TABLE_73__BapmVddGfxVidHiSidd2_4__SHIFT 0x18 1643 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11_MASK 0xff 1644 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_11__SHIFT 0x0 1645 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10_MASK 0xff00 1646 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_10__SHIFT 0x8 1647 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9_MASK 0xff0000 1648 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_9__SHIFT 0x10 1649 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8_MASK 0xff000000 1650 + #define DPM_TABLE_74__BapmVddGfxVidHiSidd2_8__SHIFT 0x18 1651 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15_MASK 0xff 1652 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_15__SHIFT 0x0 1653 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14_MASK 0xff00 1654 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_14__SHIFT 0x8 1655 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13_MASK 0xff0000 1656 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_13__SHIFT 0x10 1657 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12_MASK 0xff000000 1658 + #define DPM_TABLE_75__BapmVddGfxVidHiSidd2_12__SHIFT 0x18 1659 + #define DPM_TABLE_76__BapmVddcVidHiSidd_3_MASK 0xff 1660 + #define DPM_TABLE_76__BapmVddcVidHiSidd_3__SHIFT 0x0 1661 + #define DPM_TABLE_76__BapmVddcVidHiSidd_2_MASK 0xff00 1662 + #define DPM_TABLE_76__BapmVddcVidHiSidd_2__SHIFT 0x8 1663 + #define DPM_TABLE_76__BapmVddcVidHiSidd_1_MASK 0xff0000 1664 + #define DPM_TABLE_76__BapmVddcVidHiSidd_1__SHIFT 0x10 1665 + #define DPM_TABLE_76__BapmVddcVidHiSidd_0_MASK 0xff000000 1666 + #define DPM_TABLE_76__BapmVddcVidHiSidd_0__SHIFT 0x18 1667 + #define DPM_TABLE_77__BapmVddcVidHiSidd_7_MASK 0xff 1668 + #define DPM_TABLE_77__BapmVddcVidHiSidd_7__SHIFT 0x0 1669 + #define DPM_TABLE_77__BapmVddcVidHiSidd_6_MASK 0xff00 1670 + #define DPM_TABLE_77__BapmVddcVidHiSidd_6__SHIFT 0x8 1671 + #define DPM_TABLE_77__BapmVddcVidHiSidd_5_MASK 0xff0000 1672 + #define DPM_TABLE_77__BapmVddcVidHiSidd_5__SHIFT 0x10 1673 + #define DPM_TABLE_77__BapmVddcVidHiSidd_4_MASK 0xff000000 1674 + #define DPM_TABLE_77__BapmVddcVidHiSidd_4__SHIFT 0x18 1675 + #define DPM_TABLE_78__BapmVddcVidHiSidd_11_MASK 0xff 1676 + #define DPM_TABLE_78__BapmVddcVidHiSidd_11__SHIFT 0x0 1677 + #define DPM_TABLE_78__BapmVddcVidHiSidd_10_MASK 0xff00 1678 + #define DPM_TABLE_78__BapmVddcVidHiSidd_10__SHIFT 0x8 1679 + #define DPM_TABLE_78__BapmVddcVidHiSidd_9_MASK 0xff0000 1680 + #define DPM_TABLE_78__BapmVddcVidHiSidd_9__SHIFT 0x10 1681 + #define DPM_TABLE_78__BapmVddcVidHiSidd_8_MASK 0xff000000 1682 + #define DPM_TABLE_78__BapmVddcVidHiSidd_8__SHIFT 0x18 1683 + #define DPM_TABLE_79__BapmVddcVidHiSidd_15_MASK 0xff 1684 + #define DPM_TABLE_79__BapmVddcVidHiSidd_15__SHIFT 0x0 1685 + #define DPM_TABLE_79__BapmVddcVidHiSidd_14_MASK 0xff00 1686 + #define DPM_TABLE_79__BapmVddcVidHiSidd_14__SHIFT 0x8 1687 + #define DPM_TABLE_79__BapmVddcVidHiSidd_13_MASK 0xff0000 1688 + #define DPM_TABLE_79__BapmVddcVidHiSidd_13__SHIFT 0x10 1689 + #define DPM_TABLE_79__BapmVddcVidHiSidd_12_MASK 0xff000000 1690 + #define DPM_TABLE_79__BapmVddcVidHiSidd_12__SHIFT 0x18 1691 + #define DPM_TABLE_80__BapmVddcVidLoSidd_3_MASK 0xff 1692 + #define DPM_TABLE_80__BapmVddcVidLoSidd_3__SHIFT 0x0 1693 + #define DPM_TABLE_80__BapmVddcVidLoSidd_2_MASK 0xff00 1694 + #define DPM_TABLE_80__BapmVddcVidLoSidd_2__SHIFT 0x8 1695 + #define DPM_TABLE_80__BapmVddcVidLoSidd_1_MASK 0xff0000 1696 + #define DPM_TABLE_80__BapmVddcVidLoSidd_1__SHIFT 0x10 1697 + #define DPM_TABLE_80__BapmVddcVidLoSidd_0_MASK 0xff000000 1698 + #define DPM_TABLE_80__BapmVddcVidLoSidd_0__SHIFT 0x18 1699 + #define DPM_TABLE_81__BapmVddcVidLoSidd_7_MASK 0xff 1700 + #define DPM_TABLE_81__BapmVddcVidLoSidd_7__SHIFT 0x0 1701 + #define DPM_TABLE_81__BapmVddcVidLoSidd_6_MASK 0xff00 1702 + #define DPM_TABLE_81__BapmVddcVidLoSidd_6__SHIFT 0x8 1703 + #define DPM_TABLE_81__BapmVddcVidLoSidd_5_MASK 0xff0000 1704 + #define DPM_TABLE_81__BapmVddcVidLoSidd_5__SHIFT 0x10 1705 + #define DPM_TABLE_81__BapmVddcVidLoSidd_4_MASK 0xff000000 1706 + #define DPM_TABLE_81__BapmVddcVidLoSidd_4__SHIFT 0x18 1707 + #define DPM_TABLE_82__BapmVddcVidLoSidd_11_MASK 0xff 1708 + #define DPM_TABLE_82__BapmVddcVidLoSidd_11__SHIFT 0x0 1709 + #define DPM_TABLE_82__BapmVddcVidLoSidd_10_MASK 0xff00 1710 + #define DPM_TABLE_82__BapmVddcVidLoSidd_10__SHIFT 0x8 1711 + #define DPM_TABLE_82__BapmVddcVidLoSidd_9_MASK 0xff0000 1712 + #define DPM_TABLE_82__BapmVddcVidLoSidd_9__SHIFT 0x10 1713 + #define DPM_TABLE_82__BapmVddcVidLoSidd_8_MASK 0xff000000 1714 + #define DPM_TABLE_82__BapmVddcVidLoSidd_8__SHIFT 0x18 1715 + #define DPM_TABLE_83__BapmVddcVidLoSidd_15_MASK 0xff 1716 + #define DPM_TABLE_83__BapmVddcVidLoSidd_15__SHIFT 0x0 1717 + #define DPM_TABLE_83__BapmVddcVidLoSidd_14_MASK 0xff00 1718 + #define DPM_TABLE_83__BapmVddcVidLoSidd_14__SHIFT 0x8 1719 + #define DPM_TABLE_83__BapmVddcVidLoSidd_13_MASK 0xff0000 1720 + #define DPM_TABLE_83__BapmVddcVidLoSidd_13__SHIFT 0x10 1721 + #define DPM_TABLE_83__BapmVddcVidLoSidd_12_MASK 0xff000000 1722 + #define DPM_TABLE_83__BapmVddcVidLoSidd_12__SHIFT 0x18 1723 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_3_MASK 0xff 1724 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_3__SHIFT 0x0 1725 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_2_MASK 0xff00 1726 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_2__SHIFT 0x8 1727 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_1_MASK 0xff0000 1728 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_1__SHIFT 0x10 1729 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_0_MASK 0xff000000 1730 + #define DPM_TABLE_84__BapmVddcVidHiSidd2_0__SHIFT 0x18 1731 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_7_MASK 0xff 1732 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_7__SHIFT 0x0 1733 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_6_MASK 0xff00 1734 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_6__SHIFT 0x8 1735 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_5_MASK 0xff0000 1736 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_5__SHIFT 0x10 1737 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_4_MASK 0xff000000 1738 + #define DPM_TABLE_85__BapmVddcVidHiSidd2_4__SHIFT 0x18 1739 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_11_MASK 0xff 1740 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_11__SHIFT 0x0 1741 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_10_MASK 0xff00 1742 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_10__SHIFT 0x8 1743 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_9_MASK 0xff0000 1744 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_9__SHIFT 0x10 1745 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_8_MASK 0xff000000 1746 + #define DPM_TABLE_86__BapmVddcVidHiSidd2_8__SHIFT 0x18 1747 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_15_MASK 0xff 1748 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_15__SHIFT 0x0 1749 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_14_MASK 0xff00 1750 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_14__SHIFT 0x8 1751 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_13_MASK 0xff0000 1752 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_13__SHIFT 0x10 1753 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_12_MASK 0xff000000 1754 + #define DPM_TABLE_87__BapmVddcVidHiSidd2_12__SHIFT 0x18 1755 + #define DPM_TABLE_88__MasterDeepSleepControl_MASK 0xff 1756 + #define DPM_TABLE_88__MasterDeepSleepControl__SHIFT 0x0 1757 + #define DPM_TABLE_88__LinkLevelCount_MASK 0xff00 1758 + #define DPM_TABLE_88__LinkLevelCount__SHIFT 0x8 1759 + #define DPM_TABLE_88__MemoryDpmLevelCount_MASK 0xff0000 1760 + #define DPM_TABLE_88__MemoryDpmLevelCount__SHIFT 0x10 1761 + #define DPM_TABLE_88__GraphicsDpmLevelCount_MASK 0xff000000 1762 + #define DPM_TABLE_88__GraphicsDpmLevelCount__SHIFT 0x18 1763 + #define DPM_TABLE_89__SamuLevelCount_MASK 0xff 1764 + #define DPM_TABLE_89__SamuLevelCount__SHIFT 0x0 1765 + #define DPM_TABLE_89__AcpLevelCount_MASK 0xff00 1766 + #define DPM_TABLE_89__AcpLevelCount__SHIFT 0x8 1767 + #define DPM_TABLE_89__VceLevelCount_MASK 0xff0000 1768 + #define DPM_TABLE_89__VceLevelCount__SHIFT 0x10 1769 + #define DPM_TABLE_89__UvdLevelCount_MASK 0xff000000 1770 + #define DPM_TABLE_89__UvdLevelCount__SHIFT 0x18 1771 + #define DPM_TABLE_90__Reserved_0_MASK 0xff 1772 + #define DPM_TABLE_90__Reserved_0__SHIFT 0x0 1773 + #define DPM_TABLE_90__ThermOutMode_MASK 0xff00 1774 + #define DPM_TABLE_90__ThermOutMode__SHIFT 0x8 1775 + #define DPM_TABLE_90__ThermOutPolarity_MASK 0xff0000 1776 + #define DPM_TABLE_90__ThermOutPolarity__SHIFT 0x10 1777 + #define DPM_TABLE_90__ThermOutGpio_MASK 0xff000000 1778 + #define DPM_TABLE_90__ThermOutGpio__SHIFT 0x18 1779 + #define DPM_TABLE_91__Reserved_0_MASK 0xffffffff 1780 + #define DPM_TABLE_91__Reserved_0__SHIFT 0x0 1781 + #define DPM_TABLE_92__Reserved_1_MASK 0xffffffff 1782 + #define DPM_TABLE_92__Reserved_1__SHIFT 0x0 1783 + #define DPM_TABLE_93__Reserved_2_MASK 0xffffffff 1784 + #define DPM_TABLE_93__Reserved_2__SHIFT 0x0 1785 + #define DPM_TABLE_94__Reserved_3_MASK 0xffffffff 1786 + #define DPM_TABLE_94__Reserved_3__SHIFT 0x0 1787 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases_MASK 0xff 1788 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Phases__SHIFT 0x0 1789 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx_MASK 0xff00 1790 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_VddGfx__SHIFT 0x8 1791 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci_MASK 0xff0000 1792 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddci__SHIFT 0x10 1793 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc_MASK 0xff000000 1794 + #define DPM_TABLE_95__GraphicsLevel_0_MinVoltage_Vddc__SHIFT 0x18 1795 + #define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff 1796 + #define DPM_TABLE_96__GraphicsLevel_0_SclkFrequency__SHIFT 0x0 1797 + #define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel_MASK 0xffff 1798 + #define DPM_TABLE_97__GraphicsLevel_0_ActivityLevel__SHIFT 0x0 1799 + #define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId_MASK 0xff0000 1800 + #define DPM_TABLE_97__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x10 1801 + #define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel_MASK 0xff000000 1802 + #define DPM_TABLE_97__GraphicsLevel_0_pcieDpmLevel__SHIFT 0x18 1803 + #define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3_MASK 0xffffffff 1804 + #define DPM_TABLE_98__GraphicsLevel_0_CgSpllFuncCntl3__SHIFT 0x0 1805 + #define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4_MASK 0xffffffff 1806 + #define DPM_TABLE_99__GraphicsLevel_0_CgSpllFuncCntl4__SHIFT 0x0 1807 + #define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum_MASK 0xffffffff 1808 + #define DPM_TABLE_100__GraphicsLevel_0_SpllSpreadSpectrum__SHIFT 0x0 1809 + #define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2_MASK 0xffffffff 1810 + #define DPM_TABLE_101__GraphicsLevel_0_SpllSpreadSpectrum2__SHIFT 0x0 1811 + #define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm_MASK 0xffffffff 1812 + #define DPM_TABLE_102__GraphicsLevel_0_CcPwrDynRm__SHIFT 0x0 1813 + #define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1_MASK 0xffffffff 1814 + #define DPM_TABLE_103__GraphicsLevel_0_CcPwrDynRm1__SHIFT 0x0 1815 + #define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle_MASK 0xff 1816 + #define DPM_TABLE_104__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x0 1817 + #define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity_MASK 0xff00 1818 + #define DPM_TABLE_104__GraphicsLevel_0_EnabledForActivity__SHIFT 0x8 1819 + #define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark_MASK 0xff0000 1820 + #define DPM_TABLE_104__GraphicsLevel_0_DisplayWatermark__SHIFT 0x10 1821 + #define DPM_TABLE_104__GraphicsLevel_0_SclkDid_MASK 0xff000000 1822 + #define DPM_TABLE_104__GraphicsLevel_0_SclkDid__SHIFT 0x18 1823 + #define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle_MASK 0xff 1824 + #define DPM_TABLE_105__GraphicsLevel_0_PowerThrottle__SHIFT 0x0 1825 + #define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst_MASK 0xff00 1826 + #define DPM_TABLE_105__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x8 1827 + #define DPM_TABLE_105__GraphicsLevel_0_DownHyst_MASK 0xff0000 1828 + #define DPM_TABLE_105__GraphicsLevel_0_DownHyst__SHIFT 0x10 1829 + #define DPM_TABLE_105__GraphicsLevel_0_UpHyst_MASK 0xff000000 1830 + #define DPM_TABLE_105__GraphicsLevel_0_UpHyst__SHIFT 0x18 1831 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases_MASK 0xff 1832 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Phases__SHIFT 0x0 1833 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx_MASK 0xff00 1834 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_VddGfx__SHIFT 0x8 1835 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci_MASK 0xff0000 1836 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddci__SHIFT 0x10 1837 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc_MASK 0xff000000 1838 + #define DPM_TABLE_106__GraphicsLevel_1_MinVoltage_Vddc__SHIFT 0x18 1839 + #define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff 1840 + #define DPM_TABLE_107__GraphicsLevel_1_SclkFrequency__SHIFT 0x0 1841 + #define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel_MASK 0xffff 1842 + #define DPM_TABLE_108__GraphicsLevel_1_ActivityLevel__SHIFT 0x0 1843 + #define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId_MASK 0xff0000 1844 + #define DPM_TABLE_108__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x10 1845 + #define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel_MASK 0xff000000 1846 + #define DPM_TABLE_108__GraphicsLevel_1_pcieDpmLevel__SHIFT 0x18 1847 + #define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3_MASK 0xffffffff 1848 + #define DPM_TABLE_109__GraphicsLevel_1_CgSpllFuncCntl3__SHIFT 0x0 1849 + #define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4_MASK 0xffffffff 1850 + #define DPM_TABLE_110__GraphicsLevel_1_CgSpllFuncCntl4__SHIFT 0x0 1851 + #define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum_MASK 0xffffffff 1852 + #define DPM_TABLE_111__GraphicsLevel_1_SpllSpreadSpectrum__SHIFT 0x0 1853 + #define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2_MASK 0xffffffff 1854 + #define DPM_TABLE_112__GraphicsLevel_1_SpllSpreadSpectrum2__SHIFT 0x0 1855 + #define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm_MASK 0xffffffff 1856 + #define DPM_TABLE_113__GraphicsLevel_1_CcPwrDynRm__SHIFT 0x0 1857 + #define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1_MASK 0xffffffff 1858 + #define DPM_TABLE_114__GraphicsLevel_1_CcPwrDynRm1__SHIFT 0x0 1859 + #define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle_MASK 0xff 1860 + #define DPM_TABLE_115__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x0 1861 + #define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity_MASK 0xff00 1862 + #define DPM_TABLE_115__GraphicsLevel_1_EnabledForActivity__SHIFT 0x8 1863 + #define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark_MASK 0xff0000 1864 + #define DPM_TABLE_115__GraphicsLevel_1_DisplayWatermark__SHIFT 0x10 1865 + #define DPM_TABLE_115__GraphicsLevel_1_SclkDid_MASK 0xff000000 1866 + #define DPM_TABLE_115__GraphicsLevel_1_SclkDid__SHIFT 0x18 1867 + #define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle_MASK 0xff 1868 + #define DPM_TABLE_116__GraphicsLevel_1_PowerThrottle__SHIFT 0x0 1869 + #define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst_MASK 0xff00 1870 + #define DPM_TABLE_116__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x8 1871 + #define DPM_TABLE_116__GraphicsLevel_1_DownHyst_MASK 0xff0000 1872 + #define DPM_TABLE_116__GraphicsLevel_1_DownHyst__SHIFT 0x10 1873 + #define DPM_TABLE_116__GraphicsLevel_1_UpHyst_MASK 0xff000000 1874 + #define DPM_TABLE_116__GraphicsLevel_1_UpHyst__SHIFT 0x18 1875 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases_MASK 0xff 1876 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Phases__SHIFT 0x0 1877 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx_MASK 0xff00 1878 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_VddGfx__SHIFT 0x8 1879 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci_MASK 0xff0000 1880 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddci__SHIFT 0x10 1881 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc_MASK 0xff000000 1882 + #define DPM_TABLE_117__GraphicsLevel_2_MinVoltage_Vddc__SHIFT 0x18 1883 + #define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff 1884 + #define DPM_TABLE_118__GraphicsLevel_2_SclkFrequency__SHIFT 0x0 1885 + #define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel_MASK 0xffff 1886 + #define DPM_TABLE_119__GraphicsLevel_2_ActivityLevel__SHIFT 0x0 1887 + #define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId_MASK 0xff0000 1888 + #define DPM_TABLE_119__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x10 1889 + #define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel_MASK 0xff000000 1890 + #define DPM_TABLE_119__GraphicsLevel_2_pcieDpmLevel__SHIFT 0x18 1891 + #define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3_MASK 0xffffffff 1892 + #define DPM_TABLE_120__GraphicsLevel_2_CgSpllFuncCntl3__SHIFT 0x0 1893 + #define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4_MASK 0xffffffff 1894 + #define DPM_TABLE_121__GraphicsLevel_2_CgSpllFuncCntl4__SHIFT 0x0 1895 + #define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum_MASK 0xffffffff 1896 + #define DPM_TABLE_122__GraphicsLevel_2_SpllSpreadSpectrum__SHIFT 0x0 1897 + #define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2_MASK 0xffffffff 1898 + #define DPM_TABLE_123__GraphicsLevel_2_SpllSpreadSpectrum2__SHIFT 0x0 1899 + #define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm_MASK 0xffffffff 1900 + #define DPM_TABLE_124__GraphicsLevel_2_CcPwrDynRm__SHIFT 0x0 1901 + #define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1_MASK 0xffffffff 1902 + #define DPM_TABLE_125__GraphicsLevel_2_CcPwrDynRm1__SHIFT 0x0 1903 + #define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle_MASK 0xff 1904 + #define DPM_TABLE_126__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x0 1905 + #define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity_MASK 0xff00 1906 + #define DPM_TABLE_126__GraphicsLevel_2_EnabledForActivity__SHIFT 0x8 1907 + #define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark_MASK 0xff0000 1908 + #define DPM_TABLE_126__GraphicsLevel_2_DisplayWatermark__SHIFT 0x10 1909 + #define DPM_TABLE_126__GraphicsLevel_2_SclkDid_MASK 0xff000000 1910 + #define DPM_TABLE_126__GraphicsLevel_2_SclkDid__SHIFT 0x18 1911 + #define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle_MASK 0xff 1912 + #define DPM_TABLE_127__GraphicsLevel_2_PowerThrottle__SHIFT 0x0 1913 + #define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst_MASK 0xff00 1914 + #define DPM_TABLE_127__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x8 1915 + #define DPM_TABLE_127__GraphicsLevel_2_DownHyst_MASK 0xff0000 1916 + #define DPM_TABLE_127__GraphicsLevel_2_DownHyst__SHIFT 0x10 1917 + #define DPM_TABLE_127__GraphicsLevel_2_UpHyst_MASK 0xff000000 1918 + #define DPM_TABLE_127__GraphicsLevel_2_UpHyst__SHIFT 0x18 1919 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases_MASK 0xff 1920 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Phases__SHIFT 0x0 1921 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx_MASK 0xff00 1922 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_VddGfx__SHIFT 0x8 1923 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci_MASK 0xff0000 1924 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddci__SHIFT 0x10 1925 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc_MASK 0xff000000 1926 + #define DPM_TABLE_128__GraphicsLevel_3_MinVoltage_Vddc__SHIFT 0x18 1927 + #define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff 1928 + #define DPM_TABLE_129__GraphicsLevel_3_SclkFrequency__SHIFT 0x0 1929 + #define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel_MASK 0xffff 1930 + #define DPM_TABLE_130__GraphicsLevel_3_ActivityLevel__SHIFT 0x0 1931 + #define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId_MASK 0xff0000 1932 + #define DPM_TABLE_130__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x10 1933 + #define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel_MASK 0xff000000 1934 + #define DPM_TABLE_130__GraphicsLevel_3_pcieDpmLevel__SHIFT 0x18 1935 + #define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3_MASK 0xffffffff 1936 + #define DPM_TABLE_131__GraphicsLevel_3_CgSpllFuncCntl3__SHIFT 0x0 1937 + #define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4_MASK 0xffffffff 1938 + #define DPM_TABLE_132__GraphicsLevel_3_CgSpllFuncCntl4__SHIFT 0x0 1939 + #define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum_MASK 0xffffffff 1940 + #define DPM_TABLE_133__GraphicsLevel_3_SpllSpreadSpectrum__SHIFT 0x0 1941 + #define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2_MASK 0xffffffff 1942 + #define DPM_TABLE_134__GraphicsLevel_3_SpllSpreadSpectrum2__SHIFT 0x0 1943 + #define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm_MASK 0xffffffff 1944 + #define DPM_TABLE_135__GraphicsLevel_3_CcPwrDynRm__SHIFT 0x0 1945 + #define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1_MASK 0xffffffff 1946 + #define DPM_TABLE_136__GraphicsLevel_3_CcPwrDynRm1__SHIFT 0x0 1947 + #define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle_MASK 0xff 1948 + #define DPM_TABLE_137__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x0 1949 + #define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity_MASK 0xff00 1950 + #define DPM_TABLE_137__GraphicsLevel_3_EnabledForActivity__SHIFT 0x8 1951 + #define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark_MASK 0xff0000 1952 + #define DPM_TABLE_137__GraphicsLevel_3_DisplayWatermark__SHIFT 0x10 1953 + #define DPM_TABLE_137__GraphicsLevel_3_SclkDid_MASK 0xff000000 1954 + #define DPM_TABLE_137__GraphicsLevel_3_SclkDid__SHIFT 0x18 1955 + #define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle_MASK 0xff 1956 + #define DPM_TABLE_138__GraphicsLevel_3_PowerThrottle__SHIFT 0x0 1957 + #define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst_MASK 0xff00 1958 + #define DPM_TABLE_138__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x8 1959 + #define DPM_TABLE_138__GraphicsLevel_3_DownHyst_MASK 0xff0000 1960 + #define DPM_TABLE_138__GraphicsLevel_3_DownHyst__SHIFT 0x10 1961 + #define DPM_TABLE_138__GraphicsLevel_3_UpHyst_MASK 0xff000000 1962 + #define DPM_TABLE_138__GraphicsLevel_3_UpHyst__SHIFT 0x18 1963 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases_MASK 0xff 1964 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Phases__SHIFT 0x0 1965 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx_MASK 0xff00 1966 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_VddGfx__SHIFT 0x8 1967 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci_MASK 0xff0000 1968 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddci__SHIFT 0x10 1969 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc_MASK 0xff000000 1970 + #define DPM_TABLE_139__GraphicsLevel_4_MinVoltage_Vddc__SHIFT 0x18 1971 + #define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff 1972 + #define DPM_TABLE_140__GraphicsLevel_4_SclkFrequency__SHIFT 0x0 1973 + #define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel_MASK 0xffff 1974 + #define DPM_TABLE_141__GraphicsLevel_4_ActivityLevel__SHIFT 0x0 1975 + #define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId_MASK 0xff0000 1976 + #define DPM_TABLE_141__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x10 1977 + #define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel_MASK 0xff000000 1978 + #define DPM_TABLE_141__GraphicsLevel_4_pcieDpmLevel__SHIFT 0x18 1979 + #define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3_MASK 0xffffffff 1980 + #define DPM_TABLE_142__GraphicsLevel_4_CgSpllFuncCntl3__SHIFT 0x0 1981 + #define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4_MASK 0xffffffff 1982 + #define DPM_TABLE_143__GraphicsLevel_4_CgSpllFuncCntl4__SHIFT 0x0 1983 + #define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum_MASK 0xffffffff 1984 + #define DPM_TABLE_144__GraphicsLevel_4_SpllSpreadSpectrum__SHIFT 0x0 1985 + #define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2_MASK 0xffffffff 1986 + #define DPM_TABLE_145__GraphicsLevel_4_SpllSpreadSpectrum2__SHIFT 0x0 1987 + #define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm_MASK 0xffffffff 1988 + #define DPM_TABLE_146__GraphicsLevel_4_CcPwrDynRm__SHIFT 0x0 1989 + #define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1_MASK 0xffffffff 1990 + #define DPM_TABLE_147__GraphicsLevel_4_CcPwrDynRm1__SHIFT 0x0 1991 + #define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle_MASK 0xff 1992 + #define DPM_TABLE_148__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x0 1993 + #define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity_MASK 0xff00 1994 + #define DPM_TABLE_148__GraphicsLevel_4_EnabledForActivity__SHIFT 0x8 1995 + #define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark_MASK 0xff0000 1996 + #define DPM_TABLE_148__GraphicsLevel_4_DisplayWatermark__SHIFT 0x10 1997 + #define DPM_TABLE_148__GraphicsLevel_4_SclkDid_MASK 0xff000000 1998 + #define DPM_TABLE_148__GraphicsLevel_4_SclkDid__SHIFT 0x18 1999 + #define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle_MASK 0xff 2000 + #define DPM_TABLE_149__GraphicsLevel_4_PowerThrottle__SHIFT 0x0 2001 + #define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst_MASK 0xff00 2002 + #define DPM_TABLE_149__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x8 2003 + #define DPM_TABLE_149__GraphicsLevel_4_DownHyst_MASK 0xff0000 2004 + #define DPM_TABLE_149__GraphicsLevel_4_DownHyst__SHIFT 0x10 2005 + #define DPM_TABLE_149__GraphicsLevel_4_UpHyst_MASK 0xff000000 2006 + #define DPM_TABLE_149__GraphicsLevel_4_UpHyst__SHIFT 0x18 2007 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases_MASK 0xff 2008 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Phases__SHIFT 0x0 2009 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx_MASK 0xff00 2010 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2011 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci_MASK 0xff0000 2012 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddci__SHIFT 0x10 2013 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc_MASK 0xff000000 2014 + #define DPM_TABLE_150__GraphicsLevel_5_MinVoltage_Vddc__SHIFT 0x18 2015 + #define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff 2016 + #define DPM_TABLE_151__GraphicsLevel_5_SclkFrequency__SHIFT 0x0 2017 + #define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel_MASK 0xffff 2018 + #define DPM_TABLE_152__GraphicsLevel_5_ActivityLevel__SHIFT 0x0 2019 + #define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId_MASK 0xff0000 2020 + #define DPM_TABLE_152__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x10 2021 + #define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel_MASK 0xff000000 2022 + #define DPM_TABLE_152__GraphicsLevel_5_pcieDpmLevel__SHIFT 0x18 2023 + #define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3_MASK 0xffffffff 2024 + #define DPM_TABLE_153__GraphicsLevel_5_CgSpllFuncCntl3__SHIFT 0x0 2025 + #define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4_MASK 0xffffffff 2026 + #define DPM_TABLE_154__GraphicsLevel_5_CgSpllFuncCntl4__SHIFT 0x0 2027 + #define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum_MASK 0xffffffff 2028 + #define DPM_TABLE_155__GraphicsLevel_5_SpllSpreadSpectrum__SHIFT 0x0 2029 + #define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2_MASK 0xffffffff 2030 + #define DPM_TABLE_156__GraphicsLevel_5_SpllSpreadSpectrum2__SHIFT 0x0 2031 + #define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm_MASK 0xffffffff 2032 + #define DPM_TABLE_157__GraphicsLevel_5_CcPwrDynRm__SHIFT 0x0 2033 + #define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1_MASK 0xffffffff 2034 + #define DPM_TABLE_158__GraphicsLevel_5_CcPwrDynRm1__SHIFT 0x0 2035 + #define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle_MASK 0xff 2036 + #define DPM_TABLE_159__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x0 2037 + #define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity_MASK 0xff00 2038 + #define DPM_TABLE_159__GraphicsLevel_5_EnabledForActivity__SHIFT 0x8 2039 + #define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark_MASK 0xff0000 2040 + #define DPM_TABLE_159__GraphicsLevel_5_DisplayWatermark__SHIFT 0x10 2041 + #define DPM_TABLE_159__GraphicsLevel_5_SclkDid_MASK 0xff000000 2042 + #define DPM_TABLE_159__GraphicsLevel_5_SclkDid__SHIFT 0x18 2043 + #define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle_MASK 0xff 2044 + #define DPM_TABLE_160__GraphicsLevel_5_PowerThrottle__SHIFT 0x0 2045 + #define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst_MASK 0xff00 2046 + #define DPM_TABLE_160__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x8 2047 + #define DPM_TABLE_160__GraphicsLevel_5_DownHyst_MASK 0xff0000 2048 + #define DPM_TABLE_160__GraphicsLevel_5_DownHyst__SHIFT 0x10 2049 + #define DPM_TABLE_160__GraphicsLevel_5_UpHyst_MASK 0xff000000 2050 + #define DPM_TABLE_160__GraphicsLevel_5_UpHyst__SHIFT 0x18 2051 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases_MASK 0xff 2052 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Phases__SHIFT 0x0 2053 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx_MASK 0xff00 2054 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2055 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci_MASK 0xff0000 2056 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddci__SHIFT 0x10 2057 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc_MASK 0xff000000 2058 + #define DPM_TABLE_161__GraphicsLevel_6_MinVoltage_Vddc__SHIFT 0x18 2059 + #define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff 2060 + #define DPM_TABLE_162__GraphicsLevel_6_SclkFrequency__SHIFT 0x0 2061 + #define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel_MASK 0xffff 2062 + #define DPM_TABLE_163__GraphicsLevel_6_ActivityLevel__SHIFT 0x0 2063 + #define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId_MASK 0xff0000 2064 + #define DPM_TABLE_163__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x10 2065 + #define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel_MASK 0xff000000 2066 + #define DPM_TABLE_163__GraphicsLevel_6_pcieDpmLevel__SHIFT 0x18 2067 + #define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3_MASK 0xffffffff 2068 + #define DPM_TABLE_164__GraphicsLevel_6_CgSpllFuncCntl3__SHIFT 0x0 2069 + #define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4_MASK 0xffffffff 2070 + #define DPM_TABLE_165__GraphicsLevel_6_CgSpllFuncCntl4__SHIFT 0x0 2071 + #define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum_MASK 0xffffffff 2072 + #define DPM_TABLE_166__GraphicsLevel_6_SpllSpreadSpectrum__SHIFT 0x0 2073 + #define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2_MASK 0xffffffff 2074 + #define DPM_TABLE_167__GraphicsLevel_6_SpllSpreadSpectrum2__SHIFT 0x0 2075 + #define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm_MASK 0xffffffff 2076 + #define DPM_TABLE_168__GraphicsLevel_6_CcPwrDynRm__SHIFT 0x0 2077 + #define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1_MASK 0xffffffff 2078 + #define DPM_TABLE_169__GraphicsLevel_6_CcPwrDynRm1__SHIFT 0x0 2079 + #define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle_MASK 0xff 2080 + #define DPM_TABLE_170__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x0 2081 + #define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity_MASK 0xff00 2082 + #define DPM_TABLE_170__GraphicsLevel_6_EnabledForActivity__SHIFT 0x8 2083 + #define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark_MASK 0xff0000 2084 + #define DPM_TABLE_170__GraphicsLevel_6_DisplayWatermark__SHIFT 0x10 2085 + #define DPM_TABLE_170__GraphicsLevel_6_SclkDid_MASK 0xff000000 2086 + #define DPM_TABLE_170__GraphicsLevel_6_SclkDid__SHIFT 0x18 2087 + #define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle_MASK 0xff 2088 + #define DPM_TABLE_171__GraphicsLevel_6_PowerThrottle__SHIFT 0x0 2089 + #define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst_MASK 0xff00 2090 + #define DPM_TABLE_171__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x8 2091 + #define DPM_TABLE_171__GraphicsLevel_6_DownHyst_MASK 0xff0000 2092 + #define DPM_TABLE_171__GraphicsLevel_6_DownHyst__SHIFT 0x10 2093 + #define DPM_TABLE_171__GraphicsLevel_6_UpHyst_MASK 0xff000000 2094 + #define DPM_TABLE_171__GraphicsLevel_6_UpHyst__SHIFT 0x18 2095 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases_MASK 0xff 2096 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Phases__SHIFT 0x0 2097 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx_MASK 0xff00 2098 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2099 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci_MASK 0xff0000 2100 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddci__SHIFT 0x10 2101 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc_MASK 0xff000000 2102 + #define DPM_TABLE_172__GraphicsLevel_7_MinVoltage_Vddc__SHIFT 0x18 2103 + #define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff 2104 + #define DPM_TABLE_173__GraphicsLevel_7_SclkFrequency__SHIFT 0x0 2105 + #define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel_MASK 0xffff 2106 + #define DPM_TABLE_174__GraphicsLevel_7_ActivityLevel__SHIFT 0x0 2107 + #define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId_MASK 0xff0000 2108 + #define DPM_TABLE_174__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x10 2109 + #define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel_MASK 0xff000000 2110 + #define DPM_TABLE_174__GraphicsLevel_7_pcieDpmLevel__SHIFT 0x18 2111 + #define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3_MASK 0xffffffff 2112 + #define DPM_TABLE_175__GraphicsLevel_7_CgSpllFuncCntl3__SHIFT 0x0 2113 + #define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4_MASK 0xffffffff 2114 + #define DPM_TABLE_176__GraphicsLevel_7_CgSpllFuncCntl4__SHIFT 0x0 2115 + #define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum_MASK 0xffffffff 2116 + #define DPM_TABLE_177__GraphicsLevel_7_SpllSpreadSpectrum__SHIFT 0x0 2117 + #define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2_MASK 0xffffffff 2118 + #define DPM_TABLE_178__GraphicsLevel_7_SpllSpreadSpectrum2__SHIFT 0x0 2119 + #define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm_MASK 0xffffffff 2120 + #define DPM_TABLE_179__GraphicsLevel_7_CcPwrDynRm__SHIFT 0x0 2121 + #define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1_MASK 0xffffffff 2122 + #define DPM_TABLE_180__GraphicsLevel_7_CcPwrDynRm1__SHIFT 0x0 2123 + #define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle_MASK 0xff 2124 + #define DPM_TABLE_181__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x0 2125 + #define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity_MASK 0xff00 2126 + #define DPM_TABLE_181__GraphicsLevel_7_EnabledForActivity__SHIFT 0x8 2127 + #define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark_MASK 0xff0000 2128 + #define DPM_TABLE_181__GraphicsLevel_7_DisplayWatermark__SHIFT 0x10 2129 + #define DPM_TABLE_181__GraphicsLevel_7_SclkDid_MASK 0xff000000 2130 + #define DPM_TABLE_181__GraphicsLevel_7_SclkDid__SHIFT 0x18 2131 + #define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle_MASK 0xff 2132 + #define DPM_TABLE_182__GraphicsLevel_7_PowerThrottle__SHIFT 0x0 2133 + #define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst_MASK 0xff00 2134 + #define DPM_TABLE_182__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x8 2135 + #define DPM_TABLE_182__GraphicsLevel_7_DownHyst_MASK 0xff0000 2136 + #define DPM_TABLE_182__GraphicsLevel_7_DownHyst__SHIFT 0x10 2137 + #define DPM_TABLE_182__GraphicsLevel_7_UpHyst_MASK 0xff000000 2138 + #define DPM_TABLE_182__GraphicsLevel_7_UpHyst__SHIFT 0x18 2139 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases_MASK 0xff 2140 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Phases__SHIFT 0x0 2141 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx_MASK 0xff00 2142 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_VddGfx__SHIFT 0x8 2143 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci_MASK 0xff0000 2144 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddci__SHIFT 0x10 2145 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc_MASK 0xff000000 2146 + #define DPM_TABLE_183__MemoryACPILevel_MinVoltage_Vddc__SHIFT 0x18 2147 + #define DPM_TABLE_184__MemoryACPILevel_MinMvdd_MASK 0xffffffff 2148 + #define DPM_TABLE_184__MemoryACPILevel_MinMvdd__SHIFT 0x0 2149 + #define DPM_TABLE_185__MemoryACPILevel_MclkFrequency_MASK 0xffffffff 2150 + #define DPM_TABLE_185__MemoryACPILevel_MclkFrequency__SHIFT 0x0 2151 + #define DPM_TABLE_186__MemoryACPILevel_EnabledForActivity_MASK 0xff 2152 + #define DPM_TABLE_186__MemoryACPILevel_EnabledForActivity__SHIFT 0x0 2153 + #define DPM_TABLE_186__MemoryACPILevel_EnabledForThrottle_MASK 0xff00 2154 + #define DPM_TABLE_186__MemoryACPILevel_EnabledForThrottle__SHIFT 0x8 2155 + #define DPM_TABLE_186__MemoryACPILevel_FreqRange_MASK 0xff0000 2156 + #define DPM_TABLE_186__MemoryACPILevel_FreqRange__SHIFT 0x10 2157 + #define DPM_TABLE_186__MemoryACPILevel_StutterEnable_MASK 0xff000000 2158 + #define DPM_TABLE_186__MemoryACPILevel_StutterEnable__SHIFT 0x18 2159 + #define DPM_TABLE_187__MemoryACPILevel_padding_MASK 0xff 2160 + #define DPM_TABLE_187__MemoryACPILevel_padding__SHIFT 0x0 2161 + #define DPM_TABLE_187__MemoryACPILevel_VoltageDownHyst_MASK 0xff00 2162 + #define DPM_TABLE_187__MemoryACPILevel_VoltageDownHyst__SHIFT 0x8 2163 + #define DPM_TABLE_187__MemoryACPILevel_DownHyst_MASK 0xff0000 2164 + #define DPM_TABLE_187__MemoryACPILevel_DownHyst__SHIFT 0x10 2165 + #define DPM_TABLE_187__MemoryACPILevel_UpHyst_MASK 0xff000000 2166 + #define DPM_TABLE_187__MemoryACPILevel_UpHyst__SHIFT 0x18 2167 + #define DPM_TABLE_188__MemoryACPILevel_MclkDivider_MASK 0xff 2168 + #define DPM_TABLE_188__MemoryACPILevel_MclkDivider__SHIFT 0x0 2169 + #define DPM_TABLE_188__MemoryACPILevel_DisplayWatermark_MASK 0xff00 2170 + #define DPM_TABLE_188__MemoryACPILevel_DisplayWatermark__SHIFT 0x8 2171 + #define DPM_TABLE_188__MemoryACPILevel_ActivityLevel_MASK 0xffff0000 2172 + #define DPM_TABLE_188__MemoryACPILevel_ActivityLevel__SHIFT 0x10 2173 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Phases_MASK 0xff 2174 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Phases__SHIFT 0x0 2175 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_VddGfx_MASK 0xff00 2176 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2177 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddci_MASK 0xff0000 2178 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddci__SHIFT 0x10 2179 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddc_MASK 0xff000000 2180 + #define DPM_TABLE_189__MemoryLevel_0_MinVoltage_Vddc__SHIFT 0x18 2181 + #define DPM_TABLE_190__MemoryLevel_0_MinMvdd_MASK 0xffffffff 2182 + #define DPM_TABLE_190__MemoryLevel_0_MinMvdd__SHIFT 0x0 2183 + #define DPM_TABLE_191__MemoryLevel_0_MclkFrequency_MASK 0xffffffff 2184 + #define DPM_TABLE_191__MemoryLevel_0_MclkFrequency__SHIFT 0x0 2185 + #define DPM_TABLE_192__MemoryLevel_0_EnabledForActivity_MASK 0xff 2186 + #define DPM_TABLE_192__MemoryLevel_0_EnabledForActivity__SHIFT 0x0 2187 + #define DPM_TABLE_192__MemoryLevel_0_EnabledForThrottle_MASK 0xff00 2188 + #define DPM_TABLE_192__MemoryLevel_0_EnabledForThrottle__SHIFT 0x8 2189 + #define DPM_TABLE_192__MemoryLevel_0_FreqRange_MASK 0xff0000 2190 + #define DPM_TABLE_192__MemoryLevel_0_FreqRange__SHIFT 0x10 2191 + #define DPM_TABLE_192__MemoryLevel_0_StutterEnable_MASK 0xff000000 2192 + #define DPM_TABLE_192__MemoryLevel_0_StutterEnable__SHIFT 0x18 2193 + #define DPM_TABLE_193__MemoryLevel_0_padding_MASK 0xff 2194 + #define DPM_TABLE_193__MemoryLevel_0_padding__SHIFT 0x0 2195 + #define DPM_TABLE_193__MemoryLevel_0_VoltageDownHyst_MASK 0xff00 2196 + #define DPM_TABLE_193__MemoryLevel_0_VoltageDownHyst__SHIFT 0x8 2197 + #define DPM_TABLE_193__MemoryLevel_0_DownHyst_MASK 0xff0000 2198 + #define DPM_TABLE_193__MemoryLevel_0_DownHyst__SHIFT 0x10 2199 + #define DPM_TABLE_193__MemoryLevel_0_UpHyst_MASK 0xff000000 2200 + #define DPM_TABLE_193__MemoryLevel_0_UpHyst__SHIFT 0x18 2201 + #define DPM_TABLE_194__MemoryLevel_0_MclkDivider_MASK 0xff 2202 + #define DPM_TABLE_194__MemoryLevel_0_MclkDivider__SHIFT 0x0 2203 + #define DPM_TABLE_194__MemoryLevel_0_DisplayWatermark_MASK 0xff00 2204 + #define DPM_TABLE_194__MemoryLevel_0_DisplayWatermark__SHIFT 0x8 2205 + #define DPM_TABLE_194__MemoryLevel_0_ActivityLevel_MASK 0xffff0000 2206 + #define DPM_TABLE_194__MemoryLevel_0_ActivityLevel__SHIFT 0x10 2207 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Phases_MASK 0xff 2208 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Phases__SHIFT 0x0 2209 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_VddGfx_MASK 0xff00 2210 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2211 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddci_MASK 0xff0000 2212 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddci__SHIFT 0x10 2213 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddc_MASK 0xff000000 2214 + #define DPM_TABLE_195__MemoryLevel_1_MinVoltage_Vddc__SHIFT 0x18 2215 + #define DPM_TABLE_196__MemoryLevel_1_MinMvdd_MASK 0xffffffff 2216 + #define DPM_TABLE_196__MemoryLevel_1_MinMvdd__SHIFT 0x0 2217 + #define DPM_TABLE_197__MemoryLevel_1_MclkFrequency_MASK 0xffffffff 2218 + #define DPM_TABLE_197__MemoryLevel_1_MclkFrequency__SHIFT 0x0 2219 + #define DPM_TABLE_198__MemoryLevel_1_EnabledForActivity_MASK 0xff 2220 + #define DPM_TABLE_198__MemoryLevel_1_EnabledForActivity__SHIFT 0x0 2221 + #define DPM_TABLE_198__MemoryLevel_1_EnabledForThrottle_MASK 0xff00 2222 + #define DPM_TABLE_198__MemoryLevel_1_EnabledForThrottle__SHIFT 0x8 2223 + #define DPM_TABLE_198__MemoryLevel_1_FreqRange_MASK 0xff0000 2224 + #define DPM_TABLE_198__MemoryLevel_1_FreqRange__SHIFT 0x10 2225 + #define DPM_TABLE_198__MemoryLevel_1_StutterEnable_MASK 0xff000000 2226 + #define DPM_TABLE_198__MemoryLevel_1_StutterEnable__SHIFT 0x18 2227 + #define DPM_TABLE_199__MemoryLevel_1_padding_MASK 0xff 2228 + #define DPM_TABLE_199__MemoryLevel_1_padding__SHIFT 0x0 2229 + #define DPM_TABLE_199__MemoryLevel_1_VoltageDownHyst_MASK 0xff00 2230 + #define DPM_TABLE_199__MemoryLevel_1_VoltageDownHyst__SHIFT 0x8 2231 + #define DPM_TABLE_199__MemoryLevel_1_DownHyst_MASK 0xff0000 2232 + #define DPM_TABLE_199__MemoryLevel_1_DownHyst__SHIFT 0x10 2233 + #define DPM_TABLE_199__MemoryLevel_1_UpHyst_MASK 0xff000000 2234 + #define DPM_TABLE_199__MemoryLevel_1_UpHyst__SHIFT 0x18 2235 + #define DPM_TABLE_200__MemoryLevel_1_MclkDivider_MASK 0xff 2236 + #define DPM_TABLE_200__MemoryLevel_1_MclkDivider__SHIFT 0x0 2237 + #define DPM_TABLE_200__MemoryLevel_1_DisplayWatermark_MASK 0xff00 2238 + #define DPM_TABLE_200__MemoryLevel_1_DisplayWatermark__SHIFT 0x8 2239 + #define DPM_TABLE_200__MemoryLevel_1_ActivityLevel_MASK 0xffff0000 2240 + #define DPM_TABLE_200__MemoryLevel_1_ActivityLevel__SHIFT 0x10 2241 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Phases_MASK 0xff 2242 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Phases__SHIFT 0x0 2243 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_VddGfx_MASK 0xff00 2244 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2245 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddci_MASK 0xff0000 2246 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddci__SHIFT 0x10 2247 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddc_MASK 0xff000000 2248 + #define DPM_TABLE_201__MemoryLevel_2_MinVoltage_Vddc__SHIFT 0x18 2249 + #define DPM_TABLE_202__MemoryLevel_2_MinMvdd_MASK 0xffffffff 2250 + #define DPM_TABLE_202__MemoryLevel_2_MinMvdd__SHIFT 0x0 2251 + #define DPM_TABLE_203__MemoryLevel_2_MclkFrequency_MASK 0xffffffff 2252 + #define DPM_TABLE_203__MemoryLevel_2_MclkFrequency__SHIFT 0x0 2253 + #define DPM_TABLE_204__MemoryLevel_2_EnabledForActivity_MASK 0xff 2254 + #define DPM_TABLE_204__MemoryLevel_2_EnabledForActivity__SHIFT 0x0 2255 + #define DPM_TABLE_204__MemoryLevel_2_EnabledForThrottle_MASK 0xff00 2256 + #define DPM_TABLE_204__MemoryLevel_2_EnabledForThrottle__SHIFT 0x8 2257 + #define DPM_TABLE_204__MemoryLevel_2_FreqRange_MASK 0xff0000 2258 + #define DPM_TABLE_204__MemoryLevel_2_FreqRange__SHIFT 0x10 2259 + #define DPM_TABLE_204__MemoryLevel_2_StutterEnable_MASK 0xff000000 2260 + #define DPM_TABLE_204__MemoryLevel_2_StutterEnable__SHIFT 0x18 2261 + #define DPM_TABLE_205__MemoryLevel_2_padding_MASK 0xff 2262 + #define DPM_TABLE_205__MemoryLevel_2_padding__SHIFT 0x0 2263 + #define DPM_TABLE_205__MemoryLevel_2_VoltageDownHyst_MASK 0xff00 2264 + #define DPM_TABLE_205__MemoryLevel_2_VoltageDownHyst__SHIFT 0x8 2265 + #define DPM_TABLE_205__MemoryLevel_2_DownHyst_MASK 0xff0000 2266 + #define DPM_TABLE_205__MemoryLevel_2_DownHyst__SHIFT 0x10 2267 + #define DPM_TABLE_205__MemoryLevel_2_UpHyst_MASK 0xff000000 2268 + #define DPM_TABLE_205__MemoryLevel_2_UpHyst__SHIFT 0x18 2269 + #define DPM_TABLE_206__MemoryLevel_2_MclkDivider_MASK 0xff 2270 + #define DPM_TABLE_206__MemoryLevel_2_MclkDivider__SHIFT 0x0 2271 + #define DPM_TABLE_206__MemoryLevel_2_DisplayWatermark_MASK 0xff00 2272 + #define DPM_TABLE_206__MemoryLevel_2_DisplayWatermark__SHIFT 0x8 2273 + #define DPM_TABLE_206__MemoryLevel_2_ActivityLevel_MASK 0xffff0000 2274 + #define DPM_TABLE_206__MemoryLevel_2_ActivityLevel__SHIFT 0x10 2275 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Phases_MASK 0xff 2276 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Phases__SHIFT 0x0 2277 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_VddGfx_MASK 0xff00 2278 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2279 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddci_MASK 0xff0000 2280 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddci__SHIFT 0x10 2281 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddc_MASK 0xff000000 2282 + #define DPM_TABLE_207__MemoryLevel_3_MinVoltage_Vddc__SHIFT 0x18 2283 + #define DPM_TABLE_208__MemoryLevel_3_MinMvdd_MASK 0xffffffff 2284 + #define DPM_TABLE_208__MemoryLevel_3_MinMvdd__SHIFT 0x0 2285 + #define DPM_TABLE_209__MemoryLevel_3_MclkFrequency_MASK 0xffffffff 2286 + #define DPM_TABLE_209__MemoryLevel_3_MclkFrequency__SHIFT 0x0 2287 + #define DPM_TABLE_210__MemoryLevel_3_EnabledForActivity_MASK 0xff 2288 + #define DPM_TABLE_210__MemoryLevel_3_EnabledForActivity__SHIFT 0x0 2289 + #define DPM_TABLE_210__MemoryLevel_3_EnabledForThrottle_MASK 0xff00 2290 + #define DPM_TABLE_210__MemoryLevel_3_EnabledForThrottle__SHIFT 0x8 2291 + #define DPM_TABLE_210__MemoryLevel_3_FreqRange_MASK 0xff0000 2292 + #define DPM_TABLE_210__MemoryLevel_3_FreqRange__SHIFT 0x10 2293 + #define DPM_TABLE_210__MemoryLevel_3_StutterEnable_MASK 0xff000000 2294 + #define DPM_TABLE_210__MemoryLevel_3_StutterEnable__SHIFT 0x18 2295 + #define DPM_TABLE_211__MemoryLevel_3_padding_MASK 0xff 2296 + #define DPM_TABLE_211__MemoryLevel_3_padding__SHIFT 0x0 2297 + #define DPM_TABLE_211__MemoryLevel_3_VoltageDownHyst_MASK 0xff00 2298 + #define DPM_TABLE_211__MemoryLevel_3_VoltageDownHyst__SHIFT 0x8 2299 + #define DPM_TABLE_211__MemoryLevel_3_DownHyst_MASK 0xff0000 2300 + #define DPM_TABLE_211__MemoryLevel_3_DownHyst__SHIFT 0x10 2301 + #define DPM_TABLE_211__MemoryLevel_3_UpHyst_MASK 0xff000000 2302 + #define DPM_TABLE_211__MemoryLevel_3_UpHyst__SHIFT 0x18 2303 + #define DPM_TABLE_212__MemoryLevel_3_MclkDivider_MASK 0xff 2304 + #define DPM_TABLE_212__MemoryLevel_3_MclkDivider__SHIFT 0x0 2305 + #define DPM_TABLE_212__MemoryLevel_3_DisplayWatermark_MASK 0xff00 2306 + #define DPM_TABLE_212__MemoryLevel_3_DisplayWatermark__SHIFT 0x8 2307 + #define DPM_TABLE_212__MemoryLevel_3_ActivityLevel_MASK 0xffff0000 2308 + #define DPM_TABLE_212__MemoryLevel_3_ActivityLevel__SHIFT 0x10 2309 + #define DPM_TABLE_213__LinkLevel_0_SPC_MASK 0xff 2310 + #define DPM_TABLE_213__LinkLevel_0_SPC__SHIFT 0x0 2311 + #define DPM_TABLE_213__LinkLevel_0_EnabledForActivity_MASK 0xff00 2312 + #define DPM_TABLE_213__LinkLevel_0_EnabledForActivity__SHIFT 0x8 2313 + #define DPM_TABLE_213__LinkLevel_0_PcieLaneCount_MASK 0xff0000 2314 + #define DPM_TABLE_213__LinkLevel_0_PcieLaneCount__SHIFT 0x10 2315 + #define DPM_TABLE_213__LinkLevel_0_PcieGenSpeed_MASK 0xff000000 2316 + #define DPM_TABLE_213__LinkLevel_0_PcieGenSpeed__SHIFT 0x18 2317 + #define DPM_TABLE_214__LinkLevel_0_DownThreshold_MASK 0xffffffff 2318 + #define DPM_TABLE_214__LinkLevel_0_DownThreshold__SHIFT 0x0 2319 + #define DPM_TABLE_215__LinkLevel_0_UpThreshold_MASK 0xffffffff 2320 + #define DPM_TABLE_215__LinkLevel_0_UpThreshold__SHIFT 0x0 2321 + #define DPM_TABLE_216__LinkLevel_0_Reserved_MASK 0xffffffff 2322 + #define DPM_TABLE_216__LinkLevel_0_Reserved__SHIFT 0x0 2323 + #define DPM_TABLE_217__LinkLevel_1_SPC_MASK 0xff 2324 + #define DPM_TABLE_217__LinkLevel_1_SPC__SHIFT 0x0 2325 + #define DPM_TABLE_217__LinkLevel_1_EnabledForActivity_MASK 0xff00 2326 + #define DPM_TABLE_217__LinkLevel_1_EnabledForActivity__SHIFT 0x8 2327 + #define DPM_TABLE_217__LinkLevel_1_PcieLaneCount_MASK 0xff0000 2328 + #define DPM_TABLE_217__LinkLevel_1_PcieLaneCount__SHIFT 0x10 2329 + #define DPM_TABLE_217__LinkLevel_1_PcieGenSpeed_MASK 0xff000000 2330 + #define DPM_TABLE_217__LinkLevel_1_PcieGenSpeed__SHIFT 0x18 2331 + #define DPM_TABLE_218__LinkLevel_1_DownThreshold_MASK 0xffffffff 2332 + #define DPM_TABLE_218__LinkLevel_1_DownThreshold__SHIFT 0x0 2333 + #define DPM_TABLE_219__LinkLevel_1_UpThreshold_MASK 0xffffffff 2334 + #define DPM_TABLE_219__LinkLevel_1_UpThreshold__SHIFT 0x0 2335 + #define DPM_TABLE_220__LinkLevel_1_Reserved_MASK 0xffffffff 2336 + #define DPM_TABLE_220__LinkLevel_1_Reserved__SHIFT 0x0 2337 + #define DPM_TABLE_221__LinkLevel_2_SPC_MASK 0xff 2338 + #define DPM_TABLE_221__LinkLevel_2_SPC__SHIFT 0x0 2339 + #define DPM_TABLE_221__LinkLevel_2_EnabledForActivity_MASK 0xff00 2340 + #define DPM_TABLE_221__LinkLevel_2_EnabledForActivity__SHIFT 0x8 2341 + #define DPM_TABLE_221__LinkLevel_2_PcieLaneCount_MASK 0xff0000 2342 + #define DPM_TABLE_221__LinkLevel_2_PcieLaneCount__SHIFT 0x10 2343 + #define DPM_TABLE_221__LinkLevel_2_PcieGenSpeed_MASK 0xff000000 2344 + #define DPM_TABLE_221__LinkLevel_2_PcieGenSpeed__SHIFT 0x18 2345 + #define DPM_TABLE_222__LinkLevel_2_DownThreshold_MASK 0xffffffff 2346 + #define DPM_TABLE_222__LinkLevel_2_DownThreshold__SHIFT 0x0 2347 + #define DPM_TABLE_223__LinkLevel_2_UpThreshold_MASK 0xffffffff 2348 + #define DPM_TABLE_223__LinkLevel_2_UpThreshold__SHIFT 0x0 2349 + #define DPM_TABLE_224__LinkLevel_2_Reserved_MASK 0xffffffff 2350 + #define DPM_TABLE_224__LinkLevel_2_Reserved__SHIFT 0x0 2351 + #define DPM_TABLE_225__LinkLevel_3_SPC_MASK 0xff 2352 + #define DPM_TABLE_225__LinkLevel_3_SPC__SHIFT 0x0 2353 + #define DPM_TABLE_225__LinkLevel_3_EnabledForActivity_MASK 0xff00 2354 + #define DPM_TABLE_225__LinkLevel_3_EnabledForActivity__SHIFT 0x8 2355 + #define DPM_TABLE_225__LinkLevel_3_PcieLaneCount_MASK 0xff0000 2356 + #define DPM_TABLE_225__LinkLevel_3_PcieLaneCount__SHIFT 0x10 2357 + #define DPM_TABLE_225__LinkLevel_3_PcieGenSpeed_MASK 0xff000000 2358 + #define DPM_TABLE_225__LinkLevel_3_PcieGenSpeed__SHIFT 0x18 2359 + #define DPM_TABLE_226__LinkLevel_3_DownThreshold_MASK 0xffffffff 2360 + #define DPM_TABLE_226__LinkLevel_3_DownThreshold__SHIFT 0x0 2361 + #define DPM_TABLE_227__LinkLevel_3_UpThreshold_MASK 0xffffffff 2362 + #define DPM_TABLE_227__LinkLevel_3_UpThreshold__SHIFT 0x0 2363 + #define DPM_TABLE_228__LinkLevel_3_Reserved_MASK 0xffffffff 2364 + #define DPM_TABLE_228__LinkLevel_3_Reserved__SHIFT 0x0 2365 + #define DPM_TABLE_229__LinkLevel_4_SPC_MASK 0xff 2366 + #define DPM_TABLE_229__LinkLevel_4_SPC__SHIFT 0x0 2367 + #define DPM_TABLE_229__LinkLevel_4_EnabledForActivity_MASK 0xff00 2368 + #define DPM_TABLE_229__LinkLevel_4_EnabledForActivity__SHIFT 0x8 2369 + #define DPM_TABLE_229__LinkLevel_4_PcieLaneCount_MASK 0xff0000 2370 + #define DPM_TABLE_229__LinkLevel_4_PcieLaneCount__SHIFT 0x10 2371 + #define DPM_TABLE_229__LinkLevel_4_PcieGenSpeed_MASK 0xff000000 2372 + #define DPM_TABLE_229__LinkLevel_4_PcieGenSpeed__SHIFT 0x18 2373 + #define DPM_TABLE_230__LinkLevel_4_DownThreshold_MASK 0xffffffff 2374 + #define DPM_TABLE_230__LinkLevel_4_DownThreshold__SHIFT 0x0 2375 + #define DPM_TABLE_231__LinkLevel_4_UpThreshold_MASK 0xffffffff 2376 + #define DPM_TABLE_231__LinkLevel_4_UpThreshold__SHIFT 0x0 2377 + #define DPM_TABLE_232__LinkLevel_4_Reserved_MASK 0xffffffff 2378 + #define DPM_TABLE_232__LinkLevel_4_Reserved__SHIFT 0x0 2379 + #define DPM_TABLE_233__LinkLevel_5_SPC_MASK 0xff 2380 + #define DPM_TABLE_233__LinkLevel_5_SPC__SHIFT 0x0 2381 + #define DPM_TABLE_233__LinkLevel_5_EnabledForActivity_MASK 0xff00 2382 + #define DPM_TABLE_233__LinkLevel_5_EnabledForActivity__SHIFT 0x8 2383 + #define DPM_TABLE_233__LinkLevel_5_PcieLaneCount_MASK 0xff0000 2384 + #define DPM_TABLE_233__LinkLevel_5_PcieLaneCount__SHIFT 0x10 2385 + #define DPM_TABLE_233__LinkLevel_5_PcieGenSpeed_MASK 0xff000000 2386 + #define DPM_TABLE_233__LinkLevel_5_PcieGenSpeed__SHIFT 0x18 2387 + #define DPM_TABLE_234__LinkLevel_5_DownThreshold_MASK 0xffffffff 2388 + #define DPM_TABLE_234__LinkLevel_5_DownThreshold__SHIFT 0x0 2389 + #define DPM_TABLE_235__LinkLevel_5_UpThreshold_MASK 0xffffffff 2390 + #define DPM_TABLE_235__LinkLevel_5_UpThreshold__SHIFT 0x0 2391 + #define DPM_TABLE_236__LinkLevel_5_Reserved_MASK 0xffffffff 2392 + #define DPM_TABLE_236__LinkLevel_5_Reserved__SHIFT 0x0 2393 + #define DPM_TABLE_237__LinkLevel_6_SPC_MASK 0xff 2394 + #define DPM_TABLE_237__LinkLevel_6_SPC__SHIFT 0x0 2395 + #define DPM_TABLE_237__LinkLevel_6_EnabledForActivity_MASK 0xff00 2396 + #define DPM_TABLE_237__LinkLevel_6_EnabledForActivity__SHIFT 0x8 2397 + #define DPM_TABLE_237__LinkLevel_6_PcieLaneCount_MASK 0xff0000 2398 + #define DPM_TABLE_237__LinkLevel_6_PcieLaneCount__SHIFT 0x10 2399 + #define DPM_TABLE_237__LinkLevel_6_PcieGenSpeed_MASK 0xff000000 2400 + #define DPM_TABLE_237__LinkLevel_6_PcieGenSpeed__SHIFT 0x18 2401 + #define DPM_TABLE_238__LinkLevel_6_DownThreshold_MASK 0xffffffff 2402 + #define DPM_TABLE_238__LinkLevel_6_DownThreshold__SHIFT 0x0 2403 + #define DPM_TABLE_239__LinkLevel_6_UpThreshold_MASK 0xffffffff 2404 + #define DPM_TABLE_239__LinkLevel_6_UpThreshold__SHIFT 0x0 2405 + #define DPM_TABLE_240__LinkLevel_6_Reserved_MASK 0xffffffff 2406 + #define DPM_TABLE_240__LinkLevel_6_Reserved__SHIFT 0x0 2407 + #define DPM_TABLE_241__LinkLevel_7_SPC_MASK 0xff 2408 + #define DPM_TABLE_241__LinkLevel_7_SPC__SHIFT 0x0 2409 + #define DPM_TABLE_241__LinkLevel_7_EnabledForActivity_MASK 0xff00 2410 + #define DPM_TABLE_241__LinkLevel_7_EnabledForActivity__SHIFT 0x8 2411 + #define DPM_TABLE_241__LinkLevel_7_PcieLaneCount_MASK 0xff0000 2412 + #define DPM_TABLE_241__LinkLevel_7_PcieLaneCount__SHIFT 0x10 2413 + #define DPM_TABLE_241__LinkLevel_7_PcieGenSpeed_MASK 0xff000000 2414 + #define DPM_TABLE_241__LinkLevel_7_PcieGenSpeed__SHIFT 0x18 2415 + #define DPM_TABLE_242__LinkLevel_7_DownThreshold_MASK 0xffffffff 2416 + #define DPM_TABLE_242__LinkLevel_7_DownThreshold__SHIFT 0x0 2417 + #define DPM_TABLE_243__LinkLevel_7_UpThreshold_MASK 0xffffffff 2418 + #define DPM_TABLE_243__LinkLevel_7_UpThreshold__SHIFT 0x0 2419 + #define DPM_TABLE_244__LinkLevel_7_Reserved_MASK 0xffffffff 2420 + #define DPM_TABLE_244__LinkLevel_7_Reserved__SHIFT 0x0 2421 + #define DPM_TABLE_245__ACPILevel_Flags_MASK 0xffffffff 2422 + #define DPM_TABLE_245__ACPILevel_Flags__SHIFT 0x0 2423 + #define DPM_TABLE_246__ACPILevel_MinVoltage_Phases_MASK 0xff 2424 + #define DPM_TABLE_246__ACPILevel_MinVoltage_Phases__SHIFT 0x0 2425 + #define DPM_TABLE_246__ACPILevel_MinVoltage_VddGfx_MASK 0xff00 2426 + #define DPM_TABLE_246__ACPILevel_MinVoltage_VddGfx__SHIFT 0x8 2427 + #define DPM_TABLE_246__ACPILevel_MinVoltage_Vddci_MASK 0xff0000 2428 + #define DPM_TABLE_246__ACPILevel_MinVoltage_Vddci__SHIFT 0x10 2429 + #define DPM_TABLE_246__ACPILevel_MinVoltage_Vddc_MASK 0xff000000 2430 + #define DPM_TABLE_246__ACPILevel_MinVoltage_Vddc__SHIFT 0x18 2431 + #define DPM_TABLE_247__ACPILevel_SclkFrequency_MASK 0xffffffff 2432 + #define DPM_TABLE_247__ACPILevel_SclkFrequency__SHIFT 0x0 2433 + #define DPM_TABLE_248__ACPILevel_padding_MASK 0xff 2434 + #define DPM_TABLE_248__ACPILevel_padding__SHIFT 0x0 2435 + #define DPM_TABLE_248__ACPILevel_DeepSleepDivId_MASK 0xff00 2436 + #define DPM_TABLE_248__ACPILevel_DeepSleepDivId__SHIFT 0x8 2437 + #define DPM_TABLE_248__ACPILevel_DisplayWatermark_MASK 0xff0000 2438 + #define DPM_TABLE_248__ACPILevel_DisplayWatermark__SHIFT 0x10 2439 + #define DPM_TABLE_248__ACPILevel_SclkDid_MASK 0xff000000 2440 + #define DPM_TABLE_248__ACPILevel_SclkDid__SHIFT 0x18 2441 + #define DPM_TABLE_249__ACPILevel_CgSpllFuncCntl_MASK 0xffffffff 2442 + #define DPM_TABLE_249__ACPILevel_CgSpllFuncCntl__SHIFT 0x0 2443 + #define DPM_TABLE_250__ACPILevel_CgSpllFuncCntl2_MASK 0xffffffff 2444 + #define DPM_TABLE_250__ACPILevel_CgSpllFuncCntl2__SHIFT 0x0 2445 + #define DPM_TABLE_251__ACPILevel_CgSpllFuncCntl3_MASK 0xffffffff 2446 + #define DPM_TABLE_251__ACPILevel_CgSpllFuncCntl3__SHIFT 0x0 2447 + #define DPM_TABLE_252__ACPILevel_CgSpllFuncCntl4_MASK 0xffffffff 2448 + #define DPM_TABLE_252__ACPILevel_CgSpllFuncCntl4__SHIFT 0x0 2449 + #define DPM_TABLE_253__ACPILevel_SpllSpreadSpectrum_MASK 0xffffffff 2450 + #define DPM_TABLE_253__ACPILevel_SpllSpreadSpectrum__SHIFT 0x0 2451 + #define DPM_TABLE_254__ACPILevel_SpllSpreadSpectrum2_MASK 0xffffffff 2452 + #define DPM_TABLE_254__ACPILevel_SpllSpreadSpectrum2__SHIFT 0x0 2453 + #define DPM_TABLE_255__ACPILevel_CcPwrDynRm_MASK 0xffffffff 2454 + #define DPM_TABLE_255__ACPILevel_CcPwrDynRm__SHIFT 0x0 2455 + #define DPM_TABLE_256__ACPILevel_CcPwrDynRm1_MASK 0xffffffff 2456 + #define DPM_TABLE_256__ACPILevel_CcPwrDynRm1__SHIFT 0x0 2457 + #define DPM_TABLE_257__UvdLevel_0_VclkFrequency_MASK 0xffffffff 2458 + #define DPM_TABLE_257__UvdLevel_0_VclkFrequency__SHIFT 0x0 2459 + #define DPM_TABLE_258__UvdLevel_0_DclkFrequency_MASK 0xffffffff 2460 + #define DPM_TABLE_258__UvdLevel_0_DclkFrequency__SHIFT 0x0 2461 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_Phases_MASK 0xff 2462 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_Phases__SHIFT 0x0 2463 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_VddGfx_MASK 0xff00 2464 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2465 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddci_MASK 0xff0000 2466 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddci__SHIFT 0x10 2467 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddc_MASK 0xff000000 2468 + #define DPM_TABLE_259__UvdLevel_0_MinVoltage_Vddc__SHIFT 0x18 2469 + #define DPM_TABLE_260__UvdLevel_0_padding_1_MASK 0xff 2470 + #define DPM_TABLE_260__UvdLevel_0_padding_1__SHIFT 0x0 2471 + #define DPM_TABLE_260__UvdLevel_0_padding_0_MASK 0xff00 2472 + #define DPM_TABLE_260__UvdLevel_0_padding_0__SHIFT 0x8 2473 + #define DPM_TABLE_260__UvdLevel_0_DclkDivider_MASK 0xff0000 2474 + #define DPM_TABLE_260__UvdLevel_0_DclkDivider__SHIFT 0x10 2475 + #define DPM_TABLE_260__UvdLevel_0_VclkDivider_MASK 0xff000000 2476 + #define DPM_TABLE_260__UvdLevel_0_VclkDivider__SHIFT 0x18 2477 + #define DPM_TABLE_261__UvdLevel_1_VclkFrequency_MASK 0xffffffff 2478 + #define DPM_TABLE_261__UvdLevel_1_VclkFrequency__SHIFT 0x0 2479 + #define DPM_TABLE_262__UvdLevel_1_DclkFrequency_MASK 0xffffffff 2480 + #define DPM_TABLE_262__UvdLevel_1_DclkFrequency__SHIFT 0x0 2481 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_Phases_MASK 0xff 2482 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_Phases__SHIFT 0x0 2483 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_VddGfx_MASK 0xff00 2484 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2485 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddci_MASK 0xff0000 2486 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddci__SHIFT 0x10 2487 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddc_MASK 0xff000000 2488 + #define DPM_TABLE_263__UvdLevel_1_MinVoltage_Vddc__SHIFT 0x18 2489 + #define DPM_TABLE_264__UvdLevel_1_padding_1_MASK 0xff 2490 + #define DPM_TABLE_264__UvdLevel_1_padding_1__SHIFT 0x0 2491 + #define DPM_TABLE_264__UvdLevel_1_padding_0_MASK 0xff00 2492 + #define DPM_TABLE_264__UvdLevel_1_padding_0__SHIFT 0x8 2493 + #define DPM_TABLE_264__UvdLevel_1_DclkDivider_MASK 0xff0000 2494 + #define DPM_TABLE_264__UvdLevel_1_DclkDivider__SHIFT 0x10 2495 + #define DPM_TABLE_264__UvdLevel_1_VclkDivider_MASK 0xff000000 2496 + #define DPM_TABLE_264__UvdLevel_1_VclkDivider__SHIFT 0x18 2497 + #define DPM_TABLE_265__UvdLevel_2_VclkFrequency_MASK 0xffffffff 2498 + #define DPM_TABLE_265__UvdLevel_2_VclkFrequency__SHIFT 0x0 2499 + #define DPM_TABLE_266__UvdLevel_2_DclkFrequency_MASK 0xffffffff 2500 + #define DPM_TABLE_266__UvdLevel_2_DclkFrequency__SHIFT 0x0 2501 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_Phases_MASK 0xff 2502 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_Phases__SHIFT 0x0 2503 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_VddGfx_MASK 0xff00 2504 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2505 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddci_MASK 0xff0000 2506 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddci__SHIFT 0x10 2507 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddc_MASK 0xff000000 2508 + #define DPM_TABLE_267__UvdLevel_2_MinVoltage_Vddc__SHIFT 0x18 2509 + #define DPM_TABLE_268__UvdLevel_2_padding_1_MASK 0xff 2510 + #define DPM_TABLE_268__UvdLevel_2_padding_1__SHIFT 0x0 2511 + #define DPM_TABLE_268__UvdLevel_2_padding_0_MASK 0xff00 2512 + #define DPM_TABLE_268__UvdLevel_2_padding_0__SHIFT 0x8 2513 + #define DPM_TABLE_268__UvdLevel_2_DclkDivider_MASK 0xff0000 2514 + #define DPM_TABLE_268__UvdLevel_2_DclkDivider__SHIFT 0x10 2515 + #define DPM_TABLE_268__UvdLevel_2_VclkDivider_MASK 0xff000000 2516 + #define DPM_TABLE_268__UvdLevel_2_VclkDivider__SHIFT 0x18 2517 + #define DPM_TABLE_269__UvdLevel_3_VclkFrequency_MASK 0xffffffff 2518 + #define DPM_TABLE_269__UvdLevel_3_VclkFrequency__SHIFT 0x0 2519 + #define DPM_TABLE_270__UvdLevel_3_DclkFrequency_MASK 0xffffffff 2520 + #define DPM_TABLE_270__UvdLevel_3_DclkFrequency__SHIFT 0x0 2521 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_Phases_MASK 0xff 2522 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_Phases__SHIFT 0x0 2523 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_VddGfx_MASK 0xff00 2524 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2525 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddci_MASK 0xff0000 2526 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddci__SHIFT 0x10 2527 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddc_MASK 0xff000000 2528 + #define DPM_TABLE_271__UvdLevel_3_MinVoltage_Vddc__SHIFT 0x18 2529 + #define DPM_TABLE_272__UvdLevel_3_padding_1_MASK 0xff 2530 + #define DPM_TABLE_272__UvdLevel_3_padding_1__SHIFT 0x0 2531 + #define DPM_TABLE_272__UvdLevel_3_padding_0_MASK 0xff00 2532 + #define DPM_TABLE_272__UvdLevel_3_padding_0__SHIFT 0x8 2533 + #define DPM_TABLE_272__UvdLevel_3_DclkDivider_MASK 0xff0000 2534 + #define DPM_TABLE_272__UvdLevel_3_DclkDivider__SHIFT 0x10 2535 + #define DPM_TABLE_272__UvdLevel_3_VclkDivider_MASK 0xff000000 2536 + #define DPM_TABLE_272__UvdLevel_3_VclkDivider__SHIFT 0x18 2537 + #define DPM_TABLE_273__UvdLevel_4_VclkFrequency_MASK 0xffffffff 2538 + #define DPM_TABLE_273__UvdLevel_4_VclkFrequency__SHIFT 0x0 2539 + #define DPM_TABLE_274__UvdLevel_4_DclkFrequency_MASK 0xffffffff 2540 + #define DPM_TABLE_274__UvdLevel_4_DclkFrequency__SHIFT 0x0 2541 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_Phases_MASK 0xff 2542 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_Phases__SHIFT 0x0 2543 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_VddGfx_MASK 0xff00 2544 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2545 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddci_MASK 0xff0000 2546 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddci__SHIFT 0x10 2547 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddc_MASK 0xff000000 2548 + #define DPM_TABLE_275__UvdLevel_4_MinVoltage_Vddc__SHIFT 0x18 2549 + #define DPM_TABLE_276__UvdLevel_4_padding_1_MASK 0xff 2550 + #define DPM_TABLE_276__UvdLevel_4_padding_1__SHIFT 0x0 2551 + #define DPM_TABLE_276__UvdLevel_4_padding_0_MASK 0xff00 2552 + #define DPM_TABLE_276__UvdLevel_4_padding_0__SHIFT 0x8 2553 + #define DPM_TABLE_276__UvdLevel_4_DclkDivider_MASK 0xff0000 2554 + #define DPM_TABLE_276__UvdLevel_4_DclkDivider__SHIFT 0x10 2555 + #define DPM_TABLE_276__UvdLevel_4_VclkDivider_MASK 0xff000000 2556 + #define DPM_TABLE_276__UvdLevel_4_VclkDivider__SHIFT 0x18 2557 + #define DPM_TABLE_277__UvdLevel_5_VclkFrequency_MASK 0xffffffff 2558 + #define DPM_TABLE_277__UvdLevel_5_VclkFrequency__SHIFT 0x0 2559 + #define DPM_TABLE_278__UvdLevel_5_DclkFrequency_MASK 0xffffffff 2560 + #define DPM_TABLE_278__UvdLevel_5_DclkFrequency__SHIFT 0x0 2561 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_Phases_MASK 0xff 2562 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_Phases__SHIFT 0x0 2563 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_VddGfx_MASK 0xff00 2564 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2565 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddci_MASK 0xff0000 2566 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddci__SHIFT 0x10 2567 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddc_MASK 0xff000000 2568 + #define DPM_TABLE_279__UvdLevel_5_MinVoltage_Vddc__SHIFT 0x18 2569 + #define DPM_TABLE_280__UvdLevel_5_padding_1_MASK 0xff 2570 + #define DPM_TABLE_280__UvdLevel_5_padding_1__SHIFT 0x0 2571 + #define DPM_TABLE_280__UvdLevel_5_padding_0_MASK 0xff00 2572 + #define DPM_TABLE_280__UvdLevel_5_padding_0__SHIFT 0x8 2573 + #define DPM_TABLE_280__UvdLevel_5_DclkDivider_MASK 0xff0000 2574 + #define DPM_TABLE_280__UvdLevel_5_DclkDivider__SHIFT 0x10 2575 + #define DPM_TABLE_280__UvdLevel_5_VclkDivider_MASK 0xff000000 2576 + #define DPM_TABLE_280__UvdLevel_5_VclkDivider__SHIFT 0x18 2577 + #define DPM_TABLE_281__UvdLevel_6_VclkFrequency_MASK 0xffffffff 2578 + #define DPM_TABLE_281__UvdLevel_6_VclkFrequency__SHIFT 0x0 2579 + #define DPM_TABLE_282__UvdLevel_6_DclkFrequency_MASK 0xffffffff 2580 + #define DPM_TABLE_282__UvdLevel_6_DclkFrequency__SHIFT 0x0 2581 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_Phases_MASK 0xff 2582 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_Phases__SHIFT 0x0 2583 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_VddGfx_MASK 0xff00 2584 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2585 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddci_MASK 0xff0000 2586 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddci__SHIFT 0x10 2587 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddc_MASK 0xff000000 2588 + #define DPM_TABLE_283__UvdLevel_6_MinVoltage_Vddc__SHIFT 0x18 2589 + #define DPM_TABLE_284__UvdLevel_6_padding_1_MASK 0xff 2590 + #define DPM_TABLE_284__UvdLevel_6_padding_1__SHIFT 0x0 2591 + #define DPM_TABLE_284__UvdLevel_6_padding_0_MASK 0xff00 2592 + #define DPM_TABLE_284__UvdLevel_6_padding_0__SHIFT 0x8 2593 + #define DPM_TABLE_284__UvdLevel_6_DclkDivider_MASK 0xff0000 2594 + #define DPM_TABLE_284__UvdLevel_6_DclkDivider__SHIFT 0x10 2595 + #define DPM_TABLE_284__UvdLevel_6_VclkDivider_MASK 0xff000000 2596 + #define DPM_TABLE_284__UvdLevel_6_VclkDivider__SHIFT 0x18 2597 + #define DPM_TABLE_285__UvdLevel_7_VclkFrequency_MASK 0xffffffff 2598 + #define DPM_TABLE_285__UvdLevel_7_VclkFrequency__SHIFT 0x0 2599 + #define DPM_TABLE_286__UvdLevel_7_DclkFrequency_MASK 0xffffffff 2600 + #define DPM_TABLE_286__UvdLevel_7_DclkFrequency__SHIFT 0x0 2601 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_Phases_MASK 0xff 2602 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_Phases__SHIFT 0x0 2603 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_VddGfx_MASK 0xff00 2604 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2605 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddci_MASK 0xff0000 2606 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddci__SHIFT 0x10 2607 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddc_MASK 0xff000000 2608 + #define DPM_TABLE_287__UvdLevel_7_MinVoltage_Vddc__SHIFT 0x18 2609 + #define DPM_TABLE_288__UvdLevel_7_padding_1_MASK 0xff 2610 + #define DPM_TABLE_288__UvdLevel_7_padding_1__SHIFT 0x0 2611 + #define DPM_TABLE_288__UvdLevel_7_padding_0_MASK 0xff00 2612 + #define DPM_TABLE_288__UvdLevel_7_padding_0__SHIFT 0x8 2613 + #define DPM_TABLE_288__UvdLevel_7_DclkDivider_MASK 0xff0000 2614 + #define DPM_TABLE_288__UvdLevel_7_DclkDivider__SHIFT 0x10 2615 + #define DPM_TABLE_288__UvdLevel_7_VclkDivider_MASK 0xff000000 2616 + #define DPM_TABLE_288__UvdLevel_7_VclkDivider__SHIFT 0x18 2617 + #define DPM_TABLE_289__VceLevel_0_Frequency_MASK 0xffffffff 2618 + #define DPM_TABLE_289__VceLevel_0_Frequency__SHIFT 0x0 2619 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_Phases_MASK 0xff 2620 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_Phases__SHIFT 0x0 2621 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_VddGfx_MASK 0xff00 2622 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2623 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddci_MASK 0xff0000 2624 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddci__SHIFT 0x10 2625 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddc_MASK 0xff000000 2626 + #define DPM_TABLE_290__VceLevel_0_MinVoltage_Vddc__SHIFT 0x18 2627 + #define DPM_TABLE_291__VceLevel_0_padding_2_MASK 0xff 2628 + #define DPM_TABLE_291__VceLevel_0_padding_2__SHIFT 0x0 2629 + #define DPM_TABLE_291__VceLevel_0_padding_1_MASK 0xff00 2630 + #define DPM_TABLE_291__VceLevel_0_padding_1__SHIFT 0x8 2631 + #define DPM_TABLE_291__VceLevel_0_padding_0_MASK 0xff0000 2632 + #define DPM_TABLE_291__VceLevel_0_padding_0__SHIFT 0x10 2633 + #define DPM_TABLE_291__VceLevel_0_Divider_MASK 0xff000000 2634 + #define DPM_TABLE_291__VceLevel_0_Divider__SHIFT 0x18 2635 + #define DPM_TABLE_292__VceLevel_1_Frequency_MASK 0xffffffff 2636 + #define DPM_TABLE_292__VceLevel_1_Frequency__SHIFT 0x0 2637 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_Phases_MASK 0xff 2638 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_Phases__SHIFT 0x0 2639 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_VddGfx_MASK 0xff00 2640 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2641 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddci_MASK 0xff0000 2642 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddci__SHIFT 0x10 2643 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddc_MASK 0xff000000 2644 + #define DPM_TABLE_293__VceLevel_1_MinVoltage_Vddc__SHIFT 0x18 2645 + #define DPM_TABLE_294__VceLevel_1_padding_2_MASK 0xff 2646 + #define DPM_TABLE_294__VceLevel_1_padding_2__SHIFT 0x0 2647 + #define DPM_TABLE_294__VceLevel_1_padding_1_MASK 0xff00 2648 + #define DPM_TABLE_294__VceLevel_1_padding_1__SHIFT 0x8 2649 + #define DPM_TABLE_294__VceLevel_1_padding_0_MASK 0xff0000 2650 + #define DPM_TABLE_294__VceLevel_1_padding_0__SHIFT 0x10 2651 + #define DPM_TABLE_294__VceLevel_1_Divider_MASK 0xff000000 2652 + #define DPM_TABLE_294__VceLevel_1_Divider__SHIFT 0x18 2653 + #define DPM_TABLE_295__VceLevel_2_Frequency_MASK 0xffffffff 2654 + #define DPM_TABLE_295__VceLevel_2_Frequency__SHIFT 0x0 2655 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_Phases_MASK 0xff 2656 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_Phases__SHIFT 0x0 2657 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_VddGfx_MASK 0xff00 2658 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2659 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddci_MASK 0xff0000 2660 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddci__SHIFT 0x10 2661 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddc_MASK 0xff000000 2662 + #define DPM_TABLE_296__VceLevel_2_MinVoltage_Vddc__SHIFT 0x18 2663 + #define DPM_TABLE_297__VceLevel_2_padding_2_MASK 0xff 2664 + #define DPM_TABLE_297__VceLevel_2_padding_2__SHIFT 0x0 2665 + #define DPM_TABLE_297__VceLevel_2_padding_1_MASK 0xff00 2666 + #define DPM_TABLE_297__VceLevel_2_padding_1__SHIFT 0x8 2667 + #define DPM_TABLE_297__VceLevel_2_padding_0_MASK 0xff0000 2668 + #define DPM_TABLE_297__VceLevel_2_padding_0__SHIFT 0x10 2669 + #define DPM_TABLE_297__VceLevel_2_Divider_MASK 0xff000000 2670 + #define DPM_TABLE_297__VceLevel_2_Divider__SHIFT 0x18 2671 + #define DPM_TABLE_298__VceLevel_3_Frequency_MASK 0xffffffff 2672 + #define DPM_TABLE_298__VceLevel_3_Frequency__SHIFT 0x0 2673 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_Phases_MASK 0xff 2674 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_Phases__SHIFT 0x0 2675 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_VddGfx_MASK 0xff00 2676 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2677 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddci_MASK 0xff0000 2678 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddci__SHIFT 0x10 2679 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddc_MASK 0xff000000 2680 + #define DPM_TABLE_299__VceLevel_3_MinVoltage_Vddc__SHIFT 0x18 2681 + #define DPM_TABLE_300__VceLevel_3_padding_2_MASK 0xff 2682 + #define DPM_TABLE_300__VceLevel_3_padding_2__SHIFT 0x0 2683 + #define DPM_TABLE_300__VceLevel_3_padding_1_MASK 0xff00 2684 + #define DPM_TABLE_300__VceLevel_3_padding_1__SHIFT 0x8 2685 + #define DPM_TABLE_300__VceLevel_3_padding_0_MASK 0xff0000 2686 + #define DPM_TABLE_300__VceLevel_3_padding_0__SHIFT 0x10 2687 + #define DPM_TABLE_300__VceLevel_3_Divider_MASK 0xff000000 2688 + #define DPM_TABLE_300__VceLevel_3_Divider__SHIFT 0x18 2689 + #define DPM_TABLE_301__VceLevel_4_Frequency_MASK 0xffffffff 2690 + #define DPM_TABLE_301__VceLevel_4_Frequency__SHIFT 0x0 2691 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_Phases_MASK 0xff 2692 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_Phases__SHIFT 0x0 2693 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_VddGfx_MASK 0xff00 2694 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2695 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddci_MASK 0xff0000 2696 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddci__SHIFT 0x10 2697 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddc_MASK 0xff000000 2698 + #define DPM_TABLE_302__VceLevel_4_MinVoltage_Vddc__SHIFT 0x18 2699 + #define DPM_TABLE_303__VceLevel_4_padding_2_MASK 0xff 2700 + #define DPM_TABLE_303__VceLevel_4_padding_2__SHIFT 0x0 2701 + #define DPM_TABLE_303__VceLevel_4_padding_1_MASK 0xff00 2702 + #define DPM_TABLE_303__VceLevel_4_padding_1__SHIFT 0x8 2703 + #define DPM_TABLE_303__VceLevel_4_padding_0_MASK 0xff0000 2704 + #define DPM_TABLE_303__VceLevel_4_padding_0__SHIFT 0x10 2705 + #define DPM_TABLE_303__VceLevel_4_Divider_MASK 0xff000000 2706 + #define DPM_TABLE_303__VceLevel_4_Divider__SHIFT 0x18 2707 + #define DPM_TABLE_304__VceLevel_5_Frequency_MASK 0xffffffff 2708 + #define DPM_TABLE_304__VceLevel_5_Frequency__SHIFT 0x0 2709 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_Phases_MASK 0xff 2710 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_Phases__SHIFT 0x0 2711 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_VddGfx_MASK 0xff00 2712 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2713 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddci_MASK 0xff0000 2714 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddci__SHIFT 0x10 2715 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddc_MASK 0xff000000 2716 + #define DPM_TABLE_305__VceLevel_5_MinVoltage_Vddc__SHIFT 0x18 2717 + #define DPM_TABLE_306__VceLevel_5_padding_2_MASK 0xff 2718 + #define DPM_TABLE_306__VceLevel_5_padding_2__SHIFT 0x0 2719 + #define DPM_TABLE_306__VceLevel_5_padding_1_MASK 0xff00 2720 + #define DPM_TABLE_306__VceLevel_5_padding_1__SHIFT 0x8 2721 + #define DPM_TABLE_306__VceLevel_5_padding_0_MASK 0xff0000 2722 + #define DPM_TABLE_306__VceLevel_5_padding_0__SHIFT 0x10 2723 + #define DPM_TABLE_306__VceLevel_5_Divider_MASK 0xff000000 2724 + #define DPM_TABLE_306__VceLevel_5_Divider__SHIFT 0x18 2725 + #define DPM_TABLE_307__VceLevel_6_Frequency_MASK 0xffffffff 2726 + #define DPM_TABLE_307__VceLevel_6_Frequency__SHIFT 0x0 2727 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_Phases_MASK 0xff 2728 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_Phases__SHIFT 0x0 2729 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_VddGfx_MASK 0xff00 2730 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2731 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddci_MASK 0xff0000 2732 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddci__SHIFT 0x10 2733 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddc_MASK 0xff000000 2734 + #define DPM_TABLE_308__VceLevel_6_MinVoltage_Vddc__SHIFT 0x18 2735 + #define DPM_TABLE_309__VceLevel_6_padding_2_MASK 0xff 2736 + #define DPM_TABLE_309__VceLevel_6_padding_2__SHIFT 0x0 2737 + #define DPM_TABLE_309__VceLevel_6_padding_1_MASK 0xff00 2738 + #define DPM_TABLE_309__VceLevel_6_padding_1__SHIFT 0x8 2739 + #define DPM_TABLE_309__VceLevel_6_padding_0_MASK 0xff0000 2740 + #define DPM_TABLE_309__VceLevel_6_padding_0__SHIFT 0x10 2741 + #define DPM_TABLE_309__VceLevel_6_Divider_MASK 0xff000000 2742 + #define DPM_TABLE_309__VceLevel_6_Divider__SHIFT 0x18 2743 + #define DPM_TABLE_310__VceLevel_7_Frequency_MASK 0xffffffff 2744 + #define DPM_TABLE_310__VceLevel_7_Frequency__SHIFT 0x0 2745 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_Phases_MASK 0xff 2746 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_Phases__SHIFT 0x0 2747 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_VddGfx_MASK 0xff00 2748 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2749 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddci_MASK 0xff0000 2750 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddci__SHIFT 0x10 2751 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddc_MASK 0xff000000 2752 + #define DPM_TABLE_311__VceLevel_7_MinVoltage_Vddc__SHIFT 0x18 2753 + #define DPM_TABLE_312__VceLevel_7_padding_2_MASK 0xff 2754 + #define DPM_TABLE_312__VceLevel_7_padding_2__SHIFT 0x0 2755 + #define DPM_TABLE_312__VceLevel_7_padding_1_MASK 0xff00 2756 + #define DPM_TABLE_312__VceLevel_7_padding_1__SHIFT 0x8 2757 + #define DPM_TABLE_312__VceLevel_7_padding_0_MASK 0xff0000 2758 + #define DPM_TABLE_312__VceLevel_7_padding_0__SHIFT 0x10 2759 + #define DPM_TABLE_312__VceLevel_7_Divider_MASK 0xff000000 2760 + #define DPM_TABLE_312__VceLevel_7_Divider__SHIFT 0x18 2761 + #define DPM_TABLE_313__AcpLevel_0_Frequency_MASK 0xffffffff 2762 + #define DPM_TABLE_313__AcpLevel_0_Frequency__SHIFT 0x0 2763 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_Phases_MASK 0xff 2764 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_Phases__SHIFT 0x0 2765 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_VddGfx_MASK 0xff00 2766 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2767 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddci_MASK 0xff0000 2768 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddci__SHIFT 0x10 2769 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddc_MASK 0xff000000 2770 + #define DPM_TABLE_314__AcpLevel_0_MinVoltage_Vddc__SHIFT 0x18 2771 + #define DPM_TABLE_315__AcpLevel_0_padding_2_MASK 0xff 2772 + #define DPM_TABLE_315__AcpLevel_0_padding_2__SHIFT 0x0 2773 + #define DPM_TABLE_315__AcpLevel_0_padding_1_MASK 0xff00 2774 + #define DPM_TABLE_315__AcpLevel_0_padding_1__SHIFT 0x8 2775 + #define DPM_TABLE_315__AcpLevel_0_padding_0_MASK 0xff0000 2776 + #define DPM_TABLE_315__AcpLevel_0_padding_0__SHIFT 0x10 2777 + #define DPM_TABLE_315__AcpLevel_0_Divider_MASK 0xff000000 2778 + #define DPM_TABLE_315__AcpLevel_0_Divider__SHIFT 0x18 2779 + #define DPM_TABLE_316__AcpLevel_1_Frequency_MASK 0xffffffff 2780 + #define DPM_TABLE_316__AcpLevel_1_Frequency__SHIFT 0x0 2781 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_Phases_MASK 0xff 2782 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_Phases__SHIFT 0x0 2783 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_VddGfx_MASK 0xff00 2784 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2785 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddci_MASK 0xff0000 2786 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddci__SHIFT 0x10 2787 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddc_MASK 0xff000000 2788 + #define DPM_TABLE_317__AcpLevel_1_MinVoltage_Vddc__SHIFT 0x18 2789 + #define DPM_TABLE_318__AcpLevel_1_padding_2_MASK 0xff 2790 + #define DPM_TABLE_318__AcpLevel_1_padding_2__SHIFT 0x0 2791 + #define DPM_TABLE_318__AcpLevel_1_padding_1_MASK 0xff00 2792 + #define DPM_TABLE_318__AcpLevel_1_padding_1__SHIFT 0x8 2793 + #define DPM_TABLE_318__AcpLevel_1_padding_0_MASK 0xff0000 2794 + #define DPM_TABLE_318__AcpLevel_1_padding_0__SHIFT 0x10 2795 + #define DPM_TABLE_318__AcpLevel_1_Divider_MASK 0xff000000 2796 + #define DPM_TABLE_318__AcpLevel_1_Divider__SHIFT 0x18 2797 + #define DPM_TABLE_319__AcpLevel_2_Frequency_MASK 0xffffffff 2798 + #define DPM_TABLE_319__AcpLevel_2_Frequency__SHIFT 0x0 2799 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_Phases_MASK 0xff 2800 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_Phases__SHIFT 0x0 2801 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_VddGfx_MASK 0xff00 2802 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2803 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddci_MASK 0xff0000 2804 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddci__SHIFT 0x10 2805 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddc_MASK 0xff000000 2806 + #define DPM_TABLE_320__AcpLevel_2_MinVoltage_Vddc__SHIFT 0x18 2807 + #define DPM_TABLE_321__AcpLevel_2_padding_2_MASK 0xff 2808 + #define DPM_TABLE_321__AcpLevel_2_padding_2__SHIFT 0x0 2809 + #define DPM_TABLE_321__AcpLevel_2_padding_1_MASK 0xff00 2810 + #define DPM_TABLE_321__AcpLevel_2_padding_1__SHIFT 0x8 2811 + #define DPM_TABLE_321__AcpLevel_2_padding_0_MASK 0xff0000 2812 + #define DPM_TABLE_321__AcpLevel_2_padding_0__SHIFT 0x10 2813 + #define DPM_TABLE_321__AcpLevel_2_Divider_MASK 0xff000000 2814 + #define DPM_TABLE_321__AcpLevel_2_Divider__SHIFT 0x18 2815 + #define DPM_TABLE_322__AcpLevel_3_Frequency_MASK 0xffffffff 2816 + #define DPM_TABLE_322__AcpLevel_3_Frequency__SHIFT 0x0 2817 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_Phases_MASK 0xff 2818 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_Phases__SHIFT 0x0 2819 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_VddGfx_MASK 0xff00 2820 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2821 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddci_MASK 0xff0000 2822 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddci__SHIFT 0x10 2823 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddc_MASK 0xff000000 2824 + #define DPM_TABLE_323__AcpLevel_3_MinVoltage_Vddc__SHIFT 0x18 2825 + #define DPM_TABLE_324__AcpLevel_3_padding_2_MASK 0xff 2826 + #define DPM_TABLE_324__AcpLevel_3_padding_2__SHIFT 0x0 2827 + #define DPM_TABLE_324__AcpLevel_3_padding_1_MASK 0xff00 2828 + #define DPM_TABLE_324__AcpLevel_3_padding_1__SHIFT 0x8 2829 + #define DPM_TABLE_324__AcpLevel_3_padding_0_MASK 0xff0000 2830 + #define DPM_TABLE_324__AcpLevel_3_padding_0__SHIFT 0x10 2831 + #define DPM_TABLE_324__AcpLevel_3_Divider_MASK 0xff000000 2832 + #define DPM_TABLE_324__AcpLevel_3_Divider__SHIFT 0x18 2833 + #define DPM_TABLE_325__AcpLevel_4_Frequency_MASK 0xffffffff 2834 + #define DPM_TABLE_325__AcpLevel_4_Frequency__SHIFT 0x0 2835 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_Phases_MASK 0xff 2836 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_Phases__SHIFT 0x0 2837 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_VddGfx_MASK 0xff00 2838 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2839 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddci_MASK 0xff0000 2840 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddci__SHIFT 0x10 2841 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddc_MASK 0xff000000 2842 + #define DPM_TABLE_326__AcpLevel_4_MinVoltage_Vddc__SHIFT 0x18 2843 + #define DPM_TABLE_327__AcpLevel_4_padding_2_MASK 0xff 2844 + #define DPM_TABLE_327__AcpLevel_4_padding_2__SHIFT 0x0 2845 + #define DPM_TABLE_327__AcpLevel_4_padding_1_MASK 0xff00 2846 + #define DPM_TABLE_327__AcpLevel_4_padding_1__SHIFT 0x8 2847 + #define DPM_TABLE_327__AcpLevel_4_padding_0_MASK 0xff0000 2848 + #define DPM_TABLE_327__AcpLevel_4_padding_0__SHIFT 0x10 2849 + #define DPM_TABLE_327__AcpLevel_4_Divider_MASK 0xff000000 2850 + #define DPM_TABLE_327__AcpLevel_4_Divider__SHIFT 0x18 2851 + #define DPM_TABLE_328__AcpLevel_5_Frequency_MASK 0xffffffff 2852 + #define DPM_TABLE_328__AcpLevel_5_Frequency__SHIFT 0x0 2853 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_Phases_MASK 0xff 2854 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_Phases__SHIFT 0x0 2855 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_VddGfx_MASK 0xff00 2856 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_VddGfx__SHIFT 0x8 2857 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddci_MASK 0xff0000 2858 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddci__SHIFT 0x10 2859 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddc_MASK 0xff000000 2860 + #define DPM_TABLE_329__AcpLevel_5_MinVoltage_Vddc__SHIFT 0x18 2861 + #define DPM_TABLE_330__AcpLevel_5_padding_2_MASK 0xff 2862 + #define DPM_TABLE_330__AcpLevel_5_padding_2__SHIFT 0x0 2863 + #define DPM_TABLE_330__AcpLevel_5_padding_1_MASK 0xff00 2864 + #define DPM_TABLE_330__AcpLevel_5_padding_1__SHIFT 0x8 2865 + #define DPM_TABLE_330__AcpLevel_5_padding_0_MASK 0xff0000 2866 + #define DPM_TABLE_330__AcpLevel_5_padding_0__SHIFT 0x10 2867 + #define DPM_TABLE_330__AcpLevel_5_Divider_MASK 0xff000000 2868 + #define DPM_TABLE_330__AcpLevel_5_Divider__SHIFT 0x18 2869 + #define DPM_TABLE_331__AcpLevel_6_Frequency_MASK 0xffffffff 2870 + #define DPM_TABLE_331__AcpLevel_6_Frequency__SHIFT 0x0 2871 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_Phases_MASK 0xff 2872 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_Phases__SHIFT 0x0 2873 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_VddGfx_MASK 0xff00 2874 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_VddGfx__SHIFT 0x8 2875 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddci_MASK 0xff0000 2876 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddci__SHIFT 0x10 2877 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddc_MASK 0xff000000 2878 + #define DPM_TABLE_332__AcpLevel_6_MinVoltage_Vddc__SHIFT 0x18 2879 + #define DPM_TABLE_333__AcpLevel_6_padding_2_MASK 0xff 2880 + #define DPM_TABLE_333__AcpLevel_6_padding_2__SHIFT 0x0 2881 + #define DPM_TABLE_333__AcpLevel_6_padding_1_MASK 0xff00 2882 + #define DPM_TABLE_333__AcpLevel_6_padding_1__SHIFT 0x8 2883 + #define DPM_TABLE_333__AcpLevel_6_padding_0_MASK 0xff0000 2884 + #define DPM_TABLE_333__AcpLevel_6_padding_0__SHIFT 0x10 2885 + #define DPM_TABLE_333__AcpLevel_6_Divider_MASK 0xff000000 2886 + #define DPM_TABLE_333__AcpLevel_6_Divider__SHIFT 0x18 2887 + #define DPM_TABLE_334__AcpLevel_7_Frequency_MASK 0xffffffff 2888 + #define DPM_TABLE_334__AcpLevel_7_Frequency__SHIFT 0x0 2889 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_Phases_MASK 0xff 2890 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_Phases__SHIFT 0x0 2891 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_VddGfx_MASK 0xff00 2892 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_VddGfx__SHIFT 0x8 2893 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddci_MASK 0xff0000 2894 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddci__SHIFT 0x10 2895 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddc_MASK 0xff000000 2896 + #define DPM_TABLE_335__AcpLevel_7_MinVoltage_Vddc__SHIFT 0x18 2897 + #define DPM_TABLE_336__AcpLevel_7_padding_2_MASK 0xff 2898 + #define DPM_TABLE_336__AcpLevel_7_padding_2__SHIFT 0x0 2899 + #define DPM_TABLE_336__AcpLevel_7_padding_1_MASK 0xff00 2900 + #define DPM_TABLE_336__AcpLevel_7_padding_1__SHIFT 0x8 2901 + #define DPM_TABLE_336__AcpLevel_7_padding_0_MASK 0xff0000 2902 + #define DPM_TABLE_336__AcpLevel_7_padding_0__SHIFT 0x10 2903 + #define DPM_TABLE_336__AcpLevel_7_Divider_MASK 0xff000000 2904 + #define DPM_TABLE_336__AcpLevel_7_Divider__SHIFT 0x18 2905 + #define DPM_TABLE_337__SamuLevel_0_Frequency_MASK 0xffffffff 2906 + #define DPM_TABLE_337__SamuLevel_0_Frequency__SHIFT 0x0 2907 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_Phases_MASK 0xff 2908 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_Phases__SHIFT 0x0 2909 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_VddGfx_MASK 0xff00 2910 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_VddGfx__SHIFT 0x8 2911 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddci_MASK 0xff0000 2912 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddci__SHIFT 0x10 2913 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddc_MASK 0xff000000 2914 + #define DPM_TABLE_338__SamuLevel_0_MinVoltage_Vddc__SHIFT 0x18 2915 + #define DPM_TABLE_339__SamuLevel_0_padding_2_MASK 0xff 2916 + #define DPM_TABLE_339__SamuLevel_0_padding_2__SHIFT 0x0 2917 + #define DPM_TABLE_339__SamuLevel_0_padding_1_MASK 0xff00 2918 + #define DPM_TABLE_339__SamuLevel_0_padding_1__SHIFT 0x8 2919 + #define DPM_TABLE_339__SamuLevel_0_padding_0_MASK 0xff0000 2920 + #define DPM_TABLE_339__SamuLevel_0_padding_0__SHIFT 0x10 2921 + #define DPM_TABLE_339__SamuLevel_0_Divider_MASK 0xff000000 2922 + #define DPM_TABLE_339__SamuLevel_0_Divider__SHIFT 0x18 2923 + #define DPM_TABLE_340__SamuLevel_1_Frequency_MASK 0xffffffff 2924 + #define DPM_TABLE_340__SamuLevel_1_Frequency__SHIFT 0x0 2925 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_Phases_MASK 0xff 2926 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_Phases__SHIFT 0x0 2927 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_VddGfx_MASK 0xff00 2928 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_VddGfx__SHIFT 0x8 2929 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddci_MASK 0xff0000 2930 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddci__SHIFT 0x10 2931 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddc_MASK 0xff000000 2932 + #define DPM_TABLE_341__SamuLevel_1_MinVoltage_Vddc__SHIFT 0x18 2933 + #define DPM_TABLE_342__SamuLevel_1_padding_2_MASK 0xff 2934 + #define DPM_TABLE_342__SamuLevel_1_padding_2__SHIFT 0x0 2935 + #define DPM_TABLE_342__SamuLevel_1_padding_1_MASK 0xff00 2936 + #define DPM_TABLE_342__SamuLevel_1_padding_1__SHIFT 0x8 2937 + #define DPM_TABLE_342__SamuLevel_1_padding_0_MASK 0xff0000 2938 + #define DPM_TABLE_342__SamuLevel_1_padding_0__SHIFT 0x10 2939 + #define DPM_TABLE_342__SamuLevel_1_Divider_MASK 0xff000000 2940 + #define DPM_TABLE_342__SamuLevel_1_Divider__SHIFT 0x18 2941 + #define DPM_TABLE_343__SamuLevel_2_Frequency_MASK 0xffffffff 2942 + #define DPM_TABLE_343__SamuLevel_2_Frequency__SHIFT 0x0 2943 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_Phases_MASK 0xff 2944 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_Phases__SHIFT 0x0 2945 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_VddGfx_MASK 0xff00 2946 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_VddGfx__SHIFT 0x8 2947 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddci_MASK 0xff0000 2948 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddci__SHIFT 0x10 2949 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddc_MASK 0xff000000 2950 + #define DPM_TABLE_344__SamuLevel_2_MinVoltage_Vddc__SHIFT 0x18 2951 + #define DPM_TABLE_345__SamuLevel_2_padding_2_MASK 0xff 2952 + #define DPM_TABLE_345__SamuLevel_2_padding_2__SHIFT 0x0 2953 + #define DPM_TABLE_345__SamuLevel_2_padding_1_MASK 0xff00 2954 + #define DPM_TABLE_345__SamuLevel_2_padding_1__SHIFT 0x8 2955 + #define DPM_TABLE_345__SamuLevel_2_padding_0_MASK 0xff0000 2956 + #define DPM_TABLE_345__SamuLevel_2_padding_0__SHIFT 0x10 2957 + #define DPM_TABLE_345__SamuLevel_2_Divider_MASK 0xff000000 2958 + #define DPM_TABLE_345__SamuLevel_2_Divider__SHIFT 0x18 2959 + #define DPM_TABLE_346__SamuLevel_3_Frequency_MASK 0xffffffff 2960 + #define DPM_TABLE_346__SamuLevel_3_Frequency__SHIFT 0x0 2961 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_Phases_MASK 0xff 2962 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_Phases__SHIFT 0x0 2963 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_VddGfx_MASK 0xff00 2964 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_VddGfx__SHIFT 0x8 2965 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddci_MASK 0xff0000 2966 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddci__SHIFT 0x10 2967 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddc_MASK 0xff000000 2968 + #define DPM_TABLE_347__SamuLevel_3_MinVoltage_Vddc__SHIFT 0x18 2969 + #define DPM_TABLE_348__SamuLevel_3_padding_2_MASK 0xff 2970 + #define DPM_TABLE_348__SamuLevel_3_padding_2__SHIFT 0x0 2971 + #define DPM_TABLE_348__SamuLevel_3_padding_1_MASK 0xff00 2972 + #define DPM_TABLE_348__SamuLevel_3_padding_1__SHIFT 0x8 2973 + #define DPM_TABLE_348__SamuLevel_3_padding_0_MASK 0xff0000 2974 + #define DPM_TABLE_348__SamuLevel_3_padding_0__SHIFT 0x10 2975 + #define DPM_TABLE_348__SamuLevel_3_Divider_MASK 0xff000000 2976 + #define DPM_TABLE_348__SamuLevel_3_Divider__SHIFT 0x18 2977 + #define DPM_TABLE_349__SamuLevel_4_Frequency_MASK 0xffffffff 2978 + #define DPM_TABLE_349__SamuLevel_4_Frequency__SHIFT 0x0 2979 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_Phases_MASK 0xff 2980 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_Phases__SHIFT 0x0 2981 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_VddGfx_MASK 0xff00 2982 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_VddGfx__SHIFT 0x8 2983 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddci_MASK 0xff0000 2984 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddci__SHIFT 0x10 2985 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddc_MASK 0xff000000 2986 + #define DPM_TABLE_350__SamuLevel_4_MinVoltage_Vddc__SHIFT 0x18 2987 + #define DPM_TABLE_351__SamuLevel_4_padding_2_MASK 0xff 2988 + #define DPM_TABLE_351__SamuLevel_4_padding_2__SHIFT 0x0 2989 + #define DPM_TABLE_351__SamuLevel_4_padding_1_MASK 0xff00 2990 + #define DPM_TABLE_351__SamuLevel_4_padding_1__SHIFT 0x8 2991 + #define DPM_TABLE_351__SamuLevel_4_padding_0_MASK 0xff0000 2992 + #define DPM_TABLE_351__SamuLevel_4_padding_0__SHIFT 0x10 2993 + #define DPM_TABLE_351__SamuLevel_4_Divider_MASK 0xff000000 2994 + #define DPM_TABLE_351__SamuLevel_4_Divider__SHIFT 0x18 2995 + #define DPM_TABLE_352__SamuLevel_5_Frequency_MASK 0xffffffff 2996 + #define DPM_TABLE_352__SamuLevel_5_Frequency__SHIFT 0x0 2997 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_Phases_MASK 0xff 2998 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_Phases__SHIFT 0x0 2999 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_VddGfx_MASK 0xff00 3000 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_VddGfx__SHIFT 0x8 3001 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddci_MASK 0xff0000 3002 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddci__SHIFT 0x10 3003 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddc_MASK 0xff000000 3004 + #define DPM_TABLE_353__SamuLevel_5_MinVoltage_Vddc__SHIFT 0x18 3005 + #define DPM_TABLE_354__SamuLevel_5_padding_2_MASK 0xff 3006 + #define DPM_TABLE_354__SamuLevel_5_padding_2__SHIFT 0x0 3007 + #define DPM_TABLE_354__SamuLevel_5_padding_1_MASK 0xff00 3008 + #define DPM_TABLE_354__SamuLevel_5_padding_1__SHIFT 0x8 3009 + #define DPM_TABLE_354__SamuLevel_5_padding_0_MASK 0xff0000 3010 + #define DPM_TABLE_354__SamuLevel_5_padding_0__SHIFT 0x10 3011 + #define DPM_TABLE_354__SamuLevel_5_Divider_MASK 0xff000000 3012 + #define DPM_TABLE_354__SamuLevel_5_Divider__SHIFT 0x18 3013 + #define DPM_TABLE_355__SamuLevel_6_Frequency_MASK 0xffffffff 3014 + #define DPM_TABLE_355__SamuLevel_6_Frequency__SHIFT 0x0 3015 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_Phases_MASK 0xff 3016 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_Phases__SHIFT 0x0 3017 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_VddGfx_MASK 0xff00 3018 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_VddGfx__SHIFT 0x8 3019 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddci_MASK 0xff0000 3020 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddci__SHIFT 0x10 3021 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddc_MASK 0xff000000 3022 + #define DPM_TABLE_356__SamuLevel_6_MinVoltage_Vddc__SHIFT 0x18 3023 + #define DPM_TABLE_357__SamuLevel_6_padding_2_MASK 0xff 3024 + #define DPM_TABLE_357__SamuLevel_6_padding_2__SHIFT 0x0 3025 + #define DPM_TABLE_357__SamuLevel_6_padding_1_MASK 0xff00 3026 + #define DPM_TABLE_357__SamuLevel_6_padding_1__SHIFT 0x8 3027 + #define DPM_TABLE_357__SamuLevel_6_padding_0_MASK 0xff0000 3028 + #define DPM_TABLE_357__SamuLevel_6_padding_0__SHIFT 0x10 3029 + #define DPM_TABLE_357__SamuLevel_6_Divider_MASK 0xff000000 3030 + #define DPM_TABLE_357__SamuLevel_6_Divider__SHIFT 0x18 3031 + #define DPM_TABLE_358__SamuLevel_7_Frequency_MASK 0xffffffff 3032 + #define DPM_TABLE_358__SamuLevel_7_Frequency__SHIFT 0x0 3033 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_Phases_MASK 0xff 3034 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_Phases__SHIFT 0x0 3035 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_VddGfx_MASK 0xff00 3036 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_VddGfx__SHIFT 0x8 3037 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddci_MASK 0xff0000 3038 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddci__SHIFT 0x10 3039 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddc_MASK 0xff000000 3040 + #define DPM_TABLE_359__SamuLevel_7_MinVoltage_Vddc__SHIFT 0x18 3041 + #define DPM_TABLE_360__SamuLevel_7_padding_2_MASK 0xff 3042 + #define DPM_TABLE_360__SamuLevel_7_padding_2__SHIFT 0x0 3043 + #define DPM_TABLE_360__SamuLevel_7_padding_1_MASK 0xff00 3044 + #define DPM_TABLE_360__SamuLevel_7_padding_1__SHIFT 0x8 3045 + #define DPM_TABLE_360__SamuLevel_7_padding_0_MASK 0xff0000 3046 + #define DPM_TABLE_360__SamuLevel_7_padding_0__SHIFT 0x10 3047 + #define DPM_TABLE_360__SamuLevel_7_Divider_MASK 0xff000000 3048 + #define DPM_TABLE_360__SamuLevel_7_Divider__SHIFT 0x18 3049 + #define DPM_TABLE_361__Ulv_CcPwrDynRm_MASK 0xffffffff 3050 + #define DPM_TABLE_361__Ulv_CcPwrDynRm__SHIFT 0x0 3051 + #define DPM_TABLE_362__Ulv_CcPwrDynRm1_MASK 0xffffffff 3052 + #define DPM_TABLE_362__Ulv_CcPwrDynRm1__SHIFT 0x0 3053 + #define DPM_TABLE_363__Ulv_VddcPhase_MASK 0xff 3054 + #define DPM_TABLE_363__Ulv_VddcPhase__SHIFT 0x0 3055 + #define DPM_TABLE_363__Ulv_VddcOffsetVid_MASK 0xff00 3056 + #define DPM_TABLE_363__Ulv_VddcOffsetVid__SHIFT 0x8 3057 + #define DPM_TABLE_363__Ulv_VddcOffset_MASK 0xffff0000 3058 + #define DPM_TABLE_363__Ulv_VddcOffset__SHIFT 0x10 3059 + #define DPM_TABLE_364__Ulv_Reserved_MASK 0xffffffff 3060 + #define DPM_TABLE_364__Ulv_Reserved__SHIFT 0x0 3061 + #define DPM_TABLE_365__SclkStepSize_MASK 0xffffffff 3062 + #define DPM_TABLE_365__SclkStepSize__SHIFT 0x0 3063 + #define DPM_TABLE_366__Smio_0_MASK 0xffffffff 3064 + #define DPM_TABLE_366__Smio_0__SHIFT 0x0 3065 + #define DPM_TABLE_367__Smio_1_MASK 0xffffffff 3066 + #define DPM_TABLE_367__Smio_1__SHIFT 0x0 3067 + #define DPM_TABLE_368__Smio_2_MASK 0xffffffff 3068 + #define DPM_TABLE_368__Smio_2__SHIFT 0x0 3069 + #define DPM_TABLE_369__Smio_3_MASK 0xffffffff 3070 + #define DPM_TABLE_369__Smio_3__SHIFT 0x0 3071 + #define DPM_TABLE_370__Smio_4_MASK 0xffffffff 3072 + #define DPM_TABLE_370__Smio_4__SHIFT 0x0 3073 + #define DPM_TABLE_371__Smio_5_MASK 0xffffffff 3074 + #define DPM_TABLE_371__Smio_5__SHIFT 0x0 3075 + #define DPM_TABLE_372__Smio_6_MASK 0xffffffff 3076 + #define DPM_TABLE_372__Smio_6__SHIFT 0x0 3077 + #define DPM_TABLE_373__Smio_7_MASK 0xffffffff 3078 + #define DPM_TABLE_373__Smio_7__SHIFT 0x0 3079 + #define DPM_TABLE_374__Smio_8_MASK 0xffffffff 3080 + #define DPM_TABLE_374__Smio_8__SHIFT 0x0 3081 + #define DPM_TABLE_375__Smio_9_MASK 0xffffffff 3082 + #define DPM_TABLE_375__Smio_9__SHIFT 0x0 3083 + #define DPM_TABLE_376__Smio_10_MASK 0xffffffff 3084 + #define DPM_TABLE_376__Smio_10__SHIFT 0x0 3085 + #define DPM_TABLE_377__Smio_11_MASK 0xffffffff 3086 + #define DPM_TABLE_377__Smio_11__SHIFT 0x0 3087 + #define DPM_TABLE_378__Smio_12_MASK 0xffffffff 3088 + #define DPM_TABLE_378__Smio_12__SHIFT 0x0 3089 + #define DPM_TABLE_379__Smio_13_MASK 0xffffffff 3090 + #define DPM_TABLE_379__Smio_13__SHIFT 0x0 3091 + #define DPM_TABLE_380__Smio_14_MASK 0xffffffff 3092 + #define DPM_TABLE_380__Smio_14__SHIFT 0x0 3093 + #define DPM_TABLE_381__Smio_15_MASK 0xffffffff 3094 + #define DPM_TABLE_381__Smio_15__SHIFT 0x0 3095 + #define DPM_TABLE_382__Smio_16_MASK 0xffffffff 3096 + #define DPM_TABLE_382__Smio_16__SHIFT 0x0 3097 + #define DPM_TABLE_383__Smio_17_MASK 0xffffffff 3098 + #define DPM_TABLE_383__Smio_17__SHIFT 0x0 3099 + #define DPM_TABLE_384__Smio_18_MASK 0xffffffff 3100 + #define DPM_TABLE_384__Smio_18__SHIFT 0x0 3101 + #define DPM_TABLE_385__Smio_19_MASK 0xffffffff 3102 + #define DPM_TABLE_385__Smio_19__SHIFT 0x0 3103 + #define DPM_TABLE_386__Smio_20_MASK 0xffffffff 3104 + #define DPM_TABLE_386__Smio_20__SHIFT 0x0 3105 + #define DPM_TABLE_387__Smio_21_MASK 0xffffffff 3106 + #define DPM_TABLE_387__Smio_21__SHIFT 0x0 3107 + #define DPM_TABLE_388__Smio_22_MASK 0xffffffff 3108 + #define DPM_TABLE_388__Smio_22__SHIFT 0x0 3109 + #define DPM_TABLE_389__Smio_23_MASK 0xffffffff 3110 + #define DPM_TABLE_389__Smio_23__SHIFT 0x0 3111 + #define DPM_TABLE_390__Smio_24_MASK 0xffffffff 3112 + #define DPM_TABLE_390__Smio_24__SHIFT 0x0 3113 + #define DPM_TABLE_391__Smio_25_MASK 0xffffffff 3114 + #define DPM_TABLE_391__Smio_25__SHIFT 0x0 3115 + #define DPM_TABLE_392__Smio_26_MASK 0xffffffff 3116 + #define DPM_TABLE_392__Smio_26__SHIFT 0x0 3117 + #define DPM_TABLE_393__Smio_27_MASK 0xffffffff 3118 + #define DPM_TABLE_393__Smio_27__SHIFT 0x0 3119 + #define DPM_TABLE_394__Smio_28_MASK 0xffffffff 3120 + #define DPM_TABLE_394__Smio_28__SHIFT 0x0 3121 + #define DPM_TABLE_395__Smio_29_MASK 0xffffffff 3122 + #define DPM_TABLE_395__Smio_29__SHIFT 0x0 3123 + #define DPM_TABLE_396__Smio_30_MASK 0xffffffff 3124 + #define DPM_TABLE_396__Smio_30__SHIFT 0x0 3125 + #define DPM_TABLE_397__Smio_31_MASK 0xffffffff 3126 + #define DPM_TABLE_397__Smio_31__SHIFT 0x0 3127 + #define DPM_TABLE_398__SamuBootLevel_MASK 0xff 3128 + #define DPM_TABLE_398__SamuBootLevel__SHIFT 0x0 3129 + #define DPM_TABLE_398__AcpBootLevel_MASK 0xff00 3130 + #define DPM_TABLE_398__AcpBootLevel__SHIFT 0x8 3131 + #define DPM_TABLE_398__VceBootLevel_MASK 0xff0000 3132 + #define DPM_TABLE_398__VceBootLevel__SHIFT 0x10 3133 + #define DPM_TABLE_398__UvdBootLevel_MASK 0xff000000 3134 + #define DPM_TABLE_398__UvdBootLevel__SHIFT 0x18 3135 + #define DPM_TABLE_399__GraphicsInterval_MASK 0xff 3136 + #define DPM_TABLE_399__GraphicsInterval__SHIFT 0x0 3137 + #define DPM_TABLE_399__GraphicsThermThrottleEnable_MASK 0xff00 3138 + #define DPM_TABLE_399__GraphicsThermThrottleEnable__SHIFT 0x8 3139 + #define DPM_TABLE_399__GraphicsVoltageChangeEnable_MASK 0xff0000 3140 + #define DPM_TABLE_399__GraphicsVoltageChangeEnable__SHIFT 0x10 3141 + #define DPM_TABLE_399__GraphicsBootLevel_MASK 0xff000000 3142 + #define DPM_TABLE_399__GraphicsBootLevel__SHIFT 0x18 3143 + #define DPM_TABLE_400__TemperatureLimitHigh_MASK 0xffff 3144 + #define DPM_TABLE_400__TemperatureLimitHigh__SHIFT 0x0 3145 + #define DPM_TABLE_400__ThermalInterval_MASK 0xff0000 3146 + #define DPM_TABLE_400__ThermalInterval__SHIFT 0x10 3147 + #define DPM_TABLE_400__VoltageInterval_MASK 0xff000000 3148 + #define DPM_TABLE_400__VoltageInterval__SHIFT 0x18 3149 + #define DPM_TABLE_401__MemoryVoltageChangeEnable_MASK 0xff 3150 + #define DPM_TABLE_401__MemoryVoltageChangeEnable__SHIFT 0x0 3151 + #define DPM_TABLE_401__MemoryBootLevel_MASK 0xff00 3152 + #define DPM_TABLE_401__MemoryBootLevel__SHIFT 0x8 3153 + #define DPM_TABLE_401__TemperatureLimitLow_MASK 0xffff0000 3154 + #define DPM_TABLE_401__TemperatureLimitLow__SHIFT 0x10 3155 + #define DPM_TABLE_402__MemoryThermThrottleEnable_MASK 0xff 3156 + #define DPM_TABLE_402__MemoryThermThrottleEnable__SHIFT 0x0 3157 + #define DPM_TABLE_402__MemoryInterval_MASK 0xff00 3158 + #define DPM_TABLE_402__MemoryInterval__SHIFT 0x8 3159 + #define DPM_TABLE_402__BootMVdd_MASK 0xffff0000 3160 + #define DPM_TABLE_402__BootMVdd__SHIFT 0x10 3161 + #define DPM_TABLE_403__PhaseResponseTime_MASK 0xffff 3162 + #define DPM_TABLE_403__PhaseResponseTime__SHIFT 0x0 3163 + #define DPM_TABLE_403__VoltageResponseTime_MASK 0xffff0000 3164 + #define DPM_TABLE_403__VoltageResponseTime__SHIFT 0x10 3165 + #define DPM_TABLE_404__DTEMode_MASK 0xff 3166 + #define DPM_TABLE_404__DTEMode__SHIFT 0x0 3167 + #define DPM_TABLE_404__DTEInterval_MASK 0xff00 3168 + #define DPM_TABLE_404__DTEInterval__SHIFT 0x8 3169 + #define DPM_TABLE_404__PCIeGenInterval_MASK 0xff0000 3170 + #define DPM_TABLE_404__PCIeGenInterval__SHIFT 0x10 3171 + #define DPM_TABLE_404__PCIeBootLinkLevel_MASK 0xff000000 3172 + #define DPM_TABLE_404__PCIeBootLinkLevel__SHIFT 0x18 3173 + #define DPM_TABLE_405__ThermGpio_MASK 0xff 3174 + #define DPM_TABLE_405__ThermGpio__SHIFT 0x0 3175 + #define DPM_TABLE_405__AcDcGpio_MASK 0xff00 3176 + #define DPM_TABLE_405__AcDcGpio__SHIFT 0x8 3177 + #define DPM_TABLE_405__VRHotGpio_MASK 0xff0000 3178 + #define DPM_TABLE_405__VRHotGpio__SHIFT 0x10 3179 + #define DPM_TABLE_405__SVI2Enable_MASK 0xff000000 3180 + #define DPM_TABLE_405__SVI2Enable__SHIFT 0x18 3181 + #define DPM_TABLE_406__PPM_TemperatureLimit_MASK 0xffff 3182 + #define DPM_TABLE_406__PPM_TemperatureLimit__SHIFT 0x0 3183 + #define DPM_TABLE_406__PPM_PkgPwrLimit_MASK 0xffff0000 3184 + #define DPM_TABLE_406__PPM_PkgPwrLimit__SHIFT 0x10 3185 + #define DPM_TABLE_407__TargetTdp_MASK 0xffff 3186 + #define DPM_TABLE_407__TargetTdp__SHIFT 0x0 3187 + #define DPM_TABLE_407__DefaultTdp_MASK 0xffff0000 3188 + #define DPM_TABLE_407__DefaultTdp__SHIFT 0x10 3189 + #define DPM_TABLE_408__FpsLowThreshold_MASK 0xffff 3190 + #define DPM_TABLE_408__FpsLowThreshold__SHIFT 0x0 3191 + #define DPM_TABLE_408__FpsHighThreshold_MASK 0xffff0000 3192 + #define DPM_TABLE_408__FpsHighThreshold__SHIFT 0x10 3193 + #define DPM_TABLE_409__BAPMTI_R_0_1_0_MASK 0xffff 3194 + #define DPM_TABLE_409__BAPMTI_R_0_1_0__SHIFT 0x0 3195 + #define DPM_TABLE_409__BAPMTI_R_0_0_0_MASK 0xffff0000 3196 + #define DPM_TABLE_409__BAPMTI_R_0_0_0__SHIFT 0x10 3197 + #define DPM_TABLE_410__BAPMTI_R_1_0_0_MASK 0xffff 3198 + #define DPM_TABLE_410__BAPMTI_R_1_0_0__SHIFT 0x0 3199 + #define DPM_TABLE_410__BAPMTI_R_0_2_0_MASK 0xffff0000 3200 + #define DPM_TABLE_410__BAPMTI_R_0_2_0__SHIFT 0x10 3201 + #define DPM_TABLE_411__BAPMTI_R_1_2_0_MASK 0xffff 3202 + #define DPM_TABLE_411__BAPMTI_R_1_2_0__SHIFT 0x0 3203 + #define DPM_TABLE_411__BAPMTI_R_1_1_0_MASK 0xffff0000 3204 + #define DPM_TABLE_411__BAPMTI_R_1_1_0__SHIFT 0x10 3205 + #define DPM_TABLE_412__BAPMTI_R_2_1_0_MASK 0xffff 3206 + #define DPM_TABLE_412__BAPMTI_R_2_1_0__SHIFT 0x0 3207 + #define DPM_TABLE_412__BAPMTI_R_2_0_0_MASK 0xffff0000 3208 + #define DPM_TABLE_412__BAPMTI_R_2_0_0__SHIFT 0x10 3209 + #define DPM_TABLE_413__BAPMTI_R_3_0_0_MASK 0xffff 3210 + #define DPM_TABLE_413__BAPMTI_R_3_0_0__SHIFT 0x0 3211 + #define DPM_TABLE_413__BAPMTI_R_2_2_0_MASK 0xffff0000 3212 + #define DPM_TABLE_413__BAPMTI_R_2_2_0__SHIFT 0x10 3213 + #define DPM_TABLE_414__BAPMTI_R_3_2_0_MASK 0xffff 3214 + #define DPM_TABLE_414__BAPMTI_R_3_2_0__SHIFT 0x0 3215 + #define DPM_TABLE_414__BAPMTI_R_3_1_0_MASK 0xffff0000 3216 + #define DPM_TABLE_414__BAPMTI_R_3_1_0__SHIFT 0x10 3217 + #define DPM_TABLE_415__BAPMTI_R_4_1_0_MASK 0xffff 3218 + #define DPM_TABLE_415__BAPMTI_R_4_1_0__SHIFT 0x0 3219 + #define DPM_TABLE_415__BAPMTI_R_4_0_0_MASK 0xffff0000 3220 + #define DPM_TABLE_415__BAPMTI_R_4_0_0__SHIFT 0x10 3221 + #define DPM_TABLE_416__BAPMTI_RC_0_0_0_MASK 0xffff 3222 + #define DPM_TABLE_416__BAPMTI_RC_0_0_0__SHIFT 0x0 3223 + #define DPM_TABLE_416__BAPMTI_R_4_2_0_MASK 0xffff0000 3224 + #define DPM_TABLE_416__BAPMTI_R_4_2_0__SHIFT 0x10 3225 + #define DPM_TABLE_417__BAPMTI_RC_0_2_0_MASK 0xffff 3226 + #define DPM_TABLE_417__BAPMTI_RC_0_2_0__SHIFT 0x0 3227 + #define DPM_TABLE_417__BAPMTI_RC_0_1_0_MASK 0xffff0000 3228 + #define DPM_TABLE_417__BAPMTI_RC_0_1_0__SHIFT 0x10 3229 + #define DPM_TABLE_418__BAPMTI_RC_1_1_0_MASK 0xffff 3230 + #define DPM_TABLE_418__BAPMTI_RC_1_1_0__SHIFT 0x0 3231 + #define DPM_TABLE_418__BAPMTI_RC_1_0_0_MASK 0xffff0000 3232 + #define DPM_TABLE_418__BAPMTI_RC_1_0_0__SHIFT 0x10 3233 + #define DPM_TABLE_419__BAPMTI_RC_2_0_0_MASK 0xffff 3234 + #define DPM_TABLE_419__BAPMTI_RC_2_0_0__SHIFT 0x0 3235 + #define DPM_TABLE_419__BAPMTI_RC_1_2_0_MASK 0xffff0000 3236 + #define DPM_TABLE_419__BAPMTI_RC_1_2_0__SHIFT 0x10 3237 + #define DPM_TABLE_420__BAPMTI_RC_2_2_0_MASK 0xffff 3238 + #define DPM_TABLE_420__BAPMTI_RC_2_2_0__SHIFT 0x0 3239 + #define DPM_TABLE_420__BAPMTI_RC_2_1_0_MASK 0xffff0000 3240 + #define DPM_TABLE_420__BAPMTI_RC_2_1_0__SHIFT 0x10 3241 + #define DPM_TABLE_421__BAPMTI_RC_3_1_0_MASK 0xffff 3242 + #define DPM_TABLE_421__BAPMTI_RC_3_1_0__SHIFT 0x0 3243 + #define DPM_TABLE_421__BAPMTI_RC_3_0_0_MASK 0xffff0000 3244 + #define DPM_TABLE_421__BAPMTI_RC_3_0_0__SHIFT 0x10 3245 + #define DPM_TABLE_422__BAPMTI_RC_4_0_0_MASK 0xffff 3246 + #define DPM_TABLE_422__BAPMTI_RC_4_0_0__SHIFT 0x0 3247 + #define DPM_TABLE_422__BAPMTI_RC_3_2_0_MASK 0xffff0000 3248 + #define DPM_TABLE_422__BAPMTI_RC_3_2_0__SHIFT 0x10 3249 + #define DPM_TABLE_423__BAPMTI_RC_4_2_0_MASK 0xffff 3250 + #define DPM_TABLE_423__BAPMTI_RC_4_2_0__SHIFT 0x0 3251 + #define DPM_TABLE_423__BAPMTI_RC_4_1_0_MASK 0xffff0000 3252 + #define DPM_TABLE_423__BAPMTI_RC_4_1_0__SHIFT 0x10 3253 + #define DPM_TABLE_424__GpuTjHyst_MASK 0xff 3254 + #define DPM_TABLE_424__GpuTjHyst__SHIFT 0x0 3255 + #define DPM_TABLE_424__GpuTjMax_MASK 0xff00 3256 + #define DPM_TABLE_424__GpuTjMax__SHIFT 0x8 3257 + #define DPM_TABLE_424__DTETjOffset_MASK 0xff0000 3258 + #define DPM_TABLE_424__DTETjOffset__SHIFT 0x10 3259 + #define DPM_TABLE_424__DTEAmbientTempBase_MASK 0xff000000 3260 + #define DPM_TABLE_424__DTEAmbientTempBase__SHIFT 0x18 3261 + #define DPM_TABLE_425__BootVoltage_Phases_MASK 0xff 3262 + #define DPM_TABLE_425__BootVoltage_Phases__SHIFT 0x0 3263 + #define DPM_TABLE_425__BootVoltage_VddGfx_MASK 0xff00 3264 + #define DPM_TABLE_425__BootVoltage_VddGfx__SHIFT 0x8 3265 + #define DPM_TABLE_425__BootVoltage_Vddci_MASK 0xff0000 3266 + #define DPM_TABLE_425__BootVoltage_Vddci__SHIFT 0x10 3267 + #define DPM_TABLE_425__BootVoltage_Vddc_MASK 0xff000000 3268 + #define DPM_TABLE_425__BootVoltage_Vddc__SHIFT 0x18 3269 + #define DPM_TABLE_426__BAPM_TEMP_GRADIENT_MASK 0xffffffff 3270 + #define DPM_TABLE_426__BAPM_TEMP_GRADIENT__SHIFT 0x0 3271 + #define DPM_TABLE_427__LowSclkInterruptThreshold_MASK 0xffffffff 3272 + #define DPM_TABLE_427__LowSclkInterruptThreshold__SHIFT 0x0 3273 + #define DPM_TABLE_428__VddGfxReChkWait_MASK 0xffffffff 3274 + #define DPM_TABLE_428__VddGfxReChkWait__SHIFT 0x0 3275 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1_MASK 0xff 3276 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1__SHIFT 0x0 3277 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0_MASK 0xff00 3278 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0__SHIFT 0x8 3279 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID_MASK 0xff0000 3280 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID__SHIFT 0x10 3281 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID_MASK 0xff000000 3282 + #define DPM_TABLE_429__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID__SHIFT 0x18 3283 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3_MASK 0xff 3284 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3__SHIFT 0x0 3285 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2_MASK 0xff00 3286 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2__SHIFT 0x8 3287 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1_MASK 0xff0000 3288 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1__SHIFT 0x10 3289 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0_MASK 0xff000000 3290 + #define DPM_TABLE_430__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0__SHIFT 0x18 3291 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7_MASK 0xff 3292 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7__SHIFT 0x0 3293 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6_MASK 0xff00 3294 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6__SHIFT 0x8 3295 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5_MASK 0xff0000 3296 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5__SHIFT 0x10 3297 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4_MASK 0xff000000 3298 + #define DPM_TABLE_431__ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4__SHIFT 0x18 3299 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1_MASK 0xff 3300 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1__SHIFT 0x0 3301 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0_MASK 0xff00 3302 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0__SHIFT 0x8 3303 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID_MASK 0xff0000 3304 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID__SHIFT 0x10 3305 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID_MASK 0xff000000 3306 + #define DPM_TABLE_432__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID__SHIFT 0x18 3307 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3_MASK 0xff 3308 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3__SHIFT 0x0 3309 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2_MASK 0xff00 3310 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2__SHIFT 0x8 3311 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1_MASK 0xff0000 3312 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1__SHIFT 0x10 3313 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0_MASK 0xff000000 3314 + #define DPM_TABLE_433__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0__SHIFT 0x18 3315 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7_MASK 0xff 3316 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7__SHIFT 0x0 3317 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6_MASK 0xff00 3318 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6__SHIFT 0x8 3319 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5_MASK 0xff0000 3320 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5__SHIFT 0x10 3321 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4_MASK 0xff000000 3322 + #define DPM_TABLE_434__ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4__SHIFT 0x18 3323 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1_MASK 0xff 3324 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1__SHIFT 0x0 3325 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0_MASK 0xff00 3326 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0__SHIFT 0x8 3327 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID_MASK 0xff0000 3328 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID__SHIFT 0x10 3329 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID_MASK 0xff000000 3330 + #define DPM_TABLE_435__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID__SHIFT 0x18 3331 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3_MASK 0xff 3332 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3__SHIFT 0x0 3333 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2_MASK 0xff00 3334 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2__SHIFT 0x8 3335 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1_MASK 0xff0000 3336 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1__SHIFT 0x10 3337 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0_MASK 0xff000000 3338 + #define DPM_TABLE_436__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0__SHIFT 0x18 3339 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7_MASK 0xff 3340 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7__SHIFT 0x0 3341 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6_MASK 0xff00 3342 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6__SHIFT 0x8 3343 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5_MASK 0xff0000 3344 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5__SHIFT 0x10 3345 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4_MASK 0xff000000 3346 + #define DPM_TABLE_437__ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4__SHIFT 0x18 3347 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1_MASK 0xff 3348 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1__SHIFT 0x0 3349 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0_MASK 0xff00 3350 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0__SHIFT 0x8 3351 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID_MASK 0xff0000 3352 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID__SHIFT 0x10 3353 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID_MASK 0xff000000 3354 + #define DPM_TABLE_438__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID__SHIFT 0x18 3355 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3_MASK 0xff 3356 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3__SHIFT 0x0 3357 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2_MASK 0xff00 3358 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2__SHIFT 0x8 3359 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1_MASK 0xff0000 3360 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1__SHIFT 0x10 3361 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0_MASK 0xff000000 3362 + #define DPM_TABLE_439__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0__SHIFT 0x18 3363 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7_MASK 0xff 3364 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7__SHIFT 0x0 3365 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6_MASK 0xff00 3366 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6__SHIFT 0x8 3367 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5_MASK 0xff0000 3368 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5__SHIFT 0x10 3369 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4_MASK 0xff000000 3370 + #define DPM_TABLE_440__ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4__SHIFT 0x18 3371 + #define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff 3372 + #define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0 3373 + #define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff 3374 + #define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0 3375 + #define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff 3376 + #define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0 3377 + #define SOFT_REGISTERS_TABLE_4__PreVBlankGap_MASK 0xffffffff 3378 + #define SOFT_REGISTERS_TABLE_4__PreVBlankGap__SHIFT 0x0 3379 + #define SOFT_REGISTERS_TABLE_5__VBlankTimeout_MASK 0xffffffff 3380 + #define SOFT_REGISTERS_TABLE_5__VBlankTimeout__SHIFT 0x0 3381 + #define SOFT_REGISTERS_TABLE_6__TrainTimeGap_MASK 0xffffffff 3382 + #define SOFT_REGISTERS_TABLE_6__TrainTimeGap__SHIFT 0x0 3383 + #define SOFT_REGISTERS_TABLE_7__MvddSwitchTime_MASK 0xffffffff 3384 + #define SOFT_REGISTERS_TABLE_7__MvddSwitchTime__SHIFT 0x0 3385 + #define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime_MASK 0xffffffff 3386 + #define SOFT_REGISTERS_TABLE_8__LongestAcpiTrainTime__SHIFT 0x0 3387 + #define SOFT_REGISTERS_TABLE_9__AcpiDelay_MASK 0xffffffff 3388 + #define SOFT_REGISTERS_TABLE_9__AcpiDelay__SHIFT 0x0 3389 + #define SOFT_REGISTERS_TABLE_10__G5TrainTime_MASK 0xffffffff 3390 + #define SOFT_REGISTERS_TABLE_10__G5TrainTime__SHIFT 0x0 3391 + #define SOFT_REGISTERS_TABLE_11__DelayMpllPwron_MASK 0xffffffff 3392 + #define SOFT_REGISTERS_TABLE_11__DelayMpllPwron__SHIFT 0x0 3393 + #define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout_MASK 0xffffffff 3394 + #define SOFT_REGISTERS_TABLE_12__VoltageChangeTimeout__SHIFT 0x0 3395 + #define SOFT_REGISTERS_TABLE_13__HandshakeDisables_MASK 0xffffffff 3396 + #define SOFT_REGISTERS_TABLE_13__HandshakeDisables__SHIFT 0x0 3397 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff 3398 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config__SHIFT 0x0 3399 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config_MASK 0xff00 3400 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy3Config__SHIFT 0x8 3401 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config_MASK 0xff0000 3402 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy2Config__SHIFT 0x10 3403 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config_MASK 0xff000000 3404 + #define SOFT_REGISTERS_TABLE_14__DisplayPhy1Config__SHIFT 0x18 3405 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config_MASK 0xff 3406 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy8Config__SHIFT 0x0 3407 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 3408 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config__SHIFT 0x8 3409 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 3410 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config__SHIFT 0x10 3411 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config_MASK 0xff000000 3412 + #define SOFT_REGISTERS_TABLE_15__DisplayPhy5Config__SHIFT 0x18 3413 + #define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity_MASK 0xffffffff 3414 + #define SOFT_REGISTERS_TABLE_16__AverageGraphicsActivity__SHIFT 0x0 3415 + #define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity_MASK 0xffffffff 3416 + #define SOFT_REGISTERS_TABLE_17__AverageMemoryActivity__SHIFT 0x0 3417 + #define SOFT_REGISTERS_TABLE_18__AverageGioActivity_MASK 0xffffffff 3418 + #define SOFT_REGISTERS_TABLE_18__AverageGioActivity__SHIFT 0x0 3419 + #define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels_MASK 0xff 3420 + #define SOFT_REGISTERS_TABLE_19__PCIeDpmEnabledLevels__SHIFT 0x0 3421 + #define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels_MASK 0xff00 3422 + #define SOFT_REGISTERS_TABLE_19__LClkDpmEnabledLevels__SHIFT 0x8 3423 + #define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels_MASK 0xff0000 3424 + #define SOFT_REGISTERS_TABLE_19__MClkDpmEnabledLevels__SHIFT 0x10 3425 + #define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels_MASK 0xff000000 3426 + #define SOFT_REGISTERS_TABLE_19__SClkDpmEnabledLevels__SHIFT 0x18 3427 + #define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels_MASK 0xff 3428 + #define SOFT_REGISTERS_TABLE_20__VCEDpmEnabledLevels__SHIFT 0x0 3429 + #define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels_MASK 0xff00 3430 + #define SOFT_REGISTERS_TABLE_20__ACPDpmEnabledLevels__SHIFT 0x8 3431 + #define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels_MASK 0xff0000 3432 + #define SOFT_REGISTERS_TABLE_20__SAMUDpmEnabledLevels__SHIFT 0x10 3433 + #define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels_MASK 0xff000000 3434 + #define SOFT_REGISTERS_TABLE_20__UVDDpmEnabledLevels__SHIFT 0x18 3435 + #define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H_MASK 0xffffffff 3436 + #define SOFT_REGISTERS_TABLE_21__DRAM_LOG_ADDR_H__SHIFT 0x0 3437 + #define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L_MASK 0xffffffff 3438 + #define SOFT_REGISTERS_TABLE_22__DRAM_LOG_ADDR_L__SHIFT 0x0 3439 + #define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H_MASK 0xffffffff 3440 + #define SOFT_REGISTERS_TABLE_23__DRAM_LOG_PHY_ADDR_H__SHIFT 0x0 3441 + #define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L_MASK 0xffffffff 3442 + #define SOFT_REGISTERS_TABLE_24__DRAM_LOG_PHY_ADDR_L__SHIFT 0x0 3443 + #define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE_MASK 0xffffffff 3444 + #define SOFT_REGISTERS_TABLE_25__DRAM_LOG_BUFF_SIZE__SHIFT 0x0 3445 + #define SOFT_REGISTERS_TABLE_26__UlvEnterCount_MASK 0xffffffff 3446 + #define SOFT_REGISTERS_TABLE_26__UlvEnterCount__SHIFT 0x0 3447 + #define SOFT_REGISTERS_TABLE_27__UlvTime_MASK 0xffffffff 3448 + #define SOFT_REGISTERS_TABLE_27__UlvTime__SHIFT 0x0 3449 + #define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus_MASK 0xffffffff 3450 + #define SOFT_REGISTERS_TABLE_28__UcodeLoadStatus__SHIFT 0x0 3451 + #define SOFT_REGISTERS_TABLE_29__Reserved_0_MASK 0xffffffff 3452 + #define SOFT_REGISTERS_TABLE_29__Reserved_0__SHIFT 0x0 3453 + #define SOFT_REGISTERS_TABLE_30__Reserved_1_MASK 0xffffffff 3454 + #define SOFT_REGISTERS_TABLE_30__Reserved_1__SHIFT 0x0 3455 + #define PM_FUSES_1__SviLoadLineOffsetVddC_MASK 0xff 3456 + #define PM_FUSES_1__SviLoadLineOffsetVddC__SHIFT 0x0 3457 + #define PM_FUSES_1__SviLoadLineTrimVddC_MASK 0xff00 3458 + #define PM_FUSES_1__SviLoadLineTrimVddC__SHIFT 0x8 3459 + #define PM_FUSES_1__SviLoadLineVddC_MASK 0xff0000 3460 + #define PM_FUSES_1__SviLoadLineVddC__SHIFT 0x10 3461 + #define PM_FUSES_1__SviLoadLineEn_MASK 0xff000000 3462 + #define PM_FUSES_1__SviLoadLineEn__SHIFT 0x18 3463 + #define PM_FUSES_2__TDC_MAWt_MASK 0xff 3464 + #define PM_FUSES_2__TDC_MAWt__SHIFT 0x0 3465 + #define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc_MASK 0xff00 3466 + #define PM_FUSES_2__TDC_VDDC_ThrottleReleaseLimitPerc__SHIFT 0x8 3467 + #define PM_FUSES_2__TDC_VDDC_PkgLimit_MASK 0xffff0000 3468 + #define PM_FUSES_2__TDC_VDDC_PkgLimit__SHIFT 0x10 3469 + #define PM_FUSES_3__Reserved_MASK 0xff 3470 + #define PM_FUSES_3__Reserved__SHIFT 0x0 3471 + #define PM_FUSES_3__LPMLTemperatureMax_MASK 0xff00 3472 + #define PM_FUSES_3__LPMLTemperatureMax__SHIFT 0x8 3473 + #define PM_FUSES_3__LPMLTemperatureMin_MASK 0xff0000 3474 + #define PM_FUSES_3__LPMLTemperatureMin__SHIFT 0x10 3475 + #define PM_FUSES_3__TdcWaterfallCtl_MASK 0xff000000 3476 + #define PM_FUSES_3__TdcWaterfallCtl__SHIFT 0x18 3477 + #define PM_FUSES_4__LPMLTemperatureScaler_3_MASK 0xff 3478 + #define PM_FUSES_4__LPMLTemperatureScaler_3__SHIFT 0x0 3479 + #define PM_FUSES_4__LPMLTemperatureScaler_2_MASK 0xff00 3480 + #define PM_FUSES_4__LPMLTemperatureScaler_2__SHIFT 0x8 3481 + #define PM_FUSES_4__LPMLTemperatureScaler_1_MASK 0xff0000 3482 + #define PM_FUSES_4__LPMLTemperatureScaler_1__SHIFT 0x10 3483 + #define PM_FUSES_4__LPMLTemperatureScaler_0_MASK 0xff000000 3484 + #define PM_FUSES_4__LPMLTemperatureScaler_0__SHIFT 0x18 3485 + #define PM_FUSES_5__LPMLTemperatureScaler_7_MASK 0xff 3486 + #define PM_FUSES_5__LPMLTemperatureScaler_7__SHIFT 0x0 3487 + #define PM_FUSES_5__LPMLTemperatureScaler_6_MASK 0xff00 3488 + #define PM_FUSES_5__LPMLTemperatureScaler_6__SHIFT 0x8 3489 + #define PM_FUSES_5__LPMLTemperatureScaler_5_MASK 0xff0000 3490 + #define PM_FUSES_5__LPMLTemperatureScaler_5__SHIFT 0x10 3491 + #define PM_FUSES_5__LPMLTemperatureScaler_4_MASK 0xff000000 3492 + #define PM_FUSES_5__LPMLTemperatureScaler_4__SHIFT 0x18 3493 + #define PM_FUSES_6__LPMLTemperatureScaler_11_MASK 0xff 3494 + #define PM_FUSES_6__LPMLTemperatureScaler_11__SHIFT 0x0 3495 + #define PM_FUSES_6__LPMLTemperatureScaler_10_MASK 0xff00 3496 + #define PM_FUSES_6__LPMLTemperatureScaler_10__SHIFT 0x8 3497 + #define PM_FUSES_6__LPMLTemperatureScaler_9_MASK 0xff0000 3498 + #define PM_FUSES_6__LPMLTemperatureScaler_9__SHIFT 0x10 3499 + #define PM_FUSES_6__LPMLTemperatureScaler_8_MASK 0xff000000 3500 + #define PM_FUSES_6__LPMLTemperatureScaler_8__SHIFT 0x18 3501 + #define PM_FUSES_7__LPMLTemperatureScaler_15_MASK 0xff 3502 + #define PM_FUSES_7__LPMLTemperatureScaler_15__SHIFT 0x0 3503 + #define PM_FUSES_7__LPMLTemperatureScaler_14_MASK 0xff00 3504 + #define PM_FUSES_7__LPMLTemperatureScaler_14__SHIFT 0x8 3505 + #define PM_FUSES_7__LPMLTemperatureScaler_13_MASK 0xff0000 3506 + #define PM_FUSES_7__LPMLTemperatureScaler_13__SHIFT 0x10 3507 + #define PM_FUSES_7__LPMLTemperatureScaler_12_MASK 0xff000000 3508 + #define PM_FUSES_7__LPMLTemperatureScaler_12__SHIFT 0x18 3509 + #define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta_MASK 0xffff 3510 + #define PM_FUSES_8__FuzzyFan_ErrorRateSetDelta__SHIFT 0x0 3511 + #define PM_FUSES_8__FuzzyFan_ErrorSetDelta_MASK 0xffff0000 3512 + #define PM_FUSES_8__FuzzyFan_ErrorSetDelta__SHIFT 0x10 3513 + #define PM_FUSES_9__Reserved6_MASK 0xffff 3514 + #define PM_FUSES_9__Reserved6__SHIFT 0x0 3515 + #define PM_FUSES_9__FuzzyFan_PwmSetDelta_MASK 0xffff0000 3516 + #define PM_FUSES_9__FuzzyFan_PwmSetDelta__SHIFT 0x10 3517 + #define PM_FUSES_10__GnbLPML_3_MASK 0xff 3518 + #define PM_FUSES_10__GnbLPML_3__SHIFT 0x0 3519 + #define PM_FUSES_10__GnbLPML_2_MASK 0xff00 3520 + #define PM_FUSES_10__GnbLPML_2__SHIFT 0x8 3521 + #define PM_FUSES_10__GnbLPML_1_MASK 0xff0000 3522 + #define PM_FUSES_10__GnbLPML_1__SHIFT 0x10 3523 + #define PM_FUSES_10__GnbLPML_0_MASK 0xff000000 3524 + #define PM_FUSES_10__GnbLPML_0__SHIFT 0x18 3525 + #define PM_FUSES_11__GnbLPML_7_MASK 0xff 3526 + #define PM_FUSES_11__GnbLPML_7__SHIFT 0x0 3527 + #define PM_FUSES_11__GnbLPML_6_MASK 0xff00 3528 + #define PM_FUSES_11__GnbLPML_6__SHIFT 0x8 3529 + #define PM_FUSES_11__GnbLPML_5_MASK 0xff0000 3530 + #define PM_FUSES_11__GnbLPML_5__SHIFT 0x10 3531 + #define PM_FUSES_11__GnbLPML_4_MASK 0xff000000 3532 + #define PM_FUSES_11__GnbLPML_4__SHIFT 0x18 3533 + #define PM_FUSES_12__GnbLPML_11_MASK 0xff 3534 + #define PM_FUSES_12__GnbLPML_11__SHIFT 0x0 3535 + #define PM_FUSES_12__GnbLPML_10_MASK 0xff00 3536 + #define PM_FUSES_12__GnbLPML_10__SHIFT 0x8 3537 + #define PM_FUSES_12__GnbLPML_9_MASK 0xff0000 3538 + #define PM_FUSES_12__GnbLPML_9__SHIFT 0x10 3539 + #define PM_FUSES_12__GnbLPML_8_MASK 0xff000000 3540 + #define PM_FUSES_12__GnbLPML_8__SHIFT 0x18 3541 + #define PM_FUSES_13__GnbLPML_15_MASK 0xff 3542 + #define PM_FUSES_13__GnbLPML_15__SHIFT 0x0 3543 + #define PM_FUSES_13__GnbLPML_14_MASK 0xff00 3544 + #define PM_FUSES_13__GnbLPML_14__SHIFT 0x8 3545 + #define PM_FUSES_13__GnbLPML_13_MASK 0xff0000 3546 + #define PM_FUSES_13__GnbLPML_13__SHIFT 0x10 3547 + #define PM_FUSES_13__GnbLPML_12_MASK 0xff000000 3548 + #define PM_FUSES_13__GnbLPML_12__SHIFT 0x18 3549 + #define PM_FUSES_14__Reserved1_1_MASK 0xff 3550 + #define PM_FUSES_14__Reserved1_1__SHIFT 0x0 3551 + #define PM_FUSES_14__Reserved1_0_MASK 0xff00 3552 + #define PM_FUSES_14__Reserved1_0__SHIFT 0x8 3553 + #define PM_FUSES_14__GnbLPMLMinVid_MASK 0xff0000 3554 + #define PM_FUSES_14__GnbLPMLMinVid__SHIFT 0x10 3555 + #define PM_FUSES_14__GnbLPMLMaxVid_MASK 0xff000000 3556 + #define PM_FUSES_14__GnbLPMLMaxVid__SHIFT 0x18 3557 + #define PM_FUSES_15__BapmVddCBaseLeakageLoSidd_MASK 0xffff 3558 + #define PM_FUSES_15__BapmVddCBaseLeakageLoSidd__SHIFT 0x0 3559 + #define PM_FUSES_15__BapmVddCBaseLeakageHiSidd_MASK 0xffff0000 3560 + #define PM_FUSES_15__BapmVddCBaseLeakageHiSidd__SHIFT 0x10 3561 + #define SMU_PM_STATUS_0__DATA_MASK 0xffffffff 3562 + #define SMU_PM_STATUS_0__DATA__SHIFT 0x0 3563 + #define SMU_PM_STATUS_1__DATA_MASK 0xffffffff 3564 + #define SMU_PM_STATUS_1__DATA__SHIFT 0x0 3565 + #define SMU_PM_STATUS_2__DATA_MASK 0xffffffff 3566 + #define SMU_PM_STATUS_2__DATA__SHIFT 0x0 3567 + #define SMU_PM_STATUS_3__DATA_MASK 0xffffffff 3568 + #define SMU_PM_STATUS_3__DATA__SHIFT 0x0 3569 + #define SMU_PM_STATUS_4__DATA_MASK 0xffffffff 3570 + #define SMU_PM_STATUS_4__DATA__SHIFT 0x0 3571 + #define SMU_PM_STATUS_5__DATA_MASK 0xffffffff 3572 + #define SMU_PM_STATUS_5__DATA__SHIFT 0x0 3573 + #define SMU_PM_STATUS_6__DATA_MASK 0xffffffff 3574 + #define SMU_PM_STATUS_6__DATA__SHIFT 0x0 3575 + #define SMU_PM_STATUS_7__DATA_MASK 0xffffffff 3576 + #define SMU_PM_STATUS_7__DATA__SHIFT 0x0 3577 + #define SMU_PM_STATUS_8__DATA_MASK 0xffffffff 3578 + #define SMU_PM_STATUS_8__DATA__SHIFT 0x0 3579 + #define SMU_PM_STATUS_9__DATA_MASK 0xffffffff 3580 + #define SMU_PM_STATUS_9__DATA__SHIFT 0x0 3581 + #define SMU_PM_STATUS_10__DATA_MASK 0xffffffff 3582 + #define SMU_PM_STATUS_10__DATA__SHIFT 0x0 3583 + #define SMU_PM_STATUS_11__DATA_MASK 0xffffffff 3584 + #define SMU_PM_STATUS_11__DATA__SHIFT 0x0 3585 + #define SMU_PM_STATUS_12__DATA_MASK 0xffffffff 3586 + #define SMU_PM_STATUS_12__DATA__SHIFT 0x0 3587 + #define SMU_PM_STATUS_13__DATA_MASK 0xffffffff 3588 + #define SMU_PM_STATUS_13__DATA__SHIFT 0x0 3589 + #define SMU_PM_STATUS_14__DATA_MASK 0xffffffff 3590 + #define SMU_PM_STATUS_14__DATA__SHIFT 0x0 3591 + #define SMU_PM_STATUS_15__DATA_MASK 0xffffffff 3592 + #define SMU_PM_STATUS_15__DATA__SHIFT 0x0 3593 + #define SMU_PM_STATUS_16__DATA_MASK 0xffffffff 3594 + #define SMU_PM_STATUS_16__DATA__SHIFT 0x0 3595 + #define SMU_PM_STATUS_17__DATA_MASK 0xffffffff 3596 + #define SMU_PM_STATUS_17__DATA__SHIFT 0x0 3597 + #define SMU_PM_STATUS_18__DATA_MASK 0xffffffff 3598 + #define SMU_PM_STATUS_18__DATA__SHIFT 0x0 3599 + #define SMU_PM_STATUS_19__DATA_MASK 0xffffffff 3600 + #define SMU_PM_STATUS_19__DATA__SHIFT 0x0 3601 + #define SMU_PM_STATUS_20__DATA_MASK 0xffffffff 3602 + #define SMU_PM_STATUS_20__DATA__SHIFT 0x0 3603 + #define SMU_PM_STATUS_21__DATA_MASK 0xffffffff 3604 + #define SMU_PM_STATUS_21__DATA__SHIFT 0x0 3605 + #define SMU_PM_STATUS_22__DATA_MASK 0xffffffff 3606 + #define SMU_PM_STATUS_22__DATA__SHIFT 0x0 3607 + #define SMU_PM_STATUS_23__DATA_MASK 0xffffffff 3608 + #define SMU_PM_STATUS_23__DATA__SHIFT 0x0 3609 + #define SMU_PM_STATUS_24__DATA_MASK 0xffffffff 3610 + #define SMU_PM_STATUS_24__DATA__SHIFT 0x0 3611 + #define SMU_PM_STATUS_25__DATA_MASK 0xffffffff 3612 + #define SMU_PM_STATUS_25__DATA__SHIFT 0x0 3613 + #define SMU_PM_STATUS_26__DATA_MASK 0xffffffff 3614 + #define SMU_PM_STATUS_26__DATA__SHIFT 0x0 3615 + #define SMU_PM_STATUS_27__DATA_MASK 0xffffffff 3616 + #define SMU_PM_STATUS_27__DATA__SHIFT 0x0 3617 + #define SMU_PM_STATUS_28__DATA_MASK 0xffffffff 3618 + #define SMU_PM_STATUS_28__DATA__SHIFT 0x0 3619 + #define SMU_PM_STATUS_29__DATA_MASK 0xffffffff 3620 + #define SMU_PM_STATUS_29__DATA__SHIFT 0x0 3621 + #define SMU_PM_STATUS_30__DATA_MASK 0xffffffff 3622 + #define SMU_PM_STATUS_30__DATA__SHIFT 0x0 3623 + #define SMU_PM_STATUS_31__DATA_MASK 0xffffffff 3624 + #define SMU_PM_STATUS_31__DATA__SHIFT 0x0 3625 + #define SMU_PM_STATUS_32__DATA_MASK 0xffffffff 3626 + #define SMU_PM_STATUS_32__DATA__SHIFT 0x0 3627 + #define SMU_PM_STATUS_33__DATA_MASK 0xffffffff 3628 + #define SMU_PM_STATUS_33__DATA__SHIFT 0x0 3629 + #define SMU_PM_STATUS_34__DATA_MASK 0xffffffff 3630 + #define SMU_PM_STATUS_34__DATA__SHIFT 0x0 3631 + #define SMU_PM_STATUS_35__DATA_MASK 0xffffffff 3632 + #define SMU_PM_STATUS_35__DATA__SHIFT 0x0 3633 + #define SMU_PM_STATUS_36__DATA_MASK 0xffffffff 3634 + #define SMU_PM_STATUS_36__DATA__SHIFT 0x0 3635 + #define SMU_PM_STATUS_37__DATA_MASK 0xffffffff 3636 + #define SMU_PM_STATUS_37__DATA__SHIFT 0x0 3637 + #define SMU_PM_STATUS_38__DATA_MASK 0xffffffff 3638 + #define SMU_PM_STATUS_38__DATA__SHIFT 0x0 3639 + #define SMU_PM_STATUS_39__DATA_MASK 0xffffffff 3640 + #define SMU_PM_STATUS_39__DATA__SHIFT 0x0 3641 + #define SMU_PM_STATUS_40__DATA_MASK 0xffffffff 3642 + #define SMU_PM_STATUS_40__DATA__SHIFT 0x0 3643 + #define SMU_PM_STATUS_41__DATA_MASK 0xffffffff 3644 + #define SMU_PM_STATUS_41__DATA__SHIFT 0x0 3645 + #define SMU_PM_STATUS_42__DATA_MASK 0xffffffff 3646 + #define SMU_PM_STATUS_42__DATA__SHIFT 0x0 3647 + #define SMU_PM_STATUS_43__DATA_MASK 0xffffffff 3648 + #define SMU_PM_STATUS_43__DATA__SHIFT 0x0 3649 + #define SMU_PM_STATUS_44__DATA_MASK 0xffffffff 3650 + #define SMU_PM_STATUS_44__DATA__SHIFT 0x0 3651 + #define SMU_PM_STATUS_45__DATA_MASK 0xffffffff 3652 + #define SMU_PM_STATUS_45__DATA__SHIFT 0x0 3653 + #define SMU_PM_STATUS_46__DATA_MASK 0xffffffff 3654 + #define SMU_PM_STATUS_46__DATA__SHIFT 0x0 3655 + #define SMU_PM_STATUS_47__DATA_MASK 0xffffffff 3656 + #define SMU_PM_STATUS_47__DATA__SHIFT 0x0 3657 + #define SMU_PM_STATUS_48__DATA_MASK 0xffffffff 3658 + #define SMU_PM_STATUS_48__DATA__SHIFT 0x0 3659 + #define SMU_PM_STATUS_49__DATA_MASK 0xffffffff 3660 + #define SMU_PM_STATUS_49__DATA__SHIFT 0x0 3661 + #define SMU_PM_STATUS_50__DATA_MASK 0xffffffff 3662 + #define SMU_PM_STATUS_50__DATA__SHIFT 0x0 3663 + #define SMU_PM_STATUS_51__DATA_MASK 0xffffffff 3664 + #define SMU_PM_STATUS_51__DATA__SHIFT 0x0 3665 + #define SMU_PM_STATUS_52__DATA_MASK 0xffffffff 3666 + #define SMU_PM_STATUS_52__DATA__SHIFT 0x0 3667 + #define SMU_PM_STATUS_53__DATA_MASK 0xffffffff 3668 + #define SMU_PM_STATUS_53__DATA__SHIFT 0x0 3669 + #define SMU_PM_STATUS_54__DATA_MASK 0xffffffff 3670 + #define SMU_PM_STATUS_54__DATA__SHIFT 0x0 3671 + #define SMU_PM_STATUS_55__DATA_MASK 0xffffffff 3672 + #define SMU_PM_STATUS_55__DATA__SHIFT 0x0 3673 + #define SMU_PM_STATUS_56__DATA_MASK 0xffffffff 3674 + #define SMU_PM_STATUS_56__DATA__SHIFT 0x0 3675 + #define SMU_PM_STATUS_57__DATA_MASK 0xffffffff 3676 + #define SMU_PM_STATUS_57__DATA__SHIFT 0x0 3677 + #define SMU_PM_STATUS_58__DATA_MASK 0xffffffff 3678 + #define SMU_PM_STATUS_58__DATA__SHIFT 0x0 3679 + #define SMU_PM_STATUS_59__DATA_MASK 0xffffffff 3680 + #define SMU_PM_STATUS_59__DATA__SHIFT 0x0 3681 + #define SMU_PM_STATUS_60__DATA_MASK 0xffffffff 3682 + #define SMU_PM_STATUS_60__DATA__SHIFT 0x0 3683 + #define SMU_PM_STATUS_61__DATA_MASK 0xffffffff 3684 + #define SMU_PM_STATUS_61__DATA__SHIFT 0x0 3685 + #define SMU_PM_STATUS_62__DATA_MASK 0xffffffff 3686 + #define SMU_PM_STATUS_62__DATA__SHIFT 0x0 3687 + #define SMU_PM_STATUS_63__DATA_MASK 0xffffffff 3688 + #define SMU_PM_STATUS_63__DATA__SHIFT 0x0 3689 + #define SMU_PM_STATUS_64__DATA_MASK 0xffffffff 3690 + #define SMU_PM_STATUS_64__DATA__SHIFT 0x0 3691 + #define SMU_PM_STATUS_65__DATA_MASK 0xffffffff 3692 + #define SMU_PM_STATUS_65__DATA__SHIFT 0x0 3693 + #define SMU_PM_STATUS_66__DATA_MASK 0xffffffff 3694 + #define SMU_PM_STATUS_66__DATA__SHIFT 0x0 3695 + #define SMU_PM_STATUS_67__DATA_MASK 0xffffffff 3696 + #define SMU_PM_STATUS_67__DATA__SHIFT 0x0 3697 + #define SMU_PM_STATUS_68__DATA_MASK 0xffffffff 3698 + #define SMU_PM_STATUS_68__DATA__SHIFT 0x0 3699 + #define SMU_PM_STATUS_69__DATA_MASK 0xffffffff 3700 + #define SMU_PM_STATUS_69__DATA__SHIFT 0x0 3701 + #define SMU_PM_STATUS_70__DATA_MASK 0xffffffff 3702 + #define SMU_PM_STATUS_70__DATA__SHIFT 0x0 3703 + #define SMU_PM_STATUS_71__DATA_MASK 0xffffffff 3704 + #define SMU_PM_STATUS_71__DATA__SHIFT 0x0 3705 + #define SMU_PM_STATUS_72__DATA_MASK 0xffffffff 3706 + #define SMU_PM_STATUS_72__DATA__SHIFT 0x0 3707 + #define SMU_PM_STATUS_73__DATA_MASK 0xffffffff 3708 + #define SMU_PM_STATUS_73__DATA__SHIFT 0x0 3709 + #define SMU_PM_STATUS_74__DATA_MASK 0xffffffff 3710 + #define SMU_PM_STATUS_74__DATA__SHIFT 0x0 3711 + #define SMU_PM_STATUS_75__DATA_MASK 0xffffffff 3712 + #define SMU_PM_STATUS_75__DATA__SHIFT 0x0 3713 + #define SMU_PM_STATUS_76__DATA_MASK 0xffffffff 3714 + #define SMU_PM_STATUS_76__DATA__SHIFT 0x0 3715 + #define SMU_PM_STATUS_77__DATA_MASK 0xffffffff 3716 + #define SMU_PM_STATUS_77__DATA__SHIFT 0x0 3717 + #define SMU_PM_STATUS_78__DATA_MASK 0xffffffff 3718 + #define SMU_PM_STATUS_78__DATA__SHIFT 0x0 3719 + #define SMU_PM_STATUS_79__DATA_MASK 0xffffffff 3720 + #define SMU_PM_STATUS_79__DATA__SHIFT 0x0 3721 + #define SMU_PM_STATUS_80__DATA_MASK 0xffffffff 3722 + #define SMU_PM_STATUS_80__DATA__SHIFT 0x0 3723 + #define SMU_PM_STATUS_81__DATA_MASK 0xffffffff 3724 + #define SMU_PM_STATUS_81__DATA__SHIFT 0x0 3725 + #define SMU_PM_STATUS_82__DATA_MASK 0xffffffff 3726 + #define SMU_PM_STATUS_82__DATA__SHIFT 0x0 3727 + #define SMU_PM_STATUS_83__DATA_MASK 0xffffffff 3728 + #define SMU_PM_STATUS_83__DATA__SHIFT 0x0 3729 + #define SMU_PM_STATUS_84__DATA_MASK 0xffffffff 3730 + #define SMU_PM_STATUS_84__DATA__SHIFT 0x0 3731 + #define SMU_PM_STATUS_85__DATA_MASK 0xffffffff 3732 + #define SMU_PM_STATUS_85__DATA__SHIFT 0x0 3733 + #define SMU_PM_STATUS_86__DATA_MASK 0xffffffff 3734 + #define SMU_PM_STATUS_86__DATA__SHIFT 0x0 3735 + #define SMU_PM_STATUS_87__DATA_MASK 0xffffffff 3736 + #define SMU_PM_STATUS_87__DATA__SHIFT 0x0 3737 + #define SMU_PM_STATUS_88__DATA_MASK 0xffffffff 3738 + #define SMU_PM_STATUS_88__DATA__SHIFT 0x0 3739 + #define SMU_PM_STATUS_89__DATA_MASK 0xffffffff 3740 + #define SMU_PM_STATUS_89__DATA__SHIFT 0x0 3741 + #define SMU_PM_STATUS_90__DATA_MASK 0xffffffff 3742 + #define SMU_PM_STATUS_90__DATA__SHIFT 0x0 3743 + #define SMU_PM_STATUS_91__DATA_MASK 0xffffffff 3744 + #define SMU_PM_STATUS_91__DATA__SHIFT 0x0 3745 + #define SMU_PM_STATUS_92__DATA_MASK 0xffffffff 3746 + #define SMU_PM_STATUS_92__DATA__SHIFT 0x0 3747 + #define SMU_PM_STATUS_93__DATA_MASK 0xffffffff 3748 + #define SMU_PM_STATUS_93__DATA__SHIFT 0x0 3749 + #define SMU_PM_STATUS_94__DATA_MASK 0xffffffff 3750 + #define SMU_PM_STATUS_94__DATA__SHIFT 0x0 3751 + #define SMU_PM_STATUS_95__DATA_MASK 0xffffffff 3752 + #define SMU_PM_STATUS_95__DATA__SHIFT 0x0 3753 + #define SMU_PM_STATUS_96__DATA_MASK 0xffffffff 3754 + #define SMU_PM_STATUS_96__DATA__SHIFT 0x0 3755 + #define SMU_PM_STATUS_97__DATA_MASK 0xffffffff 3756 + #define SMU_PM_STATUS_97__DATA__SHIFT 0x0 3757 + #define SMU_PM_STATUS_98__DATA_MASK 0xffffffff 3758 + #define SMU_PM_STATUS_98__DATA__SHIFT 0x0 3759 + #define SMU_PM_STATUS_99__DATA_MASK 0xffffffff 3760 + #define SMU_PM_STATUS_99__DATA__SHIFT 0x0 3761 + #define SMU_PM_STATUS_100__DATA_MASK 0xffffffff 3762 + #define SMU_PM_STATUS_100__DATA__SHIFT 0x0 3763 + #define SMU_PM_STATUS_101__DATA_MASK 0xffffffff 3764 + #define SMU_PM_STATUS_101__DATA__SHIFT 0x0 3765 + #define SMU_PM_STATUS_102__DATA_MASK 0xffffffff 3766 + #define SMU_PM_STATUS_102__DATA__SHIFT 0x0 3767 + #define SMU_PM_STATUS_103__DATA_MASK 0xffffffff 3768 + #define SMU_PM_STATUS_103__DATA__SHIFT 0x0 3769 + #define SMU_PM_STATUS_104__DATA_MASK 0xffffffff 3770 + #define SMU_PM_STATUS_104__DATA__SHIFT 0x0 3771 + #define SMU_PM_STATUS_105__DATA_MASK 0xffffffff 3772 + #define SMU_PM_STATUS_105__DATA__SHIFT 0x0 3773 + #define SMU_PM_STATUS_106__DATA_MASK 0xffffffff 3774 + #define SMU_PM_STATUS_106__DATA__SHIFT 0x0 3775 + #define SMU_PM_STATUS_107__DATA_MASK 0xffffffff 3776 + #define SMU_PM_STATUS_107__DATA__SHIFT 0x0 3777 + #define SMU_PM_STATUS_108__DATA_MASK 0xffffffff 3778 + #define SMU_PM_STATUS_108__DATA__SHIFT 0x0 3779 + #define SMU_PM_STATUS_109__DATA_MASK 0xffffffff 3780 + #define SMU_PM_STATUS_109__DATA__SHIFT 0x0 3781 + #define SMU_PM_STATUS_110__DATA_MASK 0xffffffff 3782 + #define SMU_PM_STATUS_110__DATA__SHIFT 0x0 3783 + #define SMU_PM_STATUS_111__DATA_MASK 0xffffffff 3784 + #define SMU_PM_STATUS_111__DATA__SHIFT 0x0 3785 + #define SMU_PM_STATUS_112__DATA_MASK 0xffffffff 3786 + #define SMU_PM_STATUS_112__DATA__SHIFT 0x0 3787 + #define SMU_PM_STATUS_113__DATA_MASK 0xffffffff 3788 + #define SMU_PM_STATUS_113__DATA__SHIFT 0x0 3789 + #define SMU_PM_STATUS_114__DATA_MASK 0xffffffff 3790 + #define SMU_PM_STATUS_114__DATA__SHIFT 0x0 3791 + #define SMU_PM_STATUS_115__DATA_MASK 0xffffffff 3792 + #define SMU_PM_STATUS_115__DATA__SHIFT 0x0 3793 + #define SMU_PM_STATUS_116__DATA_MASK 0xffffffff 3794 + #define SMU_PM_STATUS_116__DATA__SHIFT 0x0 3795 + #define SMU_PM_STATUS_117__DATA_MASK 0xffffffff 3796 + #define SMU_PM_STATUS_117__DATA__SHIFT 0x0 3797 + #define SMU_PM_STATUS_118__DATA_MASK 0xffffffff 3798 + #define SMU_PM_STATUS_118__DATA__SHIFT 0x0 3799 + #define SMU_PM_STATUS_119__DATA_MASK 0xffffffff 3800 + #define SMU_PM_STATUS_119__DATA__SHIFT 0x0 3801 + #define SMU_PM_STATUS_120__DATA_MASK 0xffffffff 3802 + #define SMU_PM_STATUS_120__DATA__SHIFT 0x0 3803 + #define SMU_PM_STATUS_121__DATA_MASK 0xffffffff 3804 + #define SMU_PM_STATUS_121__DATA__SHIFT 0x0 3805 + #define SMU_PM_STATUS_122__DATA_MASK 0xffffffff 3806 + #define SMU_PM_STATUS_122__DATA__SHIFT 0x0 3807 + #define SMU_PM_STATUS_123__DATA_MASK 0xffffffff 3808 + #define SMU_PM_STATUS_123__DATA__SHIFT 0x0 3809 + #define SMU_PM_STATUS_124__DATA_MASK 0xffffffff 3810 + #define SMU_PM_STATUS_124__DATA__SHIFT 0x0 3811 + #define SMU_PM_STATUS_125__DATA_MASK 0xffffffff 3812 + #define SMU_PM_STATUS_125__DATA__SHIFT 0x0 3813 + #define SMU_PM_STATUS_126__DATA_MASK 0xffffffff 3814 + #define SMU_PM_STATUS_126__DATA__SHIFT 0x0 3815 + #define SMU_PM_STATUS_127__DATA_MASK 0xffffffff 3816 + #define SMU_PM_STATUS_127__DATA__SHIFT 0x0 3817 + #define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1 3818 + #define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 3819 + #define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2 3820 + #define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 3821 + #define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4 3822 + #define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 3823 + #define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8 3824 + #define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 3825 + #define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10 3826 + #define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 3827 + #define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20 3828 + #define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 3829 + #define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff 3830 + #define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 3831 + #define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00 3832 + #define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 3833 + #define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000 3834 + #define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10 3835 + #define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000 3836 + #define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 3837 + #define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000 3838 + #define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 3839 + #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000 3840 + #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 3841 + #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000 3842 + #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b 3843 + #define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000 3844 + #define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c 3845 + #define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1 3846 + #define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 3847 + #define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2 3848 + #define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 3849 + #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4 3850 + #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 3851 + #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8 3852 + #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3 3853 + #define CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK 0x7 3854 + #define CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT 0x0 3855 + #define CG_THERMAL_CTRL__THERM_INC_CLK_MASK 0x8 3856 + #define CG_THERMAL_CTRL__THERM_INC_CLK__SHIFT 0x3 3857 + #define CG_THERMAL_CTRL__SPARE_MASK 0x3ff0 3858 + #define CG_THERMAL_CTRL__SPARE__SHIFT 0x4 3859 + #define CG_THERMAL_CTRL__DIG_THERM_DPM_MASK 0x3fc000 3860 + #define CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT 0xe 3861 + #define CG_THERMAL_CTRL__RESERVED_MASK 0x1c00000 3862 + #define CG_THERMAL_CTRL__RESERVED__SHIFT 0x16 3863 + #define CG_THERMAL_CTRL__CTF_PAD_POLARITY_MASK 0x2000000 3864 + #define CG_THERMAL_CTRL__CTF_PAD_POLARITY__SHIFT 0x19 3865 + #define CG_THERMAL_CTRL__CTF_PAD_EN_MASK 0x4000000 3866 + #define CG_THERMAL_CTRL__CTF_PAD_EN__SHIFT 0x1a 3867 + #define CG_THERMAL_STATUS__SPARE_MASK 0x1ff 3868 + #define CG_THERMAL_STATUS__SPARE__SHIFT 0x0 3869 + #define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x1fe00 3870 + #define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 3871 + #define CG_THERMAL_STATUS__THERM_ALERT_MASK 0x20000 3872 + #define CG_THERMAL_STATUS__THERM_ALERT__SHIFT 0x11 3873 + #define CG_THERMAL_STATUS__GEN_STATUS_MASK 0x3c0000 3874 + #define CG_THERMAL_STATUS__GEN_STATUS__SHIFT 0x12 3875 + #define CG_THERMAL_INT__DIG_THERM_CTF_MASK 0xff 3876 + #define CG_THERMAL_INT__DIG_THERM_CTF__SHIFT 0x0 3877 + #define CG_THERMAL_INT__DIG_THERM_INTH_MASK 0xff00 3878 + #define CG_THERMAL_INT__DIG_THERM_INTH__SHIFT 0x8 3879 + #define CG_THERMAL_INT__DIG_THERM_INTL_MASK 0xff0000 3880 + #define CG_THERMAL_INT__DIG_THERM_INTL__SHIFT 0x10 3881 + #define CG_THERMAL_INT__THERM_INT_MASK_MASK 0xf000000 3882 + #define CG_THERMAL_INT__THERM_INT_MASK__SHIFT 0x18 3883 + #define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0xf 3884 + #define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 3885 + #define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x1f0 3886 + #define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 3887 + #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x200 3888 + #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 3889 + #define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0xff00000 3890 + #define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 3891 + #define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR_MASK 0x10000000 3892 + #define CG_MULT_THERMAL_CTRL__THM_READY_CLEAR__SHIFT 0x1c 3893 + #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x1ff 3894 + #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 3895 + #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x3fe00 3896 + #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 3897 + #define THM_TMON2_CTRL__POWER_DOWN_MASK 0x1 3898 + #define THM_TMON2_CTRL__POWER_DOWN__SHIFT 0x0 3899 + #define THM_TMON2_CTRL__BGADJ_MASK 0x1fe 3900 + #define THM_TMON2_CTRL__BGADJ__SHIFT 0x1 3901 + #define THM_TMON2_CTRL__BGADJ_MODE_MASK 0x200 3902 + #define THM_TMON2_CTRL__BGADJ_MODE__SHIFT 0x9 3903 + #define THM_TMON2_CTRL__TMON_PAUSE_MASK 0x400 3904 + #define THM_TMON2_CTRL__TMON_PAUSE__SHIFT 0xa 3905 + #define THM_TMON2_CTRL__INT_MEAS_EN_MASK 0x800 3906 + #define THM_TMON2_CTRL__INT_MEAS_EN__SHIFT 0xb 3907 + #define THM_TMON2_CTRL__DEBUG_MODE_MASK 0x1000 3908 + #define THM_TMON2_CTRL__DEBUG_MODE__SHIFT 0xc 3909 + #define THM_TMON2_CTRL__EN_CFG_SERDES_MASK 0x2000 3910 + #define THM_TMON2_CTRL__EN_CFG_SERDES__SHIFT 0xd 3911 + #define THM_TMON2_CTRL2__RDIL_PRESENT_MASK 0xffff 3912 + #define THM_TMON2_CTRL2__RDIL_PRESENT__SHIFT 0x0 3913 + #define THM_TMON2_CTRL2__RDIR_PRESENT_MASK 0xffff0000 3914 + #define THM_TMON2_CTRL2__RDIR_PRESENT__SHIFT 0x10 3915 + #define THM_TMON2_CSR_WR__CSR_WRITE_MASK 0x1 3916 + #define THM_TMON2_CSR_WR__CSR_WRITE__SHIFT 0x0 3917 + #define THM_TMON2_CSR_WR__CSR_READ_MASK 0x2 3918 + #define THM_TMON2_CSR_WR__CSR_READ__SHIFT 0x1 3919 + #define THM_TMON2_CSR_WR__CSR_ADDR_MASK 0xffc 3920 + #define THM_TMON2_CSR_WR__CSR_ADDR__SHIFT 0x2 3921 + #define THM_TMON2_CSR_WR__WRITE_DATA_MASK 0xfff000 3922 + #define THM_TMON2_CSR_WR__WRITE_DATA__SHIFT 0xc 3923 + #define THM_TMON2_CSR_WR__SPARE_MASK 0x1000000 3924 + #define THM_TMON2_CSR_WR__SPARE__SHIFT 0x18 3925 + #define THM_TMON2_CSR_RD__READ_DATA_MASK 0xfff 3926 + #define THM_TMON2_CSR_RD__READ_DATA__SHIFT 0x0 3927 + #define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0xff 3928 + #define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 3929 + #define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0xff00 3930 + #define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 3931 + #define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x10000 3932 + #define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 3933 + #define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x7e0000 3934 + #define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 3935 + #define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x800000 3936 + #define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 3937 + #define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xff000000 3938 + #define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 3939 + #define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0xff 3940 + #define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 3941 + #define CG_FDO_CTRL1__FMIN_DUTY_MASK 0xff00 3942 + #define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 3943 + #define CG_FDO_CTRL1__M_MASK 0xff0000 3944 + #define CG_FDO_CTRL1__M__SHIFT 0x10 3945 + #define CG_FDO_CTRL1__RESERVED_MASK 0x3f000000 3946 + #define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 3947 + #define CG_FDO_CTRL1__FDO_PWRDNB_MASK 0x40000000 3948 + #define CG_FDO_CTRL1__FDO_PWRDNB__SHIFT 0x1e 3949 + #define CG_FDO_CTRL2__TMIN_MASK 0xff 3950 + #define CG_FDO_CTRL2__TMIN__SHIFT 0x0 3951 + #define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x700 3952 + #define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 3953 + #define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x3800 3954 + #define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 3955 + #define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x1c000 3956 + #define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 3957 + #define CG_FDO_CTRL2__TMAX_MASK 0x1fe0000 3958 + #define CG_FDO_CTRL2__TMAX__SHIFT 0x11 3959 + #define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xfe000000 3960 + #define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 3961 + #define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x7 3962 + #define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 3963 + #define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xfffffff8 3964 + #define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 3965 + #define CG_TACH_STATUS__TACH_PERIOD_MASK 0xffffffff 3966 + #define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 3967 + #define CC_THM_STRAPS0__TMON0_BGADJ_MASK 0x1fe 3968 + #define CC_THM_STRAPS0__TMON0_BGADJ__SHIFT 0x1 3969 + #define CC_THM_STRAPS0__TMON1_BGADJ_MASK 0x1fe00 3970 + #define CC_THM_STRAPS0__TMON1_BGADJ__SHIFT 0x9 3971 + #define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL_MASK 0x20000 3972 + #define CC_THM_STRAPS0__TMON_CMON_FUSE_SEL__SHIFT 0x11 3973 + #define CC_THM_STRAPS0__NUM_ACQ_MASK 0x1c0000 3974 + #define CC_THM_STRAPS0__NUM_ACQ__SHIFT 0x12 3975 + #define CC_THM_STRAPS0__TMON_CLK_SEL_MASK 0xe00000 3976 + #define CC_THM_STRAPS0__TMON_CLK_SEL__SHIFT 0x15 3977 + #define CC_THM_STRAPS0__TMON_CONFIG_SOURCE_MASK 0x1000000 3978 + #define CC_THM_STRAPS0__TMON_CONFIG_SOURCE__SHIFT 0x18 3979 + #define CC_THM_STRAPS0__CTF_DISABLE_MASK 0x2000000 3980 + #define CC_THM_STRAPS0__CTF_DISABLE__SHIFT 0x19 3981 + #define CC_THM_STRAPS0__TMON0_DISABLE_MASK 0x4000000 3982 + #define CC_THM_STRAPS0__TMON0_DISABLE__SHIFT 0x1a 3983 + #define CC_THM_STRAPS0__TMON1_DISABLE_MASK 0x8000000 3984 + #define CC_THM_STRAPS0__TMON1_DISABLE__SHIFT 0x1b 3985 + #define CC_THM_STRAPS0__TMON2_DISABLE_MASK 0x10000000 3986 + #define CC_THM_STRAPS0__TMON2_DISABLE__SHIFT 0x1c 3987 + #define CC_THM_STRAPS0__TMON3_DISABLE_MASK 0x20000000 3988 + #define CC_THM_STRAPS0__TMON3_DISABLE__SHIFT 0x1d 3989 + #define CC_THM_STRAPS0__UNUSED_MASK 0x80000000 3990 + #define CC_THM_STRAPS0__UNUSED__SHIFT 0x1f 3991 + #define THM_TMON0_RDIL0_DATA__Z_MASK 0x7ff 3992 + #define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 3993 + #define THM_TMON0_RDIL0_DATA__VALID_MASK 0x800 3994 + #define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 3995 + #define THM_TMON0_RDIL0_DATA__TEMP_MASK 0xfff000 3996 + #define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 3997 + #define THM_TMON0_RDIL1_DATA__Z_MASK 0x7ff 3998 + #define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 3999 + #define THM_TMON0_RDIL1_DATA__VALID_MASK 0x800 4000 + #define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 4001 + #define THM_TMON0_RDIL1_DATA__TEMP_MASK 0xfff000 4002 + #define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 4003 + #define THM_TMON0_RDIL2_DATA__Z_MASK 0x7ff 4004 + #define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 4005 + #define THM_TMON0_RDIL2_DATA__VALID_MASK 0x800 4006 + #define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 4007 + #define THM_TMON0_RDIL2_DATA__TEMP_MASK 0xfff000 4008 + #define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 4009 + #define THM_TMON0_RDIL3_DATA__Z_MASK 0x7ff 4010 + #define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 4011 + #define THM_TMON0_RDIL3_DATA__VALID_MASK 0x800 4012 + #define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 4013 + #define THM_TMON0_RDIL3_DATA__TEMP_MASK 0xfff000 4014 + #define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 4015 + #define THM_TMON0_RDIL4_DATA__Z_MASK 0x7ff 4016 + #define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 4017 + #define THM_TMON0_RDIL4_DATA__VALID_MASK 0x800 4018 + #define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 4019 + #define THM_TMON0_RDIL4_DATA__TEMP_MASK 0xfff000 4020 + #define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 4021 + #define THM_TMON0_RDIL5_DATA__Z_MASK 0x7ff 4022 + #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 4023 + #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x800 4024 + #define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 4025 + #define THM_TMON0_RDIL5_DATA__TEMP_MASK 0xfff000 4026 + #define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 4027 + #define THM_TMON0_RDIL6_DATA__Z_MASK 0x7ff 4028 + #define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 4029 + #define THM_TMON0_RDIL6_DATA__VALID_MASK 0x800 4030 + #define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 4031 + #define THM_TMON0_RDIL6_DATA__TEMP_MASK 0xfff000 4032 + #define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 4033 + #define THM_TMON0_RDIL7_DATA__Z_MASK 0x7ff 4034 + #define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 4035 + #define THM_TMON0_RDIL7_DATA__VALID_MASK 0x800 4036 + #define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 4037 + #define THM_TMON0_RDIL7_DATA__TEMP_MASK 0xfff000 4038 + #define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 4039 + #define THM_TMON0_RDIL8_DATA__Z_MASK 0x7ff 4040 + #define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 4041 + #define THM_TMON0_RDIL8_DATA__VALID_MASK 0x800 4042 + #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 4043 + #define THM_TMON0_RDIL8_DATA__TEMP_MASK 0xfff000 4044 + #define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 4045 + #define THM_TMON0_RDIL9_DATA__Z_MASK 0x7ff 4046 + #define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 4047 + #define THM_TMON0_RDIL9_DATA__VALID_MASK 0x800 4048 + #define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 4049 + #define THM_TMON0_RDIL9_DATA__TEMP_MASK 0xfff000 4050 + #define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 4051 + #define THM_TMON0_RDIL10_DATA__Z_MASK 0x7ff 4052 + #define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 4053 + #define THM_TMON0_RDIL10_DATA__VALID_MASK 0x800 4054 + #define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 4055 + #define THM_TMON0_RDIL10_DATA__TEMP_MASK 0xfff000 4056 + #define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 4057 + #define THM_TMON0_RDIL11_DATA__Z_MASK 0x7ff 4058 + #define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 4059 + #define THM_TMON0_RDIL11_DATA__VALID_MASK 0x800 4060 + #define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 4061 + #define THM_TMON0_RDIL11_DATA__TEMP_MASK 0xfff000 4062 + #define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 4063 + #define THM_TMON0_RDIL12_DATA__Z_MASK 0x7ff 4064 + #define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 4065 + #define THM_TMON0_RDIL12_DATA__VALID_MASK 0x800 4066 + #define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 4067 + #define THM_TMON0_RDIL12_DATA__TEMP_MASK 0xfff000 4068 + #define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 4069 + #define THM_TMON0_RDIL13_DATA__Z_MASK 0x7ff 4070 + #define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 4071 + #define THM_TMON0_RDIL13_DATA__VALID_MASK 0x800 4072 + #define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 4073 + #define THM_TMON0_RDIL13_DATA__TEMP_MASK 0xfff000 4074 + #define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 4075 + #define THM_TMON0_RDIL14_DATA__Z_MASK 0x7ff 4076 + #define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 4077 + #define THM_TMON0_RDIL14_DATA__VALID_MASK 0x800 4078 + #define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 4079 + #define THM_TMON0_RDIL14_DATA__TEMP_MASK 0xfff000 4080 + #define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 4081 + #define THM_TMON0_RDIL15_DATA__Z_MASK 0x7ff 4082 + #define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 4083 + #define THM_TMON0_RDIL15_DATA__VALID_MASK 0x800 4084 + #define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 4085 + #define THM_TMON0_RDIL15_DATA__TEMP_MASK 0xfff000 4086 + #define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 4087 + #define THM_TMON0_RDIR0_DATA__Z_MASK 0x7ff 4088 + #define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 4089 + #define THM_TMON0_RDIR0_DATA__VALID_MASK 0x800 4090 + #define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 4091 + #define THM_TMON0_RDIR0_DATA__TEMP_MASK 0xfff000 4092 + #define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 4093 + #define THM_TMON0_RDIR1_DATA__Z_MASK 0x7ff 4094 + #define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 4095 + #define THM_TMON0_RDIR1_DATA__VALID_MASK 0x800 4096 + #define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 4097 + #define THM_TMON0_RDIR1_DATA__TEMP_MASK 0xfff000 4098 + #define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 4099 + #define THM_TMON0_RDIR2_DATA__Z_MASK 0x7ff 4100 + #define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 4101 + #define THM_TMON0_RDIR2_DATA__VALID_MASK 0x800 4102 + #define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 4103 + #define THM_TMON0_RDIR2_DATA__TEMP_MASK 0xfff000 4104 + #define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 4105 + #define THM_TMON0_RDIR3_DATA__Z_MASK 0x7ff 4106 + #define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 4107 + #define THM_TMON0_RDIR3_DATA__VALID_MASK 0x800 4108 + #define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 4109 + #define THM_TMON0_RDIR3_DATA__TEMP_MASK 0xfff000 4110 + #define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 4111 + #define THM_TMON0_RDIR4_DATA__Z_MASK 0x7ff 4112 + #define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 4113 + #define THM_TMON0_RDIR4_DATA__VALID_MASK 0x800 4114 + #define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 4115 + #define THM_TMON0_RDIR4_DATA__TEMP_MASK 0xfff000 4116 + #define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 4117 + #define THM_TMON0_RDIR5_DATA__Z_MASK 0x7ff 4118 + #define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 4119 + #define THM_TMON0_RDIR5_DATA__VALID_MASK 0x800 4120 + #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 4121 + #define THM_TMON0_RDIR5_DATA__TEMP_MASK 0xfff000 4122 + #define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 4123 + #define THM_TMON0_RDIR6_DATA__Z_MASK 0x7ff 4124 + #define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 4125 + #define THM_TMON0_RDIR6_DATA__VALID_MASK 0x800 4126 + #define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 4127 + #define THM_TMON0_RDIR6_DATA__TEMP_MASK 0xfff000 4128 + #define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 4129 + #define THM_TMON0_RDIR7_DATA__Z_MASK 0x7ff 4130 + #define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 4131 + #define THM_TMON0_RDIR7_DATA__VALID_MASK 0x800 4132 + #define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 4133 + #define THM_TMON0_RDIR7_DATA__TEMP_MASK 0xfff000 4134 + #define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 4135 + #define THM_TMON0_RDIR8_DATA__Z_MASK 0x7ff 4136 + #define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 4137 + #define THM_TMON0_RDIR8_DATA__VALID_MASK 0x800 4138 + #define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 4139 + #define THM_TMON0_RDIR8_DATA__TEMP_MASK 0xfff000 4140 + #define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 4141 + #define THM_TMON0_RDIR9_DATA__Z_MASK 0x7ff 4142 + #define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 4143 + #define THM_TMON0_RDIR9_DATA__VALID_MASK 0x800 4144 + #define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 4145 + #define THM_TMON0_RDIR9_DATA__TEMP_MASK 0xfff000 4146 + #define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 4147 + #define THM_TMON0_RDIR10_DATA__Z_MASK 0x7ff 4148 + #define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 4149 + #define THM_TMON0_RDIR10_DATA__VALID_MASK 0x800 4150 + #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 4151 + #define THM_TMON0_RDIR10_DATA__TEMP_MASK 0xfff000 4152 + #define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 4153 + #define THM_TMON0_RDIR11_DATA__Z_MASK 0x7ff 4154 + #define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 4155 + #define THM_TMON0_RDIR11_DATA__VALID_MASK 0x800 4156 + #define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 4157 + #define THM_TMON0_RDIR11_DATA__TEMP_MASK 0xfff000 4158 + #define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 4159 + #define THM_TMON0_RDIR12_DATA__Z_MASK 0x7ff 4160 + #define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 4161 + #define THM_TMON0_RDIR12_DATA__VALID_MASK 0x800 4162 + #define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 4163 + #define THM_TMON0_RDIR12_DATA__TEMP_MASK 0xfff000 4164 + #define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 4165 + #define THM_TMON0_RDIR13_DATA__Z_MASK 0x7ff 4166 + #define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 4167 + #define THM_TMON0_RDIR13_DATA__VALID_MASK 0x800 4168 + #define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 4169 + #define THM_TMON0_RDIR13_DATA__TEMP_MASK 0xfff000 4170 + #define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 4171 + #define THM_TMON0_RDIR14_DATA__Z_MASK 0x7ff 4172 + #define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 4173 + #define THM_TMON0_RDIR14_DATA__VALID_MASK 0x800 4174 + #define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 4175 + #define THM_TMON0_RDIR14_DATA__TEMP_MASK 0xfff000 4176 + #define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 4177 + #define THM_TMON0_RDIR15_DATA__Z_MASK 0x7ff 4178 + #define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 4179 + #define THM_TMON0_RDIR15_DATA__VALID_MASK 0x800 4180 + #define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 4181 + #define THM_TMON0_RDIR15_DATA__TEMP_MASK 0xfff000 4182 + #define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 4183 + #define THM_TMON1_RDIL0_DATA__Z_MASK 0x7ff 4184 + #define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 4185 + #define THM_TMON1_RDIL0_DATA__VALID_MASK 0x800 4186 + #define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb 4187 + #define THM_TMON1_RDIL0_DATA__TEMP_MASK 0xfff000 4188 + #define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc 4189 + #define THM_TMON1_RDIL1_DATA__Z_MASK 0x7ff 4190 + #define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 4191 + #define THM_TMON1_RDIL1_DATA__VALID_MASK 0x800 4192 + #define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb 4193 + #define THM_TMON1_RDIL1_DATA__TEMP_MASK 0xfff000 4194 + #define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc 4195 + #define THM_TMON1_RDIL2_DATA__Z_MASK 0x7ff 4196 + #define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 4197 + #define THM_TMON1_RDIL2_DATA__VALID_MASK 0x800 4198 + #define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb 4199 + #define THM_TMON1_RDIL2_DATA__TEMP_MASK 0xfff000 4200 + #define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc 4201 + #define THM_TMON1_RDIL3_DATA__Z_MASK 0x7ff 4202 + #define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 4203 + #define THM_TMON1_RDIL3_DATA__VALID_MASK 0x800 4204 + #define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb 4205 + #define THM_TMON1_RDIL3_DATA__TEMP_MASK 0xfff000 4206 + #define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc 4207 + #define THM_TMON1_RDIL4_DATA__Z_MASK 0x7ff 4208 + #define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 4209 + #define THM_TMON1_RDIL4_DATA__VALID_MASK 0x800 4210 + #define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb 4211 + #define THM_TMON1_RDIL4_DATA__TEMP_MASK 0xfff000 4212 + #define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc 4213 + #define THM_TMON1_RDIL5_DATA__Z_MASK 0x7ff 4214 + #define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 4215 + #define THM_TMON1_RDIL5_DATA__VALID_MASK 0x800 4216 + #define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb 4217 + #define THM_TMON1_RDIL5_DATA__TEMP_MASK 0xfff000 4218 + #define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc 4219 + #define THM_TMON1_RDIL6_DATA__Z_MASK 0x7ff 4220 + #define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 4221 + #define THM_TMON1_RDIL6_DATA__VALID_MASK 0x800 4222 + #define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb 4223 + #define THM_TMON1_RDIL6_DATA__TEMP_MASK 0xfff000 4224 + #define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc 4225 + #define THM_TMON1_RDIL7_DATA__Z_MASK 0x7ff 4226 + #define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 4227 + #define THM_TMON1_RDIL7_DATA__VALID_MASK 0x800 4228 + #define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb 4229 + #define THM_TMON1_RDIL7_DATA__TEMP_MASK 0xfff000 4230 + #define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc 4231 + #define THM_TMON1_RDIL8_DATA__Z_MASK 0x7ff 4232 + #define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 4233 + #define THM_TMON1_RDIL8_DATA__VALID_MASK 0x800 4234 + #define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb 4235 + #define THM_TMON1_RDIL8_DATA__TEMP_MASK 0xfff000 4236 + #define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc 4237 + #define THM_TMON1_RDIL9_DATA__Z_MASK 0x7ff 4238 + #define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 4239 + #define THM_TMON1_RDIL9_DATA__VALID_MASK 0x800 4240 + #define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb 4241 + #define THM_TMON1_RDIL9_DATA__TEMP_MASK 0xfff000 4242 + #define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc 4243 + #define THM_TMON1_RDIL10_DATA__Z_MASK 0x7ff 4244 + #define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 4245 + #define THM_TMON1_RDIL10_DATA__VALID_MASK 0x800 4246 + #define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb 4247 + #define THM_TMON1_RDIL10_DATA__TEMP_MASK 0xfff000 4248 + #define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc 4249 + #define THM_TMON1_RDIL11_DATA__Z_MASK 0x7ff 4250 + #define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 4251 + #define THM_TMON1_RDIL11_DATA__VALID_MASK 0x800 4252 + #define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb 4253 + #define THM_TMON1_RDIL11_DATA__TEMP_MASK 0xfff000 4254 + #define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc 4255 + #define THM_TMON1_RDIL12_DATA__Z_MASK 0x7ff 4256 + #define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 4257 + #define THM_TMON1_RDIL12_DATA__VALID_MASK 0x800 4258 + #define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb 4259 + #define THM_TMON1_RDIL12_DATA__TEMP_MASK 0xfff000 4260 + #define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc 4261 + #define THM_TMON1_RDIL13_DATA__Z_MASK 0x7ff 4262 + #define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 4263 + #define THM_TMON1_RDIL13_DATA__VALID_MASK 0x800 4264 + #define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb 4265 + #define THM_TMON1_RDIL13_DATA__TEMP_MASK 0xfff000 4266 + #define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc 4267 + #define THM_TMON1_RDIL14_DATA__Z_MASK 0x7ff 4268 + #define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 4269 + #define THM_TMON1_RDIL14_DATA__VALID_MASK 0x800 4270 + #define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb 4271 + #define THM_TMON1_RDIL14_DATA__TEMP_MASK 0xfff000 4272 + #define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc 4273 + #define THM_TMON1_RDIL15_DATA__Z_MASK 0x7ff 4274 + #define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 4275 + #define THM_TMON1_RDIL15_DATA__VALID_MASK 0x800 4276 + #define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb 4277 + #define THM_TMON1_RDIL15_DATA__TEMP_MASK 0xfff000 4278 + #define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc 4279 + #define THM_TMON1_RDIR0_DATA__Z_MASK 0x7ff 4280 + #define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 4281 + #define THM_TMON1_RDIR0_DATA__VALID_MASK 0x800 4282 + #define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb 4283 + #define THM_TMON1_RDIR0_DATA__TEMP_MASK 0xfff000 4284 + #define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc 4285 + #define THM_TMON1_RDIR1_DATA__Z_MASK 0x7ff 4286 + #define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 4287 + #define THM_TMON1_RDIR1_DATA__VALID_MASK 0x800 4288 + #define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb 4289 + #define THM_TMON1_RDIR1_DATA__TEMP_MASK 0xfff000 4290 + #define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc 4291 + #define THM_TMON1_RDIR2_DATA__Z_MASK 0x7ff 4292 + #define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 4293 + #define THM_TMON1_RDIR2_DATA__VALID_MASK 0x800 4294 + #define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb 4295 + #define THM_TMON1_RDIR2_DATA__TEMP_MASK 0xfff000 4296 + #define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc 4297 + #define THM_TMON1_RDIR3_DATA__Z_MASK 0x7ff 4298 + #define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 4299 + #define THM_TMON1_RDIR3_DATA__VALID_MASK 0x800 4300 + #define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb 4301 + #define THM_TMON1_RDIR3_DATA__TEMP_MASK 0xfff000 4302 + #define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc 4303 + #define THM_TMON1_RDIR4_DATA__Z_MASK 0x7ff 4304 + #define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 4305 + #define THM_TMON1_RDIR4_DATA__VALID_MASK 0x800 4306 + #define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb 4307 + #define THM_TMON1_RDIR4_DATA__TEMP_MASK 0xfff000 4308 + #define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc 4309 + #define THM_TMON1_RDIR5_DATA__Z_MASK 0x7ff 4310 + #define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 4311 + #define THM_TMON1_RDIR5_DATA__VALID_MASK 0x800 4312 + #define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb 4313 + #define THM_TMON1_RDIR5_DATA__TEMP_MASK 0xfff000 4314 + #define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc 4315 + #define THM_TMON1_RDIR6_DATA__Z_MASK 0x7ff 4316 + #define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 4317 + #define THM_TMON1_RDIR6_DATA__VALID_MASK 0x800 4318 + #define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb 4319 + #define THM_TMON1_RDIR6_DATA__TEMP_MASK 0xfff000 4320 + #define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc 4321 + #define THM_TMON1_RDIR7_DATA__Z_MASK 0x7ff 4322 + #define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 4323 + #define THM_TMON1_RDIR7_DATA__VALID_MASK 0x800 4324 + #define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb 4325 + #define THM_TMON1_RDIR7_DATA__TEMP_MASK 0xfff000 4326 + #define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc 4327 + #define THM_TMON1_RDIR8_DATA__Z_MASK 0x7ff 4328 + #define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 4329 + #define THM_TMON1_RDIR8_DATA__VALID_MASK 0x800 4330 + #define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb 4331 + #define THM_TMON1_RDIR8_DATA__TEMP_MASK 0xfff000 4332 + #define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc 4333 + #define THM_TMON1_RDIR9_DATA__Z_MASK 0x7ff 4334 + #define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 4335 + #define THM_TMON1_RDIR9_DATA__VALID_MASK 0x800 4336 + #define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb 4337 + #define THM_TMON1_RDIR9_DATA__TEMP_MASK 0xfff000 4338 + #define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc 4339 + #define THM_TMON1_RDIR10_DATA__Z_MASK 0x7ff 4340 + #define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 4341 + #define THM_TMON1_RDIR10_DATA__VALID_MASK 0x800 4342 + #define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb 4343 + #define THM_TMON1_RDIR10_DATA__TEMP_MASK 0xfff000 4344 + #define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc 4345 + #define THM_TMON1_RDIR11_DATA__Z_MASK 0x7ff 4346 + #define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 4347 + #define THM_TMON1_RDIR11_DATA__VALID_MASK 0x800 4348 + #define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb 4349 + #define THM_TMON1_RDIR11_DATA__TEMP_MASK 0xfff000 4350 + #define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc 4351 + #define THM_TMON1_RDIR12_DATA__Z_MASK 0x7ff 4352 + #define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 4353 + #define THM_TMON1_RDIR12_DATA__VALID_MASK 0x800 4354 + #define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb 4355 + #define THM_TMON1_RDIR12_DATA__TEMP_MASK 0xfff000 4356 + #define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc 4357 + #define THM_TMON1_RDIR13_DATA__Z_MASK 0x7ff 4358 + #define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 4359 + #define THM_TMON1_RDIR13_DATA__VALID_MASK 0x800 4360 + #define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb 4361 + #define THM_TMON1_RDIR13_DATA__TEMP_MASK 0xfff000 4362 + #define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc 4363 + #define THM_TMON1_RDIR14_DATA__Z_MASK 0x7ff 4364 + #define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 4365 + #define THM_TMON1_RDIR14_DATA__VALID_MASK 0x800 4366 + #define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb 4367 + #define THM_TMON1_RDIR14_DATA__TEMP_MASK 0xfff000 4368 + #define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc 4369 + #define THM_TMON1_RDIR15_DATA__Z_MASK 0x7ff 4370 + #define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 4371 + #define THM_TMON1_RDIR15_DATA__VALID_MASK 0x800 4372 + #define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb 4373 + #define THM_TMON1_RDIR15_DATA__TEMP_MASK 0xfff000 4374 + #define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc 4375 + #define THM_TMON2_RDIL0_DATA__Z_MASK 0x7ff 4376 + #define THM_TMON2_RDIL0_DATA__Z__SHIFT 0x0 4377 + #define THM_TMON2_RDIL0_DATA__VALID_MASK 0x800 4378 + #define THM_TMON2_RDIL0_DATA__VALID__SHIFT 0xb 4379 + #define THM_TMON2_RDIL0_DATA__TEMP_MASK 0xfff000 4380 + #define THM_TMON2_RDIL0_DATA__TEMP__SHIFT 0xc 4381 + #define THM_TMON2_RDIL1_DATA__Z_MASK 0x7ff 4382 + #define THM_TMON2_RDIL1_DATA__Z__SHIFT 0x0 4383 + #define THM_TMON2_RDIL1_DATA__VALID_MASK 0x800 4384 + #define THM_TMON2_RDIL1_DATA__VALID__SHIFT 0xb 4385 + #define THM_TMON2_RDIL1_DATA__TEMP_MASK 0xfff000 4386 + #define THM_TMON2_RDIL1_DATA__TEMP__SHIFT 0xc 4387 + #define THM_TMON2_RDIL2_DATA__Z_MASK 0x7ff 4388 + #define THM_TMON2_RDIL2_DATA__Z__SHIFT 0x0 4389 + #define THM_TMON2_RDIL2_DATA__VALID_MASK 0x800 4390 + #define THM_TMON2_RDIL2_DATA__VALID__SHIFT 0xb 4391 + #define THM_TMON2_RDIL2_DATA__TEMP_MASK 0xfff000 4392 + #define THM_TMON2_RDIL2_DATA__TEMP__SHIFT 0xc 4393 + #define THM_TMON2_RDIL3_DATA__Z_MASK 0x7ff 4394 + #define THM_TMON2_RDIL3_DATA__Z__SHIFT 0x0 4395 + #define THM_TMON2_RDIL3_DATA__VALID_MASK 0x800 4396 + #define THM_TMON2_RDIL3_DATA__VALID__SHIFT 0xb 4397 + #define THM_TMON2_RDIL3_DATA__TEMP_MASK 0xfff000 4398 + #define THM_TMON2_RDIL3_DATA__TEMP__SHIFT 0xc 4399 + #define THM_TMON2_RDIL4_DATA__Z_MASK 0x7ff 4400 + #define THM_TMON2_RDIL4_DATA__Z__SHIFT 0x0 4401 + #define THM_TMON2_RDIL4_DATA__VALID_MASK 0x800 4402 + #define THM_TMON2_RDIL4_DATA__VALID__SHIFT 0xb 4403 + #define THM_TMON2_RDIL4_DATA__TEMP_MASK 0xfff000 4404 + #define THM_TMON2_RDIL4_DATA__TEMP__SHIFT 0xc 4405 + #define THM_TMON2_RDIL5_DATA__Z_MASK 0x7ff 4406 + #define THM_TMON2_RDIL5_DATA__Z__SHIFT 0x0 4407 + #define THM_TMON2_RDIL5_DATA__VALID_MASK 0x800 4408 + #define THM_TMON2_RDIL5_DATA__VALID__SHIFT 0xb 4409 + #define THM_TMON2_RDIL5_DATA__TEMP_MASK 0xfff000 4410 + #define THM_TMON2_RDIL5_DATA__TEMP__SHIFT 0xc 4411 + #define THM_TMON2_RDIL6_DATA__Z_MASK 0x7ff 4412 + #define THM_TMON2_RDIL6_DATA__Z__SHIFT 0x0 4413 + #define THM_TMON2_RDIL6_DATA__VALID_MASK 0x800 4414 + #define THM_TMON2_RDIL6_DATA__VALID__SHIFT 0xb 4415 + #define THM_TMON2_RDIL6_DATA__TEMP_MASK 0xfff000 4416 + #define THM_TMON2_RDIL6_DATA__TEMP__SHIFT 0xc 4417 + #define THM_TMON2_RDIL7_DATA__Z_MASK 0x7ff 4418 + #define THM_TMON2_RDIL7_DATA__Z__SHIFT 0x0 4419 + #define THM_TMON2_RDIL7_DATA__VALID_MASK 0x800 4420 + #define THM_TMON2_RDIL7_DATA__VALID__SHIFT 0xb 4421 + #define THM_TMON2_RDIL7_DATA__TEMP_MASK 0xfff000 4422 + #define THM_TMON2_RDIL7_DATA__TEMP__SHIFT 0xc 4423 + #define THM_TMON2_RDIL8_DATA__Z_MASK 0x7ff 4424 + #define THM_TMON2_RDIL8_DATA__Z__SHIFT 0x0 4425 + #define THM_TMON2_RDIL8_DATA__VALID_MASK 0x800 4426 + #define THM_TMON2_RDIL8_DATA__VALID__SHIFT 0xb 4427 + #define THM_TMON2_RDIL8_DATA__TEMP_MASK 0xfff000 4428 + #define THM_TMON2_RDIL8_DATA__TEMP__SHIFT 0xc 4429 + #define THM_TMON2_RDIL9_DATA__Z_MASK 0x7ff 4430 + #define THM_TMON2_RDIL9_DATA__Z__SHIFT 0x0 4431 + #define THM_TMON2_RDIL9_DATA__VALID_MASK 0x800 4432 + #define THM_TMON2_RDIL9_DATA__VALID__SHIFT 0xb 4433 + #define THM_TMON2_RDIL9_DATA__TEMP_MASK 0xfff000 4434 + #define THM_TMON2_RDIL9_DATA__TEMP__SHIFT 0xc 4435 + #define THM_TMON2_RDIL10_DATA__Z_MASK 0x7ff 4436 + #define THM_TMON2_RDIL10_DATA__Z__SHIFT 0x0 4437 + #define THM_TMON2_RDIL10_DATA__VALID_MASK 0x800 4438 + #define THM_TMON2_RDIL10_DATA__VALID__SHIFT 0xb 4439 + #define THM_TMON2_RDIL10_DATA__TEMP_MASK 0xfff000 4440 + #define THM_TMON2_RDIL10_DATA__TEMP__SHIFT 0xc 4441 + #define THM_TMON2_RDIL11_DATA__Z_MASK 0x7ff 4442 + #define THM_TMON2_RDIL11_DATA__Z__SHIFT 0x0 4443 + #define THM_TMON2_RDIL11_DATA__VALID_MASK 0x800 4444 + #define THM_TMON2_RDIL11_DATA__VALID__SHIFT 0xb 4445 + #define THM_TMON2_RDIL11_DATA__TEMP_MASK 0xfff000 4446 + #define THM_TMON2_RDIL11_DATA__TEMP__SHIFT 0xc 4447 + #define THM_TMON2_RDIL12_DATA__Z_MASK 0x7ff 4448 + #define THM_TMON2_RDIL12_DATA__Z__SHIFT 0x0 4449 + #define THM_TMON2_RDIL12_DATA__VALID_MASK 0x800 4450 + #define THM_TMON2_RDIL12_DATA__VALID__SHIFT 0xb 4451 + #define THM_TMON2_RDIL12_DATA__TEMP_MASK 0xfff000 4452 + #define THM_TMON2_RDIL12_DATA__TEMP__SHIFT 0xc 4453 + #define THM_TMON2_RDIL13_DATA__Z_MASK 0x7ff 4454 + #define THM_TMON2_RDIL13_DATA__Z__SHIFT 0x0 4455 + #define THM_TMON2_RDIL13_DATA__VALID_MASK 0x800 4456 + #define THM_TMON2_RDIL13_DATA__VALID__SHIFT 0xb 4457 + #define THM_TMON2_RDIL13_DATA__TEMP_MASK 0xfff000 4458 + #define THM_TMON2_RDIL13_DATA__TEMP__SHIFT 0xc 4459 + #define THM_TMON2_RDIL14_DATA__Z_MASK 0x7ff 4460 + #define THM_TMON2_RDIL14_DATA__Z__SHIFT 0x0 4461 + #define THM_TMON2_RDIL14_DATA__VALID_MASK 0x800 4462 + #define THM_TMON2_RDIL14_DATA__VALID__SHIFT 0xb 4463 + #define THM_TMON2_RDIL14_DATA__TEMP_MASK 0xfff000 4464 + #define THM_TMON2_RDIL14_DATA__TEMP__SHIFT 0xc 4465 + #define THM_TMON2_RDIL15_DATA__Z_MASK 0x7ff 4466 + #define THM_TMON2_RDIL15_DATA__Z__SHIFT 0x0 4467 + #define THM_TMON2_RDIL15_DATA__VALID_MASK 0x800 4468 + #define THM_TMON2_RDIL15_DATA__VALID__SHIFT 0xb 4469 + #define THM_TMON2_RDIL15_DATA__TEMP_MASK 0xfff000 4470 + #define THM_TMON2_RDIL15_DATA__TEMP__SHIFT 0xc 4471 + #define THM_TMON2_RDIR0_DATA__Z_MASK 0x7ff 4472 + #define THM_TMON2_RDIR0_DATA__Z__SHIFT 0x0 4473 + #define THM_TMON2_RDIR0_DATA__VALID_MASK 0x800 4474 + #define THM_TMON2_RDIR0_DATA__VALID__SHIFT 0xb 4475 + #define THM_TMON2_RDIR0_DATA__TEMP_MASK 0xfff000 4476 + #define THM_TMON2_RDIR0_DATA__TEMP__SHIFT 0xc 4477 + #define THM_TMON2_RDIR1_DATA__Z_MASK 0x7ff 4478 + #define THM_TMON2_RDIR1_DATA__Z__SHIFT 0x0 4479 + #define THM_TMON2_RDIR1_DATA__VALID_MASK 0x800 4480 + #define THM_TMON2_RDIR1_DATA__VALID__SHIFT 0xb 4481 + #define THM_TMON2_RDIR1_DATA__TEMP_MASK 0xfff000 4482 + #define THM_TMON2_RDIR1_DATA__TEMP__SHIFT 0xc 4483 + #define THM_TMON2_RDIR2_DATA__Z_MASK 0x7ff 4484 + #define THM_TMON2_RDIR2_DATA__Z__SHIFT 0x0 4485 + #define THM_TMON2_RDIR2_DATA__VALID_MASK 0x800 4486 + #define THM_TMON2_RDIR2_DATA__VALID__SHIFT 0xb 4487 + #define THM_TMON2_RDIR2_DATA__TEMP_MASK 0xfff000 4488 + #define THM_TMON2_RDIR2_DATA__TEMP__SHIFT 0xc 4489 + #define THM_TMON2_RDIR3_DATA__Z_MASK 0x7ff 4490 + #define THM_TMON2_RDIR3_DATA__Z__SHIFT 0x0 4491 + #define THM_TMON2_RDIR3_DATA__VALID_MASK 0x800 4492 + #define THM_TMON2_RDIR3_DATA__VALID__SHIFT 0xb 4493 + #define THM_TMON2_RDIR3_DATA__TEMP_MASK 0xfff000 4494 + #define THM_TMON2_RDIR3_DATA__TEMP__SHIFT 0xc 4495 + #define THM_TMON2_RDIR4_DATA__Z_MASK 0x7ff 4496 + #define THM_TMON2_RDIR4_DATA__Z__SHIFT 0x0 4497 + #define THM_TMON2_RDIR4_DATA__VALID_MASK 0x800 4498 + #define THM_TMON2_RDIR4_DATA__VALID__SHIFT 0xb 4499 + #define THM_TMON2_RDIR4_DATA__TEMP_MASK 0xfff000 4500 + #define THM_TMON2_RDIR4_DATA__TEMP__SHIFT 0xc 4501 + #define THM_TMON2_RDIR5_DATA__Z_MASK 0x7ff 4502 + #define THM_TMON2_RDIR5_DATA__Z__SHIFT 0x0 4503 + #define THM_TMON2_RDIR5_DATA__VALID_MASK 0x800 4504 + #define THM_TMON2_RDIR5_DATA__VALID__SHIFT 0xb 4505 + #define THM_TMON2_RDIR5_DATA__TEMP_MASK 0xfff000 4506 + #define THM_TMON2_RDIR5_DATA__TEMP__SHIFT 0xc 4507 + #define THM_TMON2_RDIR6_DATA__Z_MASK 0x7ff 4508 + #define THM_TMON2_RDIR6_DATA__Z__SHIFT 0x0 4509 + #define THM_TMON2_RDIR6_DATA__VALID_MASK 0x800 4510 + #define THM_TMON2_RDIR6_DATA__VALID__SHIFT 0xb 4511 + #define THM_TMON2_RDIR6_DATA__TEMP_MASK 0xfff000 4512 + #define THM_TMON2_RDIR6_DATA__TEMP__SHIFT 0xc 4513 + #define THM_TMON2_RDIR7_DATA__Z_MASK 0x7ff 4514 + #define THM_TMON2_RDIR7_DATA__Z__SHIFT 0x0 4515 + #define THM_TMON2_RDIR7_DATA__VALID_MASK 0x800 4516 + #define THM_TMON2_RDIR7_DATA__VALID__SHIFT 0xb 4517 + #define THM_TMON2_RDIR7_DATA__TEMP_MASK 0xfff000 4518 + #define THM_TMON2_RDIR7_DATA__TEMP__SHIFT 0xc 4519 + #define THM_TMON2_RDIR8_DATA__Z_MASK 0x7ff 4520 + #define THM_TMON2_RDIR8_DATA__Z__SHIFT 0x0 4521 + #define THM_TMON2_RDIR8_DATA__VALID_MASK 0x800 4522 + #define THM_TMON2_RDIR8_DATA__VALID__SHIFT 0xb 4523 + #define THM_TMON2_RDIR8_DATA__TEMP_MASK 0xfff000 4524 + #define THM_TMON2_RDIR8_DATA__TEMP__SHIFT 0xc 4525 + #define THM_TMON2_RDIR9_DATA__Z_MASK 0x7ff 4526 + #define THM_TMON2_RDIR9_DATA__Z__SHIFT 0x0 4527 + #define THM_TMON2_RDIR9_DATA__VALID_MASK 0x800 4528 + #define THM_TMON2_RDIR9_DATA__VALID__SHIFT 0xb 4529 + #define THM_TMON2_RDIR9_DATA__TEMP_MASK 0xfff000 4530 + #define THM_TMON2_RDIR9_DATA__TEMP__SHIFT 0xc 4531 + #define THM_TMON2_RDIR10_DATA__Z_MASK 0x7ff 4532 + #define THM_TMON2_RDIR10_DATA__Z__SHIFT 0x0 4533 + #define THM_TMON2_RDIR10_DATA__VALID_MASK 0x800 4534 + #define THM_TMON2_RDIR10_DATA__VALID__SHIFT 0xb 4535 + #define THM_TMON2_RDIR10_DATA__TEMP_MASK 0xfff000 4536 + #define THM_TMON2_RDIR10_DATA__TEMP__SHIFT 0xc 4537 + #define THM_TMON2_RDIR11_DATA__Z_MASK 0x7ff 4538 + #define THM_TMON2_RDIR11_DATA__Z__SHIFT 0x0 4539 + #define THM_TMON2_RDIR11_DATA__VALID_MASK 0x800 4540 + #define THM_TMON2_RDIR11_DATA__VALID__SHIFT 0xb 4541 + #define THM_TMON2_RDIR11_DATA__TEMP_MASK 0xfff000 4542 + #define THM_TMON2_RDIR11_DATA__TEMP__SHIFT 0xc 4543 + #define THM_TMON2_RDIR12_DATA__Z_MASK 0x7ff 4544 + #define THM_TMON2_RDIR12_DATA__Z__SHIFT 0x0 4545 + #define THM_TMON2_RDIR12_DATA__VALID_MASK 0x800 4546 + #define THM_TMON2_RDIR12_DATA__VALID__SHIFT 0xb 4547 + #define THM_TMON2_RDIR12_DATA__TEMP_MASK 0xfff000 4548 + #define THM_TMON2_RDIR12_DATA__TEMP__SHIFT 0xc 4549 + #define THM_TMON2_RDIR13_DATA__Z_MASK 0x7ff 4550 + #define THM_TMON2_RDIR13_DATA__Z__SHIFT 0x0 4551 + #define THM_TMON2_RDIR13_DATA__VALID_MASK 0x800 4552 + #define THM_TMON2_RDIR13_DATA__VALID__SHIFT 0xb 4553 + #define THM_TMON2_RDIR13_DATA__TEMP_MASK 0xfff000 4554 + #define THM_TMON2_RDIR13_DATA__TEMP__SHIFT 0xc 4555 + #define THM_TMON2_RDIR14_DATA__Z_MASK 0x7ff 4556 + #define THM_TMON2_RDIR14_DATA__Z__SHIFT 0x0 4557 + #define THM_TMON2_RDIR14_DATA__VALID_MASK 0x800 4558 + #define THM_TMON2_RDIR14_DATA__VALID__SHIFT 0xb 4559 + #define THM_TMON2_RDIR14_DATA__TEMP_MASK 0xfff000 4560 + #define THM_TMON2_RDIR14_DATA__TEMP__SHIFT 0xc 4561 + #define THM_TMON2_RDIR15_DATA__Z_MASK 0x7ff 4562 + #define THM_TMON2_RDIR15_DATA__Z__SHIFT 0x0 4563 + #define THM_TMON2_RDIR15_DATA__VALID_MASK 0x800 4564 + #define THM_TMON2_RDIR15_DATA__VALID__SHIFT 0xb 4565 + #define THM_TMON2_RDIR15_DATA__TEMP_MASK 0xfff000 4566 + #define THM_TMON2_RDIR15_DATA__TEMP__SHIFT 0xc 4567 + #define THM_TMON0_INT_DATA__Z_MASK 0x7ff 4568 + #define THM_TMON0_INT_DATA__Z__SHIFT 0x0 4569 + #define THM_TMON0_INT_DATA__VALID_MASK 0x800 4570 + #define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 4571 + #define THM_TMON0_INT_DATA__TEMP_MASK 0xfff000 4572 + #define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 4573 + #define THM_TMON1_INT_DATA__Z_MASK 0x7ff 4574 + #define THM_TMON1_INT_DATA__Z__SHIFT 0x0 4575 + #define THM_TMON1_INT_DATA__VALID_MASK 0x800 4576 + #define THM_TMON1_INT_DATA__VALID__SHIFT 0xb 4577 + #define THM_TMON1_INT_DATA__TEMP_MASK 0xfff000 4578 + #define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc 4579 + #define THM_TMON2_INT_DATA__Z_MASK 0x7ff 4580 + #define THM_TMON2_INT_DATA__Z__SHIFT 0x0 4581 + #define THM_TMON2_INT_DATA__VALID_MASK 0x800 4582 + #define THM_TMON2_INT_DATA__VALID__SHIFT 0xb 4583 + #define THM_TMON2_INT_DATA__TEMP_MASK 0xfff000 4584 + #define THM_TMON2_INT_DATA__TEMP__SHIFT 0xc 4585 + #define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x1f 4586 + #define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 4587 + #define THM_TMON0_DEBUG__DEBUG_Z_MASK 0xffe0 4588 + #define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 4589 + #define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x1f 4590 + #define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 4591 + #define THM_TMON1_DEBUG__DEBUG_Z_MASK 0xffe0 4592 + #define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 4593 + #define THM_TMON2_DEBUG__DEBUG_RDI_MASK 0x1f 4594 + #define THM_TMON2_DEBUG__DEBUG_RDI__SHIFT 0x0 4595 + #define THM_TMON2_DEBUG__DEBUG_Z_MASK 0xffe0 4596 + #define THM_TMON2_DEBUG__DEBUG_Z__SHIFT 0x5 4597 + #define THM_TMON0_STATUS__CURRENT_RDI_MASK 0x1f 4598 + #define THM_TMON0_STATUS__CURRENT_RDI__SHIFT 0x0 4599 + #define THM_TMON0_STATUS__MEAS_DONE_MASK 0x20 4600 + #define THM_TMON0_STATUS__MEAS_DONE__SHIFT 0x5 4601 + #define THM_TMON1_STATUS__CURRENT_RDI_MASK 0x1f 4602 + #define THM_TMON1_STATUS__CURRENT_RDI__SHIFT 0x0 4603 + #define THM_TMON1_STATUS__MEAS_DONE_MASK 0x20 4604 + #define THM_TMON1_STATUS__MEAS_DONE__SHIFT 0x5 4605 + #define THM_TMON2_STATUS__CURRENT_RDI_MASK 0x1f 4606 + #define THM_TMON2_STATUS__CURRENT_RDI__SHIFT 0x0 4607 + #define THM_TMON2_STATUS__MEAS_DONE_MASK 0x20 4608 + #define THM_TMON2_STATUS__MEAS_DONE__SHIFT 0x5 4609 + #define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1 4610 + #define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0 4611 + #define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2 4612 + #define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1 4613 + #define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4 4614 + #define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2 4615 + #define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8 4616 + #define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3 4617 + #define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40 4618 + #define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6 4619 + #define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100 4620 + #define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8 4621 + #define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200 4622 + #define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9 4623 + #define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400 4624 + #define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa 4625 + #define GENERAL_PWRMGT__SPARE11_MASK 0x800 4626 + #define GENERAL_PWRMGT__SPARE11__SHIFT 0xb 4627 + #define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000 4628 + #define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe 4629 + #define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000 4630 + #define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf 4631 + #define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000 4632 + #define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10 4633 + #define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000 4634 + #define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11 4635 + #define GENERAL_PWRMGT__SPARE18_MASK 0x40000 4636 + #define GENERAL_PWRMGT__SPARE18__SHIFT 0x12 4637 + #define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000 4638 + #define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13 4639 + #define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000 4640 + #define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17 4641 + #define GENERAL_PWRMGT__SPARE27_MASK 0x8000000 4642 + #define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b 4643 + #define GENERAL_PWRMGT__SPARE_MASK 0xf0000000 4644 + #define GENERAL_PWRMGT__SPARE__SHIFT 0x1c 4645 + #define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3 4646 + #define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0 4647 + #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4 4648 + #define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2 4649 + #define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8 4650 + #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3 4651 + #define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10 4652 + #define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4 4653 + #define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0 4654 + #define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5 4655 + #define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1 4656 + #define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0 4657 + #define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10 4658 + #define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4 4659 + #define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20 4660 + #define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5 4661 + #define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000 4662 + #define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe 4663 + #define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000 4664 + #define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf 4665 + #define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000 4666 + #define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10 4667 + #define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000 4668 + #define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15 4669 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf 4670 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0 4671 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0 4672 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4 4673 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00 4674 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8 4675 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000 4676 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc 4677 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000 4678 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10 4679 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000 4680 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15 4681 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000 4682 + #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a 4683 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000 4684 + #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d 4685 + #define PWR_PCC_CONTROL__PCC_POLARITY_MASK 0x1 4686 + #define PWR_PCC_CONTROL__PCC_POLARITY__SHIFT 0x0 4687 + #define PWR_PCC_GPIO_SELECT__GPIO_MASK 0xffffffff 4688 + #define PWR_PCC_GPIO_SELECT__GPIO__SHIFT 0x0 4689 + #define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4690 + #define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4691 + #define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4692 + #define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4693 + #define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4694 + #define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4695 + #define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4696 + #define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4697 + #define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4698 + #define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4699 + #define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4700 + #define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4701 + #define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4702 + #define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4703 + #define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4704 + #define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4705 + #define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4706 + #define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4707 + #define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4708 + #define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4709 + #define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4710 + #define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4711 + #define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4712 + #define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4713 + #define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4714 + #define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4715 + #define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4716 + #define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4717 + #define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4718 + #define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4719 + #define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4720 + #define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4721 + #define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4722 + #define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4723 + #define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4724 + #define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4725 + #define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4726 + #define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4727 + #define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4728 + #define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4729 + #define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4730 + #define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4731 + #define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4732 + #define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4733 + #define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4734 + #define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4735 + #define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4736 + #define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4737 + #define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4738 + #define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4739 + #define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4740 + #define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4741 + #define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4742 + #define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4743 + #define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4744 + #define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4745 + #define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4746 + #define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4747 + #define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4748 + #define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4749 + #define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4750 + #define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4751 + #define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4752 + #define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4753 + #define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4754 + #define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4755 + #define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4756 + #define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4757 + #define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4758 + #define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4759 + #define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4760 + #define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4761 + #define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4762 + #define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4763 + #define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4764 + #define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4765 + #define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4766 + #define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4767 + #define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4768 + #define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4769 + #define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4770 + #define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4771 + #define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4772 + #define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4773 + #define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4774 + #define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4775 + #define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4776 + #define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4777 + #define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4778 + #define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4779 + #define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4780 + #define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4781 + #define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4782 + #define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4783 + #define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4784 + #define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4785 + #define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4786 + #define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4787 + #define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4788 + #define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4789 + #define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4790 + #define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4791 + #define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4792 + #define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4793 + #define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4794 + #define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4795 + #define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4796 + #define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4797 + #define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4798 + #define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4799 + #define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4800 + #define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4801 + #define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4802 + #define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4803 + #define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4804 + #define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4805 + #define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4806 + #define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4807 + #define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4808 + #define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4809 + #define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4810 + #define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4811 + #define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4812 + #define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4813 + #define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4814 + #define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4815 + #define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4816 + #define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4817 + #define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4818 + #define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4819 + #define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4820 + #define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4821 + #define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4822 + #define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4823 + #define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4824 + #define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4825 + #define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4826 + #define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4827 + #define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4828 + #define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4829 + #define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4830 + #define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4831 + #define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4832 + #define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4833 + #define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4834 + #define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4835 + #define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4836 + #define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4837 + #define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4838 + #define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4839 + #define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4840 + #define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4841 + #define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4842 + #define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4843 + #define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4844 + #define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4845 + #define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4846 + #define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4847 + #define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4848 + #define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4849 + #define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4850 + #define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4851 + #define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4852 + #define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4853 + #define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4854 + #define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4855 + #define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4856 + #define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4857 + #define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4858 + #define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4859 + #define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4860 + #define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4861 + #define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4862 + #define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4863 + #define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4864 + #define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4865 + #define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4866 + #define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4867 + #define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4868 + #define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4869 + #define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4870 + #define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4871 + #define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4872 + #define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4873 + #define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4874 + #define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4875 + #define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4876 + #define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4877 + #define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4878 + #define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4879 + #define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4880 + #define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4881 + #define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4882 + #define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4883 + #define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4884 + #define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4885 + #define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4886 + #define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4887 + #define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4888 + #define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4889 + #define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4890 + #define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4891 + #define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4892 + #define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4893 + #define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4894 + #define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4895 + #define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4896 + #define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4897 + #define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4898 + #define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4899 + #define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4900 + #define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4901 + #define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4902 + #define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4903 + #define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4904 + #define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4905 + #define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4906 + #define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4907 + #define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4908 + #define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4909 + #define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4910 + #define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4911 + #define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4912 + #define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4913 + #define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4914 + #define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4915 + #define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4916 + #define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4917 + #define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4918 + #define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4919 + #define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4920 + #define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4921 + #define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4922 + #define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4923 + #define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4924 + #define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4925 + #define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4926 + #define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4927 + #define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4928 + #define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4929 + #define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4930 + #define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4931 + #define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4932 + #define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4933 + #define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4934 + #define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4935 + #define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4936 + #define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4937 + #define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 4938 + #define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 4939 + #define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 4940 + #define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 4941 + #define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 4942 + #define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 4943 + #define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 4944 + #define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 4945 + #define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 4946 + #define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 4947 + #define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 4948 + #define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 4949 + #define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 4950 + #define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 4951 + #define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 4952 + #define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 4953 + #define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 4954 + #define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 4955 + #define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 4956 + #define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 4957 + #define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 4958 + #define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 4959 + #define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 4960 + #define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 4961 + #define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 4962 + #define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 4963 + #define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 4964 + #define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 4965 + #define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 4966 + #define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 4967 + #define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 4968 + #define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 4969 + #define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 4970 + #define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 4971 + #define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 4972 + #define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 4973 + #define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 4974 + #define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 4975 + #define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 4976 + #define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 4977 + #define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 4978 + #define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 4979 + #define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 4980 + #define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 4981 + #define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 4982 + #define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 4983 + #define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 4984 + #define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 4985 + #define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 4986 + #define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 4987 + #define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 4988 + #define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 4989 + #define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 4990 + #define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 4991 + #define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 4992 + #define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 4993 + #define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 4994 + #define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 4995 + #define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 4996 + #define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 4997 + #define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 4998 + #define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 4999 + #define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5000 + #define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5001 + #define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5002 + #define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5003 + #define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5004 + #define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5005 + #define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5006 + #define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5007 + #define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5008 + #define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5009 + #define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5010 + #define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5011 + #define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5012 + #define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5013 + #define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5014 + #define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5015 + #define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5016 + #define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5017 + #define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5018 + #define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5019 + #define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5020 + #define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5021 + #define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5022 + #define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5023 + #define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5024 + #define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5025 + #define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5026 + #define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5027 + #define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5028 + #define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5029 + #define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5030 + #define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5031 + #define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5032 + #define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5033 + #define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5034 + #define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5035 + #define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5036 + #define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5037 + #define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5038 + #define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5039 + #define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5040 + #define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5041 + #define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5042 + #define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5043 + #define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5044 + #define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5045 + #define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5046 + #define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5047 + #define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5048 + #define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5049 + #define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5050 + #define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5051 + #define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5052 + #define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5053 + #define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5054 + #define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5055 + #define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5056 + #define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5057 + #define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5058 + #define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5059 + #define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5060 + #define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5061 + #define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5062 + #define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5063 + #define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5064 + #define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5065 + #define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5066 + #define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5067 + #define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5068 + #define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5069 + #define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5070 + #define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5071 + #define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5072 + #define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5073 + #define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5074 + #define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5075 + #define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5076 + #define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5077 + #define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5078 + #define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5079 + #define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5080 + #define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5081 + #define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5082 + #define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5083 + #define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5084 + #define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5085 + #define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5086 + #define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5087 + #define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5088 + #define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5089 + #define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5090 + #define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5091 + #define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5092 + #define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5093 + #define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5094 + #define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5095 + #define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5096 + #define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5097 + #define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5098 + #define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5099 + #define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5100 + #define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5101 + #define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5102 + #define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5103 + #define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5104 + #define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5105 + #define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5106 + #define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5107 + #define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5108 + #define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5109 + #define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5110 + #define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5111 + #define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5112 + #define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5113 + #define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5114 + #define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5115 + #define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5116 + #define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5117 + #define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5118 + #define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5119 + #define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5120 + #define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5121 + #define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5122 + #define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5123 + #define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1 5124 + #define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0 5125 + #define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2 5126 + #define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1 5127 + #define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4 5128 + #define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2 5129 + #define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8 5130 + #define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3 5131 + #define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10 5132 + #define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4 5133 + #define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20 5134 + #define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5 5135 + #define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40 5136 + #define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6 5137 + #define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80 5138 + #define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7 5139 + #define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100 5140 + #define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8 5141 + #define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200 5142 + #define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9 5143 + #define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400 5144 + #define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa 5145 + #define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800 5146 + #define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb 5147 + #define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000 5148 + #define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc 5149 + #define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000 5150 + #define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd 5151 + #define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000 5152 + #define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe 5153 + #define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000 5154 + #define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf 5155 + #define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000 5156 + #define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10 5157 + #define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000 5158 + #define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11 5159 + #define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000 5160 + #define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12 5161 + #define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000 5162 + #define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13 5163 + #define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000 5164 + #define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14 5165 + #define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000 5166 + #define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15 5167 + #define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000 5168 + #define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16 5169 + #define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000 5170 + #define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17 5171 + #define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000 5172 + #define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18 5173 + #define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000 5174 + #define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19 5175 + #define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000 5176 + #define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a 5177 + #define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000 5178 + #define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b 5179 + #define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000 5180 + #define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c 5181 + #define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000 5182 + #define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d 5183 + #define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000 5184 + #define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e 5185 + #define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf 5186 + #define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0 5187 + #define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0 5188 + #define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4 5189 + #define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00 5190 + #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8 5191 + #define PLL_TEST_CNTL__TST_RESET_MASK 0x8000 5192 + #define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf 5193 + #define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000 5194 + #define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11 5195 + #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff 5196 + #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0 5197 + #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000 5198 + #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10 5199 + #define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3 5200 + #define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0 5201 + #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0 5202 + #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4 5203 + #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000 5204 + #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14 5205 + #define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000 5206 + #define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18 5207 + #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000 5208 + #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c 5209 + #define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff 5210 + #define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0 5211 + #define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f 5212 + #define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0 5213 + #define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80 5214 + #define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7 5215 + #define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 5216 + #define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 5217 + #define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 5218 + #define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 5219 + #define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 5220 + #define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 5221 + #define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000 5222 + #define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10 5223 + #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000 5224 + #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11 5225 + #define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000 5226 + #define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12 5227 + #define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000 5228 + #define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13 5229 + #define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000 5230 + #define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14 5231 + #define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000 5232 + #define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15 5233 + #define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000 5234 + #define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16 5235 + #define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000 5236 + #define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17 5237 + #define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000 5238 + #define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18 5239 + #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000 5240 + #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19 5241 + #define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000 5242 + #define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a 5243 + #define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000 5244 + #define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b 5245 + #define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000 5246 + #define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c 5247 + #define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000 5248 + #define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d 5249 + #define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000 5250 + #define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e 5251 + #define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 5252 + #define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 5253 + #define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1 5254 + #define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0 5255 + #define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2 5256 + #define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1 5257 + #define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4 5258 + #define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2 5259 + #define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8 5260 + #define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3 5261 + #define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10 5262 + #define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4 5263 + #define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40 5264 + #define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6 5265 + #define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80 5266 + #define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7 5267 + #define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100 5268 + #define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8 5269 + #define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200 5270 + #define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9 5271 + #define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400 5272 + #define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa 5273 + #define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800 5274 + #define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb 5275 + #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000 5276 + #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc 5277 + #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000 5278 + #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd 5279 + #define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000 5280 + #define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe 5281 + #define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000 5282 + #define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15 5283 + #define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000 5284 + #define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18 5285 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1 5286 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0 5287 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2 5288 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1 5289 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4 5290 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2 5291 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8 5292 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3 5293 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10 5294 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4 5295 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20 5296 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5 5297 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40 5298 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6 5299 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80 5300 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7 5301 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100 5302 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8 5303 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200 5304 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9 5305 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400 5306 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa 5307 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800 5308 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb 5309 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000 5310 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc 5311 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000 5312 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd 5313 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000 5314 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe 5315 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000 5316 + #define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf 5317 + #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7 5318 + #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0 5319 + #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38 5320 + #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3 5321 + #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000 5322 + #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10 5323 + #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000 5324 + #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11 5325 + #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000 5326 + #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14 5327 + #define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7 5328 + #define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0 5329 + #define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8 5330 + #define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3 5331 + #define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0 5332 + #define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4 5333 + #define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000 5334 + #define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10 5335 + #define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000 5336 + #define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f 5337 + #define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1 5338 + #define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0 5339 + #define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2 5340 + #define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1 5341 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4 5342 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2 5343 + #define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8 5344 + #define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3 5345 + #define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10 5346 + #define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4 5347 + #define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20 5348 + #define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5 5349 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40 5350 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6 5351 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80 5352 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7 5353 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100 5354 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8 5355 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200 5356 + #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9 5357 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400 5358 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa 5359 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800 5360 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb 5361 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000 5362 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc 5363 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000 5364 + #define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd 5365 + #define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000 5366 + #define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe 5367 + #define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000 5368 + #define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf 5369 + #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000 5370 + #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10 5371 + #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000 5372 + #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11 5373 + #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000 5374 + #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12 5375 + #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000 5376 + #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13 5377 + #define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000 5378 + #define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14 5379 + #define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000 5380 + #define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15 5381 + #define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000 5382 + #define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16 5383 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf 5384 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0 5385 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0 5386 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4 5387 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00 5388 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8 5389 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000 5390 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc 5391 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000 5392 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10 5393 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000 5394 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14 5395 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000 5396 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18 5397 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000 5398 + #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c 5399 + #define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff 5400 + #define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0 5401 + #define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000 5402 + #define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10 5403 + #define SCLK_MIN_DIV__FRACV_MASK 0xfff 5404 + #define SCLK_MIN_DIV__FRACV__SHIFT 0x0 5405 + #define SCLK_MIN_DIV__INTV_MASK 0x7f000 5406 + #define SCLK_MIN_DIV__INTV__SHIFT 0xc 5407 + #define PWR_AVFS_SEL__AvfsSel_MASK 0xfffffff 5408 + #define PWR_AVFS_SEL__AvfsSel__SHIFT 0x0 5409 + #define PWR_AVFS_CNTL__MmBusIn_MASK 0xff 5410 + #define PWR_AVFS_CNTL__MmBusIn__SHIFT 0x0 5411 + #define PWR_AVFS_CNTL__MmLclRdEn_MASK 0x100 5412 + #define PWR_AVFS_CNTL__MmLclRdEn__SHIFT 0x8 5413 + #define PWR_AVFS_CNTL__MmLclWrEn_MASK 0x200 5414 + #define PWR_AVFS_CNTL__MmLclWrEn__SHIFT 0x9 5415 + #define PWR_AVFS_CNTL__MmLclSz_MASK 0xc00 5416 + #define PWR_AVFS_CNTL__MmLclSz__SHIFT 0xa 5417 + #define PWR_AVFS_CNTL__MmState_MASK 0x3f000 5418 + #define PWR_AVFS_CNTL__MmState__SHIFT 0xc 5419 + #define PWR_AVFS_CNTL__PsmScanMode_MASK 0x40000 5420 + #define PWR_AVFS_CNTL__PsmScanMode__SHIFT 0x12 5421 + #define PWR_AVFS_CNTL__PsmGater_MASK 0x80000 5422 + #define PWR_AVFS_CNTL__PsmGater__SHIFT 0x13 5423 + #define PWR_AVFS_CNTL__PsmTrst_MASK 0x100000 5424 + #define PWR_AVFS_CNTL__PsmTrst__SHIFT 0x14 5425 + #define PWR_AVFS_CNTL__PsmEn_MASK 0x200000 5426 + #define PWR_AVFS_CNTL__PsmEn__SHIFT 0x15 5427 + #define PWR_AVFS_CNTL__SkipPhaseEn_MASK 0x400000 5428 + #define PWR_AVFS_CNTL__SkipPhaseEn__SHIFT 0x16 5429 + #define PWR_AVFS_CNTL__Isolate_MASK 0x800000 5430 + #define PWR_AVFS_CNTL__Isolate__SHIFT 0x17 5431 + #define PWR_AVFS_CNTL__AvfsRst_MASK 0x1000000 5432 + #define PWR_AVFS_CNTL__AvfsRst__SHIFT 0x18 5433 + #define PWR_AVFS_CNTL__PccIsolateEn_MASK 0x2000000 5434 + #define PWR_AVFS_CNTL__PccIsolateEn__SHIFT 0x19 5435 + #define PWR_AVFS_CNTL__DeepSleepIsolateEn_MASK 0x4000000 5436 + #define PWR_AVFS_CNTL__DeepSleepIsolateEn__SHIFT 0x1a 5437 + #define PWR_AVFS0_CNTL_STATUS__MmDatOut_MASK 0xff 5438 + #define PWR_AVFS0_CNTL_STATUS__MmDatOut__SHIFT 0x0 5439 + #define PWR_AVFS0_CNTL_STATUS__PsmTdo_MASK 0x100 5440 + #define PWR_AVFS0_CNTL_STATUS__PsmTdo__SHIFT 0x8 5441 + #define PWR_AVFS0_CNTL_STATUS__AlarmFlag_MASK 0x200 5442 + #define PWR_AVFS0_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5443 + #define PWR_AVFS1_CNTL_STATUS__MmDatOut_MASK 0xff 5444 + #define PWR_AVFS1_CNTL_STATUS__MmDatOut__SHIFT 0x0 5445 + #define PWR_AVFS1_CNTL_STATUS__PsmTdo_MASK 0x100 5446 + #define PWR_AVFS1_CNTL_STATUS__PsmTdo__SHIFT 0x8 5447 + #define PWR_AVFS1_CNTL_STATUS__AlarmFlag_MASK 0x200 5448 + #define PWR_AVFS1_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5449 + #define PWR_AVFS2_CNTL_STATUS__MmDatOut_MASK 0xff 5450 + #define PWR_AVFS2_CNTL_STATUS__MmDatOut__SHIFT 0x0 5451 + #define PWR_AVFS2_CNTL_STATUS__PsmTdo_MASK 0x100 5452 + #define PWR_AVFS2_CNTL_STATUS__PsmTdo__SHIFT 0x8 5453 + #define PWR_AVFS2_CNTL_STATUS__AlarmFlag_MASK 0x200 5454 + #define PWR_AVFS2_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5455 + #define PWR_AVFS3_CNTL_STATUS__MmDatOut_MASK 0xff 5456 + #define PWR_AVFS3_CNTL_STATUS__MmDatOut__SHIFT 0x0 5457 + #define PWR_AVFS3_CNTL_STATUS__PsmTdo_MASK 0x100 5458 + #define PWR_AVFS3_CNTL_STATUS__PsmTdo__SHIFT 0x8 5459 + #define PWR_AVFS3_CNTL_STATUS__AlarmFlag_MASK 0x200 5460 + #define PWR_AVFS3_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5461 + #define PWR_AVFS4_CNTL_STATUS__MmDatOut_MASK 0xff 5462 + #define PWR_AVFS4_CNTL_STATUS__MmDatOut__SHIFT 0x0 5463 + #define PWR_AVFS4_CNTL_STATUS__PsmTdo_MASK 0x100 5464 + #define PWR_AVFS4_CNTL_STATUS__PsmTdo__SHIFT 0x8 5465 + #define PWR_AVFS4_CNTL_STATUS__AlarmFlag_MASK 0x200 5466 + #define PWR_AVFS4_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5467 + #define PWR_AVFS5_CNTL_STATUS__MmDatOut_MASK 0xff 5468 + #define PWR_AVFS5_CNTL_STATUS__MmDatOut__SHIFT 0x0 5469 + #define PWR_AVFS5_CNTL_STATUS__PsmTdo_MASK 0x100 5470 + #define PWR_AVFS5_CNTL_STATUS__PsmTdo__SHIFT 0x8 5471 + #define PWR_AVFS5_CNTL_STATUS__AlarmFlag_MASK 0x200 5472 + #define PWR_AVFS5_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5473 + #define PWR_AVFS6_CNTL_STATUS__MmDatOut_MASK 0xff 5474 + #define PWR_AVFS6_CNTL_STATUS__MmDatOut__SHIFT 0x0 5475 + #define PWR_AVFS6_CNTL_STATUS__PsmTdo_MASK 0x100 5476 + #define PWR_AVFS6_CNTL_STATUS__PsmTdo__SHIFT 0x8 5477 + #define PWR_AVFS6_CNTL_STATUS__AlarmFlag_MASK 0x200 5478 + #define PWR_AVFS6_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5479 + #define PWR_AVFS7_CNTL_STATUS__MmDatOut_MASK 0xff 5480 + #define PWR_AVFS7_CNTL_STATUS__MmDatOut__SHIFT 0x0 5481 + #define PWR_AVFS7_CNTL_STATUS__PsmTdo_MASK 0x100 5482 + #define PWR_AVFS7_CNTL_STATUS__PsmTdo__SHIFT 0x8 5483 + #define PWR_AVFS7_CNTL_STATUS__AlarmFlag_MASK 0x200 5484 + #define PWR_AVFS7_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5485 + #define PWR_AVFS8_CNTL_STATUS__MmDatOut_MASK 0xff 5486 + #define PWR_AVFS8_CNTL_STATUS__MmDatOut__SHIFT 0x0 5487 + #define PWR_AVFS8_CNTL_STATUS__PsmTdo_MASK 0x100 5488 + #define PWR_AVFS8_CNTL_STATUS__PsmTdo__SHIFT 0x8 5489 + #define PWR_AVFS8_CNTL_STATUS__AlarmFlag_MASK 0x200 5490 + #define PWR_AVFS8_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5491 + #define PWR_AVFS9_CNTL_STATUS__MmDatOut_MASK 0xff 5492 + #define PWR_AVFS9_CNTL_STATUS__MmDatOut__SHIFT 0x0 5493 + #define PWR_AVFS9_CNTL_STATUS__PsmTdo_MASK 0x100 5494 + #define PWR_AVFS9_CNTL_STATUS__PsmTdo__SHIFT 0x8 5495 + #define PWR_AVFS9_CNTL_STATUS__AlarmFlag_MASK 0x200 5496 + #define PWR_AVFS9_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5497 + #define PWR_AVFS10_CNTL_STATUS__MmDatOut_MASK 0xff 5498 + #define PWR_AVFS10_CNTL_STATUS__MmDatOut__SHIFT 0x0 5499 + #define PWR_AVFS10_CNTL_STATUS__PsmTdo_MASK 0x100 5500 + #define PWR_AVFS10_CNTL_STATUS__PsmTdo__SHIFT 0x8 5501 + #define PWR_AVFS10_CNTL_STATUS__AlarmFlag_MASK 0x200 5502 + #define PWR_AVFS10_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5503 + #define PWR_AVFS11_CNTL_STATUS__MmDatOut_MASK 0xff 5504 + #define PWR_AVFS11_CNTL_STATUS__MmDatOut__SHIFT 0x0 5505 + #define PWR_AVFS11_CNTL_STATUS__PsmTdo_MASK 0x100 5506 + #define PWR_AVFS11_CNTL_STATUS__PsmTdo__SHIFT 0x8 5507 + #define PWR_AVFS11_CNTL_STATUS__AlarmFlag_MASK 0x200 5508 + #define PWR_AVFS11_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5509 + #define PWR_AVFS12_CNTL_STATUS__MmDatOut_MASK 0xff 5510 + #define PWR_AVFS12_CNTL_STATUS__MmDatOut__SHIFT 0x0 5511 + #define PWR_AVFS12_CNTL_STATUS__PsmTdo_MASK 0x100 5512 + #define PWR_AVFS12_CNTL_STATUS__PsmTdo__SHIFT 0x8 5513 + #define PWR_AVFS12_CNTL_STATUS__AlarmFlag_MASK 0x200 5514 + #define PWR_AVFS12_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5515 + #define PWR_AVFS13_CNTL_STATUS__MmDatOut_MASK 0xff 5516 + #define PWR_AVFS13_CNTL_STATUS__MmDatOut__SHIFT 0x0 5517 + #define PWR_AVFS13_CNTL_STATUS__PsmTdo_MASK 0x100 5518 + #define PWR_AVFS13_CNTL_STATUS__PsmTdo__SHIFT 0x8 5519 + #define PWR_AVFS13_CNTL_STATUS__AlarmFlag_MASK 0x200 5520 + #define PWR_AVFS13_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5521 + #define PWR_AVFS14_CNTL_STATUS__MmDatOut_MASK 0xff 5522 + #define PWR_AVFS14_CNTL_STATUS__MmDatOut__SHIFT 0x0 5523 + #define PWR_AVFS14_CNTL_STATUS__PsmTdo_MASK 0x100 5524 + #define PWR_AVFS14_CNTL_STATUS__PsmTdo__SHIFT 0x8 5525 + #define PWR_AVFS14_CNTL_STATUS__AlarmFlag_MASK 0x200 5526 + #define PWR_AVFS14_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5527 + #define PWR_AVFS15_CNTL_STATUS__MmDatOut_MASK 0xff 5528 + #define PWR_AVFS15_CNTL_STATUS__MmDatOut__SHIFT 0x0 5529 + #define PWR_AVFS15_CNTL_STATUS__PsmTdo_MASK 0x100 5530 + #define PWR_AVFS15_CNTL_STATUS__PsmTdo__SHIFT 0x8 5531 + #define PWR_AVFS15_CNTL_STATUS__AlarmFlag_MASK 0x200 5532 + #define PWR_AVFS15_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5533 + #define PWR_AVFS16_CNTL_STATUS__MmDatOut_MASK 0xff 5534 + #define PWR_AVFS16_CNTL_STATUS__MmDatOut__SHIFT 0x0 5535 + #define PWR_AVFS16_CNTL_STATUS__PsmTdo_MASK 0x100 5536 + #define PWR_AVFS16_CNTL_STATUS__PsmTdo__SHIFT 0x8 5537 + #define PWR_AVFS16_CNTL_STATUS__AlarmFlag_MASK 0x200 5538 + #define PWR_AVFS16_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5539 + #define PWR_AVFS17_CNTL_STATUS__MmDatOut_MASK 0xff 5540 + #define PWR_AVFS17_CNTL_STATUS__MmDatOut__SHIFT 0x0 5541 + #define PWR_AVFS17_CNTL_STATUS__PsmTdo_MASK 0x100 5542 + #define PWR_AVFS17_CNTL_STATUS__PsmTdo__SHIFT 0x8 5543 + #define PWR_AVFS17_CNTL_STATUS__AlarmFlag_MASK 0x200 5544 + #define PWR_AVFS17_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5545 + #define PWR_AVFS18_CNTL_STATUS__MmDatOut_MASK 0xff 5546 + #define PWR_AVFS18_CNTL_STATUS__MmDatOut__SHIFT 0x0 5547 + #define PWR_AVFS18_CNTL_STATUS__PsmTdo_MASK 0x100 5548 + #define PWR_AVFS18_CNTL_STATUS__PsmTdo__SHIFT 0x8 5549 + #define PWR_AVFS18_CNTL_STATUS__AlarmFlag_MASK 0x200 5550 + #define PWR_AVFS18_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5551 + #define PWR_AVFS19_CNTL_STATUS__MmDatOut_MASK 0xff 5552 + #define PWR_AVFS19_CNTL_STATUS__MmDatOut__SHIFT 0x0 5553 + #define PWR_AVFS19_CNTL_STATUS__PsmTdo_MASK 0x100 5554 + #define PWR_AVFS19_CNTL_STATUS__PsmTdo__SHIFT 0x8 5555 + #define PWR_AVFS19_CNTL_STATUS__AlarmFlag_MASK 0x200 5556 + #define PWR_AVFS19_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5557 + #define PWR_AVFS20_CNTL_STATUS__MmDatOut_MASK 0xff 5558 + #define PWR_AVFS20_CNTL_STATUS__MmDatOut__SHIFT 0x0 5559 + #define PWR_AVFS20_CNTL_STATUS__PsmTdo_MASK 0x100 5560 + #define PWR_AVFS20_CNTL_STATUS__PsmTdo__SHIFT 0x8 5561 + #define PWR_AVFS20_CNTL_STATUS__AlarmFlag_MASK 0x200 5562 + #define PWR_AVFS20_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5563 + #define PWR_AVFS21_CNTL_STATUS__MmDatOut_MASK 0xff 5564 + #define PWR_AVFS21_CNTL_STATUS__MmDatOut__SHIFT 0x0 5565 + #define PWR_AVFS21_CNTL_STATUS__PsmTdo_MASK 0x100 5566 + #define PWR_AVFS21_CNTL_STATUS__PsmTdo__SHIFT 0x8 5567 + #define PWR_AVFS21_CNTL_STATUS__AlarmFlag_MASK 0x200 5568 + #define PWR_AVFS21_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5569 + #define PWR_AVFS22_CNTL_STATUS__MmDatOut_MASK 0xff 5570 + #define PWR_AVFS22_CNTL_STATUS__MmDatOut__SHIFT 0x0 5571 + #define PWR_AVFS22_CNTL_STATUS__PsmTdo_MASK 0x100 5572 + #define PWR_AVFS22_CNTL_STATUS__PsmTdo__SHIFT 0x8 5573 + #define PWR_AVFS22_CNTL_STATUS__AlarmFlag_MASK 0x200 5574 + #define PWR_AVFS22_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5575 + #define PWR_AVFS23_CNTL_STATUS__MmDatOut_MASK 0xff 5576 + #define PWR_AVFS23_CNTL_STATUS__MmDatOut__SHIFT 0x0 5577 + #define PWR_AVFS23_CNTL_STATUS__PsmTdo_MASK 0x100 5578 + #define PWR_AVFS23_CNTL_STATUS__PsmTdo__SHIFT 0x8 5579 + #define PWR_AVFS23_CNTL_STATUS__AlarmFlag_MASK 0x200 5580 + #define PWR_AVFS23_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5581 + #define PWR_AVFS24_CNTL_STATUS__MmDatOut_MASK 0xff 5582 + #define PWR_AVFS24_CNTL_STATUS__MmDatOut__SHIFT 0x0 5583 + #define PWR_AVFS24_CNTL_STATUS__PsmTdo_MASK 0x100 5584 + #define PWR_AVFS24_CNTL_STATUS__PsmTdo__SHIFT 0x8 5585 + #define PWR_AVFS24_CNTL_STATUS__AlarmFlag_MASK 0x200 5586 + #define PWR_AVFS24_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5587 + #define PWR_AVFS25_CNTL_STATUS__MmDatOut_MASK 0xff 5588 + #define PWR_AVFS25_CNTL_STATUS__MmDatOut__SHIFT 0x0 5589 + #define PWR_AVFS25_CNTL_STATUS__PsmTdo_MASK 0x100 5590 + #define PWR_AVFS25_CNTL_STATUS__PsmTdo__SHIFT 0x8 5591 + #define PWR_AVFS25_CNTL_STATUS__AlarmFlag_MASK 0x200 5592 + #define PWR_AVFS25_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5593 + #define PWR_AVFS26_CNTL_STATUS__MmDatOut_MASK 0xff 5594 + #define PWR_AVFS26_CNTL_STATUS__MmDatOut__SHIFT 0x0 5595 + #define PWR_AVFS26_CNTL_STATUS__PsmTdo_MASK 0x100 5596 + #define PWR_AVFS26_CNTL_STATUS__PsmTdo__SHIFT 0x8 5597 + #define PWR_AVFS26_CNTL_STATUS__AlarmFlag_MASK 0x200 5598 + #define PWR_AVFS26_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5599 + #define PWR_AVFS27_CNTL_STATUS__MmDatOut_MASK 0xff 5600 + #define PWR_AVFS27_CNTL_STATUS__MmDatOut__SHIFT 0x0 5601 + #define PWR_AVFS27_CNTL_STATUS__PsmTdo_MASK 0x100 5602 + #define PWR_AVFS27_CNTL_STATUS__PsmTdo__SHIFT 0x8 5603 + #define PWR_AVFS27_CNTL_STATUS__AlarmFlag_MASK 0x200 5604 + #define PWR_AVFS27_CNTL_STATUS__AlarmFlag__SHIFT 0x9 5605 + #define PWR_CKS_ENABLE__STRETCH_ENABLE_MASK 0x1 5606 + #define PWR_CKS_ENABLE__STRETCH_ENABLE__SHIFT 0x0 5607 + #define PWR_CKS_ENABLE__masterReset_MASK 0x2 5608 + #define PWR_CKS_ENABLE__masterReset__SHIFT 0x1 5609 + #define PWR_CKS_ENABLE__staticEnable_MASK 0x4 5610 + #define PWR_CKS_ENABLE__staticEnable__SHIFT 0x2 5611 + #define PWR_CKS_ENABLE__IGNORE_DROOP_DETECT_MASK 0x8 5612 + #define PWR_CKS_ENABLE__IGNORE_DROOP_DETECT__SHIFT 0x3 5613 + #define PWR_CKS_ENABLE__PCC_HAND_SHAKE_EN_MASK 0x10 5614 + #define PWR_CKS_ENABLE__PCC_HAND_SHAKE_EN__SHIFT 0x4 5615 + #define PWR_CKS_ENABLE__MET_CTRL_SEL_MASK 0x60 5616 + #define PWR_CKS_ENABLE__MET_CTRL_SEL__SHIFT 0x5 5617 + #define PWR_CKS_ENABLE__DS_HAND_SHAKE_EN_MASK 0x80 5618 + #define PWR_CKS_ENABLE__DS_HAND_SHAKE_EN__SHIFT 0x7 5619 + #define PWR_CKS_CNTL__CKS_BYPASS_MASK 0x1 5620 + #define PWR_CKS_CNTL__CKS_BYPASS__SHIFT 0x0 5621 + #define PWR_CKS_CNTL__CKS_PCCEnable_MASK 0x2 5622 + #define PWR_CKS_CNTL__CKS_PCCEnable__SHIFT 0x1 5623 + #define PWR_CKS_CNTL__CKS_TEMP_COMP_MASK 0x4 5624 + #define PWR_CKS_CNTL__CKS_TEMP_COMP__SHIFT 0x2 5625 + #define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT_MASK 0x78 5626 + #define PWR_CKS_CNTL__CKS_STRETCH_AMOUNT__SHIFT 0x3 5627 + #define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS_MASK 0x80 5628 + #define PWR_CKS_CNTL__CKS_SKIP_PHASE_BYPASS__SHIFT 0x7 5629 + #define PWR_CKS_CNTL__CKS_SAMPLE_SIZE_MASK 0xf00 5630 + #define PWR_CKS_CNTL__CKS_SAMPLE_SIZE__SHIFT 0x8 5631 + #define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES_MASK 0xf000 5632 + #define PWR_CKS_CNTL__CKS_FSM_WAIT_CYCLES__SHIFT 0xc 5633 + #define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ_MASK 0x10000 5634 + #define PWR_CKS_CNTL__CKS_USE_FOR_LOW_FREQ__SHIFT 0x10 5635 + #define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP_MASK 0x20000 5636 + #define PWR_CKS_CNTL__CKS_NO_EXTRA_COARSE_STEP__SHIFT 0x11 5637 + #define PWR_CKS_CNTL__CKS_LDO_REFSEL_MASK 0x3c0000 5638 + #define PWR_CKS_CNTL__CKS_LDO_REFSEL__SHIFT 0x12 5639 + #define PWR_CKS_CNTL__DDT_DEBUS_SEL_MASK 0x400000 5640 + #define PWR_CKS_CNTL__DDT_DEBUS_SEL__SHIFT 0x16 5641 + #define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL_MASK 0x7f800000 5642 + #define PWR_CKS_CNTL__CKS_LDO_READY_COUNT_VAL__SHIFT 0x17 5643 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 5644 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 5645 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 5646 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 5647 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 5648 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 5649 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 5650 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 5651 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 5652 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 5653 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 5654 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 5655 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 5656 + #define PWR_DISP_TIMER_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 5657 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 5658 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 5659 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 5660 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 5661 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT_MASK 0x4 5662 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_INT__SHIFT 0x2 5663 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 5664 + #define PWR_DISP_TIMER_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 5665 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x1ffffff 5666 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x0 5667 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x2000000 5668 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x19 5669 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE_MASK 0x4000000 5670 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_DISABLE__SHIFT 0x1a 5671 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK_MASK 0x8000000 5672 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MASK__SHIFT 0x1b 5673 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x10000000 5674 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x1c 5675 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE_MASK 0x20000000 5676 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_TYPE__SHIFT 0x1d 5677 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE_MASK 0x40000000 5678 + #define PWR_DISP_TIMER2_CONTROL__DISP_TIMER_INT_MODE__SHIFT 0x1e 5679 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING_MASK 0x1 5680 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_RUNNING__SHIFT 0x0 5681 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT_MASK 0x2 5682 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_STAT__SHIFT 0x1 5683 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT_MASK 0x4 5684 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_INT__SHIFT 0x2 5685 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL_MASK 0xffffff80 5686 + #define PWR_DISP_TIMER2_DEBUG__DISP_TIMER_RUN_VAL__SHIFT 0x7 5687 + #define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH_MASK 0x3ff 5688 + #define PWR_DISP_TIMER_CONTROL2__DISP_TIMER_PULSE_WIDTH__SHIFT 0x0 5689 + #define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK 0xffff 5690 + #define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT 0x0 5691 + #define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK 0xf0000 5692 + #define VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT 0x10 5693 + #define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK 0x1 5694 + #define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT 0x0 5695 + #define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK 0x2 5696 + #define VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT 0x1 5697 + #define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK 0x4 5698 + #define VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT 0x2 5699 + #define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK 0x8 5700 + #define VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT 0x3 5701 + #define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK 0x1 5702 + #define VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT 0x0 5703 + #define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1 5704 + #define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0 5705 + #define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe 5706 + #define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1 5707 + #define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000 5708 + #define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11 5709 + #define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000 5710 + #define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16 5711 + #define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff 5712 + #define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0 5713 + #define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff 5714 + #define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0 5715 + #define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1 5716 + #define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0 5717 + #define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe 5718 + #define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1 5719 + #define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000 5720 + #define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11 5721 + #define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000 5722 + #define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16 5723 + #define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff 5724 + #define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0 5725 + #define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff 5726 + #define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0 5727 + #define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1 5728 + #define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0 5729 + #define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe 5730 + #define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1 5731 + #define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000 5732 + #define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11 5733 + #define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000 5734 + #define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16 5735 + #define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff 5736 + #define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0 5737 + #define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff 5738 + #define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0 5739 + #define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1 5740 + #define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0 5741 + #define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe 5742 + #define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1 5743 + #define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000 5744 + #define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11 5745 + #define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000 5746 + #define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16 5747 + #define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff 5748 + #define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0 5749 + #define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff 5750 + #define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0 5751 + #define LCAC_MC4_CNTL__MC4_ENABLE_MASK 0x1 5752 + #define LCAC_MC4_CNTL__MC4_ENABLE__SHIFT 0x0 5753 + #define LCAC_MC4_CNTL__MC4_THRESHOLD_MASK 0x1fffe 5754 + #define LCAC_MC4_CNTL__MC4_THRESHOLD__SHIFT 0x1 5755 + #define LCAC_MC4_CNTL__MC4_BLOCK_ID_MASK 0x3e0000 5756 + #define LCAC_MC4_CNTL__MC4_BLOCK_ID__SHIFT 0x11 5757 + #define LCAC_MC4_CNTL__MC4_SIGNAL_ID_MASK 0x3fc00000 5758 + #define LCAC_MC4_CNTL__MC4_SIGNAL_ID__SHIFT 0x16 5759 + #define LCAC_MC4_OVR_SEL__MC4_OVR_SEL_MASK 0xffffffff 5760 + #define LCAC_MC4_OVR_SEL__MC4_OVR_SEL__SHIFT 0x0 5761 + #define LCAC_MC4_OVR_VAL__MC4_OVR_VAL_MASK 0xffffffff 5762 + #define LCAC_MC4_OVR_VAL__MC4_OVR_VAL__SHIFT 0x0 5763 + #define LCAC_MC5_CNTL__MC5_ENABLE_MASK 0x1 5764 + #define LCAC_MC5_CNTL__MC5_ENABLE__SHIFT 0x0 5765 + #define LCAC_MC5_CNTL__MC5_THRESHOLD_MASK 0x1fffe 5766 + #define LCAC_MC5_CNTL__MC5_THRESHOLD__SHIFT 0x1 5767 + #define LCAC_MC5_CNTL__MC5_BLOCK_ID_MASK 0x3e0000 5768 + #define LCAC_MC5_CNTL__MC5_BLOCK_ID__SHIFT 0x11 5769 + #define LCAC_MC5_CNTL__MC5_SIGNAL_ID_MASK 0x3fc00000 5770 + #define LCAC_MC5_CNTL__MC5_SIGNAL_ID__SHIFT 0x16 5771 + #define LCAC_MC5_OVR_SEL__MC5_OVR_SEL_MASK 0xffffffff 5772 + #define LCAC_MC5_OVR_SEL__MC5_OVR_SEL__SHIFT 0x0 5773 + #define LCAC_MC5_OVR_VAL__MC5_OVR_VAL_MASK 0xffffffff 5774 + #define LCAC_MC5_OVR_VAL__MC5_OVR_VAL__SHIFT 0x0 5775 + #define LCAC_MC6_CNTL__MC6_ENABLE_MASK 0x1 5776 + #define LCAC_MC6_CNTL__MC6_ENABLE__SHIFT 0x0 5777 + #define LCAC_MC6_CNTL__MC6_THRESHOLD_MASK 0x1fffe 5778 + #define LCAC_MC6_CNTL__MC6_THRESHOLD__SHIFT 0x1 5779 + #define LCAC_MC6_CNTL__MC6_BLOCK_ID_MASK 0x3e0000 5780 + #define LCAC_MC6_CNTL__MC6_BLOCK_ID__SHIFT 0x11 5781 + #define LCAC_MC6_CNTL__MC6_SIGNAL_ID_MASK 0x3fc00000 5782 + #define LCAC_MC6_CNTL__MC6_SIGNAL_ID__SHIFT 0x16 5783 + #define LCAC_MC6_OVR_SEL__MC6_OVR_SEL_MASK 0xffffffff 5784 + #define LCAC_MC6_OVR_SEL__MC6_OVR_SEL__SHIFT 0x0 5785 + #define LCAC_MC6_OVR_VAL__MC6_OVR_VAL_MASK 0xffffffff 5786 + #define LCAC_MC6_OVR_VAL__MC6_OVR_VAL__SHIFT 0x0 5787 + #define LCAC_MC7_CNTL__MC7_ENABLE_MASK 0x1 5788 + #define LCAC_MC7_CNTL__MC7_ENABLE__SHIFT 0x0 5789 + #define LCAC_MC7_CNTL__MC7_THRESHOLD_MASK 0x1fffe 5790 + #define LCAC_MC7_CNTL__MC7_THRESHOLD__SHIFT 0x1 5791 + #define LCAC_MC7_CNTL__MC7_BLOCK_ID_MASK 0x3e0000 5792 + #define LCAC_MC7_CNTL__MC7_BLOCK_ID__SHIFT 0x11 5793 + #define LCAC_MC7_CNTL__MC7_SIGNAL_ID_MASK 0x3fc00000 5794 + #define LCAC_MC7_CNTL__MC7_SIGNAL_ID__SHIFT 0x16 5795 + #define LCAC_MC7_OVR_SEL__MC7_OVR_SEL_MASK 0xffffffff 5796 + #define LCAC_MC7_OVR_SEL__MC7_OVR_SEL__SHIFT 0x0 5797 + #define LCAC_MC7_OVR_VAL__MC7_OVR_VAL_MASK 0xffffffff 5798 + #define LCAC_MC7_OVR_VAL__MC7_OVR_VAL__SHIFT 0x0 5799 + #define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1 5800 + #define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0 5801 + #define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe 5802 + #define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1 5803 + #define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000 5804 + #define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11 5805 + #define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000 5806 + #define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16 5807 + #define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff 5808 + #define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0 5809 + #define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff 5810 + #define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0 5811 + #define ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 5812 + #define ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 5813 + #define ROM_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 5814 + #define ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 5815 + #define ROM_CNTL__SCK_OVERWRITE_MASK 0x2 5816 + #define ROM_CNTL__SCK_OVERWRITE__SHIFT 0x1 5817 + #define ROM_CNTL__CLOCK_GATING_EN_MASK 0x4 5818 + #define ROM_CNTL__CLOCK_GATING_EN__SHIFT 0x2 5819 + #define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK 0xff00 5820 + #define ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT 0x8 5821 + #define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK 0xff0000 5822 + #define ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT 0x10 5823 + #define ROM_CNTL__SCK_PRESCALE_REFCLK_MASK 0xf000000 5824 + #define ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT 0x18 5825 + #define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK 0xf0000000 5826 + #define ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT 0x1c 5827 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR_MASK 0xffffff 5828 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_BASE_ADDR__SHIFT 0x0 5829 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE_MASK 0x1000000 5830 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_INVALIDATE__SHIFT 0x18 5831 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE_MASK 0x2000000 5832 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_ENABLE__SHIFT 0x19 5833 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE_MASK 0xc000000 5834 + #define PAGE_MIRROR_CNTL__PAGE_MIRROR_USAGE__SHIFT 0x1a 5835 + #define ROM_STATUS__ROM_BUSY_MASK 0x1 5836 + #define ROM_STATUS__ROM_BUSY__SHIFT 0x0 5837 + #define CGTT_ROM_CLK_CTRL0__ON_DELAY_MASK 0xf 5838 + #define CGTT_ROM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 5839 + #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 5840 + #define CGTT_ROM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 5841 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 5842 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e 5843 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 5844 + #define CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f 5845 + #define ROM_INDEX__ROM_INDEX_MASK 0xffffff 5846 + #define ROM_INDEX__ROM_INDEX__SHIFT 0x0 5847 + #define ROM_DATA__ROM_DATA_MASK 0xffffffff 5848 + #define ROM_DATA__ROM_DATA__SHIFT 0x0 5849 + #define ROM_START__ROM_START_MASK 0xffffff 5850 + #define ROM_START__ROM_START__SHIFT 0x0 5851 + #define ROM_SW_CNTL__DATA_SIZE_MASK 0xffff 5852 + #define ROM_SW_CNTL__DATA_SIZE__SHIFT 0x0 5853 + #define ROM_SW_CNTL__COMMAND_SIZE_MASK 0x30000 5854 + #define ROM_SW_CNTL__COMMAND_SIZE__SHIFT 0x10 5855 + #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK 0x40000 5856 + #define ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT 0x12 5857 + #define ROM_SW_STATUS__ROM_SW_DONE_MASK 0x1 5858 + #define ROM_SW_STATUS__ROM_SW_DONE__SHIFT 0x0 5859 + #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK 0xff 5860 + #define ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT 0x0 5861 + #define ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK 0xffffff00 5862 + #define ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT 0x8 5863 + #define ROM_SW_DATA_1__ROM_SW_DATA_MASK 0xffffffff 5864 + #define ROM_SW_DATA_1__ROM_SW_DATA__SHIFT 0x0 5865 + #define ROM_SW_DATA_2__ROM_SW_DATA_MASK 0xffffffff 5866 + #define ROM_SW_DATA_2__ROM_SW_DATA__SHIFT 0x0 5867 + #define ROM_SW_DATA_3__ROM_SW_DATA_MASK 0xffffffff 5868 + #define ROM_SW_DATA_3__ROM_SW_DATA__SHIFT 0x0 5869 + #define ROM_SW_DATA_4__ROM_SW_DATA_MASK 0xffffffff 5870 + #define ROM_SW_DATA_4__ROM_SW_DATA__SHIFT 0x0 5871 + #define ROM_SW_DATA_5__ROM_SW_DATA_MASK 0xffffffff 5872 + #define ROM_SW_DATA_5__ROM_SW_DATA__SHIFT 0x0 5873 + #define ROM_SW_DATA_6__ROM_SW_DATA_MASK 0xffffffff 5874 + #define ROM_SW_DATA_6__ROM_SW_DATA__SHIFT 0x0 5875 + #define ROM_SW_DATA_7__ROM_SW_DATA_MASK 0xffffffff 5876 + #define ROM_SW_DATA_7__ROM_SW_DATA__SHIFT 0x0 5877 + #define ROM_SW_DATA_8__ROM_SW_DATA_MASK 0xffffffff 5878 + #define ROM_SW_DATA_8__ROM_SW_DATA__SHIFT 0x0 5879 + #define ROM_SW_DATA_9__ROM_SW_DATA_MASK 0xffffffff 5880 + #define ROM_SW_DATA_9__ROM_SW_DATA__SHIFT 0x0 5881 + #define ROM_SW_DATA_10__ROM_SW_DATA_MASK 0xffffffff 5882 + #define ROM_SW_DATA_10__ROM_SW_DATA__SHIFT 0x0 5883 + #define ROM_SW_DATA_11__ROM_SW_DATA_MASK 0xffffffff 5884 + #define ROM_SW_DATA_11__ROM_SW_DATA__SHIFT 0x0 5885 + #define ROM_SW_DATA_12__ROM_SW_DATA_MASK 0xffffffff 5886 + #define ROM_SW_DATA_12__ROM_SW_DATA__SHIFT 0x0 5887 + #define ROM_SW_DATA_13__ROM_SW_DATA_MASK 0xffffffff 5888 + #define ROM_SW_DATA_13__ROM_SW_DATA__SHIFT 0x0 5889 + #define ROM_SW_DATA_14__ROM_SW_DATA_MASK 0xffffffff 5890 + #define ROM_SW_DATA_14__ROM_SW_DATA__SHIFT 0x0 5891 + #define ROM_SW_DATA_15__ROM_SW_DATA_MASK 0xffffffff 5892 + #define ROM_SW_DATA_15__ROM_SW_DATA__SHIFT 0x0 5893 + #define ROM_SW_DATA_16__ROM_SW_DATA_MASK 0xffffffff 5894 + #define ROM_SW_DATA_16__ROM_SW_DATA__SHIFT 0x0 5895 + #define ROM_SW_DATA_17__ROM_SW_DATA_MASK 0xffffffff 5896 + #define ROM_SW_DATA_17__ROM_SW_DATA__SHIFT 0x0 5897 + #define ROM_SW_DATA_18__ROM_SW_DATA_MASK 0xffffffff 5898 + #define ROM_SW_DATA_18__ROM_SW_DATA__SHIFT 0x0 5899 + #define ROM_SW_DATA_19__ROM_SW_DATA_MASK 0xffffffff 5900 + #define ROM_SW_DATA_19__ROM_SW_DATA__SHIFT 0x0 5901 + #define ROM_SW_DATA_20__ROM_SW_DATA_MASK 0xffffffff 5902 + #define ROM_SW_DATA_20__ROM_SW_DATA__SHIFT 0x0 5903 + #define ROM_SW_DATA_21__ROM_SW_DATA_MASK 0xffffffff 5904 + #define ROM_SW_DATA_21__ROM_SW_DATA__SHIFT 0x0 5905 + #define ROM_SW_DATA_22__ROM_SW_DATA_MASK 0xffffffff 5906 + #define ROM_SW_DATA_22__ROM_SW_DATA__SHIFT 0x0 5907 + #define ROM_SW_DATA_23__ROM_SW_DATA_MASK 0xffffffff 5908 + #define ROM_SW_DATA_23__ROM_SW_DATA__SHIFT 0x0 5909 + #define ROM_SW_DATA_24__ROM_SW_DATA_MASK 0xffffffff 5910 + #define ROM_SW_DATA_24__ROM_SW_DATA__SHIFT 0x0 5911 + #define ROM_SW_DATA_25__ROM_SW_DATA_MASK 0xffffffff 5912 + #define ROM_SW_DATA_25__ROM_SW_DATA__SHIFT 0x0 5913 + #define ROM_SW_DATA_26__ROM_SW_DATA_MASK 0xffffffff 5914 + #define ROM_SW_DATA_26__ROM_SW_DATA__SHIFT 0x0 5915 + #define ROM_SW_DATA_27__ROM_SW_DATA_MASK 0xffffffff 5916 + #define ROM_SW_DATA_27__ROM_SW_DATA__SHIFT 0x0 5917 + #define ROM_SW_DATA_28__ROM_SW_DATA_MASK 0xffffffff 5918 + #define ROM_SW_DATA_28__ROM_SW_DATA__SHIFT 0x0 5919 + #define ROM_SW_DATA_29__ROM_SW_DATA_MASK 0xffffffff 5920 + #define ROM_SW_DATA_29__ROM_SW_DATA__SHIFT 0x0 5921 + #define ROM_SW_DATA_30__ROM_SW_DATA_MASK 0xffffffff 5922 + #define ROM_SW_DATA_30__ROM_SW_DATA__SHIFT 0x0 5923 + #define ROM_SW_DATA_31__ROM_SW_DATA_MASK 0xffffffff 5924 + #define ROM_SW_DATA_31__ROM_SW_DATA__SHIFT 0x0 5925 + #define ROM_SW_DATA_32__ROM_SW_DATA_MASK 0xffffffff 5926 + #define ROM_SW_DATA_32__ROM_SW_DATA__SHIFT 0x0 5927 + #define ROM_SW_DATA_33__ROM_SW_DATA_MASK 0xffffffff 5928 + #define ROM_SW_DATA_33__ROM_SW_DATA__SHIFT 0x0 5929 + #define ROM_SW_DATA_34__ROM_SW_DATA_MASK 0xffffffff 5930 + #define ROM_SW_DATA_34__ROM_SW_DATA__SHIFT 0x0 5931 + #define ROM_SW_DATA_35__ROM_SW_DATA_MASK 0xffffffff 5932 + #define ROM_SW_DATA_35__ROM_SW_DATA__SHIFT 0x0 5933 + #define ROM_SW_DATA_36__ROM_SW_DATA_MASK 0xffffffff 5934 + #define ROM_SW_DATA_36__ROM_SW_DATA__SHIFT 0x0 5935 + #define ROM_SW_DATA_37__ROM_SW_DATA_MASK 0xffffffff 5936 + #define ROM_SW_DATA_37__ROM_SW_DATA__SHIFT 0x0 5937 + #define ROM_SW_DATA_38__ROM_SW_DATA_MASK 0xffffffff 5938 + #define ROM_SW_DATA_38__ROM_SW_DATA__SHIFT 0x0 5939 + #define ROM_SW_DATA_39__ROM_SW_DATA_MASK 0xffffffff 5940 + #define ROM_SW_DATA_39__ROM_SW_DATA__SHIFT 0x0 5941 + #define ROM_SW_DATA_40__ROM_SW_DATA_MASK 0xffffffff 5942 + #define ROM_SW_DATA_40__ROM_SW_DATA__SHIFT 0x0 5943 + #define ROM_SW_DATA_41__ROM_SW_DATA_MASK 0xffffffff 5944 + #define ROM_SW_DATA_41__ROM_SW_DATA__SHIFT 0x0 5945 + #define ROM_SW_DATA_42__ROM_SW_DATA_MASK 0xffffffff 5946 + #define ROM_SW_DATA_42__ROM_SW_DATA__SHIFT 0x0 5947 + #define ROM_SW_DATA_43__ROM_SW_DATA_MASK 0xffffffff 5948 + #define ROM_SW_DATA_43__ROM_SW_DATA__SHIFT 0x0 5949 + #define ROM_SW_DATA_44__ROM_SW_DATA_MASK 0xffffffff 5950 + #define ROM_SW_DATA_44__ROM_SW_DATA__SHIFT 0x0 5951 + #define ROM_SW_DATA_45__ROM_SW_DATA_MASK 0xffffffff 5952 + #define ROM_SW_DATA_45__ROM_SW_DATA__SHIFT 0x0 5953 + #define ROM_SW_DATA_46__ROM_SW_DATA_MASK 0xffffffff 5954 + #define ROM_SW_DATA_46__ROM_SW_DATA__SHIFT 0x0 5955 + #define ROM_SW_DATA_47__ROM_SW_DATA_MASK 0xffffffff 5956 + #define ROM_SW_DATA_47__ROM_SW_DATA__SHIFT 0x0 5957 + #define ROM_SW_DATA_48__ROM_SW_DATA_MASK 0xffffffff 5958 + #define ROM_SW_DATA_48__ROM_SW_DATA__SHIFT 0x0 5959 + #define ROM_SW_DATA_49__ROM_SW_DATA_MASK 0xffffffff 5960 + #define ROM_SW_DATA_49__ROM_SW_DATA__SHIFT 0x0 5961 + #define ROM_SW_DATA_50__ROM_SW_DATA_MASK 0xffffffff 5962 + #define ROM_SW_DATA_50__ROM_SW_DATA__SHIFT 0x0 5963 + #define ROM_SW_DATA_51__ROM_SW_DATA_MASK 0xffffffff 5964 + #define ROM_SW_DATA_51__ROM_SW_DATA__SHIFT 0x0 5965 + #define ROM_SW_DATA_52__ROM_SW_DATA_MASK 0xffffffff 5966 + #define ROM_SW_DATA_52__ROM_SW_DATA__SHIFT 0x0 5967 + #define ROM_SW_DATA_53__ROM_SW_DATA_MASK 0xffffffff 5968 + #define ROM_SW_DATA_53__ROM_SW_DATA__SHIFT 0x0 5969 + #define ROM_SW_DATA_54__ROM_SW_DATA_MASK 0xffffffff 5970 + #define ROM_SW_DATA_54__ROM_SW_DATA__SHIFT 0x0 5971 + #define ROM_SW_DATA_55__ROM_SW_DATA_MASK 0xffffffff 5972 + #define ROM_SW_DATA_55__ROM_SW_DATA__SHIFT 0x0 5973 + #define ROM_SW_DATA_56__ROM_SW_DATA_MASK 0xffffffff 5974 + #define ROM_SW_DATA_56__ROM_SW_DATA__SHIFT 0x0 5975 + #define ROM_SW_DATA_57__ROM_SW_DATA_MASK 0xffffffff 5976 + #define ROM_SW_DATA_57__ROM_SW_DATA__SHIFT 0x0 5977 + #define ROM_SW_DATA_58__ROM_SW_DATA_MASK 0xffffffff 5978 + #define ROM_SW_DATA_58__ROM_SW_DATA__SHIFT 0x0 5979 + #define ROM_SW_DATA_59__ROM_SW_DATA_MASK 0xffffffff 5980 + #define ROM_SW_DATA_59__ROM_SW_DATA__SHIFT 0x0 5981 + #define ROM_SW_DATA_60__ROM_SW_DATA_MASK 0xffffffff 5982 + #define ROM_SW_DATA_60__ROM_SW_DATA__SHIFT 0x0 5983 + #define ROM_SW_DATA_61__ROM_SW_DATA_MASK 0xffffffff 5984 + #define ROM_SW_DATA_61__ROM_SW_DATA__SHIFT 0x0 5985 + #define ROM_SW_DATA_62__ROM_SW_DATA_MASK 0xffffffff 5986 + #define ROM_SW_DATA_62__ROM_SW_DATA__SHIFT 0x0 5987 + #define ROM_SW_DATA_63__ROM_SW_DATA_MASK 0xffffffff 5988 + #define ROM_SW_DATA_63__ROM_SW_DATA__SHIFT 0x0 5989 + #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xffffffff 5990 + #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 5991 + #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0xf 5992 + #define GC_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5993 + #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 5994 + #define GC_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5995 + #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 5996 + #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 5997 + #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 5998 + #define GC_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 5999 + #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY_MASK 0xf 6000 + #define SE_CAC_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6001 + #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 6002 + #define SE_CAC_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6003 + #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 6004 + #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e 6005 + #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 6006 + #define SE_CAC_CGTT_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f 6007 + #define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0_MASK 0xffffffff 6008 + #define GC_CAC_LKG_AGGR_LOWER__LKG_AGGR_31_0__SHIFT 0x0 6009 + #define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32_MASK 0xffffffff 6010 + #define GC_CAC_LKG_AGGR_UPPER__LKG_AGGR_63_32__SHIFT 0x0 6011 + #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0xffff 6012 + #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 6013 + #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1_MASK 0xffff0000 6014 + #define GC_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG1__SHIFT 0x10 6015 + #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2_MASK 0xffff 6016 + #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG2__SHIFT 0x0 6017 + #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3_MASK 0xffff0000 6018 + #define GC_CAC_WEIGHT_CU_1__WEIGHT_CU_SIG3__SHIFT 0x10 6019 + #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4_MASK 0xffff 6020 + #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG4__SHIFT 0x0 6021 + #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5_MASK 0xffff0000 6022 + #define GC_CAC_WEIGHT_CU_2__WEIGHT_CU_SIG5__SHIFT 0x10 6023 + #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6_MASK 0xffff 6024 + #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG6__SHIFT 0x0 6025 + #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7_MASK 0xffff0000 6026 + #define GC_CAC_WEIGHT_CU_3__WEIGHT_CU_SIG7__SHIFT 0x10 6027 + #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8_MASK 0xffff 6028 + #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG8__SHIFT 0x0 6029 + #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9_MASK 0xffff0000 6030 + #define GC_CAC_WEIGHT_CU_4__WEIGHT_CU_SIG9__SHIFT 0x10 6031 + #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10_MASK 0xffff 6032 + #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG10__SHIFT 0x0 6033 + #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11_MASK 0xffff0000 6034 + #define GC_CAC_WEIGHT_CU_5__WEIGHT_CU_SIG11__SHIFT 0x10 6035 + #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12_MASK 0xffff 6036 + #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG12__SHIFT 0x0 6037 + #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13_MASK 0xffff0000 6038 + #define GC_CAC_WEIGHT_CU_6__WEIGHT_CU_SIG13__SHIFT 0x10 6039 + #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14_MASK 0xffff 6040 + #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG14__SHIFT 0x0 6041 + #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15_MASK 0xffff0000 6042 + #define GC_CAC_WEIGHT_CU_7__WEIGHT_CU_SIG15__SHIFT 0x10 6043 + #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0_MASK 0xffffffff 6044 + #define GC_CAC_ACC_CU0__ACCUMULATOR_31_0__SHIFT 0x0 6045 + #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0_MASK 0xffffffff 6046 + #define GC_CAC_ACC_CU1__ACCUMULATOR_31_0__SHIFT 0x0 6047 + #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0_MASK 0xffffffff 6048 + #define GC_CAC_ACC_CU2__ACCUMULATOR_31_0__SHIFT 0x0 6049 + #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0_MASK 0xffffffff 6050 + #define GC_CAC_ACC_CU3__ACCUMULATOR_31_0__SHIFT 0x0 6051 + #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0_MASK 0xffffffff 6052 + #define GC_CAC_ACC_CU4__ACCUMULATOR_31_0__SHIFT 0x0 6053 + #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0_MASK 0xffffffff 6054 + #define GC_CAC_ACC_CU5__ACCUMULATOR_31_0__SHIFT 0x0 6055 + #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0_MASK 0xffffffff 6056 + #define GC_CAC_ACC_CU6__ACCUMULATOR_31_0__SHIFT 0x0 6057 + #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0_MASK 0xffffffff 6058 + #define GC_CAC_ACC_CU7__ACCUMULATOR_31_0__SHIFT 0x0 6059 + #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0_MASK 0xffffffff 6060 + #define GC_CAC_ACC_CU8__ACCUMULATOR_31_0__SHIFT 0x0 6061 + #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0_MASK 0xffffffff 6062 + #define GC_CAC_ACC_CU9__ACCUMULATOR_31_0__SHIFT 0x0 6063 + #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0_MASK 0xffffffff 6064 + #define GC_CAC_ACC_CU10__ACCUMULATOR_31_0__SHIFT 0x0 6065 + #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0_MASK 0xffffffff 6066 + #define GC_CAC_ACC_CU11__ACCUMULATOR_31_0__SHIFT 0x0 6067 + #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0_MASK 0xffffffff 6068 + #define GC_CAC_ACC_CU12__ACCUMULATOR_31_0__SHIFT 0x0 6069 + #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0_MASK 0xffffffff 6070 + #define GC_CAC_ACC_CU13__ACCUMULATOR_31_0__SHIFT 0x0 6071 + #define GC_CAC_ACC_CU14__ACCUMULATOR_31_0_MASK 0xffffffff 6072 + #define GC_CAC_ACC_CU14__ACCUMULATOR_31_0__SHIFT 0x0 6073 + #define GC_CAC_ACC_CU15__ACCUMULATOR_31_0_MASK 0xffffffff 6074 + #define GC_CAC_ACC_CU15__ACCUMULATOR_31_0__SHIFT 0x0 6075 + #define GC_CAC_OVRD_CU__OVRRD_SELECT_MASK 0xffff 6076 + #define GC_CAC_OVRD_CU__OVRRD_SELECT__SHIFT 0x0 6077 + #define GC_CAC_OVRD_CU__OVRRD_VALUE_MASK 0xffff0000 6078 + #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10 6079 + 6080 + #endif /* SMU_7_1_3_SH_MASK_H */