usb: pci-quirks: disable D3cold on xhci suspend for s2idle on AMD Renoir

The XHCI controller is required to enter D3hot rather than D3cold for AMD
s2idle on this hardware generation.

Otherwise, the 'Controller Not Ready' (CNR) bit is not being cleared by
host in resume and eventually this results in xhci resume failures during
the s2idle wakeup.

Link: https://lore.kernel.org/linux-usb/1612527609-7053-1-git-send-email-Prike.Liang@amd.com/
Suggested-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Cc: stable <stable@vger.kernel.org> # 5.11+
Link: https://lore.kernel.org/r/20210527154534.8900-1-mario.limonciello@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Mario Limonciello and committed by
Greg Kroah-Hartman
d1658268 1958ff5a

+7 -1
+6 -1
drivers/usb/host/xhci-pci.c
··· 59 59 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138 60 60 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e 61 61 62 + #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639 62 63 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9 63 64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba 64 65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb ··· 182 181 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) || 183 182 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1))) 184 183 xhci->quirks |= XHCI_U2_DISABLE_WAKE; 184 + 185 + if (pdev->vendor == PCI_VENDOR_ID_AMD && 186 + pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI) 187 + xhci->quirks |= XHCI_BROKEN_D3COLD; 185 188 186 189 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 187 190 xhci->quirks |= XHCI_LPM_SUPPORT; ··· 544 539 * Systems with the TI redriver that loses port status change events 545 540 * need to have the registers polled during D3, so avoid D3cold. 546 541 */ 547 - if (xhci->quirks & XHCI_COMP_MODE_QUIRK) 542 + if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD)) 548 543 pci_d3cold_disable(pdev); 549 544 550 545 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
+1
drivers/usb/host/xhci.h
··· 1892 1892 #define XHCI_DISABLE_SPARSE BIT_ULL(38) 1893 1893 #define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39) 1894 1894 #define XHCI_NO_SOFT_RETRY BIT_ULL(40) 1895 + #define XHCI_BROKEN_D3COLD BIT_ULL(41) 1895 1896 1896 1897 unsigned int num_active_eps; 1897 1898 unsigned int limit_active_eps;