tjh.dev / kernel
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drm/amdgpu: change pcie_gen_cap magic code to macro

This patch changes pcie_gen_cap magic code to macro to make it more
readable.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Cc: Eric Huang <JinHuiEric.Huang@amd.com>
Cc: Ken Wang <Qingqing.Wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Huang Rui and committed by
Alex Deucher d1371f8c 4d54588e

+20 -9
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 1978 1978 return r; 1979 1979 } 1980 1980 1981 - #define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */ 1982 - #define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */ 1983 - 1984 1981 void amdgpu_get_pcie_info(struct amdgpu_device *adev) 1985 1982 { 1986 1983 u32 mask;
+14
drivers/gpu/drm/amd/include/amd_pcie.h
··· 37 37 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF 38 38 #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 39 39 40 + /* gen: chipset 1/2, asic 1/2/3 */ 41 + #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 42 + | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 43 + | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 44 + | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 45 + | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 46 + 40 47 /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */ 41 48 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 42 49 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000 ··· 53 46 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000 54 47 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000 55 48 #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16 49 + 50 + /* 1/2/4/8/16 lanes */ 51 + #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \ 52 + | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \ 53 + | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \ 54 + | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \ 55 + | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 56 56 57 57 #endif
+2 -2
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
··· 733 733 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; 734 734 result = cgs_query_system_info(hwmgr->device, &sys_info); 735 735 if (result) 736 - data->pcie_gen_cap = 0x30007; 736 + data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; 737 737 else 738 738 data->pcie_gen_cap = (uint32_t)sys_info.value; 739 739 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) ··· 742 742 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; 743 743 result = cgs_query_system_info(hwmgr->device, &sys_info); 744 744 if (result) 745 - data->pcie_lane_cap = 0x2f0000; 745 + data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; 746 746 else 747 747 data->pcie_lane_cap = (uint32_t)sys_info.value; 748 748 } else {
+2 -2
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
··· 3293 3293 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; 3294 3294 result = cgs_query_system_info(hwmgr->device, &sys_info); 3295 3295 if (result) 3296 - data->pcie_gen_cap = 0x30007; 3296 + data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; 3297 3297 else 3298 3298 data->pcie_gen_cap = (uint32_t)sys_info.value; 3299 3299 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) ··· 3302 3302 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; 3303 3303 result = cgs_query_system_info(hwmgr->device, &sys_info); 3304 3304 if (result) 3305 - data->pcie_lane_cap = 0x2f0000; 3305 + data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; 3306 3306 else 3307 3307 data->pcie_lane_cap = (uint32_t)sys_info.value; 3308 3308
+2 -2
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
··· 4638 4638 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_GEN_INFO; 4639 4639 result = cgs_query_system_info(hwmgr->device, &sys_info); 4640 4640 if (result) 4641 - data->pcie_gen_cap = 0x30007; 4641 + data->pcie_gen_cap = AMDGPU_DEFAULT_PCIE_GEN_MASK; 4642 4642 else 4643 4643 data->pcie_gen_cap = (uint32_t)sys_info.value; 4644 4644 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) ··· 4647 4647 sys_info.info_id = CGS_SYSTEM_INFO_PCIE_MLW; 4648 4648 result = cgs_query_system_info(hwmgr->device, &sys_info); 4649 4649 if (result) 4650 - data->pcie_lane_cap = 0x2f0000; 4650 + data->pcie_lane_cap = AMDGPU_DEFAULT_PCIE_MLW_MASK; 4651 4651 else 4652 4652 data->pcie_lane_cap = (uint32_t)sys_info.value; 4653 4653 } else {