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linux
[SPARC]: Merge asm-sparc{,64}/cache.h
Signed-off-by: David S. Miller <davem@davemloft.net>
authored by David S. Miller and committed by David S. Miller d113fcd9 f610bbc6
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arch/sparc/kernel/vmlinux.lds.S
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arch/sparc/kernel/vmlinux.lds.S
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include/asm-sparc/cache.h
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include/asm-sparc/cache.h
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/* $Id: cache.h,v 1.9 1999/08/14 03:51:58 anton Exp $
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* cache.h: Cache specific code for the Sparc. These include flushing
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* and direct tag/data line access.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_CACHE_H
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#define _SPARC_CACHE_H
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#include <asm/asi.h>
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES 32
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#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
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#define SMP_CACHE_BYTES 32
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/* Direct access to the instruction cache is provided through and
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* alternate address space. The IDC bit must be off in the ICCR on
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"r" (addr), "i" (ASI_M_FLUSH_USER) :
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"memory");
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}
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#endif /* !(_SPARC_CACHE_H) */
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/* cache.h: Cache specific code for the Sparc. These include flushing
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* and direct tag/data line access.
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*
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* Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
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*/
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#ifndef _SPARC_CACHE_H
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#define _SPARC_CACHE_H
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES 32
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#define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
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#ifdef CONFIG_SPARC32
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#define SMP_CACHE_BYTES_SHIFT 5
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#else
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#define SMP_CACHE_BYTES_SHIFT 6
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#endif
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#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
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#define __read_mostly __attribute__((__section__(".data.read_mostly")))
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#ifdef CONFIG_SPARC32
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#include <asm/asi.h>
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/* Direct access to the instruction cache is provided through and
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* alternate address space. The IDC bit must be off in the ICCR on
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"r" (addr), "i" (ASI_M_FLUSH_USER) :
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"memory");
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}
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#endif /* CONFIG_SPARC32 */
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#endif /* !(_SPARC_CACHE_H) */
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include/asm-sparc64/cache.h
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include/asm-sparc64/cache.h
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/*
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* include/asm-sparc64/cache.h
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*/
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#ifndef __ARCH_SPARC64_CACHE_H
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#define __ARCH_SPARC64_CACHE_H
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/* bytes per L1 cache line */
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#define L1_CACHE_SHIFT 5
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#define L1_CACHE_BYTES 32 /* Two 16-byte sub-blocks per line. */
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#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
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#define SMP_CACHE_BYTES_SHIFT 6
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#define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */
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#define __read_mostly __attribute__((__section__(".data.read_mostly")))
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#endif