clk: qcom: Use qcom_branch_set_clk_en()

tjh.dev / kernel

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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

fork atom

clk: qcom: Use qcom_branch_set_clk_en()

Instead of magically poking at the bit0 of branch clocks' CBCR, use
the newly introduced helper.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240212-topic-clk_branch_en-v7-2-5b79eb7278b2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Konrad Dybcio and committed by

Bjorn Andersson 2 years ago d09ec6f9 a58009dc

+180 -294

38 changed files

expand all collapse all

drivers

clk

qcom

camcc-sc8280xp.c

camcc-sm8550.c

camcc-x1e80100.c

dispcc-qcm2290.c

dispcc-sc7280.c

dispcc-sc8280xp.c

dispcc-sm6115.c

dispcc-sm8250.c

dispcc-sm8450.c

dispcc-sm8550.c

dispcc-sm8650.c

dispcc-x1e80100.c

gcc-sa8775p.c

gcc-sc7180.c

gcc-sc7280.c

gcc-sc8180x.c

gcc-sc8280xp.c

gcc-sdx55.c

gcc-sdx65.c

gcc-sdx75.c

gcc-sm4450.c

gcc-sm6375.c

gcc-sm7150.c

gcc-sm8250.c

gcc-sm8350.c

gcc-sm8450.c

gcc-sm8550.c

gcc-sm8650.c

gcc-x1e80100.c

gpucc-sc7280.c

gpucc-sc8280xp.c

gpucc-sm8550.c

gpucc-x1e80100.c

lpasscorecc-sc7180.c

videocc-sm8250.c

videocc-sm8350.c

videocc-sm8450.c

videocc-sm8550.c

+2 -4

drivers/clk/qcom/camcc-sc8280xp.c

reviewed

··· 3010 3010 clk_lucid_pll_configure(&camcc_pll6, regmap, &camcc_pll6_config); 3011 3011 clk_lucid_pll_configure(&camcc_pll7, regmap, &camcc_pll7_config); 3012 3012 3013 3013 - /* 3014 3014 - * Keep camcc_gdsc_clk always enabled: 3015 3015 - */ 3016 3016 - regmap_update_bits(regmap, 0xc1e4, BIT(0), 1); 3013 3013 + /* Keep some clocks always-on */ 3014 3014 + qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAMCC_GDSC_CLK */ 3017 3015 3018 3016 ret = qcom_cc_really_probe(pdev, &camcc_sc8280xp_desc, regmap); 3019 3017 if (ret)

+3 -7

drivers/clk/qcom/camcc-sm8550.c

reviewed

··· 3536 3536 clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config); 3537 3537 clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config); 3538 3538 3539 3539 - /* 3540 3540 - * Keep clocks always enabled: 3541 3541 - * cam_cc_gdsc_clk 3542 3542 - * cam_cc_sleep_clk 3543 3543 - */ 3544 3544 - regmap_update_bits(regmap, 0x1419c, BIT(0), BIT(0)); 3545 3545 - regmap_update_bits(regmap, 0x142cc, BIT(0), BIT(0)); 3539 3539 + /* Keep some clocks always-on */ 3540 3540 + qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */ 3541 3541 + qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */ 3546 3542 3547 3543 ret = qcom_cc_really_probe(pdev, &cam_cc_sm8550_desc, regmap); 3548 3544

+2 -2

drivers/clk/qcom/camcc-x1e80100.c

reviewed

··· 2462 2462 clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); 2463 2463 2464 2464 /* Keep clocks always enabled */ 2465 2465 - regmap_update_bits(regmap, 0x13a9c, BIT(0), BIT(0)); /* cam_cc_gdsc_clk */ 2466 2466 - regmap_update_bits(regmap, 0x13ab8, BIT(0), BIT(0)); /* cam_cc_sleep_clk */ 2465 2465 + qcom_branch_set_clk_en(regmap, 0x13a9c); /* CAM_CC_GDSC_CLK */ 2466 2466 + qcom_branch_set_clk_en(regmap, 0x13ab8); /* CAM_CC_SLEEP_CLK */ 2467 2467 2468 2468 ret = qcom_cc_really_probe(pdev, &cam_cc_x1e80100_desc, regmap); 2469 2469

+2 -2

drivers/clk/qcom/dispcc-qcm2290.c

reviewed

··· 519 519 520 520 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 521 521 522 522 - /* Keep DISP_CC_XO_CLK always-ON */ 523 523 - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); 522 522 + /* Keep some clocks always-on */ 523 523 + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ 524 524 525 525 ret = qcom_cc_really_probe(pdev, &disp_cc_qcm2290_desc, regmap); 526 526 if (ret) {

+2 -5

drivers/clk/qcom/dispcc-sc7280.c

reviewed

··· 878 878 879 879 clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 880 880 881 881 - /* 882 882 - * Keep the clocks always-ON 883 883 - * DISP_CC_XO_CLK 884 884 - */ 885 885 - regmap_update_bits(regmap, 0x5008, BIT(0), BIT(0)); 881 881 + /* Keep some clocks always-on */ 882 882 + qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */ 886 883 887 884 return qcom_cc_really_probe(pdev, &disp_cc_sc7280_desc, regmap); 888 885 }

+2 -2

drivers/clk/qcom/dispcc-sc8280xp.c

reviewed

··· 3178 3178 goto out_pm_runtime_put; 3179 3179 } 3180 3180 3181 3181 - /* DISP_CC_XO_CLK always-on */ 3182 3182 - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 3181 3181 + /* Keep some clocks always-on */ 3182 3182 + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 3183 3183 3184 3184 out_pm_runtime_put: 3185 3185 pm_runtime_put_sync(&pdev->dev);

+2 -2

drivers/clk/qcom/dispcc-sm6115.c

reviewed

··· 583 583 584 584 clk_alpha_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); 585 585 586 586 - /* Keep DISP_CC_XO_CLK always-ON */ 587 587 - regmap_update_bits(regmap, 0x604c, BIT(0), BIT(0)); 586 586 + /* Keep some clocks always-on */ 587 587 + qcom_branch_set_clk_en(regmap, 0x604c); /* DISP_CC_XO_CLK */ 588 588 589 589 ret = qcom_cc_really_probe(pdev, &disp_cc_sm6115_desc, regmap); 590 590 if (ret) {

+2 -2

drivers/clk/qcom/dispcc-sm8250.c

reviewed

··· 1363 1363 /* Enable clock gating for MDP clocks */ 1364 1364 regmap_update_bits(regmap, 0x8000, 0x10, 0x10); 1365 1365 1366 1366 - /* DISP_CC_XO_CLK always-on */ 1367 1367 - regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0)); 1366 1366 + /* Keep some clocks always-on */ 1367 1367 + qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ 1368 1368 1369 1369 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap); 1370 1370

+2 -5

drivers/clk/qcom/dispcc-sm8450.c

reviewed

··· 1787 1787 /* Enable clock gating for MDP clocks */ 1788 1788 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1789 1789 1790 1790 - /* 1791 1791 - * Keep clocks always enabled: 1792 1792 - * disp_cc_xo_clk 1793 1793 - */ 1794 1794 - regmap_update_bits(regmap, 0xe05c, BIT(0), BIT(0)); 1790 1790 + /* Keep some clocks always-on */ 1791 1791 + qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ 1795 1792 1796 1793 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8450_desc, regmap); 1797 1794 if (ret)

+2 -5

drivers/clk/qcom/dispcc-sm8550.c

reviewed

··· 1780 1780 /* Enable clock gating for MDP clocks */ 1781 1781 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1782 1782 1783 1783 - /* 1784 1784 - * Keep clocks always enabled: 1785 1785 - * disp_cc_xo_clk 1786 1786 - */ 1787 1787 - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); 1783 1783 + /* Keep some clocks always-on */ 1784 1784 + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1788 1785 1789 1786 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8550_desc, regmap); 1790 1787 if (ret)

+2 -2

drivers/clk/qcom/dispcc-sm8650.c

reviewed

··· 1777 1777 /* Enable clock gating for MDP clocks */ 1778 1778 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1779 1779 1780 1780 - /* Keep clocks always enabled */ 1781 1781 - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */ 1780 1780 + /* Keep some clocks always-on */ 1781 1781 + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1782 1782 1783 1783 ret = qcom_cc_really_probe(pdev, &disp_cc_sm8650_desc, regmap); 1784 1784 if (ret)

+2 -2

drivers/clk/qcom/dispcc-x1e80100.c

reviewed

··· 1677 1677 regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); 1678 1678 1679 1679 /* Keep clocks always enabled */ 1680 1680 - regmap_update_bits(regmap, 0xe074, BIT(0), BIT(0)); /* disp_cc_sleep_clk */ 1681 1681 - regmap_update_bits(regmap, 0xe054, BIT(0), BIT(0)); /* disp_cc_xo_clk */ 1680 1680 + qcom_branch_set_clk_en(regmap, 0xe074); /* DISP_CC_SLEEP_CLK */ 1681 1681 + qcom_branch_set_clk_en(regmap, 0xe054); /* DISP_CC_XO_CLK */ 1682 1682 1683 1683 ret = qcom_cc_really_probe(pdev, &disp_cc_x1e80100_desc, regmap); 1684 1684 if (ret)

+10 -15

drivers/clk/qcom/gcc-sa8775p.c

reviewed

··· 4742 4742 if (ret) 4743 4743 return ret; 4744 4744 4745 4745 - /* 4746 4746 - * Keep the clocks always-ON 4747 4747 - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP1_AHB_CLK, 4748 4748 - * GCC_DISP1_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, 4749 4749 - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK. 4750 4750 - */ 4751 4751 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 4752 4752 - regmap_update_bits(regmap, 0x32020, BIT(0), BIT(0)); 4753 4753 - regmap_update_bits(regmap, 0xc7004, BIT(0), BIT(0)); 4754 4754 - regmap_update_bits(regmap, 0xc7018, BIT(0), BIT(0)); 4755 4755 - regmap_update_bits(regmap, 0x33004, BIT(0), BIT(0)); 4756 4756 - regmap_update_bits(regmap, 0x33018, BIT(0), BIT(0)); 4757 4757 - regmap_update_bits(regmap, 0x7d004, BIT(0), BIT(0)); 4758 4758 - regmap_update_bits(regmap, 0x34004, BIT(0), BIT(0)); 4759 4759 - regmap_update_bits(regmap, 0x34024, BIT(0), BIT(0)); 4745 4745 + /* Keep some clocks always-on */ 4746 4746 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_CAMERA_AHB_CLK */ 4747 4747 + qcom_branch_set_clk_en(regmap, 0x32020); /* GCC_CAMERA_XO_CLK */ 4748 4748 + qcom_branch_set_clk_en(regmap, 0xc7004); /* GCC_DISP1_AHB_CLK */ 4749 4749 + qcom_branch_set_clk_en(regmap, 0xc7018); /* GCC_DISP1_XO_CLK */ 4750 4750 + qcom_branch_set_clk_en(regmap, 0x33004); /* GCC_DISP_AHB_CLK */ 4751 4751 + qcom_branch_set_clk_en(regmap, 0x33018); /* GCC_DISP_XO_CLK */ 4752 4752 + qcom_branch_set_clk_en(regmap, 0x7d004); /* GCC_GPU_CFG_AHB_CLK */ 4753 4753 + qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ 4754 4754 + qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ 4760 4755 4761 4756 return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); 4762 4757 }

+9 -13

drivers/clk/qcom/gcc-sc7180.c

reviewed

··· 2443 2443 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 2444 2444 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 2445 2445 2446 2446 - /* 2447 2447 - * Keep the clocks always-ON 2448 2448 - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, 2449 2449 - * GCC_DISP_AHB_CLK, GCC_GPU_CFG_AHB_CLK 2450 2450 - */ 2451 2451 - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 2452 2452 - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 2453 2453 - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 2454 2454 - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 2455 2455 - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); 2456 2456 - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); 2457 2457 - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); 2458 2458 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 2446 2446 + /* Keep some clocks always-on */ 2447 2447 + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 2448 2448 + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ 2449 2449 + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ 2450 2450 + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ 2451 2451 + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ 2452 2452 + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ 2453 2453 + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ 2454 2454 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 2459 2455 2460 2456 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 2461 2457 ARRAY_SIZE(gcc_dfs_clocks));

+8 -12

drivers/clk/qcom/gcc-sc7280.c

reviewed

··· 3453 3453 if (IS_ERR(regmap)) 3454 3454 return PTR_ERR(regmap); 3455 3455 3456 3456 - /* 3457 3457 - * Keep the clocks always-ON 3458 3458 - * GCC_CAMERA_AHB_CLK/XO_CLK, GCC_DISP_AHB_CLK/XO_CLK 3459 3459 - * GCC_VIDEO_AHB_CLK/XO_CLK, GCC_GPU_CFG_AHB_CLK 3460 3460 - */ 3461 3461 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3462 3462 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3463 3463 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3464 3464 - regmap_update_bits(regmap, 0x2701C, BIT(0), BIT(0)); 3465 3465 - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 3466 3466 - regmap_update_bits(regmap, 0x28014, BIT(0), BIT(0)); 3467 3467 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3456 3456 + /* Keep some clocks always-on */ 3457 3457 + qcom_branch_set_clk_en(regmap, 0x26004);/* GCC_CAMERA_AHB_CLK */ 3458 3458 + qcom_branch_set_clk_en(regmap, 0x26028);/* GCC_CAMERA_XO_CLK */ 3459 3459 + qcom_branch_set_clk_en(regmap, 0x27004);/* GCC_DISP_AHB_CLK */ 3460 3460 + qcom_branch_set_clk_en(regmap, 0x2701c);/* GCC_DISP_XO_CLK */ 3461 3461 + qcom_branch_set_clk_en(regmap, 0x28004);/* GCC_VIDEO_AHB_CLK */ 3462 3462 + qcom_branch_set_clk_en(regmap, 0x28014);/* GCC_VIDEO_XO_CLK */ 3463 3463 + qcom_branch_set_clk_en(regmap, 0x71004);/* GCC_GPU_CFG_AHB_CLK */ 3468 3464 regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13)); 3469 3465 3470 3466 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,

+11 -17

drivers/clk/qcom/gcc-sc8180x.c

reviewed

··· 4607 4607 if (IS_ERR(regmap)) 4608 4608 return PTR_ERR(regmap); 4609 4609 4610 4610 - /* 4611 4611 - * Enable the following always-on clocks: 4612 4612 - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 4613 4613 - * GCC_VIDEO_XO_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_XO_CLK, 4614 4614 - * GCC_CPUSS_GNOC_CLK, GCC_CPUSS_DVM_BUS_CLK, GCC_NPU_CFG_AHB_CLK and 4615 4615 - * GCC_GPU_CFG_AHB_CLK 4616 4616 - */ 4617 4617 - regmap_update_bits(regmap, 0xb004, BIT(0), BIT(0)); 4618 4618 - regmap_update_bits(regmap, 0xb008, BIT(0), BIT(0)); 4619 4619 - regmap_update_bits(regmap, 0xb00c, BIT(0), BIT(0)); 4620 4620 - regmap_update_bits(regmap, 0xb040, BIT(0), BIT(0)); 4621 4621 - regmap_update_bits(regmap, 0xb044, BIT(0), BIT(0)); 4622 4622 - regmap_update_bits(regmap, 0xb048, BIT(0), BIT(0)); 4623 4623 - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 4624 4624 - regmap_update_bits(regmap, 0x48190, BIT(0), BIT(0)); 4625 4625 - regmap_update_bits(regmap, 0x4d004, BIT(0), BIT(0)); 4626 4626 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 4610 4610 + /* Keep some clocks always-on */ 4611 4611 + qcom_branch_set_clk_en(regmap, 0xb004); /* GCC_VIDEO_AHB_CLK */ 4612 4612 + qcom_branch_set_clk_en(regmap, 0xb008); /* GCC_CAMERA_AHB_CLK */ 4613 4613 + qcom_branch_set_clk_en(regmap, 0xb00c); /* GCC_DISP_AHB_CLK */ 4614 4614 + qcom_branch_set_clk_en(regmap, 0xb040); /* GCC_VIDEO_XO_CLK */ 4615 4615 + qcom_branch_set_clk_en(regmap, 0xb044); /* GCC_CAMERA_XO_CLK */ 4616 4616 + qcom_branch_set_clk_en(regmap, 0xb048); /* GCC_DISP_XO_CLK */ 4617 4617 + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 4618 4618 + qcom_branch_set_clk_en(regmap, 0x48190); /* GCC_CPUSS_DVM_BUS_CLK */ 4619 4619 + qcom_branch_set_clk_en(regmap, 0x4d004); /* GCC_NPU_CFG_AHB_CLK */ 4620 4620 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 4627 4621 4628 4622 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */ 4629 4623 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);

+10 -15

drivers/clk/qcom/gcc-sc8280xp.c

reviewed

··· 7543 7543 goto err_put_rpm; 7544 7544 } 7545 7545 7546 7546 - /* 7547 7547 - * Keep the clocks always-ON 7548 7548 - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, 7549 7549 - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, 7550 7550 - * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK 7551 7551 - */ 7552 7552 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 7553 7553 - regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); 7554 7554 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 7555 7555 - regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); 7556 7556 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 7557 7557 - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 7558 7558 - regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); 7559 7559 - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); 7560 7560 - regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); 7546 7546 + /* Keep some clocks always-on */ 7547 7547 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 7548 7548 + qcom_branch_set_clk_en(regmap, 0x26020); /* GCC_CAMERA_XO_CLK */ 7549 7549 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 7550 7550 + qcom_branch_set_clk_en(regmap, 0x27028); /* GCC_DISP_XO_CLK */ 7551 7551 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 7552 7552 + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ 7553 7553 + qcom_branch_set_clk_en(regmap, 0x28028); /* GCC_VIDEO_XO_CLK */ 7554 7554 + qcom_branch_set_clk_en(regmap, 0xbb004); /* GCC_DISP1_AHB_CLK */ 7555 7555 + qcom_branch_set_clk_en(regmap, 0xbb028); /* GCC_DISP1_XO_CLK */ 7561 7556 7562 7557 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 7563 7558 if (ret)

+4 -8

drivers/clk/qcom/gcc-sdx55.c

reviewed

··· 1611 1611 if (IS_ERR(regmap)) 1612 1612 return PTR_ERR(regmap); 1613 1613 1614 1614 - /* 1615 1615 - * Keep the clocks always-ON as they are critical to the functioning 1616 1616 - * of the system: 1617 1617 - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK 1618 1618 - */ 1619 1619 - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); 1620 1620 - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); 1621 1621 - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); 1614 1614 + /* Keep some clocks always-on */ 1615 1615 + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 1616 1616 + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ 1617 1617 + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ 1622 1618 1623 1619 return qcom_cc_really_probe(pdev, &gcc_sdx55_desc, regmap); 1624 1620 }

+5 -8

drivers/clk/qcom/gcc-sdx65.c

reviewed

··· 1574 1574 regmap = qcom_cc_map(pdev, &gcc_sdx65_desc); 1575 1575 if (IS_ERR(regmap)) 1576 1576 return PTR_ERR(regmap); 1577 1577 - /* 1578 1578 - * Keep the clocks always-ON as they are critical to the functioning 1579 1579 - * of the system: 1580 1580 - * GCC_SYS_NOC_CPUSS_AHB_CLK, GCC_CPUSS_AHB_CLK, GCC_CPUSS_GNOC_CLK 1581 1581 - */ 1582 1582 - regmap_update_bits(regmap, 0x6d008, BIT(0), BIT(0)); 1583 1583 - regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); 1584 1584 - regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); 1577 1577 + 1578 1578 + /* Keep some clocks always-on */ 1579 1579 + qcom_branch_set_clk_en(regmap, 0x6d008); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 1580 1580 + regmap_update_bits(regmap, 0x6d008, BIT(21), BIT(21)); /* GCC_CPUSS_AHB_CLK */ 1581 1581 + regmap_update_bits(regmap, 0x6d008, BIT(22), BIT(22)); /* GCC_CPUSS_GNOC_CLK */ 1585 1582 1586 1583 return qcom_cc_really_probe(pdev, &gcc_sdx65_desc, regmap); 1587 1584 }

+3 -7

drivers/clk/qcom/gcc-sdx75.c

reviewed

··· 2936 2936 if (ret) 2937 2937 return ret; 2938 2938 2939 2939 - /* 2940 2940 - * Keep clocks always enabled: 2941 2941 - * gcc_ahb_pcie_link_clk 2942 2942 - * gcc_xo_pcie_link_clk 2943 2943 - */ 2944 2944 - regmap_update_bits(regmap, 0x3e004, BIT(0), BIT(0)); 2945 2945 - regmap_update_bits(regmap, 0x3e008, BIT(0), BIT(0)); 2939 2939 + /* Keep some clocks always-on */ 2940 2940 + qcom_branch_set_clk_en(regmap, 0x3e004); /* GCC_AHB_PCIE_LINK_CLK */ 2941 2941 + qcom_branch_set_clk_en(regmap, 0x3e008); /* GCC_XO_PCIE_LINK_CLK */ 2946 2942 2947 2943 return qcom_cc_really_probe(pdev, &gcc_sdx75_desc, regmap); 2948 2944 }

+9 -19

drivers/clk/qcom/gcc-sm4450.c

reviewed

··· 2849 2849 2850 2850 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 2851 2851 2852 2852 - /* 2853 2853 - * Keep clocks always enabled: 2854 2854 - * gcc_camera_ahb_clk 2855 2855 - * gcc_camera_sleep_clk 2856 2856 - * gcc_camera_xo_clk 2857 2857 - * gcc_disp_ahb_clk 2858 2858 - * gcc_disp_xo_clk 2859 2859 - * gcc_gpu_cfg_ahb_clk 2860 2860 - * gcc_video_ahb_clk 2861 2861 - * gcc_video_xo_clk 2862 2862 - */ 2863 2863 - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 2864 2864 - regmap_update_bits(regmap, 0x36018, BIT(0), BIT(0)); 2865 2865 - regmap_update_bits(regmap, 0x3601c, BIT(0), BIT(0)); 2866 2866 - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 2867 2867 - regmap_update_bits(regmap, 0x37014, BIT(0), BIT(0)); 2868 2868 - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 2869 2869 - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 2870 2870 - regmap_update_bits(regmap, 0x42018, BIT(0), BIT(0)); 2852 2852 + /* Keep some clocks always-on */ 2853 2853 + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ 2854 2854 + qcom_branch_set_clk_en(regmap, 0x36018); /* GCC_CAMERA_SLEEP_CLK */ 2855 2855 + qcom_branch_set_clk_en(regmap, 0x3601c); /* GCC_CAMERA_XO_CLK */ 2856 2856 + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ 2857 2857 + qcom_branch_set_clk_en(regmap, 0x37014); /* GCC_DISP_XO_CLK */ 2858 2858 + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ 2859 2859 + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ 2860 2860 + qcom_branch_set_clk_en(regmap, 0x42018); /* GCC_VIDEO_XO_CLK */ 2871 2861 2872 2862 regmap_update_bits(regmap, 0x4201c, BIT(21), BIT(21)); 2873 2863

+4 -7

drivers/clk/qcom/gcc-sm6375.c

reviewed

··· 3882 3882 if (ret) 3883 3883 return ret; 3884 3884 3885 3885 - /* 3886 3886 - * Keep the following clocks always on: 3887 3887 - * GCC_CAMERA_XO_CLK, GCC_CPUSS_GNOC_CLK, GCC_DISP_XO_CLK 3888 3888 - */ 3889 3889 - regmap_update_bits(regmap, 0x17028, BIT(0), BIT(0)); 3890 3890 - regmap_update_bits(regmap, 0x2b004, BIT(0), BIT(0)); 3891 3891 - regmap_update_bits(regmap, 0x1702c, BIT(0), BIT(0)); 3885 3885 + /* Keep some clocks always-on */ 3886 3886 + qcom_branch_set_clk_en(regmap, 0x17028); /* GCC_CAMERA_XO_CLK */ 3887 3887 + qcom_branch_set_clk_en(regmap, 0x2b004); /* GCC_CPUSS_GNOC_CLK */ 3888 3888 + qcom_branch_set_clk_en(regmap, 0x1702c); /* GCC_DISP_XO_CLK */ 3892 3889 3893 3890 clk_lucid_pll_configure(&gpll10, regmap, &gpll10_config); 3894 3891 clk_lucid_pll_configure(&gpll11, regmap, &gpll11_config);

+9 -14

drivers/clk/qcom/gcc-sm7150.c

reviewed

··· 3002 3002 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3003 3003 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3004 3004 3005 3005 - /* 3006 3006 - * Keep the critical clocks always-ON 3007 3007 - * GCC_CPUSS_GNOC_CLK, GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, 3008 3008 - * GCC_DISP_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_VIDEO_XO_CLK, 3009 3009 - * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK 3010 3010 - */ 3011 3011 - regmap_update_bits(regmap, 0x48004, BIT(0), BIT(0)); 3012 3012 - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3013 3013 - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3014 3014 - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3015 3015 - regmap_update_bits(regmap, 0x0b02c, BIT(0), BIT(0)); 3016 3016 - regmap_update_bits(regmap, 0x0b028, BIT(0), BIT(0)); 3017 3017 - regmap_update_bits(regmap, 0x0b030, BIT(0), BIT(0)); 3018 3018 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3005 3005 + /* Keep some clocks always-on */ 3006 3006 + qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ 3007 3007 + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ 3008 3008 + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ 3009 3009 + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ 3010 3010 + qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ 3011 3011 + qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ 3012 3012 + qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ 3013 3013 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3019 3014 3020 3015 ret = qcom_cc_register_rcg_dfs(regmap, gcc_sm7150_dfs_desc, 3021 3016 ARRAY_SIZE(gcc_sm7150_dfs_desc));

+7 -12

drivers/clk/qcom/gcc-sm8250.c

reviewed

··· 3643 3643 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); 3644 3644 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); 3645 3645 3646 3646 - /* 3647 3647 - * Keep the clocks always-ON 3648 3648 - * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK, 3649 3649 - * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK, 3650 3650 - * GCC_SYS_NOC_CPUSS_AHB_CLK 3651 3651 - */ 3652 3652 - regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0)); 3653 3653 - regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0)); 3654 3654 - regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0)); 3655 3655 - regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0)); 3656 3656 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3657 3657 - regmap_update_bits(regmap, 0x52000, BIT(0), BIT(0)); 3646 3646 + /* Keep some clocks always-on */ 3647 3647 + qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ 3648 3648 + qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ 3649 3649 + qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ 3650 3650 + qcom_branch_set_clk_en(regmap, 0x4818c); /* GCC_CPUSS_DVM_BUS_CLK */ 3651 3651 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3652 3652 + qcom_branch_set_clk_en(regmap, 0x52000); /* GCC_SYS_NOC_CPUSS_AHB_CLK */ 3658 3653 3659 3654 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, 3660 3655 ARRAY_SIZE(gcc_dfs_clocks));

+8 -12

drivers/clk/qcom/gcc-sm8350.c

reviewed

··· 3806 3806 return PTR_ERR(regmap); 3807 3807 } 3808 3808 3809 3809 - /* 3810 3810 - * Keep the critical clock always-On 3811 3811 - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, GCC_DISP_XO_CLK, 3812 3812 - * GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, GCC_VIDEO_XO_CLK 3813 3813 - */ 3814 3814 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3815 3815 - regmap_update_bits(regmap, 0x26018, BIT(0), BIT(0)); 3816 3816 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3817 3817 - regmap_update_bits(regmap, 0x2701c, BIT(0), BIT(0)); 3818 3818 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3819 3819 - regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); 3820 3820 - regmap_update_bits(regmap, 0x28020, BIT(0), BIT(0)); 3809 3809 + /* Keep some clocks always-on */ 3810 3810 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3811 3811 + qcom_branch_set_clk_en(regmap, 0x26018); /* GCC_CAMERA_XO_CLK */ 3812 3812 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3813 3813 + qcom_branch_set_clk_en(regmap, 0x2701c); /* GCC_DISP_XO_CLK */ 3814 3814 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3815 3815 + qcom_branch_set_clk_en(regmap, 0x28004); /* GCC_VIDEO_AHB_CLK */ 3816 3816 + qcom_branch_set_clk_en(regmap, 0x28020); /* GCC_VIDEO_XO_CLK */ 3821 3817 3822 3818 ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks)); 3823 3819 if (ret)

+8 -13

drivers/clk/qcom/gcc-sm8450.c

reviewed

··· 3280 3280 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3281 3281 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3282 3282 3283 3283 - /* 3284 3284 - * Keep the critical clock always-On 3285 3285 - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3286 3286 - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3287 3287 - * gcc_video_xo_clk 3288 3288 - */ 3289 3289 - regmap_update_bits(regmap, 0x36004, BIT(0), BIT(0)); 3290 3290 - regmap_update_bits(regmap, 0x36020, BIT(0), BIT(0)); 3291 3291 - regmap_update_bits(regmap, 0x37004, BIT(0), BIT(0)); 3292 3292 - regmap_update_bits(regmap, 0x3701c, BIT(0), BIT(0)); 3293 3293 - regmap_update_bits(regmap, 0x81004, BIT(0), BIT(0)); 3294 3294 - regmap_update_bits(regmap, 0x42004, BIT(0), BIT(0)); 3295 3295 - regmap_update_bits(regmap, 0x42028, BIT(0), BIT(0)); 3283 3283 + /* Keep some clocks always-on */ 3284 3284 + qcom_branch_set_clk_en(regmap, 0x36004); /* GCC_CAMERA_AHB_CLK */ 3285 3285 + qcom_branch_set_clk_en(regmap, 0x36020); /* GCC_CAMERA_XO_CLK */ 3286 3286 + qcom_branch_set_clk_en(regmap, 0x37004); /* GCC_DISP_AHB_CLK */ 3287 3287 + qcom_branch_set_clk_en(regmap, 0x3701c); /* GCC_DISP_XO_CLK */ 3288 3288 + qcom_branch_set_clk_en(regmap, 0x81004); /* GCC_GPU_CFG_AHB_CLK */ 3289 3289 + qcom_branch_set_clk_en(regmap, 0x42004); /* GCC_VIDEO_AHB_CLK */ 3290 3290 + qcom_branch_set_clk_en(regmap, 0x42028); /* GCC_VIDEO_XO_CLK */ 3296 3291 3297 3292 return qcom_cc_really_probe(pdev, &gcc_sm8450_desc, regmap); 3298 3293 }

+8 -13

drivers/clk/qcom/gcc-sm8550.c

reviewed

··· 3352 3352 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3353 3353 regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14)); 3354 3354 3355 3355 - /* 3356 3356 - * Keep the critical clock always-On 3357 3357 - * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, 3358 3358 - * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, 3359 3359 - * gcc_video_xo_clk 3360 3360 - */ 3361 3361 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); 3362 3362 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); 3363 3363 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); 3364 3364 - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); 3365 3365 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); 3366 3366 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); 3367 3367 - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); 3355 3355 + /* Keep some clocks always-on */ 3356 3356 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3357 3357 + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 3358 3358 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3359 3359 + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 3360 3360 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3361 3361 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 3362 3362 + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 3368 3363 3369 3364 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 3370 3365 regmap_write(regmap, 0x52024, 0x0);

+8 -8

drivers/clk/qcom/gcc-sm8650.c

reviewed

··· 3808 3808 if (ret) 3809 3809 return ret; 3810 3810 3811 3811 - /* Keep the critical clock always-On */ 3812 3812 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ 3813 3813 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ 3814 3814 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ 3815 3815 - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ 3816 3816 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ 3817 3817 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ 3818 3818 - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ 3811 3811 + /* Keep some clocks always-on */ 3812 3812 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 3813 3813 + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 3814 3814 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 3815 3815 + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 3816 3816 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 3817 3817 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 3818 3818 + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 3819 3819 3820 3820 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3821 3821

+8 -8

drivers/clk/qcom/gcc-x1e80100.c

reviewed

··· 6769 6769 if (ret) 6770 6770 return ret; 6771 6771 6772 6772 - /* Keep the critical clock always-On */ 6773 6773 - regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ 6774 6774 - regmap_update_bits(regmap, 0x26028, BIT(0), BIT(0)); /* gcc_camera_xo_clk */ 6775 6775 - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); /* gcc_disp_ahb_clk */ 6776 6776 - regmap_update_bits(regmap, 0x27018, BIT(0), BIT(0)); /* gcc_disp_xo_clk */ 6777 6777 - regmap_update_bits(regmap, 0x32004, BIT(0), BIT(0)); /* gcc_video_ahb_clk */ 6778 6778 - regmap_update_bits(regmap, 0x32030, BIT(0), BIT(0)); /* gcc_video_xo_clk */ 6779 6779 - regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); /* gcc_gpu_cfg_ahb_clk */ 6772 6772 + /* Keep some clocks always-on */ 6773 6773 + qcom_branch_set_clk_en(regmap, 0x26004); /* GCC_CAMERA_AHB_CLK */ 6774 6774 + qcom_branch_set_clk_en(regmap, 0x26028); /* GCC_CAMERA_XO_CLK */ 6775 6775 + qcom_branch_set_clk_en(regmap, 0x27004); /* GCC_DISP_AHB_CLK */ 6776 6776 + qcom_branch_set_clk_en(regmap, 0x27018); /* GCC_DISP_XO_CLK */ 6777 6777 + qcom_branch_set_clk_en(regmap, 0x32004); /* GCC_VIDEO_AHB_CLK */ 6778 6778 + qcom_branch_set_clk_en(regmap, 0x32030); /* GCC_VIDEO_XO_CLK */ 6779 6779 + qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ 6780 6780 6781 6781 /* Clear GDSC_SLEEP_ENA_VOTE to stop votes being auto-removed in sleep. */ 6782 6782 regmap_write(regmap, 0x52224, 0x0);

+3 -6

drivers/clk/qcom/gpucc-sc7280.c

reviewed

··· 457 457 458 458 clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 459 459 460 460 - /* 461 461 - * Keep the clocks always-ON 462 462 - * GPU_CC_CB_CLK, GPUCC_CX_GMU_CLK 463 463 - */ 464 464 - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); 465 465 - regmap_update_bits(regmap, 0x1098, BIT(0), BIT(0)); 460 460 + /* Keep some clocks always-on */ 461 461 + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ 462 462 + qcom_branch_set_clk_en(regmap, 0x1098); /* GPUCC_CX_GMU_CLK */ 466 463 regmap_update_bits(regmap, 0x1098, BIT(13), BIT(13)); 467 464 468 465 return qcom_cc_really_probe(pdev, &gpu_cc_sc7280_desc, regmap);

+3 -6

drivers/clk/qcom/gpucc-sc8280xp.c

reviewed

··· 445 445 clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 446 446 clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 447 447 448 448 - /* 449 449 - * Keep the clocks always-ON 450 450 - * GPU_CC_CB_CLK, GPU_CC_CXO_CLK 451 451 - */ 452 452 - regmap_update_bits(regmap, 0x1170, BIT(0), BIT(0)); 453 453 - regmap_update_bits(regmap, 0x109c, BIT(0), BIT(0)); 448 448 + /* Keep some clocks always-on */ 449 449 + qcom_branch_set_clk_en(regmap, 0x1170); /* GPU_CC_CB_CLK */ 450 450 + qcom_branch_set_clk_en(regmap, 0x109c); /* GPU_CC_CXO_CLK */ 454 451 455 452 ret = qcom_cc_really_probe(pdev, &gpu_cc_sc8280xp_desc, regmap); 456 453 pm_runtime_put(&pdev->dev);

+3 -7

drivers/clk/qcom/gpucc-sm8550.c

reviewed

··· 575 575 clk_lucid_ole_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); 576 576 clk_lucid_ole_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 577 577 578 578 - /* 579 579 - * Keep clocks always enabled: 580 580 - * gpu_cc_cxo_aon_clk 581 581 - * gpu_cc_demet_clk 582 582 - */ 583 583 - regmap_update_bits(regmap, 0x9004, BIT(0), BIT(0)); 584 584 - regmap_update_bits(regmap, 0x900c, BIT(0), BIT(0)); 578 578 + /* Keep some clocks always-on */ 579 579 + qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ 580 580 + qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ 585 581 586 582 return qcom_cc_really_probe(pdev, &gpu_cc_sm8550_desc, regmap); 587 583 }

+1 -1

drivers/clk/qcom/gpucc-x1e80100.c

reviewed

··· 638 638 clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); 639 639 640 640 /* Keep clocks always enabled */ 641 641 - regmap_update_bits(regmap, 0x93a4, BIT(0), BIT(0)); /* gpu_cc_cb_clk */ 641 641 + qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ 642 642 643 643 return qcom_cc_really_probe(pdev, &gpu_cc_x1e80100_desc, regmap); 644 644 }

+2 -5

drivers/clk/qcom/lpasscorecc-sc7180.c

reviewed

··· 401 401 goto exit; 402 402 } 403 403 404 404 - /* 405 405 - * Keep the CLK always-ON 406 406 - * LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK 407 407 - */ 408 408 - regmap_update_bits(regmap, 0x24000, BIT(0), BIT(0)); 404 404 + /* Keep some clocks always-on */ 405 405 + qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */ 409 406 410 407 /* PLL settings */ 411 408 regmap_write(regmap, 0x1008, 0x20);

+3 -3

drivers/clk/qcom/videocc-sm8250.c

reviewed

··· 383 383 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); 384 384 clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); 385 385 386 386 - /* Keep VIDEO_CC_AHB_CLK and VIDEO_CC_XO_CLK ALWAYS-ON */ 387 387 - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); 388 388 - regmap_update_bits(regmap, 0xeec, BIT(0), BIT(0)); 386 386 + /* Keep some clocks always-on */ 387 387 + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ 388 388 + qcom_branch_set_clk_en(regmap, 0xeec); /* VIDEO_CC_XO_CLK */ 389 389 390 390 ret = qcom_cc_really_probe(pdev, &video_cc_sm8250_desc, regmap); 391 391

+3 -7

drivers/clk/qcom/videocc-sm8350.c

reviewed

··· 558 558 clk_lucid_pll_configure(&video_pll0, regmap, &video_pll0_config); 559 559 clk_lucid_pll_configure(&video_pll1, regmap, &video_pll1_config); 560 560 561 561 - /* 562 562 - * Keep clocks always enabled: 563 563 - * video_cc_ahb_clk 564 564 - * video_cc_xo_clk 565 565 - */ 566 566 - regmap_update_bits(regmap, 0xe58, BIT(0), BIT(0)); 567 567 - regmap_update_bits(regmap, video_cc_xo_clk_cbcr, BIT(0), BIT(0)); 561 561 + /* Keep some clocks always-on */ 562 562 + qcom_branch_set_clk_en(regmap, 0xe58); /* VIDEO_CC_AHB_CLK */ 563 563 + qcom_branch_set_clk_en(regmap, video_cc_xo_clk_cbcr); /* VIDEO_CC_XO_CLK */ 568 564 569 565 ret = qcom_cc_really_probe(pdev, &video_cc_sm8350_desc, regmap); 570 566 pm_runtime_put(&pdev->dev);

+4 -9

drivers/clk/qcom/videocc-sm8450.c

reviewed

··· 423 423 clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 424 424 clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 425 425 426 426 - /* 427 427 - * Keep clocks always enabled: 428 428 - * video_cc_ahb_clk 429 429 - * video_cc_sleep_clk 430 430 - * video_cc_xo_clk 431 431 - */ 432 432 - regmap_update_bits(regmap, 0x80e4, BIT(0), BIT(0)); 433 433 - regmap_update_bits(regmap, 0x8130, BIT(0), BIT(0)); 434 434 - regmap_update_bits(regmap, 0x8114, BIT(0), BIT(0)); 426 426 + /* Keep some clocks always-on */ 427 427 + qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ 428 428 + qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ 429 429 + qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ 435 430 436 431 ret = qcom_cc_really_probe(pdev, &video_cc_sm8450_desc, regmap); 437 432

+4 -9

drivers/clk/qcom/videocc-sm8550.c

reviewed

··· 428 428 clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 429 429 clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 430 430 431 431 - /* 432 432 - * Keep clocks always enabled: 433 433 - * video_cc_ahb_clk 434 434 - * video_cc_sleep_clk 435 435 - * video_cc_xo_clk 436 436 - */ 437 437 - regmap_update_bits(regmap, 0x80f4, BIT(0), BIT(0)); 438 438 - regmap_update_bits(regmap, 0x8140, BIT(0), BIT(0)); 439 439 - regmap_update_bits(regmap, 0x8124, BIT(0), BIT(0)); 431 431 + /* Keep some clocks always-on */ 432 432 + qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ 433 433 + qcom_branch_set_clk_en(regmap, 0x8140); /* VIDEO_CC_SLEEP_CLK */ 434 434 + qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ 440 435 441 436 ret = qcom_cc_really_probe(pdev, &video_cc_sm8550_desc, regmap); 442 437