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ARC: MMUv4 preps/2 - Reshuffle PTE bits
With previous commit freeing up PTE bits, reassign them so as to:
- Match the bit to H/w counterpart where possible
(e.g. MMUv2 GLOBAL/PRESENT, this avoids a shift in create_tlb())
- Avoid holes in _PAGE_xxx definitions
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
+11
-25
+8
-14
arch/arc/include/asm/pgtable.h
+8
-14
arch/arc/include/asm/pgtable.h
···
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#define _PAGE_EXECUTE (1<<3) /* Page has user execute perm (H) */
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#define _PAGE_WRITE (1<<4) /* Page has user write perm (H) */
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#define _PAGE_READ (1<<5) /* Page has user read perm (H) */
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-
#define _PAGE_GLOBAL (1<<9) /* Page is global (H) */
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-
#define _PAGE_MODIFIED (1<<10) /* Page modified (dirty) (S) */
65
-
#define _PAGE_FILE (1<<10) /* page cache/ swap (S) */
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-
#define _PAGE_PRESENT (1<<11) /* TLB entry is valid (H) */
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+
#define _PAGE_MODIFIED (1<<6) /* Page modified (dirty) (S) */
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+
#define _PAGE_FILE (1<<7) /* page cache/ swap (S) */
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+
#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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+
#define _PAGE_PRESENT (1<<10) /* TLB entry is valid (H) */
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#else /* MMU v3 onwards */
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-
/* PD1 */
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#define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */
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#define _PAGE_EXECUTE (1<<1) /* Page has user execute perm (H) */
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#define _PAGE_WRITE (1<<2) /* Page has user write perm (H) */
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#define _PAGE_READ (1<<3) /* Page has user read perm (H) */
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-
#define _PAGE_ACCESSED (1<<7) /* Page is accessed (S) */
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-
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-
/* PD0 */
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+
#define _PAGE_ACCESSED (1<<4) /* Page is accessed (S) */
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+
#define _PAGE_MODIFIED (1<<5) /* Page modified (dirty) (S) */
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+
#define _PAGE_FILE (1<<6) /* page cache/ swap (S) */
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#define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
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#define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
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-
#define _PAGE_SHARED_CODE (1<<10) /* Shared Code page with cmn vaddr
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+
#define _PAGE_SHARED_CODE (1<<11) /* Shared Code page with cmn vaddr
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usable for shared TLB entries (H) */
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-
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-
#define _PAGE_MODIFIED (1<<11) /* Page modified (dirty) (S) */
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-
#define _PAGE_FILE (1<<12) /* page cache/ swap (S) */
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-
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-
#define _PAGE_SHARED_CODE_H (1<<31) /* Hardware counterpart of above */
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#endif
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/* vmalloc permissions */
+3
-8
arch/arc/mm/tlb.c
+3
-8
arch/arc/mm/tlb.c
···
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{
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unsigned long flags;
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unsigned int idx, asid_or_sasid, rwx;
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-
unsigned long pd0_flags;
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/*
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* create_tlb() assumes that current->mm == vma->mm, since
···
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/* update this PTE credentials */
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pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
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-
/* Create HW TLB entry Flags (in PD0) from PTE Flags */
384
-
#if (CONFIG_ARC_MMU_VER <= 2)
385
-
pd0_flags = ((pte_val(*ptep) & PTE_BITS_IN_PD0) >> 1);
386
-
#else
387
-
pd0_flags = ((pte_val(*ptep) & PTE_BITS_IN_PD0));
388
-
#endif
384
+
/* Create HW TLB(PD0,PD1) from PTE */
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/* ASID for this task */
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asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
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-
write_aux_reg(ARC_REG_TLBPD0, address | pd0_flags | asid_or_sasid);
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+
write_aux_reg(ARC_REG_TLBPD0, address | asid_or_sasid |
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+
(pte_val(*ptep) & PTE_BITS_IN_PD0));
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/*
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* ARC MMU provides fully orthogonal access bits for K/U mode,
-3
arch/arc/mm/tlbex.S
-3
arch/arc/mm/tlbex.S
···
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sr r3, [ARC_REG_TLBPD1] ; these go in PD1
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and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
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-
#if (CONFIG_ARC_MMU_VER <= 2) /* Neednot be done with v3 onwards */
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-
lsr r2, r2 ; shift PTE flags to match layout in PD0
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-
#endif
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lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
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