tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: mediatek: hdmi: mt2701: use common helper to access registers

Use MediaTek phy's common helper to access registers, then we can remove
hdmi's I/O helpers.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220920090038.15133-9-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Chunfeng Yun and committed by
Vinod Koul cff81a61 a98d935e

+70 -74
+70 -74
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
··· 5 5 */ 6 6 7 7 #include "phy-mtk-hdmi.h" 8 + #include "phy-mtk-io.h" 8 9 9 10 #define HDMI_CON0 0x00 10 11 #define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0) ··· 50 49 static int mtk_hdmi_pll_prepare(struct clk_hw *hw) 51 50 { 52 51 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 52 + void __iomem *base = hdmi_phy->regs; 53 53 54 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 55 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 56 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 57 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 54 + mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); 55 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); 56 + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); 57 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); 58 58 usleep_range(80, 100); 59 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 60 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 61 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 59 + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); 60 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 61 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 62 62 usleep_range(80, 100); 63 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 64 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 65 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 66 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 63 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 64 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); 65 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 66 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 67 67 usleep_range(80, 100); 68 68 return 0; 69 69 } ··· 72 70 static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) 73 71 { 74 72 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 73 + void __iomem *base = hdmi_phy->regs; 75 74 76 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 77 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 78 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 79 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 75 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 76 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 77 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); 78 + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 80 79 usleep_range(80, 100); 81 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 82 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 83 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 80 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 81 + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 82 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); 84 83 usleep_range(80, 100); 85 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 86 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 87 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 88 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 84 + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); 85 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); 86 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); 87 + mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); 89 88 usleep_range(80, 100); 90 89 } 91 90 ··· 100 97 unsigned long parent_rate) 101 98 { 102 99 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw); 100 + void __iomem *base = hdmi_phy->regs; 103 101 u32 pos_div; 104 102 105 103 if (rate <= 64000000) ··· 110 106 else 111 107 pos_div = 1; 112 108 113 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK); 114 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 115 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); 116 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1), 117 - RG_HTPLL_IC_MASK); 118 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1), 119 - RG_HTPLL_IR_MASK); 120 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div), 121 - RG_HDMITX_TX_POSDIV_MASK); 122 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1), 123 - RG_HTPLL_FBKSEL_MASK); 124 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19), 125 - RG_HTPLL_FBKDIV_MASK); 126 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2), 127 - RG_HTPLL_DIVEN_MASK); 128 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc), 129 - RG_HTPLL_BP_MASK); 130 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2), 131 - RG_HTPLL_BC_MASK); 132 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1), 133 - RG_HTPLL_BR_MASK); 109 + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK); 110 + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); 111 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV); 112 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1); 113 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1); 114 + mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div); 115 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1); 116 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19); 117 + mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2); 118 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc); 119 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2); 120 + mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1); 134 121 135 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP); 136 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3), 137 - RG_HDMITX_PRED_IBIAS_MASK); 138 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK); 139 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28), 140 - RG_HDMITX_DRV_IMP_MASK); 141 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK); 142 - mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa), 143 - RG_HDMITX_DRV_IBIAS_MASK); 122 + mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP); 123 + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3); 124 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK); 125 + mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28); 126 + mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28); 127 + mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa); 144 128 return 0; 145 129 } 146 130 ··· 176 184 177 185 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy) 178 186 { 179 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 180 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 181 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 182 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 187 + void __iomem *base = hdmi_phy->regs; 188 + 189 + mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); 190 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); 191 + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); 192 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); 183 193 usleep_range(80, 100); 184 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 185 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 186 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 194 + mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN); 195 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 196 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 187 197 usleep_range(80, 100); 188 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 189 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 190 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 191 - mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 198 + mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 199 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); 200 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 201 + mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 192 202 usleep_range(80, 100); 193 203 } 194 204 195 205 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) 196 206 { 197 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 198 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 199 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK); 200 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 207 + void __iomem *base = hdmi_phy->regs; 208 + 209 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK); 210 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK); 211 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK); 212 + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN); 201 213 usleep_range(80, 100); 202 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 203 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 204 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN); 214 + mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK); 215 + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO); 216 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN); 205 217 usleep_range(80, 100); 206 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS); 207 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK); 208 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN); 209 - mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN); 218 + mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS); 219 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK); 220 + mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN); 221 + mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN); 210 222 usleep_range(80, 100); 211 223 } 212 224