tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: camcc-sdm845: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-8-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson cf4cd3dc f1697f36

+25 -25
+25 -25
drivers/clk/qcom/camcc-sdm845.c
··· 190 190 .clkr.hw.init = &(struct clk_init_data){ 191 191 .name = "cam_cc_bps_clk_src", 192 192 .parent_names = cam_cc_parent_names_0, 193 - .num_parents = 6, 193 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 194 194 .flags = CLK_SET_RATE_PARENT, 195 195 .ops = &clk_rcg2_shared_ops, 196 196 }, ··· 213 213 .clkr.hw.init = &(struct clk_init_data){ 214 214 .name = "cam_cc_cci_clk_src", 215 215 .parent_names = cam_cc_parent_names_0, 216 - .num_parents = 6, 216 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 217 217 .ops = &clk_rcg2_ops, 218 218 }, 219 219 }; ··· 233 233 .clkr.hw.init = &(struct clk_init_data){ 234 234 .name = "cam_cc_cphy_rx_clk_src", 235 235 .parent_names = cam_cc_parent_names_0, 236 - .num_parents = 6, 236 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 237 237 .ops = &clk_rcg2_ops, 238 238 }, 239 239 }; ··· 254 254 .clkr.hw.init = &(struct clk_init_data){ 255 255 .name = "cam_cc_csi0phytimer_clk_src", 256 256 .parent_names = cam_cc_parent_names_0, 257 - .num_parents = 6, 257 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 258 258 .flags = CLK_SET_RATE_PARENT, 259 259 .ops = &clk_rcg2_ops, 260 260 }, ··· 269 269 .clkr.hw.init = &(struct clk_init_data){ 270 270 .name = "cam_cc_csi1phytimer_clk_src", 271 271 .parent_names = cam_cc_parent_names_0, 272 - .num_parents = 6, 272 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 273 273 .flags = CLK_SET_RATE_PARENT, 274 274 .ops = &clk_rcg2_ops, 275 275 }, ··· 284 284 .clkr.hw.init = &(struct clk_init_data){ 285 285 .name = "cam_cc_csi2phytimer_clk_src", 286 286 .parent_names = cam_cc_parent_names_0, 287 - .num_parents = 6, 287 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 288 288 .flags = CLK_SET_RATE_PARENT, 289 289 .ops = &clk_rcg2_ops, 290 290 }, ··· 299 299 .clkr.hw.init = &(struct clk_init_data){ 300 300 .name = "cam_cc_csi3phytimer_clk_src", 301 301 .parent_names = cam_cc_parent_names_0, 302 - .num_parents = 6, 302 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 303 303 .flags = CLK_SET_RATE_PARENT, 304 304 .ops = &clk_rcg2_ops, 305 305 }, ··· 324 324 .clkr.hw.init = &(struct clk_init_data){ 325 325 .name = "cam_cc_fast_ahb_clk_src", 326 326 .parent_names = cam_cc_parent_names_0, 327 - .num_parents = 6, 327 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 328 328 .ops = &clk_rcg2_ops, 329 329 }, 330 330 }; ··· 347 347 .clkr.hw.init = &(struct clk_init_data){ 348 348 .name = "cam_cc_fd_core_clk_src", 349 349 .parent_names = cam_cc_parent_names_0, 350 - .num_parents = 6, 350 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 351 351 .ops = &clk_rcg2_shared_ops, 352 352 }, 353 353 }; ··· 370 370 .clkr.hw.init = &(struct clk_init_data){ 371 371 .name = "cam_cc_icp_clk_src", 372 372 .parent_names = cam_cc_parent_names_0, 373 - .num_parents = 6, 373 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 374 374 .ops = &clk_rcg2_shared_ops, 375 375 }, 376 376 }; ··· 394 394 .clkr.hw.init = &(struct clk_init_data){ 395 395 .name = "cam_cc_ife_0_clk_src", 396 396 .parent_names = cam_cc_parent_names_0, 397 - .num_parents = 6, 397 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 398 398 .flags = CLK_SET_RATE_PARENT, 399 399 .ops = &clk_rcg2_shared_ops, 400 400 }, ··· 417 417 .clkr.hw.init = &(struct clk_init_data){ 418 418 .name = "cam_cc_ife_0_csid_clk_src", 419 419 .parent_names = cam_cc_parent_names_0, 420 - .num_parents = 6, 420 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 421 421 .ops = &clk_rcg2_shared_ops, 422 422 }, 423 423 }; ··· 431 431 .clkr.hw.init = &(struct clk_init_data){ 432 432 .name = "cam_cc_ife_1_clk_src", 433 433 .parent_names = cam_cc_parent_names_0, 434 - .num_parents = 6, 434 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 435 435 .flags = CLK_SET_RATE_PARENT, 436 436 .ops = &clk_rcg2_shared_ops, 437 437 }, ··· 446 446 .clkr.hw.init = &(struct clk_init_data){ 447 447 .name = "cam_cc_ife_1_csid_clk_src", 448 448 .parent_names = cam_cc_parent_names_0, 449 - .num_parents = 6, 449 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 450 450 .ops = &clk_rcg2_shared_ops, 451 451 }, 452 452 }; ··· 460 460 .clkr.hw.init = &(struct clk_init_data){ 461 461 .name = "cam_cc_ife_lite_clk_src", 462 462 .parent_names = cam_cc_parent_names_0, 463 - .num_parents = 6, 463 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 464 464 .flags = CLK_SET_RATE_PARENT, 465 465 .ops = &clk_rcg2_shared_ops, 466 466 }, ··· 475 475 .clkr.hw.init = &(struct clk_init_data){ 476 476 .name = "cam_cc_ife_lite_csid_clk_src", 477 477 .parent_names = cam_cc_parent_names_0, 478 - .num_parents = 6, 478 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 479 479 .ops = &clk_rcg2_shared_ops, 480 480 }, 481 481 }; ··· 500 500 .clkr.hw.init = &(struct clk_init_data){ 501 501 .name = "cam_cc_ipe_0_clk_src", 502 502 .parent_names = cam_cc_parent_names_0, 503 - .num_parents = 6, 503 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 504 504 .flags = CLK_SET_RATE_PARENT, 505 505 .ops = &clk_rcg2_shared_ops, 506 506 }, ··· 515 515 .clkr.hw.init = &(struct clk_init_data){ 516 516 .name = "cam_cc_ipe_1_clk_src", 517 517 .parent_names = cam_cc_parent_names_0, 518 - .num_parents = 6, 518 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 519 519 .flags = CLK_SET_RATE_PARENT, 520 520 .ops = &clk_rcg2_shared_ops, 521 521 }, ··· 530 530 .clkr.hw.init = &(struct clk_init_data){ 531 531 .name = "cam_cc_jpeg_clk_src", 532 532 .parent_names = cam_cc_parent_names_0, 533 - .num_parents = 6, 533 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 534 534 .flags = CLK_SET_RATE_PARENT, 535 535 .ops = &clk_rcg2_shared_ops, 536 536 }, ··· 555 555 .clkr.hw.init = &(struct clk_init_data){ 556 556 .name = "cam_cc_lrme_clk_src", 557 557 .parent_names = cam_cc_parent_names_0, 558 - .num_parents = 6, 558 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 559 559 .flags = CLK_SET_RATE_PARENT, 560 560 .ops = &clk_rcg2_shared_ops, 561 561 }, ··· 578 578 .clkr.hw.init = &(struct clk_init_data){ 579 579 .name = "cam_cc_mclk0_clk_src", 580 580 .parent_names = cam_cc_parent_names_0, 581 - .num_parents = 6, 581 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 582 582 .flags = CLK_SET_RATE_PARENT, 583 583 .ops = &clk_rcg2_ops, 584 584 }, ··· 593 593 .clkr.hw.init = &(struct clk_init_data){ 594 594 .name = "cam_cc_mclk1_clk_src", 595 595 .parent_names = cam_cc_parent_names_0, 596 - .num_parents = 6, 596 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 597 597 .flags = CLK_SET_RATE_PARENT, 598 598 .ops = &clk_rcg2_ops, 599 599 }, ··· 608 608 .clkr.hw.init = &(struct clk_init_data){ 609 609 .name = "cam_cc_mclk2_clk_src", 610 610 .parent_names = cam_cc_parent_names_0, 611 - .num_parents = 6, 611 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 612 612 .flags = CLK_SET_RATE_PARENT, 613 613 .ops = &clk_rcg2_ops, 614 614 }, ··· 623 623 .clkr.hw.init = &(struct clk_init_data){ 624 624 .name = "cam_cc_mclk3_clk_src", 625 625 .parent_names = cam_cc_parent_names_0, 626 - .num_parents = 6, 626 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 627 627 .flags = CLK_SET_RATE_PARENT, 628 628 .ops = &clk_rcg2_ops, 629 629 }, ··· 647 647 .clkr.hw.init = &(struct clk_init_data){ 648 648 .name = "cam_cc_slow_ahb_clk_src", 649 649 .parent_names = cam_cc_parent_names_0, 650 - .num_parents = 6, 650 + .num_parents = ARRAY_SIZE(cam_cc_parent_names_0), 651 651 .flags = CLK_SET_RATE_PARENT, 652 652 .ops = &clk_rcg2_ops, 653 653 },