fsl_ifc: Change IO accessor based on endianness

+3

Documentation/devicetree/bindings/memory-controllers/fsl/ifc.txt

··· 18 18 interrupt (NAND_EVTER_STAT). If there is only one, 19 19 that interrupt reports both types of event. 20 20 21 + - little-endian : If this property is absent, the big-endian mode will 22 + be in use as default for registers. 21 23 22 24 - ranges : Each range corresponds to a single chipselect, and covers 23 25 the entire access window as configured. ··· 36 34 #size-cells = <1>; 37 35 reg = <0x0 0xffe1e000 0 0x2000>; 38 36 interrupts = <16 2 19 2>; 37 + little-endian; 39 38 40 39 /* NOR, NAND Flashes and CPLD on board */ 41 40 ranges = <0x0 0x0 0x0 0xee000000 0x02000000

+30 -13

drivers/memory/fsl_ifc.c

··· 62 62 return -ENODEV; 63 63 64 64 for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) { 65 - u32 cspr = in_be32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr); 65 + u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr); 66 66 if (cspr & CSPR_V && (cspr & CSPR_BA) == 67 67 convert_ifc_address(addr_base)) 68 68 return i; ··· 79 79 /* 80 80 * Clear all the common status and event registers 81 81 */ 82 - if (in_be32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER) 83 - out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER); 82 + if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER) 83 + ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat); 84 84 85 85 /* enable all error and events */ 86 - out_be32(&ifc->cm_evter_en, IFC_CM_EVTER_EN_CSEREN); 86 + ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en); 87 87 88 88 /* enable all error and event interrupts */ 89 - out_be32(&ifc->cm_evter_intr_en, IFC_CM_EVTER_INTR_EN_CSERIREN); 90 - out_be32(&ifc->cm_erattr0, 0x0); 91 - out_be32(&ifc->cm_erattr1, 0x0); 89 + ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en); 90 + ifc_out32(0x0, &ifc->cm_erattr0); 91 + ifc_out32(0x0, &ifc->cm_erattr1); 92 92 93 93 return 0; 94 94 } ··· 127 127 128 128 spin_lock_irqsave(&nand_irq_lock, flags); 129 129 130 - stat = in_be32(&ifc->ifc_nand.nand_evter_stat); 130 + stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat); 131 131 if (stat) { 132 - out_be32(&ifc->ifc_nand.nand_evter_stat, stat); 132 + ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat); 133 133 ctrl->nand_stat = stat; 134 134 wake_up(&ctrl->nand_wait); 135 135 } ··· 161 161 irqreturn_t ret = IRQ_NONE; 162 162 163 163 /* read for chip select error */ 164 - cs_err = in_be32(&ifc->cm_evter_stat); 164 + cs_err = ifc_in32(&ifc->cm_evter_stat); 165 165 if (cs_err) { 166 166 dev_err(ctrl->dev, "transaction sent to IFC is not mapped to" 167 167 "any memory bank 0x%08X\n", cs_err); 168 168 /* clear the chip select error */ 169 - out_be32(&ifc->cm_evter_stat, IFC_CM_EVTER_STAT_CSER); 169 + ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat); 170 170 171 171 /* read error attribute registers print the error information */ 172 - status = in_be32(&ifc->cm_erattr0); 173 - err_addr = in_be32(&ifc->cm_erattr1); 172 + status = ifc_in32(&ifc->cm_erattr0); 173 + err_addr = ifc_in32(&ifc->cm_erattr1); 174 174 175 175 if (status & IFC_CM_ERATTR0_ERTYP_READ) 176 176 dev_err(ctrl->dev, "Read transaction error" ··· 229 229 dev_err(&dev->dev, "failed to get memory region\n"); 230 230 ret = -ENODEV; 231 231 goto err; 232 + } 233 + 234 + version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) & 235 + FSL_IFC_VERSION_MASK; 236 + banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8; 237 + dev_info(&dev->dev, "IFC version %d.%d, %d banks\n", 238 + version >> 24, (version >> 16) & 0xf, banks); 239 + 240 + fsl_ifc_ctrl_dev->version = version; 241 + fsl_ifc_ctrl_dev->banks = banks; 242 + 243 + if (of_property_read_bool(dev->dev.of_node, "little-endian")) { 244 + fsl_ifc_ctrl_dev->little_endian = true; 245 + dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n"); 246 + } else { 247 + fsl_ifc_ctrl_dev->little_endian = false; 248 + dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n"); 232 249 } 233 250 234 251 version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &

+129 -127

drivers/mtd/nand/fsl_ifc_nand.c

··· 238 238 239 239 ifc_nand_ctrl->page = page_addr; 240 240 /* Program ROW0/COL0 */ 241 - iowrite32be(page_addr, &ifc->ifc_nand.row0); 242 - iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); 241 + ifc_out32(page_addr, &ifc->ifc_nand.row0); 242 + ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0); 243 243 244 244 buf_num = page_addr & priv->bufnum_mask; 245 245 ··· 301 301 int i; 302 302 303 303 /* set the chip select for NAND Transaction */ 304 - iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT, 305 - &ifc->ifc_nand.nand_csel); 304 + ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT, 305 + &ifc->ifc_nand.nand_csel); 306 306 307 307 dev_vdbg(priv->dev, 308 308 "%s: fir0=%08x fcr0=%08x\n", 309 309 __func__, 310 - ioread32be(&ifc->ifc_nand.nand_fir0), 311 - ioread32be(&ifc->ifc_nand.nand_fcr0)); 310 + ifc_in32(&ifc->ifc_nand.nand_fir0), 311 + ifc_in32(&ifc->ifc_nand.nand_fcr0)); 312 312 313 313 ctrl->nand_stat = 0; 314 314 315 315 /* start read/write seq */ 316 - iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); 316 + ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); 317 317 318 318 /* wait for command complete flag or timeout */ 319 319 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, ··· 336 336 int sector_end = sector + chip->ecc.steps - 1; 337 337 338 338 for (i = sector / 4; i <= sector_end / 4; i++) 339 - eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]); 339 + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); 340 340 341 341 for (i = sector; i <= sector_end; i++) { 342 342 errors = check_read_ecc(mtd, ctrl, eccstat, i); ··· 376 376 377 377 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ 378 378 if (mtd->writesize > 512) { 379 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 380 - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 381 - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 382 - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | 383 - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), 384 - &ifc->ifc_nand.nand_fir0); 385 - iowrite32be(0x0, &ifc->ifc_nand.nand_fir1); 379 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 380 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 381 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 382 + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | 383 + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT), 384 + &ifc->ifc_nand.nand_fir0); 385 + ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); 386 386 387 - iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | 388 - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), 389 - &ifc->ifc_nand.nand_fcr0); 387 + ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | 388 + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT), 389 + &ifc->ifc_nand.nand_fcr0); 390 390 } else { 391 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 392 - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 393 - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 394 - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), 395 - &ifc->ifc_nand.nand_fir0); 396 - iowrite32be(0x0, &ifc->ifc_nand.nand_fir1); 391 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 392 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 393 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 394 + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT), 395 + &ifc->ifc_nand.nand_fir0); 396 + ifc_out32(0x0, &ifc->ifc_nand.nand_fir1); 397 397 398 398 if (oob) 399 - iowrite32be(NAND_CMD_READOOB << 400 - IFC_NAND_FCR0_CMD0_SHIFT, 401 - &ifc->ifc_nand.nand_fcr0); 399 + ifc_out32(NAND_CMD_READOOB << 400 + IFC_NAND_FCR0_CMD0_SHIFT, 401 + &ifc->ifc_nand.nand_fcr0); 402 402 else 403 - iowrite32be(NAND_CMD_READ0 << 404 - IFC_NAND_FCR0_CMD0_SHIFT, 405 - &ifc->ifc_nand.nand_fcr0); 403 + ifc_out32(NAND_CMD_READ0 << 404 + IFC_NAND_FCR0_CMD0_SHIFT, 405 + &ifc->ifc_nand.nand_fcr0); 406 406 } 407 407 } 408 408 ··· 422 422 switch (command) { 423 423 /* READ0 read the entire buffer to use hardware ECC. */ 424 424 case NAND_CMD_READ0: 425 - iowrite32be(0, &ifc->ifc_nand.nand_fbcr); 425 + ifc_out32(0, &ifc->ifc_nand.nand_fbcr); 426 426 set_addr(mtd, 0, page_addr, 0); 427 427 428 428 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; ··· 437 437 438 438 /* READOOB reads only the OOB because no ECC is performed. */ 439 439 case NAND_CMD_READOOB: 440 - iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); 440 + ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr); 441 441 set_addr(mtd, column, page_addr, 1); 442 442 443 443 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; ··· 453 453 if (command == NAND_CMD_PARAM) 454 454 timing = IFC_FIR_OP_RBCD; 455 455 456 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 457 - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 458 - (timing << IFC_NAND_FIR0_OP2_SHIFT), 459 - &ifc->ifc_nand.nand_fir0); 460 - iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT, 461 - &ifc->ifc_nand.nand_fcr0); 462 - iowrite32be(column, &ifc->ifc_nand.row3); 456 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 457 + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 458 + (timing << IFC_NAND_FIR0_OP2_SHIFT), 459 + &ifc->ifc_nand.nand_fir0); 460 + ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT, 461 + &ifc->ifc_nand.nand_fcr0); 462 + ifc_out32(column, &ifc->ifc_nand.row3); 463 463 464 464 /* 465 465 * although currently it's 8 bytes for READID, we always read 466 466 * the maximum 256 bytes(for PARAM) 467 467 */ 468 - iowrite32be(256, &ifc->ifc_nand.nand_fbcr); 468 + ifc_out32(256, &ifc->ifc_nand.nand_fbcr); 469 469 ifc_nand_ctrl->read_bytes = 256; 470 470 471 471 set_addr(mtd, 0, 0, 0); ··· 480 480 481 481 /* ERASE2 uses the block and page address from ERASE1 */ 482 482 case NAND_CMD_ERASE2: 483 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 484 - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | 485 - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), 486 - &ifc->ifc_nand.nand_fir0); 483 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 484 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | 485 + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT), 486 + &ifc->ifc_nand.nand_fir0); 487 487 488 - iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | 489 - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), 490 - &ifc->ifc_nand.nand_fcr0); 488 + ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | 489 + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT), 490 + &ifc->ifc_nand.nand_fcr0); 491 491 492 - iowrite32be(0, &ifc->ifc_nand.nand_fbcr); 492 + ifc_out32(0, &ifc->ifc_nand.nand_fbcr); 493 493 ifc_nand_ctrl->read_bytes = 0; 494 494 fsl_ifc_run_command(mtd); 495 495 return; ··· 506 506 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | 507 507 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); 508 508 509 - iowrite32be( 510 - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 511 - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 512 - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 513 - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | 514 - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT), 515 - &ifc->ifc_nand.nand_fir0); 516 - iowrite32be( 517 - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | 518 - (IFC_FIR_OP_RDSTAT << 519 - IFC_NAND_FIR1_OP6_SHIFT) | 520 - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT), 521 - &ifc->ifc_nand.nand_fir1); 509 + ifc_out32( 510 + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 511 + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | 512 + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | 513 + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | 514 + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT), 515 + &ifc->ifc_nand.nand_fir0); 516 + ifc_out32( 517 + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | 518 + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | 519 + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT), 520 + &ifc->ifc_nand.nand_fir1); 522 521 } else { 523 522 nand_fcr0 = ((NAND_CMD_PAGEPROG << 524 523 IFC_NAND_FCR0_CMD1_SHIFT) | ··· 526 527 (NAND_CMD_STATUS << 527 528 IFC_NAND_FCR0_CMD3_SHIFT)); 528 529 529 - iowrite32be( 530 + ifc_out32( 530 531 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 531 532 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | 532 533 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | 533 534 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | 534 535 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT), 535 536 &ifc->ifc_nand.nand_fir0); 536 - iowrite32be( 537 - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | 538 - (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | 539 - (IFC_FIR_OP_RDSTAT << 540 - IFC_NAND_FIR1_OP7_SHIFT) | 541 - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT), 542 - &ifc->ifc_nand.nand_fir1); 537 + ifc_out32( 538 + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | 539 + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | 540 + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | 541 + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT), 542 + &ifc->ifc_nand.nand_fir1); 543 543 544 544 if (column >= mtd->writesize) 545 545 nand_fcr0 |= ··· 553 555 column -= mtd->writesize; 554 556 ifc_nand_ctrl->oob = 1; 555 557 } 556 - iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0); 558 + ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0); 557 559 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob); 558 560 return; 559 561 } ··· 561 563 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ 562 564 case NAND_CMD_PAGEPROG: { 563 565 if (ifc_nand_ctrl->oob) { 564 - iowrite32be(ifc_nand_ctrl->index - 565 - ifc_nand_ctrl->column, 566 - &ifc->ifc_nand.nand_fbcr); 566 + ifc_out32(ifc_nand_ctrl->index - 567 + ifc_nand_ctrl->column, 568 + &ifc->ifc_nand.nand_fbcr); 567 569 } else { 568 - iowrite32be(0, &ifc->ifc_nand.nand_fbcr); 570 + ifc_out32(0, &ifc->ifc_nand.nand_fbcr); 569 571 } 570 572 571 573 fsl_ifc_run_command(mtd); 572 574 return; 573 575 } 574 576 575 - case NAND_CMD_STATUS: 576 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 577 - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), 578 - &ifc->ifc_nand.nand_fir0); 579 - iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, 580 - &ifc->ifc_nand.nand_fcr0); 581 - iowrite32be(1, &ifc->ifc_nand.nand_fbcr); 577 + case NAND_CMD_STATUS: { 578 + void __iomem *addr; 579 + 580 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 581 + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT), 582 + &ifc->ifc_nand.nand_fir0); 583 + ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, 584 + &ifc->ifc_nand.nand_fcr0); 585 + ifc_out32(1, &ifc->ifc_nand.nand_fbcr); 582 586 set_addr(mtd, 0, 0, 0); 583 587 ifc_nand_ctrl->read_bytes = 1; 584 588 ··· 590 590 * The chip always seems to report that it is 591 591 * write-protected, even when it is not. 592 592 */ 593 + addr = ifc_nand_ctrl->addr; 593 594 if (chip->options & NAND_BUSWIDTH_16) 594 - setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP); 595 + ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr); 595 596 else 596 - setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); 597 + ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr); 597 598 return; 599 + } 598 600 599 601 case NAND_CMD_RESET: 600 - iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, 601 - &ifc->ifc_nand.nand_fir0); 602 - iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, 603 - &ifc->ifc_nand.nand_fcr0); 602 + ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT, 603 + &ifc->ifc_nand.nand_fir0); 604 + ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT, 605 + &ifc->ifc_nand.nand_fcr0); 604 606 fsl_ifc_run_command(mtd); 605 607 return; 606 608 ··· 660 658 */ 661 659 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { 662 660 offset = ifc_nand_ctrl->index++; 663 - return in_8(ifc_nand_ctrl->addr + offset); 661 + return ifc_in8(ifc_nand_ctrl->addr + offset); 664 662 } 665 663 666 664 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__); ··· 682 680 * next byte. 683 681 */ 684 682 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) { 685 - data = in_be16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index); 683 + data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index); 686 684 ifc_nand_ctrl->index += 2; 687 685 return (uint8_t) data; 688 686 } ··· 728 726 u32 nand_fsr; 729 727 730 728 /* Use READ_STATUS command, but wait for the device to be ready */ 731 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 732 - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), 733 - &ifc->ifc_nand.nand_fir0); 734 - iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, 735 - &ifc->ifc_nand.nand_fcr0); 736 - iowrite32be(1, &ifc->ifc_nand.nand_fbcr); 729 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 730 + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT), 731 + &ifc->ifc_nand.nand_fir0); 732 + ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT, 733 + &ifc->ifc_nand.nand_fcr0); 734 + ifc_out32(1, &ifc->ifc_nand.nand_fbcr); 737 735 set_addr(mtd, 0, 0, 0); 738 736 ifc_nand_ctrl->read_bytes = 1; 739 737 740 738 fsl_ifc_run_command(mtd); 741 739 742 - nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr); 740 + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); 743 741 744 742 /* 745 743 * The chip always seems to report that it is ··· 831 829 uint32_t cs = priv->bank; 832 830 833 831 /* Save CSOR and CSOR_ext */ 834 - csor = ioread32be(&ifc->csor_cs[cs].csor); 835 - csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext); 832 + csor = ifc_in32(&ifc->csor_cs[cs].csor); 833 + csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext); 836 834 837 835 /* chage PageSize 8K and SpareSize 1K*/ 838 836 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; 839 - iowrite32be(csor_8k, &ifc->csor_cs[cs].csor); 840 - iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext); 837 + ifc_out32(csor_8k, &ifc->csor_cs[cs].csor); 838 + ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext); 841 839 842 840 /* READID */ 843 - iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 844 - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 845 - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), 846 - &ifc->ifc_nand.nand_fir0); 847 - iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, 848 - &ifc->ifc_nand.nand_fcr0); 849 - iowrite32be(0x0, &ifc->ifc_nand.row3); 841 + ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | 842 + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | 843 + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT), 844 + &ifc->ifc_nand.nand_fir0); 845 + ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT, 846 + &ifc->ifc_nand.nand_fcr0); 847 + ifc_out32(0x0, &ifc->ifc_nand.row3); 850 848 851 - iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr); 849 + ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr); 852 850 853 851 /* Program ROW0/COL0 */ 854 - iowrite32be(0x0, &ifc->ifc_nand.row0); 855 - iowrite32be(0x0, &ifc->ifc_nand.col0); 852 + ifc_out32(0x0, &ifc->ifc_nand.row0); 853 + ifc_out32(0x0, &ifc->ifc_nand.col0); 856 854 857 855 /* set the chip select for NAND Transaction */ 858 - iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel); 856 + ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel); 859 857 860 858 /* start read seq */ 861 - iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); 859 + ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt); 862 860 863 861 /* wait for command complete flag or timeout */ 864 862 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, ··· 868 866 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n"); 869 867 870 868 /* Restore CSOR and CSOR_ext */ 871 - iowrite32be(csor, &ifc->csor_cs[cs].csor); 872 - iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext); 869 + ifc_out32(csor, &ifc->csor_cs[cs].csor); 870 + ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext); 873 871 } 874 872 875 873 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) ··· 886 884 887 885 /* fill in nand_chip structure */ 888 886 /* set up function call table */ 889 - if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16) 887 + if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16) 890 888 chip->read_byte = fsl_ifc_read_byte16; 891 889 else 892 890 chip->read_byte = fsl_ifc_read_byte; ··· 900 898 chip->bbt_td = &bbt_main_descr; 901 899 chip->bbt_md = &bbt_mirror_descr; 902 900 903 - iowrite32be(0x0, &ifc->ifc_nand.ncfgr); 901 + ifc_out32(0x0, &ifc->ifc_nand.ncfgr); 904 902 905 903 /* set up nand options */ 906 904 chip->bbt_options = NAND_BBT_USE_FLASH; 907 905 chip->options = NAND_NO_SUBPAGE_WRITE; 908 906 909 - if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { 907 + if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) { 910 908 chip->read_byte = fsl_ifc_read_byte16; 911 909 chip->options |= NAND_BUSWIDTH_16; 912 910 } else { ··· 919 917 chip->ecc.read_page = fsl_ifc_read_page; 920 918 chip->ecc.write_page = fsl_ifc_write_page; 921 919 922 - csor = ioread32be(&ifc->csor_cs[priv->bank].csor); 920 + csor = ifc_in32(&ifc->csor_cs[priv->bank].csor); 923 921 924 922 /* Hardware generates ECC per 512 Bytes */ 925 923 chip->ecc.size = 512; ··· 1008 1006 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank, 1009 1007 phys_addr_t addr) 1010 1008 { 1011 - u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr); 1009 + u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr); 1012 1010 1013 1011 if (!(cspr & CSPR_V)) 1014 1012 return 0; ··· 1094 1092 1095 1093 dev_set_drvdata(priv->dev, priv); 1096 1094 1097 - iowrite32be(IFC_NAND_EVTER_EN_OPC_EN | 1098 - IFC_NAND_EVTER_EN_FTOER_EN | 1099 - IFC_NAND_EVTER_EN_WPER_EN, 1100 - &ifc->ifc_nand.nand_evter_en); 1095 + ifc_out32(IFC_NAND_EVTER_EN_OPC_EN | 1096 + IFC_NAND_EVTER_EN_FTOER_EN | 1097 + IFC_NAND_EVTER_EN_WPER_EN, 1098 + &ifc->ifc_nand.nand_evter_en); 1101 1099 1102 1100 /* enable NAND Machine Interrupts */ 1103 - iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN | 1104 - IFC_NAND_EVTER_INTR_FTOERIR_EN | 1105 - IFC_NAND_EVTER_INTR_WPERIR_EN, 1106 - &ifc->ifc_nand.nand_evter_intr_en); 1101 + ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN | 1102 + IFC_NAND_EVTER_INTR_FTOERIR_EN | 1103 + IFC_NAND_EVTER_INTR_WPERIR_EN, 1104 + &ifc->ifc_nand.nand_evter_intr_en); 1107 1105 priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start); 1108 1106 if (!priv->mtd.name) { 1109 1107 ret = -ENOMEM;

+50

include/linux/fsl_ifc.h

··· 841 841 842 842 u32 nand_stat; 843 843 wait_queue_head_t nand_wait; 844 + bool little_endian; 844 845 }; 845 846 846 847 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; 847 848 849 + static inline u32 ifc_in32(void __iomem *addr) 850 + { 851 + u32 val; 852 + 853 + if (fsl_ifc_ctrl_dev->little_endian) 854 + val = ioread32(addr); 855 + else 856 + val = ioread32be(addr); 857 + 858 + return val; 859 + } 860 + 861 + static inline u16 ifc_in16(void __iomem *addr) 862 + { 863 + u16 val; 864 + 865 + if (fsl_ifc_ctrl_dev->little_endian) 866 + val = ioread16(addr); 867 + else 868 + val = ioread16be(addr); 869 + 870 + return val; 871 + } 872 + 873 + static inline u8 ifc_in8(void __iomem *addr) 874 + { 875 + return ioread8(addr); 876 + } 877 + 878 + static inline void ifc_out32(u32 val, void __iomem *addr) 879 + { 880 + if (fsl_ifc_ctrl_dev->little_endian) 881 + iowrite32(val, addr); 882 + else 883 + iowrite32be(val, addr); 884 + } 885 + 886 + static inline void ifc_out16(u16 val, void __iomem *addr) 887 + { 888 + if (fsl_ifc_ctrl_dev->little_endian) 889 + iowrite16(val, addr); 890 + else 891 + iowrite16be(val, addr); 892 + } 893 + 894 + static inline void ifc_out8(u8 val, void __iomem *addr) 895 + { 896 + iowrite8(val, addr); 897 + } 848 898 849 899 #endif /* __ASM_FSL_IFC_H */