iio: adc: stm32-adc: add stm32mp13 support

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Add STM32 ADC support for STM32MP13x SOCs family.

On STM32MP13x, each ADC peripheral has a single ADC block.
These ADC peripherals, ADC1 and ADC2, are fully independent.
This introduces changes in common registers handling.

Some features such as boost mode, channel preselection and
linear calibration are not supported by the STM32MP13x ADC.
Add diversity management for these features.

The STM32MP13x ADC introduces registers and bitfield variants
on existing features such as calibration factors and internal
channels. Add register diversity management.

Add also support for new internal channels VDDCPU and VDDQ_DDR.

Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20221012142205.13041-4-olivier.moysan@foss.st.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

Olivier Moysan and committed by

Jonathan Cameron 3 years ago cf0fb80a 6cafcdb1

+239 -31

3 changed files

expand all

drivers

iio

adc

stm32-adc-core.c

stm32-adc-core.h

stm32-adc.c

+26 -4

drivers/iio/adc/stm32-adc-core.c

··· 22 22 #include <linux/regmap.h> 23 23 #include <linux/regulator/consumer.h> 24 24 #include <linux/slab.h> 25 + #include <linux/units.h> 25 26 26 27 #include "stm32-adc-core.h" 27 28 ··· 307 306 static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { 308 307 .csr = STM32F4_ADC_CSR, 309 308 .ccr = STM32F4_ADC_CCR, 310 - .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3}, 311 - .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3}, 309 + .eoc_msk = { STM32F4_EOC1, STM32F4_EOC2, STM32F4_EOC3 }, 310 + .ovr_msk = { STM32F4_OVR1, STM32F4_OVR2, STM32F4_OVR3 }, 312 311 .ier = STM32F4_ADC_CR1, 313 312 .eocie_msk = STM32F4_EOCIE, 314 313 }; ··· 317 316 static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { 318 317 .csr = STM32H7_ADC_CSR, 319 318 .ccr = STM32H7_ADC_CCR, 320 - .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV}, 321 - .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV}, 319 + .eoc_msk = { STM32H7_EOC_MST, STM32H7_EOC_SLV }, 320 + .ovr_msk = { STM32H7_OVR_MST, STM32H7_OVR_SLV }, 321 + .ier = STM32H7_ADC_IER, 322 + .eocie_msk = STM32H7_EOCIE, 323 + }; 324 + 325 + /* STM32MP13 common registers definitions */ 326 + static const struct stm32_adc_common_regs stm32mp13_adc_common_regs = { 327 + .csr = STM32H7_ADC_CSR, 328 + .ccr = STM32H7_ADC_CCR, 329 + .eoc_msk = { STM32H7_EOC_MST }, 330 + .ovr_msk = { STM32H7_OVR_MST }, 322 331 .ier = STM32H7_ADC_IER, 323 332 .eocie_msk = STM32H7_EOCIE, 324 333 }; ··· 879 868 .num_irqs = 2, 880 869 }; 881 870 871 + static const struct stm32_adc_priv_cfg stm32mp13_adc_priv_cfg = { 872 + .regs = &stm32mp13_adc_common_regs, 873 + .clk_sel = stm32h7_adc_clk_sel, 874 + .max_clk_rate_hz = 75 * HZ_PER_MHZ, 875 + .ipid = STM32MP13_IPIDR_NUMBER, 876 + .num_irqs = 1, 877 + }; 878 + 882 879 static const struct of_device_id stm32_adc_of_match[] = { 883 880 { 884 881 .compatible = "st,stm32f4-adc-core", ··· 897 878 }, { 898 879 .compatible = "st,stm32mp1-adc-core", 899 880 .data = (void *)&stm32mp1_adc_priv_cfg 881 + }, { 882 + .compatible = "st,stm32mp13-adc-core", 883 + .data = (void *)&stm32mp13_adc_priv_cfg 900 884 }, { 901 885 }, 902 886 };

+30

drivers/iio/adc/stm32-adc-core.h

··· 112 112 #define STM32MP1_ADC_IPDR 0x3F8 113 113 #define STM32MP1_ADC_SIDR 0x3FC 114 114 115 + /* STM32MP13 - Registers for each ADC instance */ 116 + #define STM32MP13_ADC_DIFSEL 0xB0 117 + #define STM32MP13_ADC_CALFACT 0xB4 118 + #define STM32MP13_ADC2_OR 0xC8 119 + 115 120 /* STM32H7 - common registers for all ADC instances */ 116 121 #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) 117 122 #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) ··· 165 160 STM32H7_DMNGT_DFSDM, /* DFSDM mode */ 166 161 STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ 167 162 }; 163 + 164 + /* STM32H7_ADC_DIFSEL - bit fields */ 165 + #define STM32H7_DIFSEL_MASK GENMASK(19, 0) 168 166 169 167 /* STM32H7_ADC_CALFACT - bit fields */ 170 168 #define STM32H7_CALFACT_D_SHIFT 16 ··· 218 210 /* STM32MP1_ADC_SIDR - bit fields */ 219 211 #define STM32MP1_SIDR_MASK GENMASK(31, 0) 220 212 213 + /* STM32MP13_ADC_CFGR specific bit fields */ 214 + #define STM32MP13_DMAEN BIT(0) 215 + #define STM32MP13_DMACFG BIT(1) 216 + #define STM32MP13_DFSDMCFG BIT(2) 217 + #define STM32MP13_RES_SHIFT 3 218 + #define STM32MP13_RES_MASK GENMASK(4, 3) 219 + 220 + /* STM32MP13_ADC_DIFSEL - bit fields */ 221 + #define STM32MP13_DIFSEL_MASK GENMASK(18, 0) 222 + 223 + /* STM32MP13_ADC_CALFACT - bit fields */ 224 + #define STM32MP13_CALFACT_D_SHIFT 16 225 + #define STM32MP13_CALFACT_D_MASK GENMASK(22, 16) 226 + #define STM32MP13_CALFACT_S_SHIFT 0 227 + #define STM32MP13_CALFACT_S_MASK GENMASK(6, 0) 228 + 229 + /* STM32MP13_ADC2_OR - bit fields */ 230 + #define STM32MP13_OP2 BIT(2) 231 + #define STM32MP13_OP1 BIT(1) 232 + #define STM32MP13_OP0 BIT(0) 233 + 221 234 #define STM32MP15_IPIDR_NUMBER 0x00110005 235 + #define STM32MP13_IPIDR_NUMBER 0x00110006 222 236 223 237 /** 224 238 * struct stm32_adc_common - stm32 ADC driver common data (for all instances)

+183 -27

drivers/iio/adc/stm32-adc.c

··· 82 82 enum stm32_adc_int_ch { 83 83 STM32_ADC_INT_CH_NONE = -1, 84 84 STM32_ADC_INT_CH_VDDCORE, 85 + STM32_ADC_INT_CH_VDDCPU, 86 + STM32_ADC_INT_CH_VDDQ_DDR, 85 87 STM32_ADC_INT_CH_VREFINT, 86 88 STM32_ADC_INT_CH_VBAT, 87 89 STM32_ADC_INT_CH_NB, ··· 101 99 102 100 static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = { 103 101 { "vddcore", STM32_ADC_INT_CH_VDDCORE }, 102 + { "vddcpu", STM32_ADC_INT_CH_VDDCPU }, 103 + { "vddq_ddr", STM32_ADC_INT_CH_VDDQ_DDR }, 104 104 { "vrefint", STM32_ADC_INT_CH_VREFINT }, 105 105 { "vbat", STM32_ADC_INT_CH_VBAT }, 106 106 }; ··· 164 160 * @exten: trigger control register & bitfield 165 161 * @extsel: trigger selection register & bitfield 166 162 * @res: resolution selection register & bitfield 163 + * @difsel: differential mode selection register & bitfield 164 + * @calfact_s: single-ended calibration factors register & bitfield 165 + * @calfact_d: differential calibration factors register & bitfield 167 166 * @smpr: smpr1 & smpr2 registers offset array 168 167 * @smp_bits: smpr1 & smpr2 index and bitfields 169 - * @or_vdd: option register & vddcore bitfield 168 + * @or_vddcore: option register & vddcore bitfield 169 + * @or_vddcpu: option register & vddcpu bitfield 170 + * @or_vddq_ddr: option register & vddq_ddr bitfield 170 171 * @ccr_vbat: common register & vbat bitfield 171 172 * @ccr_vref: common register & vrefint bitfield 172 173 */ ··· 185 176 const struct stm32_adc_regs exten; 186 177 const struct stm32_adc_regs extsel; 187 178 const struct stm32_adc_regs res; 179 + const struct stm32_adc_regs difsel; 180 + const struct stm32_adc_regs calfact_s; 181 + const struct stm32_adc_regs calfact_d; 188 182 const u32 smpr[2]; 189 183 const struct stm32_adc_regs *smp_bits; 190 - const struct stm32_adc_regs or_vdd; 184 + const struct stm32_adc_regs or_vddcore; 185 + const struct stm32_adc_regs or_vddcpu; 186 + const struct stm32_adc_regs or_vddq_ddr; 191 187 const struct stm32_adc_regs ccr_vbat; 192 188 const struct stm32_adc_regs ccr_vref; 193 189 }; ··· 206 192 * @trigs: external trigger sources 207 193 * @clk_required: clock is required 208 194 * @has_vregready: vregready status flag presence 195 + * @has_boostmode: boost mode support flag 196 + * @has_linearcal: linear calibration support flag 197 + * @has_presel: channel preselection support flag 209 198 * @prepare: optional prepare routine (power-up, enable) 210 199 * @start_conv: routine to start conversions 211 200 * @stop_conv: routine to stop conversions ··· 223 206 struct stm32_adc_trig_info *trigs; 224 207 bool clk_required; 225 208 bool has_vregready; 209 + bool has_boostmode; 210 + bool has_linearcal; 211 + bool has_presel; 226 212 int (*prepare)(struct iio_dev *); 227 213 void (*start_conv)(struct iio_dev *, bool dma); 228 214 void (*stop_conv)(struct iio_dev *); ··· 330 310 .max_channels = STM32_ADC_CH_MAX, 331 311 .resolutions = stm32h7_adc_resolutions, 332 312 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 313 + }; 314 + 315 + /* stm32mp13 can have up to 19 channels */ 316 + static const struct stm32_adc_info stm32mp13_adc_info = { 317 + .max_channels = 19, 318 + .resolutions = stm32f4_adc_resolutions, 319 + .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 333 320 }; 334 321 335 322 /* ··· 524 497 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 525 498 STM32H7_EXTSEL_SHIFT }, 526 499 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 500 + .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK}, 501 + .calfact_s = { STM32H7_ADC_CALFACT, STM32H7_CALFACT_S_MASK, 502 + STM32H7_CALFACT_S_SHIFT }, 503 + .calfact_d = { STM32H7_ADC_CALFACT, STM32H7_CALFACT_D_MASK, 504 + STM32H7_CALFACT_D_SHIFT }, 527 505 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 528 506 .smp_bits = stm32h7_smp_bits, 507 + }; 508 + 509 + /* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */ 510 + static const unsigned int stm32mp13_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 511 + 2, 6, 12, 24, 47, 92, 247, 640, 512 + }; 513 + 514 + static const struct stm32_adc_regspec stm32mp13_adc_regspec = { 515 + .dr = STM32H7_ADC_DR, 516 + .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 517 + .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 518 + .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 519 + .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 520 + .sqr = stm32h7_sq, 521 + .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 522 + .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 523 + STM32H7_EXTSEL_SHIFT }, 524 + .res = { STM32H7_ADC_CFGR, STM32MP13_RES_MASK, STM32MP13_RES_SHIFT }, 525 + .difsel = { STM32MP13_ADC_DIFSEL, STM32MP13_DIFSEL_MASK}, 526 + .calfact_s = { STM32MP13_ADC_CALFACT, STM32MP13_CALFACT_S_MASK, 527 + STM32MP13_CALFACT_S_SHIFT }, 528 + .calfact_d = { STM32MP13_ADC_CALFACT, STM32MP13_CALFACT_D_MASK, 529 + STM32MP13_CALFACT_D_SHIFT }, 530 + .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 531 + .smp_bits = stm32h7_smp_bits, 532 + .or_vddcore = { STM32MP13_ADC2_OR, STM32MP13_OP0 }, 533 + .or_vddcpu = { STM32MP13_ADC2_OR, STM32MP13_OP1 }, 534 + .or_vddq_ddr = { STM32MP13_ADC2_OR, STM32MP13_OP2 }, 535 + .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 536 + .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 529 537 }; 530 538 531 539 static const struct stm32_adc_regspec stm32mp1_adc_regspec = { ··· 574 512 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 575 513 STM32H7_EXTSEL_SHIFT }, 576 514 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 515 + .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK}, 516 + .calfact_s = { STM32H7_ADC_CALFACT, STM32H7_CALFACT_S_MASK, 517 + STM32H7_CALFACT_S_SHIFT }, 518 + .calfact_d = { STM32H7_ADC_CALFACT, STM32H7_CALFACT_D_MASK, 519 + STM32H7_CALFACT_D_SHIFT }, 577 520 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 578 521 .smp_bits = stm32h7_smp_bits, 579 - .or_vdd = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, 522 + .or_vddcore = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, 580 523 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 581 524 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 582 525 }; ··· 742 675 switch (i) { 743 676 case STM32_ADC_INT_CH_VDDCORE: 744 677 dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); 745 - stm32_adc_set_bits(adc, adc->cfg->regs->or_vdd.reg, 746 - adc->cfg->regs->or_vdd.mask); 678 + stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg, 679 + adc->cfg->regs->or_vddcore.mask); 680 + break; 681 + case STM32_ADC_INT_CH_VDDCPU: 682 + dev_dbg(&indio_dev->dev, "Enable VDDCPU\n"); 683 + stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg, 684 + adc->cfg->regs->or_vddcpu.mask); 685 + break; 686 + case STM32_ADC_INT_CH_VDDQ_DDR: 687 + dev_dbg(&indio_dev->dev, "Enable VDDQ_DDR\n"); 688 + stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, 689 + adc->cfg->regs->or_vddq_ddr.mask); 747 690 break; 748 691 case STM32_ADC_INT_CH_VREFINT: 749 692 dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); ··· 779 702 780 703 switch (i) { 781 704 case STM32_ADC_INT_CH_VDDCORE: 782 - stm32_adc_clr_bits(adc, adc->cfg->regs->or_vdd.reg, 783 - adc->cfg->regs->or_vdd.mask); 705 + stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg, 706 + adc->cfg->regs->or_vddcore.mask); 707 + break; 708 + case STM32_ADC_INT_CH_VDDCPU: 709 + stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg, 710 + adc->cfg->regs->or_vddcpu.mask); 711 + break; 712 + case STM32_ADC_INT_CH_VDDQ_DDR: 713 + stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, 714 + adc->cfg->regs->or_vddq_ddr.mask); 784 715 break; 785 716 case STM32_ADC_INT_CH_VREFINT: 786 717 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, ··· 886 801 if (ret) 887 802 dev_warn(&indio_dev->dev, "stop failed\n"); 888 803 804 + /* STM32H7_DMNGT_MASK covers STM32MP13_DMAEN & STM32MP13_DMACFG */ 889 805 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 890 806 } 891 807 ··· 895 809 struct stm32_adc *adc = iio_priv(indio_dev); 896 810 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */ 897 811 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 812 + } 813 + 814 + static void stm32mp13_adc_start_conv(struct iio_dev *indio_dev, bool dma) 815 + { 816 + struct stm32_adc *adc = iio_priv(indio_dev); 817 + 818 + if (dma) 819 + stm32_adc_set_bits(adc, STM32H7_ADC_CFGR, 820 + STM32MP13_DMAEN | STM32MP13_DMACFG); 821 + 822 + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 898 823 } 899 824 900 825 static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) ··· 918 821 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 919 822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 920 823 921 - if (adc->common->rate > STM32H7_BOOST_CLKRATE) 824 + if (adc->cfg->has_boostmode && 825 + adc->common->rate > STM32H7_BOOST_CLKRATE) 922 826 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 923 827 924 828 /* Wait for startup time */ ··· 941 843 942 844 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 943 845 { 944 - stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 846 + if (adc->cfg->has_boostmode) 847 + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 945 848 946 849 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 947 850 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); ··· 1000 901 int i, ret; 1001 902 u32 lincalrdyw_mask, val; 1002 903 904 + if (!adc->cfg->has_linearcal) 905 + goto skip_linearcal; 906 + 1003 907 /* Read linearity calibration */ 1004 908 lincalrdyw_mask = STM32H7_LINCALRDYW6; 1005 909 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { ··· 1025 923 lincalrdyw_mask >>= 1; 1026 924 } 1027 925 926 + skip_linearcal: 1028 927 /* Read offset calibration */ 1029 - val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); 1030 - adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); 1031 - adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; 1032 - adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); 1033 - adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; 928 + val = stm32_adc_readl(adc, adc->cfg->regs->calfact_s.reg); 929 + adc->cal.calfact_s = (val & adc->cfg->regs->calfact_s.mask); 930 + adc->cal.calfact_s >>= adc->cfg->regs->calfact_s.shift; 931 + adc->cal.calfact_d = (val & adc->cfg->regs->calfact_d.mask); 932 + adc->cal.calfact_d >>= adc->cfg->regs->calfact_d.shift; 1034 933 adc->cal.calibrated = true; 1035 934 1036 935 return 0; ··· 1048 945 int i, ret; 1049 946 u32 lincalrdyw_mask, val; 1050 947 1051 - val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | 1052 - (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); 1053 - stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); 948 + val = (adc->cal.calfact_s << adc->cfg->regs->calfact_s.shift) | 949 + (adc->cal.calfact_d << adc->cfg->regs->calfact_d.shift); 950 + stm32_adc_writel(adc, adc->cfg->regs->calfact_s.reg, val); 951 + 952 + if (!adc->cfg->has_linearcal) 953 + return 0; 1054 954 1055 955 lincalrdyw_mask = STM32H7_LINCALRDYW6; 1056 956 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { ··· 1122 1016 { 1123 1017 struct stm32_adc *adc = iio_priv(indio_dev); 1124 1018 int ret; 1019 + u32 msk = STM32H7_ADCALDIF; 1125 1020 u32 val; 1126 1021 1127 1022 if (adc->cal.calibrated) 1128 1023 return true; 1129 1024 1025 + if (adc->cfg->has_linearcal) 1026 + msk |= STM32H7_ADCALLIN; 1130 1027 /* ADC must be disabled for calibration */ 1131 1028 stm32h7_adc_disable(indio_dev); 1132 1029 ··· 1138 1029 * - Offset calibration for single ended inputs 1139 1030 * - No linearity calibration (do it later, before reading it) 1140 1031 */ 1141 - stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); 1142 - stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); 1032 + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); 1143 1033 1144 1034 /* Start calibration, then wait for completion */ 1145 1035 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); ··· 1156 1048 * - Linearity calibration (needs to be done only once for single/diff) 1157 1049 * will run simultaneously with offset calibration. 1158 1050 */ 1159 - stm32_adc_set_bits(adc, STM32H7_ADC_CR, 1160 - STM32H7_ADCALDIF | STM32H7_ADCALLIN); 1051 + stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk); 1161 1052 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1162 1053 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1163 1054 !(val & STM32H7_ADCAL), 100, ··· 1167 1060 } 1168 1061 1169 1062 out: 1170 - stm32_adc_clr_bits(adc, STM32H7_ADC_CR, 1171 - STM32H7_ADCALDIF | STM32H7_ADCALLIN); 1063 + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); 1172 1064 1173 1065 return ret; 1174 1066 } ··· 1199 1093 1200 1094 stm32_adc_int_ch_enable(indio_dev); 1201 1095 1202 - stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); 1096 + stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel); 1203 1097 1204 1098 ret = stm32h7_adc_enable(indio_dev); 1205 1099 if (ret) ··· 1213 1107 if (ret) 1214 1108 goto disable; 1215 1109 1216 - stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 1110 + if (adc->cfg->has_presel) 1111 + stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 1217 1112 1218 1113 return 0; 1219 1114 ··· 1232 1125 { 1233 1126 struct stm32_adc *adc = iio_priv(indio_dev); 1234 1127 1235 - stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 1128 + if (adc->cfg->has_presel) 1129 + stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 1236 1130 stm32h7_adc_disable(indio_dev); 1237 1131 stm32_adc_int_ch_disable(adc); 1238 1132 stm32h7_adc_enter_pwr_down(adc); ··· 1965 1857 adc->pcsel |= BIT(chan->channel); 1966 1858 if (differential) { 1967 1859 /* pre-build diff channels mask */ 1968 - adc->difsel |= BIT(chan->channel); 1860 + adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask; 1969 1861 /* Also add negative input to pre-selected channels */ 1970 1862 adc->pcsel |= BIT(chan->channel2); 1971 1863 } ··· 2106 1998 2107 1999 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 2108 2000 if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) { 2001 + /* Check internal channel availability */ 2002 + switch (i) { 2003 + case STM32_ADC_INT_CH_VDDCORE: 2004 + if (!adc->cfg->regs->or_vddcore.reg) 2005 + dev_warn(&indio_dev->dev, 2006 + "%s channel not available\n", ch_name); 2007 + break; 2008 + case STM32_ADC_INT_CH_VDDCPU: 2009 + if (!adc->cfg->regs->or_vddcpu.reg) 2010 + dev_warn(&indio_dev->dev, 2011 + "%s channel not available\n", ch_name); 2012 + break; 2013 + case STM32_ADC_INT_CH_VDDQ_DDR: 2014 + if (!adc->cfg->regs->or_vddq_ddr.reg) 2015 + dev_warn(&indio_dev->dev, 2016 + "%s channel not available\n", ch_name); 2017 + break; 2018 + case STM32_ADC_INT_CH_VREFINT: 2019 + if (!adc->cfg->regs->ccr_vref.reg) 2020 + dev_warn(&indio_dev->dev, 2021 + "%s channel not available\n", ch_name); 2022 + break; 2023 + case STM32_ADC_INT_CH_VBAT: 2024 + if (!adc->cfg->regs->ccr_vbat.reg) 2025 + dev_warn(&indio_dev->dev, 2026 + "%s channel not available\n", ch_name); 2027 + break; 2028 + } 2029 + 2109 2030 if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) { 2110 2031 adc->int_ch[i] = chan; 2111 2032 break; ··· 2572 2435 .regs = &stm32h7_adc_regspec, 2573 2436 .adc_info = &stm32h7_adc_info, 2574 2437 .trigs = stm32h7_adc_trigs, 2438 + .has_boostmode = true, 2439 + .has_linearcal = true, 2440 + .has_presel = true, 2575 2441 .start_conv = stm32h7_adc_start_conv, 2576 2442 .stop_conv = stm32h7_adc_stop_conv, 2577 2443 .prepare = stm32h7_adc_prepare, ··· 2588 2448 .adc_info = &stm32h7_adc_info, 2589 2449 .trigs = stm32h7_adc_trigs, 2590 2450 .has_vregready = true, 2451 + .has_boostmode = true, 2452 + .has_linearcal = true, 2453 + .has_presel = true, 2591 2454 .start_conv = stm32h7_adc_start_conv, 2592 2455 .stop_conv = stm32h7_adc_stop_conv, 2593 2456 .prepare = stm32h7_adc_prepare, ··· 2600 2457 .ts_vrefint_ns = 4300, 2601 2458 }; 2602 2459 2460 + static const struct stm32_adc_cfg stm32mp13_adc_cfg = { 2461 + .regs = &stm32mp13_adc_regspec, 2462 + .adc_info = &stm32mp13_adc_info, 2463 + .trigs = stm32h7_adc_trigs, 2464 + .start_conv = stm32mp13_adc_start_conv, 2465 + .stop_conv = stm32h7_adc_stop_conv, 2466 + .prepare = stm32h7_adc_prepare, 2467 + .unprepare = stm32h7_adc_unprepare, 2468 + .smp_cycles = stm32mp13_adc_smp_cycles, 2469 + .irq_clear = stm32h7_adc_irq_clear, 2470 + }; 2471 + 2603 2472 static const struct of_device_id stm32_adc_of_match[] = { 2604 2473 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 2605 2474 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 2606 2475 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 2476 + { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg }, 2607 2477 {}, 2608 2478 }; 2609 2479 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);