tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: exynos-mipi-video: Use consistent method to address phy registers
Exynos4 MIPI phy registers are defined with macro calculating the offset
for given phyN. Use the same method for Exynos5420 to be consistent.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
authored by
Krzysztof Kozlowski
and committed by
Kishon Vijay Abraham I
cf09ee59
424c9841
+11
-13
+10
-10
drivers/phy/phy-exynos-mipi-video.c
+10
-10
drivers/phy/phy-exynos-mipi-video.c
···
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/* EXYNOS_MIPI_PHY_ID_CSIS0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
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.enable_val = EXYNOS5_PHY_ENABLE,
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-
.enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
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+
.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
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-
.resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
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+
.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM0 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
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.enable_val = EXYNOS5_PHY_ENABLE,
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-
.enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
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+
.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
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-
.resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
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+
.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
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.enable_val = EXYNOS5_PHY_ENABLE,
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-
.enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
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+
.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
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-
.resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
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+
.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_DSIM1 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
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.enable_val = EXYNOS5_PHY_ENABLE,
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-
.enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
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+
.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
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-
.resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
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+
.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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}, {
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/* EXYNOS_MIPI_PHY_ID_CSIS2 */
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.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
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.enable_val = EXYNOS5_PHY_ENABLE,
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-
.enable_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
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+
.enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
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.enable_map = EXYNOS_MIPI_REGMAP_PMU,
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.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
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-
.resetn_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
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+
.resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
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.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
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},
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},
+1
-3
include/linux/soc/samsung/exynos-regs-pmu.h
+1
-3
include/linux/soc/samsung/exynos-regs-pmu.h
···
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((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr))
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#define EXYNOS5420_USBDRD1_PHY_CONTROL 0x0708
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-
#define EXYNOS5420_MIPI_PHY0_CONTROL 0x0714
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-
#define EXYNOS5420_MIPI_PHY1_CONTROL 0x0718
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-
#define EXYNOS5420_MIPI_PHY2_CONTROL 0x071C
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+
#define EXYNOS5420_MIPI_PHY_CONTROL(n) (0x0714 + (n) * 4)
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#define EXYNOS5420_DPTX_PHY_CONTROL 0x0728
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#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020
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#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024