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kernel
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linux
ARM: at91: pm: avoid soft resetting AC DLL
Do not soft reset AC DLL as controller is buggy and this operation my
introduce glitches in the controller leading to undefined behavior.
Fixes: f0bbf17958e8 ("ARM: at91: pm: add self-refresh support for sama7g5")
Depends-on: a02875c4cbd6 ("ARM: at91: pm: fix self-refresh for sama7g5")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221026124114.985876-2-claudiu.beznea@microchip.com
+10
-2
+6
-1
arch/arm/mach-at91/pm_suspend.S
+6
-1
arch/arm/mach-at91/pm_suspend.S
···
169
169
cmp tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
170
170
bne sr_ena_2
171
171
172
-
/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
172
+
/* Disable DX DLLs for non-backup modes. */
173
173
cmp r7, #AT91_PM_BACKUP
174
174
beq sr_ena_3
175
+
176
+
/* Do not soft reset the AC DLL. */
177
+
ldr tmp1, [r3, DDR3PHY_ACDLLCR]
178
+
bic tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
179
+
str tmp1, [r3, DDR3PHY_ACDLLCR]
175
180
176
181
/* Disable DX DLLs. */
177
182
ldr tmp1, [r3, #DDR3PHY_DX0DLLCR]
+4
-1
include/soc/at91/sama7-ddr.h
+4
-1
include/soc/at91/sama7-ddr.h
···
26
26
#define DDR3PHY_PGSR (0x0C) /* DDR3PHY PHY General Status Register */
27
27
#define DDR3PHY_PGSR_IDONE (1 << 0) /* Initialization Done */
28
28
29
-
#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
29
+
#define DDR3PHY_ACDLLCR (0x14) /* DDR3PHY AC DLL Control Register */
30
+
#define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
31
+
32
+
#define DDR3PHY_ACIOCR (0x24) /* DDR3PHY AC I/O Configuration Register */
30
33
#define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
31
34
#define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
32
35
#define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */