commit cef0aa0ce8592f68fb093b2be0d341a568ff9890 · tjh.dev/kernel

+4 -19

arch/arm/boot/dts/am3517-evm.dts

··· 124 124 }; 125 125 126 126 lcd0: display@0 { 127 - compatible = "panel-dpi"; 127 + /* This isn't the exact LCD, but the timings meet spec */ 128 + /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ 129 + compatible = "newhaven,nhd-4.3-480272ef-atxl"; 128 130 label = "15"; 129 - status = "okay"; 130 - pinctrl-names = "default"; 131 + backlight = <&bl>; 131 132 enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ 132 133 vcc-supply = <&vdd_io_reg>; 133 134 ··· 136 135 lcd_in: endpoint { 137 136 remote-endpoint = <&dpi_out>; 138 137 }; 139 - }; 140 - 141 - panel-timing { 142 - clock-frequency = <9000000>; 143 - hactive = <480>; 144 - vactive = <272>; 145 - hfront-porch = <3>; 146 - hback-porch = <2>; 147 - hsync-len = <42>; 148 - vback-porch = <3>; 149 - vfront-porch = <4>; 150 - vsync-len = <11>; 151 - hsync-active = <0>; 152 - vsync-active = <0>; 153 - de-active = <1>; 154 - pixelclk-active = <1>; 155 138 }; 156 139 }; 157 140

+14 -12

arch/arm/boot/dts/logicpd-som-lv.dtsi

··· 228 228 >; 229 229 }; 230 230 231 + i2c2_pins: pinmux_i2c2_pins { 232 + pinctrl-single,pins = < 233 + OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 234 + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 235 + >; 236 + }; 237 + 238 + i2c3_pins: pinmux_i2c3_pins { 239 + pinctrl-single,pins = < 240 + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ 241 + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ 242 + >; 243 + }; 244 + 231 245 tsc2004_pins: pinmux_tsc2004_pins { 232 246 pinctrl-single,pins = < 233 247 OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ ··· 261 247 pinctrl-single,pins = < 262 248 OMAP3_WKUP_IOPAD(0x2a0a, PIN_INPUT | MUX_MODE4) /* sys_boot0.gpio_2 */ 263 249 OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */ 264 - >; 265 - }; 266 - i2c2_pins: pinmux_i2c2_pins { 267 - pinctrl-single,pins = < 268 - OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ 269 - OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ 270 - >; 271 - }; 272 - i2c3_pins: pinmux_i2c3_pins { 273 - pinctrl-single,pins = < 274 - OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */ 275 - OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */ 276 250 >; 277 251 }; 278 252 };

+7 -32

arch/arm/boot/dts/logicpd-torpedo-baseboard.dtsi

··· 108 108 &dss { 109 109 status = "ok"; 110 110 vdds_dsi-supply = <&vpll2>; 111 - vdda_video-supply = <&video_reg>; 112 111 pinctrl-names = "default"; 113 112 pinctrl-0 = <&dss_dpi_pins1>; 114 113 port { ··· 123 124 display0 = &lcd0; 124 125 }; 125 126 126 - video_reg: video_reg { 127 + lcd0: display { 128 + /* This isn't the exact LCD, but the timings meet spec */ 129 + /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ 130 + compatible = "newhaven,nhd-4.3-480272ef-atxl"; 131 + label = "15"; 127 132 pinctrl-names = "default"; 128 133 pinctrl-0 = <&panel_pwr_pins>; 129 - compatible = "regulator-fixed"; 130 - regulator-name = "fixed-supply"; 131 - regulator-min-microvolt = <3300000>; 132 - regulator-max-microvolt = <3300000>; 133 - gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>; /* gpio155, lcd INI */ 134 - }; 135 - 136 - lcd0: display { 137 - compatible = "panel-dpi"; 138 - label = "15"; 139 - status = "okay"; 140 - /* default-on; */ 141 - pinctrl-names = "default"; 142 - 134 + backlight = <&bl>; 135 + enable-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; 143 136 port { 144 137 lcd_in: endpoint { 145 138 remote-endpoint = <&dpi_out>; 146 139 }; 147 - }; 148 - 149 - panel-timing { 150 - clock-frequency = <9000000>; 151 - hactive = <480>; 152 - vactive = <272>; 153 - hfront-porch = <3>; 154 - hback-porch = <2>; 155 - hsync-len = <42>; 156 - vback-porch = <3>; 157 - vfront-porch = <4>; 158 - vsync-len = <11>; 159 - hsync-active = <0>; 160 - vsync-active = <0>; 161 - de-active = <1>; 162 - pixelclk-active = <1>; 163 140 }; 164 141 }; 165 142

+1

arch/arm/configs/omap2plus_defconfig

··· 363 363 CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m 364 364 CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m 365 365 CONFIG_DRM_TILCDC=m 366 + CONFIG_DRM_PANEL_SIMPLE=m 366 367 CONFIG_FB=y 367 368 CONFIG_FIRMWARE_EDID=y 368 369 CONFIG_FB_MODE_HELPERS=y

-1

arch/arm/mach-aspeed/Kconfig

··· 26 26 config MACH_ASPEED_G5 27 27 bool "Aspeed SoC 5th Generation" 28 28 depends on ARCH_MULTI_V6 29 - select CPU_V6 30 29 select PINCTRL_ASPEED_G5 31 30 select FTTMR010_TIMER 32 31 help

+2 -2

arch/arm/mach-omap2/pdata-quirks.c

··· 491 491 struct clk *fck, struct clk *ick, 492 492 struct ti_sysc_cookie *cookie) 493 493 { 494 - if (fck) 494 + if (!IS_ERR(fck)) 495 495 cookie->clkdm = ti_sysc_find_one_clockdomain(fck); 496 496 if (cookie->clkdm) 497 497 return 0; 498 - if (ick) 498 + if (!IS_ERR(ick)) 499 499 cookie->clkdm = ti_sysc_find_one_clockdomain(ick); 500 500 if (cookie->clkdm) 501 501 return 0;

+37 -15

drivers/bus/ti-sysc.c

··· 280 280 281 281 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 282 282 if (IS_ERR(ddata->clocks[index])) { 283 - if (PTR_ERR(ddata->clocks[index]) == -ENOENT) 284 - return 0; 285 - 286 283 dev_err(ddata->dev, "clock get error for %s: %li\n", 287 284 name, PTR_ERR(ddata->clocks[index])); 288 285 ··· 354 357 continue; 355 358 356 359 error = sysc_get_one_clock(ddata, name); 357 - if (error && error != -ENOENT) 360 + if (error) 358 361 return error; 359 362 } 360 363 ··· 1629 1632 if (error) 1630 1633 return error; 1631 1634 1632 - if (manage_clocks) { 1633 - sysc_clkdm_deny_idle(ddata); 1635 + sysc_clkdm_deny_idle(ddata); 1634 1636 1635 - error = sysc_enable_opt_clocks(ddata); 1636 - if (error) 1637 - return error; 1637 + /* 1638 + * Always enable clocks. The bootloader may or may not have enabled 1639 + * the related clocks. 1640 + */ 1641 + error = sysc_enable_opt_clocks(ddata); 1642 + if (error) 1643 + return error; 1638 1644 1639 - error = sysc_enable_main_clocks(ddata); 1640 - if (error) 1641 - goto err_opt_clocks; 1642 - } 1645 + error = sysc_enable_main_clocks(ddata); 1646 + if (error) 1647 + goto err_opt_clocks; 1643 1648 1644 1649 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 1645 1650 error = sysc_rstctrl_reset_deassert(ddata, true); ··· 1659 1660 goto err_main_clocks; 1660 1661 } 1661 1662 1662 - if (!ddata->legacy_mode && manage_clocks) { 1663 + if (!ddata->legacy_mode) { 1663 1664 error = sysc_enable_module(ddata->dev); 1664 1665 if (error) 1665 1666 goto err_main_clocks; ··· 1676 1677 if (manage_clocks) 1677 1678 sysc_disable_main_clocks(ddata); 1678 1679 err_opt_clocks: 1680 + /* No re-enable of clockdomain autoidle to prevent module autoidle */ 1679 1681 if (manage_clocks) { 1680 1682 sysc_disable_opt_clocks(ddata); 1681 1683 sysc_clkdm_allow_idle(ddata); ··· 2357 2357 2358 2358 ddata = container_of(work, struct sysc, idle_work.work); 2359 2359 2360 + /* 2361 + * One time decrement of clock usage counts if left on from init. 2362 + * Note that we disable opt clocks unconditionally in this case 2363 + * as they are enabled unconditionally during init without 2364 + * considering sysc_opt_clks_needed() at that point. 2365 + */ 2366 + if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2367 + SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2368 + sysc_disable_main_clocks(ddata); 2369 + sysc_disable_opt_clocks(ddata); 2370 + sysc_clkdm_allow_idle(ddata); 2371 + } 2372 + 2373 + /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2374 + if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2375 + return; 2376 + 2377 + /* 2378 + * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2379 + * and SYSC_QUIRK_NO_RESET_ON_INIT 2380 + */ 2360 2381 if (pm_runtime_active(ddata->dev)) 2361 2382 pm_runtime_put_sync(ddata->dev); 2362 2383 } ··· 2466 2445 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 2467 2446 2468 2447 /* At least earlycon won't survive without deferred idle */ 2469 - if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | 2448 + if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2449 + SYSC_QUIRK_NO_IDLE_ON_INIT | 2470 2450 SYSC_QUIRK_NO_RESET_ON_INIT)) { 2471 2451 schedule_delayed_work(&ddata->idle_work, 3000); 2472 2452 } else {

+1 -1

drivers/firmware/arm_scmi/reset.c

··· 150 150 dom = t->tx.buf; 151 151 dom->domain_id = cpu_to_le32(domain); 152 152 dom->flags = cpu_to_le32(flags); 153 - dom->domain_id = cpu_to_le32(state); 153 + dom->reset_state = cpu_to_le32(state); 154 154 155 155 if (rdom->async_reset) 156 156 ret = scmi_do_xfer_with_response(handle, t);

+1

drivers/reset/reset-scmi.c

··· 102 102 data->rcdev.owner = THIS_MODULE; 103 103 data->rcdev.of_node = np; 104 104 data->rcdev.nr_resets = handle->reset_ops->num_domains_get(handle); 105 + data->handle = handle; 105 106 106 107 return devm_reset_controller_register(dev, &data->rcdev); 107 108 }