tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
PCI/ACPI: Tidy up MCFG quirk whitespace
With no blank lines, it's not obvious where the macro definitions end and
the uses begin. Add some blank lines and reorder the ThunderX definitions.
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org # v4.10+
+10
-3
+10
-3
drivers/acpi/pci_mcfg.c
+10
-3
drivers/acpi/pci_mcfg.c
···
54
54
55
55
#define QCOM_ECAM32(seg) \
56
56
{ "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
57
+
57
58
QCOM_ECAM32(0),
58
59
QCOM_ECAM32(1),
59
60
QCOM_ECAM32(2),
···
69
68
{ "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
70
69
{ "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
71
70
{ "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
71
+
72
72
HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
73
73
HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
74
74
HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
···
79
77
80
78
#define THUNDER_PEM_RES(addr, node) \
81
79
DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
80
+
82
81
#define THUNDER_PEM_QUIRK(rev, node) \
83
82
{ "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
84
83
&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
···
93
90
&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
94
91
{ "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
95
92
&thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
96
-
/* SoC pass2.x */
97
-
THUNDER_PEM_QUIRK(1, 0),
98
-
THUNDER_PEM_QUIRK(1, 1),
99
93
100
94
#define THUNDER_ECAM_QUIRK(rev, seg) \
101
95
{ "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
102
96
&pci_thunder_ecam_ops }
97
+
98
+
/* SoC pass2.x */
99
+
THUNDER_PEM_QUIRK(1, 0),
100
+
THUNDER_PEM_QUIRK(1, 1),
101
+
103
102
/* SoC pass1.x */
104
103
THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
105
104
THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
···
117
112
#define XGENE_V1_ECAM_MCFG(rev, seg) \
118
113
{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
119
114
&xgene_v1_pcie_ecam_ops }
115
+
120
116
#define XGENE_V2_ECAM_MCFG(rev, seg) \
121
117
{"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
122
118
&xgene_v2_pcie_ecam_ops }
119
+
123
120
/* X-Gene SoC with v1 PCIe controller */
124
121
XGENE_V1_ECAM_MCFG(1, 0),
125
122
XGENE_V1_ECAM_MCFG(1, 1),