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dt-bindings: clock: Add SC7280 DISPCC clock binding
Add device tree bindings for display clock controller subsystem for
Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1626189143-12957-3-git-send-email-tdas@codeaurora.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Taniya Das
and committed by
Stephen Boyd
ced3aaea
8bde9dd3
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Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml
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Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display Clock & Reset Controller Binding for SC7280
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm display clock control module which supports the clocks, resets and
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power domains on SC7280.
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See also dt-bindings/clock/qcom,dispcc-sc7280.h.
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properties:
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compatible:
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const: qcom,sc7280-dispcc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 source from GCC
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- description: Byte clock from DSI PHY
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- description: Pixel clock from DSI PHY
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- description: Link clock from DP PHY
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- description: VCO DIV clock from DP PHY
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- description: Link clock from EDP PHY
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- description: VCO DIV clock from EDP PHY
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_disp_gpll0_clk
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- const: dsi0_phy_pll_out_byteclk
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- const: dsi0_phy_pll_out_dsiclk
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- const: dp_phy_pll_link_clk
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- const: dp_phy_pll_vco_div_clk
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- const: edp_phy_pll_link_clk
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- const: edp_phy_pll_vco_div_clk
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@af00000 {
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compatible = "qcom,sc7280-dispcc";
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reg = <0x0af00000 0x200000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>,
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<&dsi_phy 0>,
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<&dsi_phy 1>,
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<&dp_phy 0>,
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<&dp_phy 1>,
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<&edp_phy 0>,
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<&edp_phy 1>;
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clock-names = "bi_tcxo",
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"gcc_disp_gpll0_clk",
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"dsi0_phy_pll_out_byteclk",
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"dsi0_phy_pll_out_dsiclk",
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"dp_phy_pll_link_clk",
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"dp_phy_pll_vco_div_clk",
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"edp_phy_pll_link_clk",
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"edp_phy_pll_vco_div_clk";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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include/dt-bindings/clock/qcom,dispcc-sc7280.h
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include/dt-bindings/clock/qcom,dispcc-sc7280.h
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7280_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_DP_AUX_CLK 7
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#define DISP_CC_MDSS_DP_AUX_CLK_SRC 8
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#define DISP_CC_MDSS_DP_CRYPTO_CLK 9
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#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 10
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#define DISP_CC_MDSS_DP_LINK_CLK 11
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#define DISP_CC_MDSS_DP_LINK_CLK_SRC 12
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#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 13
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#define DISP_CC_MDSS_DP_LINK_INTF_CLK 14
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#define DISP_CC_MDSS_DP_PIXEL_CLK 15
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#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 16
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#define DISP_CC_MDSS_EDP_AUX_CLK 17
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#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 18
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#define DISP_CC_MDSS_EDP_LINK_CLK 19
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#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 20
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#define DISP_CC_MDSS_EDP_LINK_DIV_CLK_SRC 21
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#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 22
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#define DISP_CC_MDSS_EDP_PIXEL_CLK 23
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#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 24
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#define DISP_CC_MDSS_ESC0_CLK 25
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#define DISP_CC_MDSS_ESC0_CLK_SRC 26
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#define DISP_CC_MDSS_MDP_CLK 27
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#define DISP_CC_MDSS_MDP_CLK_SRC 28
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#define DISP_CC_MDSS_MDP_LUT_CLK 29
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30
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#define DISP_CC_MDSS_PCLK0_CLK 31
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 32
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#define DISP_CC_MDSS_ROT_CLK 33
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#define DISP_CC_MDSS_ROT_CLK_SRC 34
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#define DISP_CC_MDSS_RSCC_AHB_CLK 35
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 36
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#define DISP_CC_MDSS_VSYNC_CLK 37
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 38
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#define DISP_CC_SLEEP_CLK 39
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#define DISP_CC_XO_CLK 40
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#endif