tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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pinctrl: mvebu: add pin-muxing driver for the Marvell Armada 375

The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

authored by

Thomas Petazzoni and committed by
Sebastian Hesselbarth ce3ed59d 78c2c3d3

+546
+82
Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
··· 1 + * Marvell Armada 375 SoC pinctrl driver for mpp 2 + 3 + Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4 + part and usage. 5 + 6 + Required properties: 7 + - compatible: "marvell,88f6720-pinctrl" 8 + - reg: register specifier of MPP registers 9 + 10 + Available mpp pins/groups and functions: 11 + Note: brackets (x) are not part of the mpp name for marvell,function and given 12 + only for more detailed description in this document. 13 + 14 + name pins functions 15 + ================================================================================ 16 + mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) 17 + mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) 18 + mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi) 19 + mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk) 20 + mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) 21 + mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) 22 + mpp6 6 gpio, dev(ad0), led(p1), audio(rclk) 23 + mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) 24 + mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) 25 + mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck) 26 + mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1) 27 + mpp11 11 gpio, dev(a0), led(c2), audio(sdo) 28 + mpp12 12 gpio, dev(a1), audio(bclk) 29 + mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn) 30 + mpp14 14 gpio, i2c0(sda), uart1(txd) 31 + mpp15 15 gpio, i2c0(sck), uart1(rxd) 32 + mpp16 16 gpio, uart0(txd) 33 + mpp17 17 gpio, uart0(rxd) 34 + mpp18 18 gpio, tdm(intn) 35 + mpp19 19 gpio, tdm(rstn) 36 + mpp20 20 gpio, tdm(pclk) 37 + mpp21 21 gpio, tdm(fsync) 38 + mpp22 22 gpio, tdm(drx) 39 + mpp23 23 gpio, tdm(dtx) 40 + mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts) 41 + mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts) 42 + mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts) 43 + mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts) 44 + mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) 45 + mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) 46 + mpp30 30 gpio, ge1(txd0), spi1(cs0) 47 + mpp31 31 gpio, ge1(txd1), spi1(mosi) 48 + mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen) 49 + mpp33 33 gpio, ge1(txd3), spi1(miso) 50 + mpp34 34 gpio, ge1(txclkout), spi1(sck) 51 + mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) 52 + mpp36 36 gpio, pcie0(clkreq) 53 + mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc) 54 + mpp38 38 gpio, pcie1(clkreq), ge(mdio) 55 + mpp39 39 gpio, ref(clkout) 56 + mpp40 40 gpio, uart1(txd) 57 + mpp41 41 gpio, uart1(rxd) 58 + mpp42 42 gpio, spi1(cs2), led(c0) 59 + mpp43 43 gpio, sata0(prsnt), dram(vttctrl) 60 + mpp44 44 gpio, sata0(prsnt) 61 + mpp45 45 gpio, spi0(cs2), pcie0(rstoutn) 62 + mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0) 63 + mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) 64 + mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) 65 + mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) 66 + mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) 67 + mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) 68 + mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) 69 + mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3) 70 + mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl) 71 + mpp55 55 gpio, ge0(rxclk), ge1(rxclk) 72 + mpp56 56 gpio, ge0(txclkout), ge1(txclkout) 73 + mpp57 57 gpio, ge0(txctl), ge1(txctl) 74 + mpp58 58 gpio, led(c0) 75 + mpp59 59 gpio, led(c1) 76 + mpp60 60 gpio, uart1(txd), led(c2) 77 + mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) 78 + mpp62 62 gpio, i2c1(sck), led(p1) 79 + mpp63 63 gpio, ptp(triggen), led(p2) 80 + mpp64 64 gpio, dram(vttctrl), led(p3) 81 + mpp65 65 gpio, sata1(prsnt) 82 + mpp66 66 gpio, ptp(eventreq), spi1(cs3)
+4
drivers/pinctrl/mvebu/Kconfig
··· 17 17 bool 18 18 select PINCTRL_MVEBU 19 19 20 + config PINCTRL_ARMADA_375 21 + bool 22 + select PINCTRL_MVEBU 23 + 20 24 config PINCTRL_ARMADA_XP 21 25 bool 22 26 select PINCTRL_MVEBU
+1
drivers/pinctrl/mvebu/Makefile
··· 2 2 obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o 3 3 obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o 4 4 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o 5 + obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o 5 6 obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
+459
drivers/pinctrl/mvebu/pinctrl-armada-375.c
··· 1 + /* 2 + * Marvell Armada 375 pinctrl driver based on mvebu pinctrl core 3 + * 4 + * Copyright (C) 2012 Marvell 5 + * 6 + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 + * 8 + * This program is free software; you can redistribute it and/or modify 9 + * it under the terms of the GNU General Public License as published by 10 + * the Free Software Foundation; either version 2 of the License, or 11 + * (at your option) any later version. 12 + */ 13 + 14 + #include <linux/err.h> 15 + #include <linux/init.h> 16 + #include <linux/io.h> 17 + #include <linux/module.h> 18 + #include <linux/platform_device.h> 19 + #include <linux/clk.h> 20 + #include <linux/of.h> 21 + #include <linux/of_device.h> 22 + #include <linux/pinctrl/pinctrl.h> 23 + 24 + #include "pinctrl-mvebu.h" 25 + 26 + static void __iomem *mpp_base; 27 + 28 + static int armada_375_mpp_ctrl_get(unsigned pid, unsigned long *config) 29 + { 30 + return default_mpp_ctrl_get(mpp_base, pid, config); 31 + } 32 + 33 + static int armada_375_mpp_ctrl_set(unsigned pid, unsigned long config) 34 + { 35 + return default_mpp_ctrl_set(mpp_base, pid, config); 36 + } 37 + 38 + static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = { 39 + MPP_MODE(0, 40 + MPP_FUNCTION(0x0, "gpio", NULL), 41 + MPP_FUNCTION(0x1, "dev", "ad2"), 42 + MPP_FUNCTION(0x2, "spi0", "cs1"), 43 + MPP_FUNCTION(0x3, "spi1", "cs1"), 44 + MPP_FUNCTION(0x5, "nand", "io2")), 45 + MPP_MODE(1, 46 + MPP_FUNCTION(0x0, "gpio", NULL), 47 + MPP_FUNCTION(0x1, "dev", "ad3"), 48 + MPP_FUNCTION(0x2, "spi0", "mosi"), 49 + MPP_FUNCTION(0x3, "spi1", "mosi"), 50 + MPP_FUNCTION(0x5, "nand", "io3")), 51 + MPP_MODE(2, 52 + MPP_FUNCTION(0x0, "gpio", NULL), 53 + MPP_FUNCTION(0x1, "dev", "ad4"), 54 + MPP_FUNCTION(0x2, "ptp", "eventreq"), 55 + MPP_FUNCTION(0x3, "led", "c0"), 56 + MPP_FUNCTION(0x4, "audio", "sdi"), 57 + MPP_FUNCTION(0x5, "nand", "io4"), 58 + MPP_FUNCTION(0x6, "spi1", "mosi")), 59 + MPP_MODE(3, 60 + MPP_FUNCTION(0x0, "gpio", NULL), 61 + MPP_FUNCTION(0x1, "dev", "ad5"), 62 + MPP_FUNCTION(0x2, "ptp", "triggen"), 63 + MPP_FUNCTION(0x3, "led", "p3"), 64 + MPP_FUNCTION(0x4, "audio", "mclk"), 65 + MPP_FUNCTION(0x5, "nand", "io5"), 66 + MPP_FUNCTION(0x6, "spi1", "miso")), 67 + MPP_MODE(4, 68 + MPP_FUNCTION(0x0, "gpio", NULL), 69 + MPP_FUNCTION(0x1, "dev", "ad6"), 70 + MPP_FUNCTION(0x2, "spi0", "miso"), 71 + MPP_FUNCTION(0x3, "spi1", "miso"), 72 + MPP_FUNCTION(0x5, "nand", "io6")), 73 + MPP_MODE(5, 74 + MPP_FUNCTION(0x0, "gpio", NULL), 75 + MPP_FUNCTION(0x1, "dev", "ad7"), 76 + MPP_FUNCTION(0x2, "spi0", "cs2"), 77 + MPP_FUNCTION(0x3, "spi1", "cs2"), 78 + MPP_FUNCTION(0x5, "nand", "io7"), 79 + MPP_FUNCTION(0x6, "spi1", "miso")), 80 + MPP_MODE(6, 81 + MPP_FUNCTION(0x0, "gpio", NULL), 82 + MPP_FUNCTION(0x1, "dev", "ad0"), 83 + MPP_FUNCTION(0x3, "led", "p1"), 84 + MPP_FUNCTION(0x4, "audio", "rclk"), 85 + MPP_FUNCTION(0x5, "nand", "io0")), 86 + MPP_MODE(7, 87 + MPP_FUNCTION(0x0, "gpio", NULL), 88 + MPP_FUNCTION(0x1, "dev", "ad1"), 89 + MPP_FUNCTION(0x2, "ptp", "clk"), 90 + MPP_FUNCTION(0x3, "led", "p2"), 91 + MPP_FUNCTION(0x4, "audio", "extclk"), 92 + MPP_FUNCTION(0x5, "nand", "io1")), 93 + MPP_MODE(8, 94 + MPP_FUNCTION(0x0, "gpio", NULL), 95 + MPP_FUNCTION(0x1, "dev ", "bootcs"), 96 + MPP_FUNCTION(0x2, "spi0", "cs0"), 97 + MPP_FUNCTION(0x3, "spi1", "cs0"), 98 + MPP_FUNCTION(0x5, "nand", "ce")), 99 + MPP_MODE(9, 100 + MPP_FUNCTION(0x0, "gpio", NULL), 101 + MPP_FUNCTION(0x1, "nf", "wen"), 102 + MPP_FUNCTION(0x2, "spi0", "sck"), 103 + MPP_FUNCTION(0x3, "spi1", "sck"), 104 + MPP_FUNCTION(0x5, "nand", "we")), 105 + MPP_MODE(10, 106 + MPP_FUNCTION(0x0, "gpio", NULL), 107 + MPP_FUNCTION(0x1, "nf", "ren"), 108 + MPP_FUNCTION(0x2, "dram", "vttctrl"), 109 + MPP_FUNCTION(0x3, "led", "c1"), 110 + MPP_FUNCTION(0x5, "nand", "re"), 111 + MPP_FUNCTION(0x6, "spi1", "sck")), 112 + MPP_MODE(11, 113 + MPP_FUNCTION(0x0, "gpio", NULL), 114 + MPP_FUNCTION(0x1, "dev", "a0"), 115 + MPP_FUNCTION(0x3, "led", "c2"), 116 + MPP_FUNCTION(0x4, "audio", "sdo"), 117 + MPP_FUNCTION(0x5, "nand", "cle")), 118 + MPP_MODE(12, 119 + MPP_FUNCTION(0x0, "gpio", NULL), 120 + MPP_FUNCTION(0x1, "dev", "a1"), 121 + MPP_FUNCTION(0x4, "audio", "bclk"), 122 + MPP_FUNCTION(0x5, "nand", "ale")), 123 + MPP_MODE(13, 124 + MPP_FUNCTION(0x0, "gpio", NULL), 125 + MPP_FUNCTION(0x1, "dev", "readyn"), 126 + MPP_FUNCTION(0x2, "pcie0", "rstoutn"), 127 + MPP_FUNCTION(0x3, "pcie1", "rstoutn"), 128 + MPP_FUNCTION(0x5, "nand", "rb"), 129 + MPP_FUNCTION(0x6, "spi1", "mosi")), 130 + MPP_MODE(14, 131 + MPP_FUNCTION(0x0, "gpio", NULL), 132 + MPP_FUNCTION(0x2, "i2c0", "sda"), 133 + MPP_FUNCTION(0x3, "uart1", "txd")), 134 + MPP_MODE(15, 135 + MPP_FUNCTION(0x0, "gpio", NULL), 136 + MPP_FUNCTION(0x2, "i2c0", "sck"), 137 + MPP_FUNCTION(0x3, "uart1", "rxd")), 138 + MPP_MODE(16, 139 + MPP_FUNCTION(0x0, "gpio", NULL), 140 + MPP_FUNCTION(0x2, "uart0", "txd")), 141 + MPP_MODE(17, 142 + MPP_FUNCTION(0x0, "gpio", NULL), 143 + MPP_FUNCTION(0x2, "uart0", "rxd")), 144 + MPP_MODE(18, 145 + MPP_FUNCTION(0x0, "gpio", NULL), 146 + MPP_FUNCTION(0x2, "tdm", "intn")), 147 + MPP_MODE(19, 148 + MPP_FUNCTION(0x0, "gpio", NULL), 149 + MPP_FUNCTION(0x2, "tdm", "rstn")), 150 + MPP_MODE(20, 151 + MPP_FUNCTION(0x0, "gpio", NULL), 152 + MPP_FUNCTION(0x2, "tdm", "pclk")), 153 + MPP_MODE(21, 154 + MPP_FUNCTION(0x0, "gpio", NULL), 155 + MPP_FUNCTION(0x2, "tdm", "fsync")), 156 + MPP_MODE(22, 157 + MPP_FUNCTION(0x0, "gpio", NULL), 158 + MPP_FUNCTION(0x2, "tdm", "drx")), 159 + MPP_MODE(23, 160 + MPP_FUNCTION(0x0, "gpio", NULL), 161 + MPP_FUNCTION(0x2, "tdm", "dtx")), 162 + MPP_MODE(24, 163 + MPP_FUNCTION(0x0, "gpio", NULL), 164 + MPP_FUNCTION(0x1, "led", "p0"), 165 + MPP_FUNCTION(0x2, "ge1", "rxd0"), 166 + MPP_FUNCTION(0x3, "sd", "cmd"), 167 + MPP_FUNCTION(0x4, "uart0", "rts"), 168 + MPP_FUNCTION(0x5, "spi0", "cs0"), 169 + MPP_FUNCTION(0x6, "dev", "cs1")), 170 + MPP_MODE(25, 171 + MPP_FUNCTION(0x0, "gpio", NULL), 172 + MPP_FUNCTION(0x1, "led", "p2"), 173 + MPP_FUNCTION(0x2, "ge1", "rxd1"), 174 + MPP_FUNCTION(0x3, "sd", "d0"), 175 + MPP_FUNCTION(0x4, "uart0", "cts"), 176 + MPP_FUNCTION(0x5, "spi0", "mosi"), 177 + MPP_FUNCTION(0x6, "dev", "cs2")), 178 + MPP_MODE(26, 179 + MPP_FUNCTION(0x0, "gpio", NULL), 180 + MPP_FUNCTION(0x1, "pcie0", "clkreq"), 181 + MPP_FUNCTION(0x2, "ge1", "rxd2"), 182 + MPP_FUNCTION(0x3, "sd", "d2"), 183 + MPP_FUNCTION(0x4, "uart1", "rts"), 184 + MPP_FUNCTION(0x5, "spi0", "cs1"), 185 + MPP_FUNCTION(0x6, "led", "c1")), 186 + MPP_MODE(27, 187 + MPP_FUNCTION(0x0, "gpio", NULL), 188 + MPP_FUNCTION(0x1, "pcie1", "clkreq"), 189 + MPP_FUNCTION(0x2, "ge1", "rxd3"), 190 + MPP_FUNCTION(0x3, "sd", "d1"), 191 + MPP_FUNCTION(0x4, "uart1", "cts"), 192 + MPP_FUNCTION(0x5, "spi0", "miso"), 193 + MPP_FUNCTION(0x6, "led", "c2")), 194 + MPP_MODE(28, 195 + MPP_FUNCTION(0x0, "gpio", NULL), 196 + MPP_FUNCTION(0x1, "led", "p3"), 197 + MPP_FUNCTION(0x2, "ge1", "txctl"), 198 + MPP_FUNCTION(0x3, "sd", "clk"), 199 + MPP_FUNCTION(0x5, "dram", "vttctrl")), 200 + MPP_MODE(29, 201 + MPP_FUNCTION(0x0, "gpio", NULL), 202 + MPP_FUNCTION(0x1, "pcie1", "clkreq"), 203 + MPP_FUNCTION(0x2, "ge1", "rxclk"), 204 + MPP_FUNCTION(0x3, "sd", "d3"), 205 + MPP_FUNCTION(0x5, "spi0", "sck"), 206 + MPP_FUNCTION(0x6, "pcie0", "rstoutn")), 207 + MPP_MODE(30, 208 + MPP_FUNCTION(0x0, "gpio", NULL), 209 + MPP_FUNCTION(0x2, "ge1", "txd0"), 210 + MPP_FUNCTION(0x3, "spi1", "cs0"), 211 + MPP_FUNCTION(0x5, "led", "p3"), 212 + MPP_FUNCTION(0x6, "ptp", "eventreq")), 213 + MPP_MODE(31, 214 + MPP_FUNCTION(0x0, "gpio", NULL), 215 + MPP_FUNCTION(0x2, "ge1", "txd1"), 216 + MPP_FUNCTION(0x3, "spi1", "mosi"), 217 + MPP_FUNCTION(0x5, "led", "p0")), 218 + MPP_MODE(32, 219 + MPP_FUNCTION(0x0, "gpio", NULL), 220 + MPP_FUNCTION(0x2, "ge1", "txd2"), 221 + MPP_FUNCTION(0x3, "spi1", "sck"), 222 + MPP_FUNCTION(0x4, "ptp", "triggen"), 223 + MPP_FUNCTION(0x5, "led", "c0")), 224 + MPP_MODE(33, 225 + MPP_FUNCTION(0x0, "gpio", NULL), 226 + MPP_FUNCTION(0x2, "ge1", "txd3"), 227 + MPP_FUNCTION(0x3, "spi1", "miso"), 228 + MPP_FUNCTION(0x5, "led", "p2")), 229 + MPP_MODE(34, 230 + MPP_FUNCTION(0x0, "gpio", NULL), 231 + MPP_FUNCTION(0x2, "ge1", "txclkout"), 232 + MPP_FUNCTION(0x3, "spi1", "sck"), 233 + MPP_FUNCTION(0x5, "led", "c1")), 234 + MPP_MODE(35, 235 + MPP_FUNCTION(0x0, "gpio", NULL), 236 + MPP_FUNCTION(0x2, "ge1", "rxctl"), 237 + MPP_FUNCTION(0x3, "spi1", "cs1"), 238 + MPP_FUNCTION(0x4, "spi0", "cs2"), 239 + MPP_FUNCTION(0x5, "led", "p1")), 240 + MPP_MODE(36, 241 + MPP_FUNCTION(0x0, "gpio", NULL), 242 + MPP_FUNCTION(0x1, "pcie0", "clkreq"), 243 + MPP_FUNCTION(0x5, "led", "c2")), 244 + MPP_MODE(37, 245 + MPP_FUNCTION(0x0, "gpio", NULL), 246 + MPP_FUNCTION(0x1, "pcie0", "clkreq"), 247 + MPP_FUNCTION(0x2, "tdm", "intn"), 248 + MPP_FUNCTION(0x4, "ge", "mdc")), 249 + MPP_MODE(38, 250 + MPP_FUNCTION(0x0, "gpio", NULL), 251 + MPP_FUNCTION(0x1, "pcie1", "clkreq"), 252 + MPP_FUNCTION(0x4, "ge", "mdio")), 253 + MPP_MODE(39, 254 + MPP_FUNCTION(0x0, "gpio", NULL), 255 + MPP_FUNCTION(0x4, "ref", "clkout"), 256 + MPP_FUNCTION(0x5, "led", "p3")), 257 + MPP_MODE(40, 258 + MPP_FUNCTION(0x0, "gpio", NULL), 259 + MPP_FUNCTION(0x4, "uart1", "txd"), 260 + MPP_FUNCTION(0x5, "led", "p0")), 261 + MPP_MODE(41, 262 + MPP_FUNCTION(0x0, "gpio", NULL), 263 + MPP_FUNCTION(0x4, "uart1", "rxd"), 264 + MPP_FUNCTION(0x5, "led", "p1")), 265 + MPP_MODE(42, 266 + MPP_FUNCTION(0x0, "gpio", NULL), 267 + MPP_FUNCTION(0x3, "spi1", "cs2"), 268 + MPP_FUNCTION(0x4, "led", "c0"), 269 + MPP_FUNCTION(0x6, "ptp", "clk")), 270 + MPP_MODE(43, 271 + MPP_FUNCTION(0x0, "gpio", NULL), 272 + MPP_FUNCTION(0x2, "sata0", "prsnt"), 273 + MPP_FUNCTION(0x4, "dram", "vttctrl"), 274 + MPP_FUNCTION(0x5, "led", "c1")), 275 + MPP_MODE(44, 276 + MPP_FUNCTION(0x0, "gpio", NULL), 277 + MPP_FUNCTION(0x4, "sata0", "prsnt")), 278 + MPP_MODE(45, 279 + MPP_FUNCTION(0x0, "gpio", NULL), 280 + MPP_FUNCTION(0x2, "spi0", "cs2"), 281 + MPP_FUNCTION(0x4, "pcie0", "rstoutn"), 282 + MPP_FUNCTION(0x5, "led", "c2"), 283 + MPP_FUNCTION(0x6, "spi1", "cs2")), 284 + MPP_MODE(46, 285 + MPP_FUNCTION(0x0, "gpio", NULL), 286 + MPP_FUNCTION(0x1, "led", "p0"), 287 + MPP_FUNCTION(0x2, "ge0", "txd0"), 288 + MPP_FUNCTION(0x3, "ge1", "txd0"), 289 + MPP_FUNCTION(0x6, "dev", "wen1")), 290 + MPP_MODE(47, 291 + MPP_FUNCTION(0x0, "gpio", NULL), 292 + MPP_FUNCTION(0x1, "led", "p1"), 293 + MPP_FUNCTION(0x2, "ge0", "txd1"), 294 + MPP_FUNCTION(0x3, "ge1", "txd1"), 295 + MPP_FUNCTION(0x5, "ptp", "triggen"), 296 + MPP_FUNCTION(0x6, "dev", "ale0")), 297 + MPP_MODE(48, 298 + MPP_FUNCTION(0x0, "gpio", NULL), 299 + MPP_FUNCTION(0x1, "led", "p2"), 300 + MPP_FUNCTION(0x2, "ge0", "txd2"), 301 + MPP_FUNCTION(0x3, "ge1", "txd2"), 302 + MPP_FUNCTION(0x6, "dev", "ale1")), 303 + MPP_MODE(49, 304 + MPP_FUNCTION(0x0, "gpio", NULL), 305 + MPP_FUNCTION(0x1, "led", "p3"), 306 + MPP_FUNCTION(0x2, "ge0", "txd3"), 307 + MPP_FUNCTION(0x3, "ge1", "txd3"), 308 + MPP_FUNCTION(0x6, "dev", "a2")), 309 + MPP_MODE(50, 310 + MPP_FUNCTION(0x0, "gpio", NULL), 311 + MPP_FUNCTION(0x1, "led", "c0"), 312 + MPP_FUNCTION(0x2, "ge0", "rxd0"), 313 + MPP_FUNCTION(0x3, "ge1", "rxd0"), 314 + MPP_FUNCTION(0x5, "ptp", "eventreq"), 315 + MPP_FUNCTION(0x6, "dev", "ad12")), 316 + MPP_MODE(51, 317 + MPP_FUNCTION(0x0, "gpio", NULL), 318 + MPP_FUNCTION(0x1, "led", "c1"), 319 + MPP_FUNCTION(0x2, "ge0", "rxd1"), 320 + MPP_FUNCTION(0x3, "ge1", "rxd1"), 321 + MPP_FUNCTION(0x6, "dev", "ad8")), 322 + MPP_MODE(52, 323 + MPP_FUNCTION(0x0, "gpio", NULL), 324 + MPP_FUNCTION(0x1, "led", "c2"), 325 + MPP_FUNCTION(0x2, "ge0", "rxd2"), 326 + MPP_FUNCTION(0x3, "ge1", "rxd2"), 327 + MPP_FUNCTION(0x5, "i2c0", "sda"), 328 + MPP_FUNCTION(0x6, "dev", "ad9")), 329 + MPP_MODE(53, 330 + MPP_FUNCTION(0x0, "gpio", NULL), 331 + MPP_FUNCTION(0x1, "pcie1", "rstoutn"), 332 + MPP_FUNCTION(0x2, "ge0", "rxd3"), 333 + MPP_FUNCTION(0x3, "ge1", "rxd3"), 334 + MPP_FUNCTION(0x5, "i2c0", "sck"), 335 + MPP_FUNCTION(0x6, "dev", "ad10")), 336 + MPP_MODE(54, 337 + MPP_FUNCTION(0x0, "gpio", NULL), 338 + MPP_FUNCTION(0x1, "pcie0", "rstoutn"), 339 + MPP_FUNCTION(0x2, "ge0", "rxctl"), 340 + MPP_FUNCTION(0x3, "ge1", "rxctl"), 341 + MPP_FUNCTION(0x6, "dev", "ad11")), 342 + MPP_MODE(55, 343 + MPP_FUNCTION(0x0, "gpio", NULL), 344 + MPP_FUNCTION(0x2, "ge0", "rxclk"), 345 + MPP_FUNCTION(0x3, "ge1", "rxclk"), 346 + MPP_FUNCTION(0x6, "dev", "cs0")), 347 + MPP_MODE(56, 348 + MPP_FUNCTION(0x0, "gpio", NULL), 349 + MPP_FUNCTION(0x2, "ge0", "txclkout"), 350 + MPP_FUNCTION(0x3, "ge1", "txclkout"), 351 + MPP_FUNCTION(0x6, "dev", "oe")), 352 + MPP_MODE(57, 353 + MPP_FUNCTION(0x0, "gpio", NULL), 354 + MPP_FUNCTION(0x2, "ge0", "txctl"), 355 + MPP_FUNCTION(0x3, "ge1", "txctl"), 356 + MPP_FUNCTION(0x6, "dev", "wen0")), 357 + MPP_MODE(58, 358 + MPP_FUNCTION(0x0, "gpio", NULL), 359 + MPP_FUNCTION(0x4, "led", "c0")), 360 + MPP_MODE(59, 361 + MPP_FUNCTION(0x0, "gpio", NULL), 362 + MPP_FUNCTION(0x4, "led", "c1")), 363 + MPP_MODE(60, 364 + MPP_FUNCTION(0x0, "gpio", NULL), 365 + MPP_FUNCTION(0x2, "uart1", "txd"), 366 + MPP_FUNCTION(0x4, "led", "c2"), 367 + MPP_FUNCTION(0x6, "dev", "ad13")), 368 + MPP_MODE(61, 369 + MPP_FUNCTION(0x0, "gpio", NULL), 370 + MPP_FUNCTION(0x1, "i2c1", "sda"), 371 + MPP_FUNCTION(0x2, "uart1", "rxd"), 372 + MPP_FUNCTION(0x3, "spi1", "cs2"), 373 + MPP_FUNCTION(0x4, "led", "p0"), 374 + MPP_FUNCTION(0x6, "dev", "ad14")), 375 + MPP_MODE(62, 376 + MPP_FUNCTION(0x0, "gpio", NULL), 377 + MPP_FUNCTION(0x1, "i2c1", "sck"), 378 + MPP_FUNCTION(0x4, "led", "p1"), 379 + MPP_FUNCTION(0x6, "dev", "ad15")), 380 + MPP_MODE(63, 381 + MPP_FUNCTION(0x0, "gpio", NULL), 382 + MPP_FUNCTION(0x2, "ptp", "triggen"), 383 + MPP_FUNCTION(0x4, "led", "p2"), 384 + MPP_FUNCTION(0x6, "dev", "burst")), 385 + MPP_MODE(64, 386 + MPP_FUNCTION(0x0, "gpio", NULL), 387 + MPP_FUNCTION(0x2, "dram", "vttctrl"), 388 + MPP_FUNCTION(0x4, "led", "p3")), 389 + MPP_MODE(65, 390 + MPP_FUNCTION(0x0, "gpio", NULL), 391 + MPP_FUNCTION(0x1, "sata1", "prsnt")), 392 + MPP_MODE(66, 393 + MPP_FUNCTION(0x0, "gpio", NULL), 394 + MPP_FUNCTION(0x2, "ptp", "eventreq"), 395 + MPP_FUNCTION(0x4, "spi1", "cs3"), 396 + MPP_FUNCTION(0x5, "pcie0", "rstoutn"), 397 + MPP_FUNCTION(0x6, "dev", "cs3")), 398 + }; 399 + 400 + static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info; 401 + 402 + static struct of_device_id armada_375_pinctrl_of_match[] = { 403 + { .compatible = "marvell,mv88f6720-pinctrl" }, 404 + { }, 405 + }; 406 + 407 + static struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = { 408 + MPP_FUNC_CTRL(0, 69, NULL, armada_375_mpp_ctrl), 409 + }; 410 + 411 + static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = { 412 + MPP_GPIO_RANGE(0, 0, 0, 32), 413 + MPP_GPIO_RANGE(1, 32, 32, 32), 414 + MPP_GPIO_RANGE(2, 64, 64, 3), 415 + }; 416 + 417 + static int armada_375_pinctrl_probe(struct platform_device *pdev) 418 + { 419 + struct mvebu_pinctrl_soc_info *soc = &armada_375_pinctrl_info; 420 + struct resource *res; 421 + 422 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 423 + mpp_base = devm_ioremap_resource(&pdev->dev, res); 424 + if (IS_ERR(mpp_base)) 425 + return PTR_ERR(mpp_base); 426 + 427 + soc->variant = 0; /* no variants for Armada 375 */ 428 + soc->controls = mv88f6720_mpp_controls; 429 + soc->ncontrols = ARRAY_SIZE(mv88f6720_mpp_controls); 430 + soc->modes = mv88f6720_mpp_modes; 431 + soc->nmodes = ARRAY_SIZE(mv88f6720_mpp_modes); 432 + soc->gpioranges = mv88f6720_mpp_gpio_ranges; 433 + soc->ngpioranges = ARRAY_SIZE(mv88f6720_mpp_gpio_ranges); 434 + 435 + pdev->dev.platform_data = soc; 436 + 437 + return mvebu_pinctrl_probe(pdev); 438 + } 439 + 440 + static int armada_375_pinctrl_remove(struct platform_device *pdev) 441 + { 442 + return mvebu_pinctrl_remove(pdev); 443 + } 444 + 445 + static struct platform_driver armada_375_pinctrl_driver = { 446 + .driver = { 447 + .name = "armada-375-pinctrl", 448 + .owner = THIS_MODULE, 449 + .of_match_table = of_match_ptr(armada_375_pinctrl_of_match), 450 + }, 451 + .probe = armada_375_pinctrl_probe, 452 + .remove = armada_375_pinctrl_remove, 453 + }; 454 + 455 + module_platform_driver(armada_375_pinctrl_driver); 456 + 457 + MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); 458 + MODULE_DESCRIPTION("Marvell Armada 375 pinctrl driver"); 459 + MODULE_LICENSE("GPL v2");