Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Populate dtbclk entries for dcn3.02/3.03

[Why]
Populate dtbclk values from bwparams for dcn302, dcn303.

[How]
dtbclk values are fetched from bandwidthparams for all DPM levels and
for DPM levels where smu returns 0, previous level values are reported.

Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Bindu Ramamurthy and committed by
Alex Deucher
ce350c6e 0f984c94

+10 -2
+5 -1
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
··· 1398 1398 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1399 1399 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1400 1400 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1401 - dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz; 1401 + /* Populate from bw_params for DTBCLK, SOCCLK */ 1402 + if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) 1403 + dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz; 1404 + else 1405 + dcn3_02_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 1402 1406 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 1403 1407 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz; 1404 1408 else
+5 -1
drivers/gpu/drm/amd/display/dc/dcn303/dcn303_resource.c
··· 1326 1326 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz; 1327 1327 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; 1328 1328 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz; 1329 - dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz; 1329 + /* Populate from bw_params for DTBCLK, SOCCLK */ 1330 + if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0) 1331 + dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz; 1332 + else 1333 + dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz; 1330 1334 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0) 1331 1335 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz; 1332 1336 else