tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
"The most notable new addition inside this pull request is the support
for MIPS's latest and greatest core called "inter/proAptiv". The
patch series describes this core as follows.

"The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit."

The platform specific patches touch all 3 Broadcom families. It adds
support for the new Broadcom/Netlogix XLP9xx Soc, building a common
BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
and full gpio button/led descriptions for BCM47xx.

The rest of the series are cleanups and bug fixes that are MIPS
generic and consist largely of changes that Imgtec/MIPS had published
in their linux-mti-3.10.git stable tree. Random other cleanups and
patches preparing code to be merged in 3.15"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
mips: select ARCH_MIGHT_HAVE_PC_SERIO
mips: delete non-required instances of include <linux/init.h>
MIPS: KVM: remove shadow_tlb code
MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
mips/ide: flush dcache also if icache does not snoop dcache
MIPS: BCM47XX: fix position of cpu_wait disabling
MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
MIPS: ZBOOT: gather string functions into string.c
arch/mips/pci: don't check resource with devm_ioremap_resource
arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
bcma: gpio: don't cast u32 to unsigned long
ssb: gpio: add own IRQ domain
MIPS: BCM47XX: fix sparse warnings in board.c
MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
MIPS: BCM47XX: fix detection for some boards
MIPS: BCM47XX: Enable buttons support on SSB
MIPS: BCM47XX: Convert WNDR4500 to new syntax
MIPS: BCM47XX: Use "timer" trigger for status LEDs
...

Linus Torvalds cdfc8307 04a24ae4

+6631 -3312
unified split
+133 -88
arch/mips/Kconfig
··· 116 select CEVT_R4K 117 select CSRC_R4K 118 select DMA_NONCOHERENT 119 - select FW_CFE 120 select HW_HAS_PCI 121 select IRQ_CPU 122 select SYS_HAS_CPU_MIPS32_R1 ··· 123 select SYS_SUPPORTS_32BIT_KERNEL 124 select SYS_SUPPORTS_LITTLE_ENDIAN 125 select SYS_HAS_EARLY_PRINTK 126 help 127 Support for BCM47XX based boards 128 ··· 134 select CSRC_R4K 135 select DMA_NONCOHERENT 136 select IRQ_CPU 137 - select SYS_HAS_CPU_MIPS32_R1 138 - select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348 139 select SYS_SUPPORTS_32BIT_KERNEL 140 select SYS_SUPPORTS_BIG_ENDIAN 141 select SYS_HAS_EARLY_PRINTK 142 select SWAP_IO_SPACE 143 select ARCH_REQUIRE_GPIOLIB 144 select HAVE_CLK 145 help 146 Support for BCM63XX based boards 147 ··· 185 select SYS_SUPPORTS_128HZ 186 select SYS_SUPPORTS_256HZ 187 select SYS_SUPPORTS_1024HZ 188 help 189 This enables support for DEC's MIPS based workstations. For details 190 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the ··· 305 select CEVT_R4K 306 select CSRC_R4K 307 select CSRC_GIC 308 - select DMA_NONCOHERENT 309 select GENERIC_ISA_DMA 310 select HAVE_PCSPKR_PLATFORM 311 select IRQ_CPU ··· 324 select SYS_HAS_CPU_MIPS64_R2 325 select SYS_HAS_CPU_NEVADA 326 select SYS_HAS_CPU_RM7000 327 - select SYS_HAS_EARLY_PRINTK 328 select SYS_SUPPORTS_32BIT_KERNEL 329 select SYS_SUPPORTS_64BIT_KERNEL 330 select SYS_SUPPORTS_BIG_ENDIAN ··· 348 select DMA_NONCOHERENT 349 select IRQ_CPU 350 select IRQ_GIC 351 select MIPS_MSC 352 select SYS_HAS_CPU_MIPS32_R1 353 select SYS_HAS_CPU_MIPS32_R2 ··· 471 select SYS_SUPPORTS_32BIT_KERNEL 472 select SYS_SUPPORTS_64BIT_KERNEL 473 select SYS_SUPPORTS_BIG_ENDIAN 474 help 475 This are the SGI Indy, Challenge S and Indigo2, as well as certain 476 OEM variants like the Tandem CMN B006S. To compile a Linux kernel ··· 492 select SYS_SUPPORTS_BIG_ENDIAN 493 select SYS_SUPPORTS_NUMA 494 select SYS_SUPPORTS_SMP 495 help 496 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 497 workstations. To compile a Linux kernel that runs on these, say Y ··· 699 select SWAP_IO_SPACE 700 select BOOT_RAW 701 select ARCH_REQUIRE_GPIOLIB 702 help 703 Support the Mikrotik(tm) RouterBoard 532 series, 704 based on the IDT RC32434 SoC. ··· 782 select CEVT_R4K 783 select CSRC_R4K 784 select IRQ_CPU 785 select ZONE_DMA32 if 64BIT 786 select SYNC_R4K 787 select SYS_HAS_EARLY_PRINTK ··· 900 901 config ARCH_DMA_ADDR_T_64BIT 902 def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT 903 904 config DMA_COHERENT 905 bool ··· 1099 config BOOT_ELF32 1100 bool 1101 1102 config MIPS_L1_CACHE_SHIFT 1103 int 1104 - default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X 1105 - default "6" if MIPS_CPU_SCACHE 1106 - default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON 1107 default "5" 1108 1109 config HAVE_STD_PC_SERIAL_PORT ··· 1396 select LIBFDT 1397 select USE_OF 1398 select USB_EHCI_BIG_ENDIAN_MMIO 1399 help 1400 The Cavium Octeon processor is a highly integrated chip containing 1401 many ethernet hardware widgets for networking tasks. The processor 1402 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. 1403 Full details can be found at http://www.caviumnetworks.com. 1404 1405 - config CPU_BMIPS3300 1406 - bool "BMIPS3300" 1407 - depends on SYS_HAS_CPU_BMIPS3300 1408 - select CPU_BMIPS 1409 - help 1410 - Broadcom BMIPS3300 processors. 1411 - 1412 - config CPU_BMIPS4350 1413 - bool "BMIPS4350" 1414 - depends on SYS_HAS_CPU_BMIPS4350 1415 - select CPU_BMIPS 1416 - select SYS_SUPPORTS_SMP 1417 - select SYS_SUPPORTS_HOTPLUG_CPU 1418 - help 1419 - Broadcom BMIPS4350 ("VIPER") processors. 1420 - 1421 - config CPU_BMIPS4380 1422 - bool "BMIPS4380" 1423 - depends on SYS_HAS_CPU_BMIPS4380 1424 - select CPU_BMIPS 1425 - select SYS_SUPPORTS_SMP 1426 - select SYS_SUPPORTS_HOTPLUG_CPU 1427 - help 1428 - Broadcom BMIPS4380 processors. 1429 - 1430 - config CPU_BMIPS5000 1431 - bool "BMIPS5000" 1432 - depends on SYS_HAS_CPU_BMIPS5000 1433 - select CPU_BMIPS 1434 select CPU_SUPPORTS_HIGHMEM 1435 - select MIPS_CPU_SCACHE 1436 - select SYS_SUPPORTS_SMP 1437 - select SYS_SUPPORTS_HOTPLUG_CPU 1438 help 1439 - Broadcom BMIPS5000 processors. 1440 1441 config CPU_XLR 1442 bool "Netlogic XLR SoC" ··· 1503 select CPU_SUPPORTS_32BIT_KERNEL 1504 select CPU_SUPPORTS_HIGHMEM 1505 1506 - config CPU_BMIPS 1507 bool 1508 - select CPU_MIPS32 1509 - select CPU_SUPPORTS_32BIT_KERNEL 1510 - select DMA_NONCOHERENT 1511 - select IRQ_CPU 1512 - select SWAP_IO_SPACE 1513 - select WEAK_ORDERING 1514 1515 config SYS_HAS_CPU_LOONGSON2E 1516 bool ··· 1595 config SYS_HAS_CPU_CAVIUM_OCTEON 1596 bool 1597 1598 - config SYS_HAS_CPU_BMIPS3300 1599 bool 1600 1601 config SYS_HAS_CPU_BMIPS4350 1602 bool 1603 1604 config SYS_HAS_CPU_BMIPS4380 1605 bool 1606 1607 config SYS_HAS_CPU_BMIPS5000 1608 bool 1609 1610 config SYS_HAS_CPU_XLR 1611 bool ··· 1820 config MIPS_CPU_SCACHE 1821 bool 1822 select BOARD_SCACHE 1823 1824 config R5000_CPU_SCACHE 1825 bool ··· 1857 prompt "MIPS MT options" 1858 1859 config MIPS_MT_DISABLED 1860 - bool "Disable multithreading support." 1861 help 1862 - Use this option if your workload can't take advantage of 1863 - MIPS hardware multithreading support. On systems that don't have 1864 - the option of an MT-enabled processor this option will be the only 1865 - option in this menu. 1866 1867 config MIPS_MT_SMP 1868 bool "Use 1 TC on each available VPE for SMP" 1869 depends on SYS_SUPPORTS_MULTITHREADING 1870 select CPU_MIPSR2_IRQ_VI 1871 select CPU_MIPSR2_IRQ_EI 1872 select MIPS_MT 1873 select SMP 1874 - select SYS_SUPPORTS_SCHED_SMT if SMP 1875 - select SYS_SUPPORTS_SMP 1876 select SMP_UP 1877 select MIPS_PERF_SHARED_TC_COUNTERS 1878 help 1879 - This is a kernel model which is known a VSMP but lately has been 1880 - marketesed into SMVP. 1881 - Virtual SMP uses the processor's VPEs to implement virtual 1882 - processors. In currently available configuration of the 34K processor 1883 - this allows for a dual processor. Both processors will share the same 1884 - primary caches; each will obtain the half of the TLB for it's own 1885 - exclusive use. For a layman this model can be described as similar to 1886 - what Intel calls Hyperthreading. 1887 - 1888 - For further information see http://www.linux-mips.org/wiki/34K#VSMP 1889 1890 config MIPS_MT_SMTC 1891 - bool "SMTC: Use all TCs on all VPEs for SMP" 1892 depends on CPU_MIPS32_R2 1893 - #depends on CPU_MIPS64_R2 # once there is hardware ... 1894 depends on SYS_SUPPORTS_MULTITHREADING 1895 select CPU_MIPSR2_IRQ_VI 1896 select CPU_MIPSR2_IRQ_EI 1897 select MIPS_MT 1898 - select NR_CPUS_DEFAULT_8 1899 select SMP 1900 - select SYS_SUPPORTS_SMP 1901 select SMP_UP 1902 help 1903 - This is a kernel model which is known a SMTC or lately has been 1904 - marketesed into SMVP. 1905 - is presenting the available TC's of the core as processors to Linux. 1906 - On currently available 34K processors this means a Linux system will 1907 - see up to 5 processors. The implementation of the SMTC kernel differs 1908 - significantly from VSMP and cannot efficiently coexist in the same 1909 - kernel binary so the choice between VSMP and SMTC is a compile time 1910 - decision. 1911 - 1912 - For further information see http://www.linux-mips.org/wiki/34K#SMTC 1913 1914 endchoice 1915 ··· 1935 Includes a loader for loading an elf relocatable object 1936 onto another VPE and running it. 1937 1938 config MIPS_MT_SMTC_IM_BACKSTOP 1939 bool "Use per-TC register bits as backstop for inhibited IM bits" 1940 depends on MIPS_MT_SMTC ··· 1978 you to ensure the amount you put in the option and the space your 1979 program requires is less or equal to the amount physically present. 1980 1981 - # this should possibly be in drivers/char, but it is rather cpu related. Hmmm 1982 config MIPS_VPE_APSP_API 1983 bool "Enable support for AP/SP API (RTLX)" 1984 depends on MIPS_VPE_LOADER 1985 help 1986 1987 config MIPS_CMP 1988 - bool "MIPS CMP framework support" 1989 - depends on SYS_SUPPORTS_MIPS_CMP 1990 - select SMP 1991 select SYNC_R4K 1992 - select SYS_SUPPORTS_SMP 1993 - select SYS_SUPPORTS_SCHED_SMT if SMP 1994 select WEAK_ORDERING 1995 default n 1996 help 1997 - This is a placeholder option for the GCMP work. It will need to 1998 - be handled differently... 1999 2000 config SB1_PASS_1_WORKAROUNDS 2001 bool ··· 2351 defined by each seccomp mode. 2352 2353 If unsure, say Y. Only embedded should say N here. 2354 2355 config USE_OF 2356 bool
··· 116 select CEVT_R4K 117 select CSRC_R4K 118 select DMA_NONCOHERENT 119 select HW_HAS_PCI 120 select IRQ_CPU 121 select SYS_HAS_CPU_MIPS32_R1 ··· 124 select SYS_SUPPORTS_32BIT_KERNEL 125 select SYS_SUPPORTS_LITTLE_ENDIAN 126 select SYS_HAS_EARLY_PRINTK 127 + select EARLY_PRINTK_8250 if EARLY_PRINTK 128 help 129 Support for BCM47XX based boards 130 ··· 134 select CSRC_R4K 135 select DMA_NONCOHERENT 136 select IRQ_CPU 137 select SYS_SUPPORTS_32BIT_KERNEL 138 select SYS_SUPPORTS_BIG_ENDIAN 139 select SYS_HAS_EARLY_PRINTK 140 select SWAP_IO_SPACE 141 select ARCH_REQUIRE_GPIOLIB 142 select HAVE_CLK 143 + select MIPS_L1_CACHE_SHIFT_4 144 help 145 Support for BCM63XX based boards 146 ··· 186 select SYS_SUPPORTS_128HZ 187 select SYS_SUPPORTS_256HZ 188 select SYS_SUPPORTS_1024HZ 189 + select MIPS_L1_CACHE_SHIFT_4 190 help 191 This enables support for DEC's MIPS based workstations. For details 192 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the ··· 305 select CEVT_R4K 306 select CSRC_R4K 307 select CSRC_GIC 308 + select DMA_MAYBE_COHERENT 309 select GENERIC_ISA_DMA 310 select HAVE_PCSPKR_PLATFORM 311 select IRQ_CPU ··· 324 select SYS_HAS_CPU_MIPS64_R2 325 select SYS_HAS_CPU_NEVADA 326 select SYS_HAS_CPU_RM7000 327 select SYS_SUPPORTS_32BIT_KERNEL 328 select SYS_SUPPORTS_64BIT_KERNEL 329 select SYS_SUPPORTS_BIG_ENDIAN ··· 349 select DMA_NONCOHERENT 350 select IRQ_CPU 351 select IRQ_GIC 352 + select LIBFDT 353 select MIPS_MSC 354 select SYS_HAS_CPU_MIPS32_R1 355 select SYS_HAS_CPU_MIPS32_R2 ··· 471 select SYS_SUPPORTS_32BIT_KERNEL 472 select SYS_SUPPORTS_64BIT_KERNEL 473 select SYS_SUPPORTS_BIG_ENDIAN 474 + select MIPS_L1_CACHE_SHIFT_7 475 help 476 This are the SGI Indy, Challenge S and Indigo2, as well as certain 477 OEM variants like the Tandem CMN B006S. To compile a Linux kernel ··· 491 select SYS_SUPPORTS_BIG_ENDIAN 492 select SYS_SUPPORTS_NUMA 493 select SYS_SUPPORTS_SMP 494 + select MIPS_L1_CACHE_SHIFT_7 495 help 496 This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics 497 workstations. To compile a Linux kernel that runs on these, say Y ··· 697 select SWAP_IO_SPACE 698 select BOOT_RAW 699 select ARCH_REQUIRE_GPIOLIB 700 + select MIPS_L1_CACHE_SHIFT_4 701 help 702 Support the Mikrotik(tm) RouterBoard 532 series, 703 based on the IDT RC32434 SoC. ··· 779 select CEVT_R4K 780 select CSRC_R4K 781 select IRQ_CPU 782 + select ARCH_SUPPORTS_MSI 783 select ZONE_DMA32 if 64BIT 784 select SYNC_R4K 785 select SYS_HAS_EARLY_PRINTK ··· 896 897 config ARCH_DMA_ADDR_T_64BIT 898 def_bool (HIGHMEM && 64BIT_PHYS_ADDR) || 64BIT 899 + 900 + config DMA_MAYBE_COHERENT 901 + select DMA_NONCOHERENT 902 + bool 903 904 config DMA_COHERENT 905 bool ··· 1091 config BOOT_ELF32 1092 bool 1093 1094 + config MIPS_L1_CACHE_SHIFT_4 1095 + bool 1096 + 1097 + config MIPS_L1_CACHE_SHIFT_5 1098 + bool 1099 + 1100 + config MIPS_L1_CACHE_SHIFT_6 1101 + bool 1102 + 1103 + config MIPS_L1_CACHE_SHIFT_7 1104 + bool 1105 + 1106 config MIPS_L1_CACHE_SHIFT 1107 int 1108 + default "4" if MIPS_L1_CACHE_SHIFT_4 1109 + default "5" if MIPS_L1_CACHE_SHIFT_5 1110 + default "6" if MIPS_L1_CACHE_SHIFT_6 1111 + default "7" if MIPS_L1_CACHE_SHIFT_7 1112 default "5" 1113 1114 config HAVE_STD_PC_SERIAL_PORT ··· 1375 select LIBFDT 1376 select USE_OF 1377 select USB_EHCI_BIG_ENDIAN_MMIO 1378 + select SYS_HAS_DMA_OPS 1379 + select MIPS_L1_CACHE_SHIFT_7 1380 help 1381 The Cavium Octeon processor is a highly integrated chip containing 1382 many ethernet hardware widgets for networking tasks. The processor 1383 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets. 1384 Full details can be found at http://www.caviumnetworks.com. 1385 1386 + config CPU_BMIPS 1387 + bool "Broadcom BMIPS" 1388 + depends on SYS_HAS_CPU_BMIPS 1389 + select CPU_MIPS32 1390 + select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300 1391 + select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350 1392 + select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380 1393 + select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000 1394 + select CPU_SUPPORTS_32BIT_KERNEL 1395 + select DMA_NONCOHERENT 1396 + select IRQ_CPU 1397 + select SWAP_IO_SPACE 1398 + select WEAK_ORDERING 1399 select CPU_SUPPORTS_HIGHMEM 1400 + select CPU_HAS_PREFETCH 1401 help 1402 + Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors. 1403 1404 config CPU_XLR 1405 bool "Netlogic XLR SoC" ··· 1498 select CPU_SUPPORTS_32BIT_KERNEL 1499 select CPU_SUPPORTS_HIGHMEM 1500 1501 + config CPU_BMIPS32_3300 1502 + select SMP_UP if SMP 1503 bool 1504 + 1505 + config CPU_BMIPS4350 1506 + bool 1507 + select SYS_SUPPORTS_SMP 1508 + select SYS_SUPPORTS_HOTPLUG_CPU 1509 + 1510 + config CPU_BMIPS4380 1511 + bool 1512 + select SYS_SUPPORTS_SMP 1513 + select SYS_SUPPORTS_HOTPLUG_CPU 1514 + 1515 + config CPU_BMIPS5000 1516 + bool 1517 + select MIPS_CPU_SCACHE 1518 + select SYS_SUPPORTS_SMP 1519 + select SYS_SUPPORTS_HOTPLUG_CPU 1520 1521 config SYS_HAS_CPU_LOONGSON2E 1522 bool ··· 1579 config SYS_HAS_CPU_CAVIUM_OCTEON 1580 bool 1581 1582 + config SYS_HAS_CPU_BMIPS 1583 bool 1584 + 1585 + config SYS_HAS_CPU_BMIPS32_3300 1586 + bool 1587 + select SYS_HAS_CPU_BMIPS 1588 1589 config SYS_HAS_CPU_BMIPS4350 1590 bool 1591 + select SYS_HAS_CPU_BMIPS 1592 1593 config SYS_HAS_CPU_BMIPS4380 1594 bool 1595 + select SYS_HAS_CPU_BMIPS 1596 1597 config SYS_HAS_CPU_BMIPS5000 1598 bool 1599 + select SYS_HAS_CPU_BMIPS 1600 1601 config SYS_HAS_CPU_XLR 1602 bool ··· 1797 config MIPS_CPU_SCACHE 1798 bool 1799 select BOARD_SCACHE 1800 + select MIPS_L1_CACHE_SHIFT_6 1801 1802 config R5000_CPU_SCACHE 1803 bool ··· 1833 prompt "MIPS MT options" 1834 1835 config MIPS_MT_DISABLED 1836 + bool "Disable multithreading support" 1837 help 1838 + Use this option if your platform does not support the MT ASE 1839 + which is hardware multithreading support. On systems without 1840 + an MT-enabled processor, this will be the only option that is 1841 + available in this menu. 1842 1843 config MIPS_MT_SMP 1844 bool "Use 1 TC on each available VPE for SMP" 1845 depends on SYS_SUPPORTS_MULTITHREADING 1846 select CPU_MIPSR2_IRQ_VI 1847 select CPU_MIPSR2_IRQ_EI 1848 + select SYNC_R4K 1849 select MIPS_MT 1850 select SMP 1851 select SMP_UP 1852 + select SYS_SUPPORTS_SMP 1853 + select SYS_SUPPORTS_SCHED_SMT 1854 select MIPS_PERF_SHARED_TC_COUNTERS 1855 help 1856 + This is a kernel model which is known as SMVP. This is supported 1857 + on cores with the MT ASE and uses the available VPEs to implement 1858 + virtual processors which supports SMP. This is equivalent to the 1859 + Intel Hyperthreading feature. For further information go to 1860 + <http://www.imgtec.com/mips/mips-multithreading.asp>. 1861 1862 config MIPS_MT_SMTC 1863 + bool "Use all TCs on all VPEs for SMP (DEPRECATED)" 1864 depends on CPU_MIPS32_R2 1865 depends on SYS_SUPPORTS_MULTITHREADING 1866 select CPU_MIPSR2_IRQ_VI 1867 select CPU_MIPSR2_IRQ_EI 1868 select MIPS_MT 1869 select SMP 1870 select SMP_UP 1871 + select SYS_SUPPORTS_SMP 1872 + select NR_CPUS_DEFAULT_8 1873 help 1874 + This is a kernel model which is known as SMTC. This is 1875 + supported on cores with the MT ASE and presents all TCs 1876 + available on all VPEs to support SMP. For further 1877 + information see <http://www.linux-mips.org/wiki/34K#SMTC>. 1878 1879 endchoice 1880 ··· 1922 Includes a loader for loading an elf relocatable object 1923 onto another VPE and running it. 1924 1925 + config MIPS_VPE_LOADER_CMP 1926 + bool 1927 + default "y" 1928 + depends on MIPS_VPE_LOADER && MIPS_CMP 1929 + 1930 + config MIPS_VPE_LOADER_MT 1931 + bool 1932 + default "y" 1933 + depends on MIPS_VPE_LOADER && !MIPS_CMP 1934 + 1935 config MIPS_MT_SMTC_IM_BACKSTOP 1936 bool "Use per-TC register bits as backstop for inhibited IM bits" 1937 depends on MIPS_MT_SMTC ··· 1955 you to ensure the amount you put in the option and the space your 1956 program requires is less or equal to the amount physically present. 1957 1958 config MIPS_VPE_APSP_API 1959 bool "Enable support for AP/SP API (RTLX)" 1960 depends on MIPS_VPE_LOADER 1961 help 1962 1963 + config MIPS_VPE_APSP_API_CMP 1964 + bool 1965 + default "y" 1966 + depends on MIPS_VPE_APSP_API && MIPS_CMP 1967 + 1968 + config MIPS_VPE_APSP_API_MT 1969 + bool 1970 + default "y" 1971 + depends on MIPS_VPE_APSP_API && !MIPS_CMP 1972 + 1973 config MIPS_CMP 1974 + bool "MIPS CMP support" 1975 + depends on SYS_SUPPORTS_MIPS_CMP && MIPS_MT_SMP 1976 select SYNC_R4K 1977 select WEAK_ORDERING 1978 default n 1979 help 1980 + Enable Coherency Manager processor (CMP) support. 1981 1982 config SB1_PASS_1_WORKAROUNDS 1983 bool ··· 2323 defined by each seccomp mode. 2324 2325 If unsure, say Y. Only embedded should say N here. 2326 + 2327 + config MIPS_O32_FP64_SUPPORT 2328 + bool "Support for O32 binaries using 64-bit FP" 2329 + depends on 32BIT || MIPS32_O32 2330 + default y 2331 + help 2332 + When this is enabled, the kernel will support use of 64-bit floating 2333 + point registers with binaries using the O32 ABI along with the 2334 + EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On 2335 + 32-bit MIPS systems this support is at the cost of increasing the 2336 + size and complexity of the compiled FPU emulator. Thus if you are 2337 + running a MIPS32 system and know that none of your userland binaries 2338 + will require 64-bit floating point, you may wish to reduce the size 2339 + of your kernel & potentially improve FP emulation performance by 2340 + saying N here. 2341 + 2342 + If unsure, say Y. 2343 2344 config USE_OF 2345 bool
+1 -1
arch/mips/Makefile
··· 114 cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) 115 116 cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) 117 - cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips -mno-jals) 118 119 cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ 120 -fno-omit-frame-pointer
··· 114 cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le)) 115 116 cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) 117 + cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips) 118 119 cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \ 120 -fno-omit-frame-pointer
-1
arch/mips/alchemy/common/power.c
··· 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 - #include <linux/init.h> 33 #include <linux/pm.h> 34 #include <linux/sysctl.h> 35 #include <linux/jiffies.h>
··· 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 */ 31 32 #include <linux/pm.h> 33 #include <linux/sysctl.h> 34 #include <linux/jiffies.h>
-1
arch/mips/ar7/time.c
··· 18 * Setting up the clock on the MIPS boards. 19 */ 20 21 - #include <linux/init.h> 22 #include <linux/time.h> 23 #include <linux/err.h> 24 #include <linux/clk.h>
··· 18 * Setting up the clock on the MIPS boards. 19 */ 20 21 #include <linux/time.h> 22 #include <linux/err.h> 23 #include <linux/clk.h>
-1
arch/mips/ath79/common.h
··· 15 #define __ATH79_COMMON_H 16 17 #include <linux/types.h> 18 - #include <linux/init.h> 19 20 #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) 21 #define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
··· 15 #define __ATH79_COMMON_H 16 17 #include <linux/types.h> 18 19 #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024) 20 #define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
+4
arch/mips/bcm47xx/Kconfig
··· 2 3 config BCM47XX_SSB 4 bool "SSB Support for Broadcom BCM47XX" 5 select SSB 6 select SSB_DRIVER_MIPS 7 select SSB_DRIVER_EXTIF ··· 12 select SSB_PCICORE_HOSTMODE if PCI 13 select SSB_DRIVER_GPIO 14 select GPIOLIB 15 default y 16 help 17 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. ··· 22 config BCM47XX_BCMA 23 bool "BCMA Support for Broadcom BCM47XX" 24 select SYS_HAS_CPU_MIPS32_R2 25 select BCMA 26 select BCMA_HOST_SOC 27 select BCMA_DRIVER_MIPS ··· 30 select BCMA_DRIVER_PCI_HOSTMODE if PCI 31 select BCMA_DRIVER_GPIO 32 select GPIOLIB 33 default y 34 help 35 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
··· 2 3 config BCM47XX_SSB 4 bool "SSB Support for Broadcom BCM47XX" 5 + select SYS_HAS_CPU_BMIPS32_3300 6 select SSB 7 select SSB_DRIVER_MIPS 8 select SSB_DRIVER_EXTIF ··· 11 select SSB_PCICORE_HOSTMODE if PCI 12 select SSB_DRIVER_GPIO 13 select GPIOLIB 14 + select LEDS_GPIO_REGISTER 15 default y 16 help 17 Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support. ··· 20 config BCM47XX_BCMA 21 bool "BCMA Support for Broadcom BCM47XX" 22 select SYS_HAS_CPU_MIPS32_R2 23 + select CPU_MIPSR2_IRQ_VI 24 select BCMA 25 select BCMA_HOST_SOC 26 select BCMA_DRIVER_MIPS ··· 27 select BCMA_DRIVER_PCI_HOSTMODE if PCI 28 select BCMA_DRIVER_GPIO 29 select GPIOLIB 30 + select LEDS_GPIO_REGISTER 31 default y 32 help 33 Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
+1 -2
arch/mips/bcm47xx/Makefile
··· 4 # 5 6 obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o 7 - obj-y += board.o 8 - obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
··· 4 # 5 6 obj-y += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o 7 + obj-y += board.o buttons.o leds.o
+12
arch/mips/bcm47xx/bcm47xx_private.h
···
··· 1 + #ifndef LINUX_BCM47XX_PRIVATE_H_ 2 + #define LINUX_BCM47XX_PRIVATE_H_ 3 + 4 + #include <linux/kernel.h> 5 + 6 + /* buttons.c */ 7 + int __init bcm47xx_buttons_register(void); 8 + 9 + /* leds.c */ 10 + void __init bcm47xx_leds_register(void); 11 + 12 + #endif
+18 -16
arch/mips/bcm47xx/board.c
··· 36 struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = { 37 {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"}, 38 {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"}, 39 - { {0}, 0}, 40 }; 41 42 /* model_no */ 43 static const 44 struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = { 45 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"}, 46 - { {0}, 0}, 47 }; 48 49 /* machine_name */ 50 static const 51 struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = { 52 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"}, 53 - { {0}, 0}, 54 }; 55 56 /* hardware_version */ 57 static const 58 struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = { 59 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"}, 60 {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"}, 61 {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"}, ··· 72 {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"}, 73 {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"}, 74 {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"}, 75 - { {0}, 0}, 76 }; 77 78 /* productid */ ··· 81 {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"}, 82 {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"}, 83 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"}, 84 - {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RT-N10U"}, 85 - {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"}, 86 - {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RT-N12B1"}, 87 - {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RT-N12C1"}, 88 - {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RT-N12D1"}, 89 - {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RT-N12HP"}, 90 {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"}, 91 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"}, 92 {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"}, 93 {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"}, 94 {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"}, 95 {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"}, 96 - { {0}, 0}, 97 }; 98 99 /* ModelId */ ··· 97 {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"}, 98 {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"}, 99 {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"}, 100 - { {0}, 0}, 101 }; 102 103 /* melco_id or buf1falo_id */ ··· 112 {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"}, 113 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"}, 114 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"}, 115 - { {0}, 0}, 116 }; 117 118 /* boot_hw_model, boot_hw_ver */ ··· 143 {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, 144 {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, 145 {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, 146 - { {0}, 0}, 147 }; 148 149 /* board_id */ ··· 165 {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, 166 {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, 167 {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"}, 168 - { {0}, 0}, 169 }; 170 171 /* boardtype, boardnum, boardrev */ ··· 174 {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, 175 {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, 176 {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, 177 - { {0}, 0}, 178 }; 179 180 static const
··· 36 struct bcm47xx_board_type_list1 bcm47xx_board_list_model_name[] __initconst = { 37 {{BCM47XX_BOARD_DLINK_DIR130, "D-Link DIR-130"}, "DIR-130"}, 38 {{BCM47XX_BOARD_DLINK_DIR330, "D-Link DIR-330"}, "DIR-330"}, 39 + { {0}, NULL}, 40 }; 41 42 /* model_no */ 43 static const 44 struct bcm47xx_board_type_list1 bcm47xx_board_list_model_no[] __initconst = { 45 {{BCM47XX_BOARD_ASUS_WL700GE, "Asus WL700"}, "WL700"}, 46 + { {0}, NULL}, 47 }; 48 49 /* machine_name */ 50 static const 51 struct bcm47xx_board_type_list1 bcm47xx_board_list_machine_name[] __initconst = { 52 {{BCM47XX_BOARD_LINKSYS_WRTSL54GS, "Linksys WRTSL54GS"}, "WRTSL54GS"}, 53 + { {0}, NULL}, 54 }; 55 56 /* hardware_version */ 57 static const 58 struct bcm47xx_board_type_list1 bcm47xx_board_list_hardware_version[] __initconst = { 59 + {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RTN10U"}, 60 + {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"}, 61 + {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RTN12B1"}, 62 + {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RTN12C1"}, 63 + {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RTN12D1"}, 64 + {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RTN12HP"}, 65 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"}, 66 {{BCM47XX_BOARD_ASUS_WL320GE, "Asus WL320GE"}, "WL320G-"}, 67 {{BCM47XX_BOARD_ASUS_WL330GE, "Asus WL330GE"}, "WL330GE-"}, ··· 66 {{BCM47XX_BOARD_ASUS_WL520GC, "Asus WL520GC"}, "WL520GC-"}, 67 {{BCM47XX_BOARD_ASUS_WL520GU, "Asus WL520GU"}, "WL520GU-"}, 68 {{BCM47XX_BOARD_BELKIN_F7D4301, "Belkin F7D4301"}, "F7D4301"}, 69 + { {0}, NULL}, 70 }; 71 72 /* productid */ ··· 75 {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"}, 76 {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"}, 77 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"}, 78 {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"}, 79 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"}, 80 {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"}, 81 {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"}, 82 {{BCM47XX_BOARD_ASUS_WL300G, "Asus WL300G"}, "WL300g"}, 83 {{BCM47XX_BOARD_ASUS_WLHDD, "Asus WLHDD"}, "WLHDD"}, 84 + { {0}, NULL}, 85 }; 86 87 /* ModelId */ ··· 97 {{BCM47XX_BOARD_MOTOROLA_WE800G, "Motorola WE800G"}, "WE800G"}, 98 {{BCM47XX_BOARD_MOTOROLA_WR850GP, "Motorola WR850GP"}, "WR850GP"}, 99 {{BCM47XX_BOARD_MOTOROLA_WR850GV2V3, "Motorola WR850G"}, "WR850G"}, 100 + { {0}, NULL}, 101 }; 102 103 /* melco_id or buf1falo_id */ ··· 112 {{BCM47XX_BOARD_BUFFALO_WZR_G300N, "Buffalo WZR-G300N"}, "31120"}, 113 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54, "Buffalo WZR-RS-G54"}, "30083"}, 114 {{BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP, "Buffalo WZR-RS-G54HP"}, "30103"}, 115 + { {0}, NULL}, 116 }; 117 118 /* boot_hw_model, boot_hw_ver */ ··· 143 {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"}, 144 {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"}, 145 {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"}, 146 + { {0}, NULL}, 147 }; 148 149 /* board_id */ ··· 165 {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"}, 166 {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"}, 167 {{BCM47XX_BOARD_NETGEAR_WNR834BV2, "Netgear WNR834B V2"}, "U12H081T00_NETGEAR"}, 168 + { {0}, NULL}, 169 }; 170 171 /* boardtype, boardnum, boardrev */ ··· 174 {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"}, 175 {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"}, 176 {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"}, 177 + {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"}, 178 + {{BCM47XX_BOARD_LINKSYS_WRT54GSV1, "Linksys WRT54GS V1"}, "0x0101", "42", "0x10"}, 179 + { {0}, NULL}, 180 }; 181 182 static const
+531
arch/mips/bcm47xx/buttons.c
···
··· 1 + #include "bcm47xx_private.h" 2 + 3 + #include <linux/input.h> 4 + #include <linux/gpio_keys.h> 5 + #include <linux/interrupt.h> 6 + #include <bcm47xx_board.h> 7 + #include <bcm47xx.h> 8 + 9 + /************************************************** 10 + * Database 11 + **************************************************/ 12 + 13 + #define BCM47XX_GPIO_KEY(_gpio, _code) \ 14 + { \ 15 + .code = _code, \ 16 + .gpio = _gpio, \ 17 + .active_low = 1, \ 18 + } 19 + 20 + /* Asus */ 21 + 22 + static const struct gpio_keys_button 23 + bcm47xx_buttons_asus_rtn12[] __initconst = { 24 + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), 25 + BCM47XX_GPIO_KEY(1, KEY_RESTART), 26 + BCM47XX_GPIO_KEY(4, BTN_0), /* Router mode */ 27 + BCM47XX_GPIO_KEY(5, BTN_1), /* Repeater mode */ 28 + BCM47XX_GPIO_KEY(6, BTN_2), /* AP mode */ 29 + }; 30 + 31 + static const struct gpio_keys_button 32 + bcm47xx_buttons_asus_rtn16[] __initconst = { 33 + BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), 34 + BCM47XX_GPIO_KEY(8, KEY_RESTART), 35 + }; 36 + 37 + static const struct gpio_keys_button 38 + bcm47xx_buttons_asus_rtn66u[] __initconst = { 39 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 40 + BCM47XX_GPIO_KEY(9, KEY_RESTART), 41 + }; 42 + 43 + static const struct gpio_keys_button 44 + bcm47xx_buttons_asus_wl300g[] __initconst = { 45 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 46 + }; 47 + 48 + static const struct gpio_keys_button 49 + bcm47xx_buttons_asus_wl320ge[] __initconst = { 50 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 51 + }; 52 + 53 + static const struct gpio_keys_button 54 + bcm47xx_buttons_asus_wl330ge[] __initconst = { 55 + BCM47XX_GPIO_KEY(2, KEY_RESTART), 56 + }; 57 + 58 + static const struct gpio_keys_button 59 + bcm47xx_buttons_asus_wl500gd[] __initconst = { 60 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 61 + }; 62 + 63 + static const struct gpio_keys_button 64 + bcm47xx_buttons_asus_wl500gpv1[] __initconst = { 65 + BCM47XX_GPIO_KEY(0, KEY_RESTART), 66 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 67 + }; 68 + 69 + static const struct gpio_keys_button 70 + bcm47xx_buttons_asus_wl500gpv2[] __initconst = { 71 + BCM47XX_GPIO_KEY(2, KEY_RESTART), 72 + BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON), 73 + }; 74 + 75 + static const struct gpio_keys_button 76 + bcm47xx_buttons_asus_wl500w[] __initconst = { 77 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 78 + BCM47XX_GPIO_KEY(7, KEY_WPS_BUTTON), 79 + }; 80 + 81 + static const struct gpio_keys_button 82 + bcm47xx_buttons_asus_wl520gc[] __initconst = { 83 + BCM47XX_GPIO_KEY(2, KEY_RESTART), 84 + BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON), 85 + }; 86 + 87 + static const struct gpio_keys_button 88 + bcm47xx_buttons_asus_wl520gu[] __initconst = { 89 + BCM47XX_GPIO_KEY(2, KEY_RESTART), 90 + BCM47XX_GPIO_KEY(3, KEY_WPS_BUTTON), 91 + }; 92 + 93 + static const struct gpio_keys_button 94 + bcm47xx_buttons_asus_wl700ge[] __initconst = { 95 + BCM47XX_GPIO_KEY(0, KEY_POWER), /* Hard disk power switch */ 96 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), /* EZSetup */ 97 + BCM47XX_GPIO_KEY(6, KEY_COPY), /* Copy data from USB to internal disk */ 98 + BCM47XX_GPIO_KEY(7, KEY_RESTART), /* Hard reset */ 99 + }; 100 + 101 + static const struct gpio_keys_button 102 + bcm47xx_buttons_asus_wlhdd[] __initconst = { 103 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 104 + }; 105 + 106 + /* Huawei */ 107 + 108 + static const struct gpio_keys_button 109 + bcm47xx_buttons_huawei_e970[] __initconst = { 110 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 111 + }; 112 + 113 + /* Belkin */ 114 + 115 + static const struct gpio_keys_button 116 + bcm47xx_buttons_belkin_f7d4301[] __initconst = { 117 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 118 + BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON), 119 + }; 120 + 121 + /* Buffalo */ 122 + 123 + static const struct gpio_keys_button 124 + bcm47xx_buttons_buffalo_whr2_a54g54[] __initconst = { 125 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 126 + }; 127 + 128 + static const struct gpio_keys_button 129 + bcm47xx_buttons_buffalo_whr_g125[] __initconst = { 130 + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), 131 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 132 + BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */ 133 + }; 134 + 135 + static const struct gpio_keys_button 136 + bcm47xx_buttons_buffalo_whr_g54s[] __initconst = { 137 + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), 138 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 139 + BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */ 140 + }; 141 + 142 + static const struct gpio_keys_button 143 + bcm47xx_buttons_buffalo_whr_hp_g54[] __initconst = { 144 + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), 145 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 146 + BCM47XX_GPIO_KEY(5, BTN_0), /* Router / AP mode swtich */ 147 + }; 148 + 149 + static const struct gpio_keys_button 150 + bcm47xx_buttons_buffalo_wzr_g300n[] __initconst = { 151 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 152 + }; 153 + 154 + static const struct gpio_keys_button 155 + bcm47xx_buttons_buffalo_wzr_rs_g54[] __initconst = { 156 + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), 157 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 158 + }; 159 + 160 + static const struct gpio_keys_button 161 + bcm47xx_buttons_buffalo_wzr_rs_g54hp[] __initconst = { 162 + BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON), 163 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 164 + }; 165 + 166 + /* Dell */ 167 + 168 + static const struct gpio_keys_button 169 + bcm47xx_buttons_dell_tm2300[] __initconst = { 170 + BCM47XX_GPIO_KEY(0, KEY_RESTART), 171 + }; 172 + 173 + /* D-Link */ 174 + 175 + static const struct gpio_keys_button 176 + bcm47xx_buttons_dlink_dir130[] __initconst = { 177 + BCM47XX_GPIO_KEY(3, KEY_RESTART), 178 + BCM47XX_GPIO_KEY(7, KEY_UNKNOWN), 179 + }; 180 + 181 + static const struct gpio_keys_button 182 + bcm47xx_buttons_dlink_dir330[] __initconst = { 183 + BCM47XX_GPIO_KEY(3, KEY_RESTART), 184 + BCM47XX_GPIO_KEY(7, KEY_UNKNOWN), 185 + }; 186 + 187 + /* Linksys */ 188 + 189 + static const struct gpio_keys_button 190 + bcm47xx_buttons_linksys_e1000v1[] __initconst = { 191 + BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), 192 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 193 + }; 194 + 195 + static const struct gpio_keys_button 196 + bcm47xx_buttons_linksys_e1000v21[] __initconst = { 197 + BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON), 198 + BCM47XX_GPIO_KEY(10, KEY_RESTART), 199 + }; 200 + 201 + static const struct gpio_keys_button 202 + bcm47xx_buttons_linksys_e2000v1[] __initconst = { 203 + BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), 204 + BCM47XX_GPIO_KEY(8, KEY_RESTART), 205 + }; 206 + 207 + static const struct gpio_keys_button 208 + bcm47xx_buttons_linksys_e3000v1[] __initconst = { 209 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 210 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 211 + }; 212 + 213 + static const struct gpio_keys_button 214 + bcm47xx_buttons_linksys_e3200v1[] __initconst = { 215 + BCM47XX_GPIO_KEY(5, KEY_RESTART), 216 + BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON), 217 + }; 218 + 219 + static const struct gpio_keys_button 220 + bcm47xx_buttons_linksys_e4200v1[] __initconst = { 221 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 222 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 223 + }; 224 + 225 + static const struct gpio_keys_button 226 + bcm47xx_buttons_linksys_wrt150nv1[] __initconst = { 227 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 228 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 229 + }; 230 + 231 + static const struct gpio_keys_button 232 + bcm47xx_buttons_linksys_wrt150nv11[] __initconst = { 233 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 234 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 235 + }; 236 + 237 + static const struct gpio_keys_button 238 + bcm47xx_buttons_linksys_wrt160nv1[] __initconst = { 239 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 240 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 241 + }; 242 + 243 + static const struct gpio_keys_button 244 + bcm47xx_buttons_linksys_wrt160nv3[] __initconst = { 245 + BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON), 246 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 247 + }; 248 + 249 + static const struct gpio_keys_button 250 + bcm47xx_buttons_linksys_wrt300nv11[] __initconst = { 251 + BCM47XX_GPIO_KEY(4, KEY_UNKNOWN), 252 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 253 + }; 254 + 255 + static const struct gpio_keys_button 256 + bcm47xx_buttons_linksys_wrt310nv1[] __initconst = { 257 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 258 + BCM47XX_GPIO_KEY(8, KEY_UNKNOWN), 259 + }; 260 + 261 + static const struct gpio_keys_button 262 + bcm47xx_buttons_linksys_wrt610nv1[] __initconst = { 263 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 264 + BCM47XX_GPIO_KEY(8, KEY_WPS_BUTTON), 265 + }; 266 + 267 + static const struct gpio_keys_button 268 + bcm47xx_buttons_linksys_wrt610nv2[] __initconst = { 269 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 270 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 271 + }; 272 + 273 + /* Motorola */ 274 + 275 + static const struct gpio_keys_button 276 + bcm47xx_buttons_motorola_we800g[] __initconst = { 277 + BCM47XX_GPIO_KEY(0, KEY_RESTART), 278 + }; 279 + 280 + static const struct gpio_keys_button 281 + bcm47xx_buttons_motorola_wr850gp[] __initconst = { 282 + BCM47XX_GPIO_KEY(5, KEY_RESTART), 283 + }; 284 + 285 + static const struct gpio_keys_button 286 + bcm47xx_buttons_motorola_wr850gv2v3[] __initconst = { 287 + BCM47XX_GPIO_KEY(5, KEY_RESTART), 288 + }; 289 + 290 + /* Netgear */ 291 + 292 + static const struct gpio_keys_button 293 + bcm47xx_buttons_netgear_wndr3400v1[] __initconst = { 294 + BCM47XX_GPIO_KEY(4, KEY_RESTART), 295 + BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON), 296 + BCM47XX_GPIO_KEY(8, KEY_RFKILL), 297 + }; 298 + 299 + static const struct gpio_keys_button 300 + bcm47xx_buttons_netgear_wndr3700v3[] __initconst = { 301 + BCM47XX_GPIO_KEY(2, KEY_RFKILL), 302 + BCM47XX_GPIO_KEY(3, KEY_RESTART), 303 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 304 + }; 305 + 306 + static const struct gpio_keys_button 307 + bcm47xx_buttons_netgear_wndr4500v1[] __initconst = { 308 + BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON), 309 + BCM47XX_GPIO_KEY(5, KEY_RFKILL), 310 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 311 + }; 312 + 313 + static const struct gpio_keys_button 314 + bcm47xx_buttons_netgear_wnr834bv2[] __initconst = { 315 + BCM47XX_GPIO_KEY(6, KEY_RESTART), 316 + }; 317 + 318 + /* SimpleTech */ 319 + 320 + static const struct gpio_keys_button 321 + bcm47xx_buttons_simpletech_simpleshare[] __initconst = { 322 + BCM47XX_GPIO_KEY(0, KEY_RESTART), 323 + }; 324 + 325 + /************************************************** 326 + * Init 327 + **************************************************/ 328 + 329 + static struct gpio_keys_platform_data bcm47xx_button_pdata; 330 + 331 + static struct platform_device bcm47xx_buttons_gpio_keys = { 332 + .name = "gpio-keys", 333 + .dev = { 334 + .platform_data = &bcm47xx_button_pdata, 335 + } 336 + }; 337 + 338 + /* Copy data from __initconst */ 339 + static int __init bcm47xx_buttons_copy(const struct gpio_keys_button *buttons, 340 + size_t nbuttons) 341 + { 342 + size_t size = nbuttons * sizeof(*buttons); 343 + 344 + bcm47xx_button_pdata.buttons = kmalloc(size, GFP_KERNEL); 345 + if (!bcm47xx_button_pdata.buttons) 346 + return -ENOMEM; 347 + memcpy(bcm47xx_button_pdata.buttons, buttons, size); 348 + bcm47xx_button_pdata.nbuttons = nbuttons; 349 + 350 + return 0; 351 + } 352 + 353 + #define bcm47xx_copy_bdata(dev_buttons) \ 354 + bcm47xx_buttons_copy(dev_buttons, ARRAY_SIZE(dev_buttons)); 355 + 356 + int __init bcm47xx_buttons_register(void) 357 + { 358 + enum bcm47xx_board board = bcm47xx_board_get(); 359 + int err; 360 + 361 + switch (board) { 362 + case BCM47XX_BOARD_ASUS_RTN12: 363 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12); 364 + break; 365 + case BCM47XX_BOARD_ASUS_RTN16: 366 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn16); 367 + break; 368 + case BCM47XX_BOARD_ASUS_RTN66U: 369 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn66u); 370 + break; 371 + case BCM47XX_BOARD_ASUS_WL300G: 372 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl300g); 373 + break; 374 + case BCM47XX_BOARD_ASUS_WL320GE: 375 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl320ge); 376 + break; 377 + case BCM47XX_BOARD_ASUS_WL330GE: 378 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl330ge); 379 + break; 380 + case BCM47XX_BOARD_ASUS_WL500GD: 381 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gd); 382 + break; 383 + case BCM47XX_BOARD_ASUS_WL500GPV1: 384 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gpv1); 385 + break; 386 + case BCM47XX_BOARD_ASUS_WL500GPV2: 387 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500gpv2); 388 + break; 389 + case BCM47XX_BOARD_ASUS_WL500W: 390 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl500w); 391 + break; 392 + case BCM47XX_BOARD_ASUS_WL520GC: 393 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl520gc); 394 + break; 395 + case BCM47XX_BOARD_ASUS_WL520GU: 396 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl520gu); 397 + break; 398 + case BCM47XX_BOARD_ASUS_WL700GE: 399 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wl700ge); 400 + break; 401 + case BCM47XX_BOARD_ASUS_WLHDD: 402 + err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_wlhdd); 403 + break; 404 + 405 + case BCM47XX_BOARD_BELKIN_F7D4301: 406 + err = bcm47xx_copy_bdata(bcm47xx_buttons_belkin_f7d4301); 407 + break; 408 + 409 + case BCM47XX_BOARD_BUFFALO_WHR2_A54G54: 410 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr2_a54g54); 411 + break; 412 + case BCM47XX_BOARD_BUFFALO_WHR_G125: 413 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_g125); 414 + break; 415 + case BCM47XX_BOARD_BUFFALO_WHR_G54S: 416 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_g54s); 417 + break; 418 + case BCM47XX_BOARD_BUFFALO_WHR_HP_G54: 419 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_whr_hp_g54); 420 + break; 421 + case BCM47XX_BOARD_BUFFALO_WZR_G300N: 422 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_g300n); 423 + break; 424 + case BCM47XX_BOARD_BUFFALO_WZR_RS_G54: 425 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_rs_g54); 426 + break; 427 + case BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP: 428 + err = bcm47xx_copy_bdata(bcm47xx_buttons_buffalo_wzr_rs_g54hp); 429 + break; 430 + 431 + case BCM47XX_BOARD_DELL_TM2300: 432 + err = bcm47xx_copy_bdata(bcm47xx_buttons_dell_tm2300); 433 + break; 434 + 435 + case BCM47XX_BOARD_DLINK_DIR130: 436 + err = bcm47xx_copy_bdata(bcm47xx_buttons_dlink_dir130); 437 + break; 438 + case BCM47XX_BOARD_DLINK_DIR330: 439 + err = bcm47xx_copy_bdata(bcm47xx_buttons_dlink_dir330); 440 + break; 441 + 442 + case BCM47XX_BOARD_HUAWEI_E970: 443 + err = bcm47xx_copy_bdata(bcm47xx_buttons_huawei_e970); 444 + break; 445 + 446 + case BCM47XX_BOARD_LINKSYS_E1000V1: 447 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e1000v1); 448 + break; 449 + case BCM47XX_BOARD_LINKSYS_E1000V21: 450 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e1000v21); 451 + break; 452 + case BCM47XX_BOARD_LINKSYS_E2000V1: 453 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1); 454 + break; 455 + case BCM47XX_BOARD_LINKSYS_E3000V1: 456 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1); 457 + break; 458 + case BCM47XX_BOARD_LINKSYS_E3200V1: 459 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3200v1); 460 + break; 461 + case BCM47XX_BOARD_LINKSYS_E4200V1: 462 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e4200v1); 463 + break; 464 + case BCM47XX_BOARD_LINKSYS_WRT150NV1: 465 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt150nv1); 466 + break; 467 + case BCM47XX_BOARD_LINKSYS_WRT150NV11: 468 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt150nv11); 469 + break; 470 + case BCM47XX_BOARD_LINKSYS_WRT160NV1: 471 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv1); 472 + break; 473 + case BCM47XX_BOARD_LINKSYS_WRT160NV3: 474 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt160nv3); 475 + break; 476 + case BCM47XX_BOARD_LINKSYS_WRT300NV11: 477 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt300nv11); 478 + break; 479 + case BCM47XX_BOARD_LINKSYS_WRT310NV1: 480 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1); 481 + break; 482 + case BCM47XX_BOARD_LINKSYS_WRT610NV1: 483 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv1); 484 + break; 485 + case BCM47XX_BOARD_LINKSYS_WRT610NV2: 486 + err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt610nv2); 487 + break; 488 + 489 + case BCM47XX_BOARD_MOTOROLA_WE800G: 490 + err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_we800g); 491 + break; 492 + case BCM47XX_BOARD_MOTOROLA_WR850GP: 493 + err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gp); 494 + break; 495 + case BCM47XX_BOARD_MOTOROLA_WR850GV2V3: 496 + err = bcm47xx_copy_bdata(bcm47xx_buttons_motorola_wr850gv2v3); 497 + break; 498 + 499 + case BCM47XX_BOARD_NETGEAR_WNDR3400V1: 500 + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1); 501 + break; 502 + case BCM47XX_BOARD_NETGEAR_WNDR3700V3: 503 + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3700v3); 504 + break; 505 + case BCM47XX_BOARD_NETGEAR_WNDR4500V1: 506 + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr4500v1); 507 + break; 508 + case BCM47XX_BOARD_NETGEAR_WNR834BV2: 509 + err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2); 510 + break; 511 + 512 + case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE: 513 + err = bcm47xx_copy_bdata(bcm47xx_buttons_simpletech_simpleshare); 514 + break; 515 + 516 + default: 517 + pr_debug("No buttons configuration found for this device\n"); 518 + return -ENOTSUPP; 519 + } 520 + 521 + if (err) 522 + return -ENOMEM; 523 + 524 + err = platform_device_register(&bcm47xx_buttons_gpio_keys); 525 + if (err) { 526 + pr_err("Failed to register platform device: %d\n", err); 527 + return err; 528 + } 529 + 530 + return 0; 531 + }
+24 -1
arch/mips/bcm47xx/irq.c
··· 25 #include <linux/types.h> 26 #include <linux/interrupt.h> 27 #include <linux/irq.h> 28 #include <asm/irq_cpu.h> 29 #include <bcm47xx.h> 30 31 - void plat_irq_dispatch(void) 32 { 33 u32 cause; 34 ··· 51 do_IRQ(6); 52 } 53 54 void __init arch_init_irq(void) 55 { 56 #ifdef CONFIG_BCM47XX_BCMA ··· 77 } 78 #endif 79 mips_cpu_irq_init(); 80 }
··· 25 #include <linux/types.h> 26 #include <linux/interrupt.h> 27 #include <linux/irq.h> 28 + #include <asm/setup.h> 29 #include <asm/irq_cpu.h> 30 #include <bcm47xx.h> 31 32 + asmlinkage void plat_irq_dispatch(void) 33 { 34 u32 cause; 35 ··· 50 do_IRQ(6); 51 } 52 53 + #define DEFINE_HWx_IRQDISPATCH(x) \ 54 + static void bcm47xx_hw ## x ## _irqdispatch(void) \ 55 + { \ 56 + do_IRQ(x); \ 57 + } 58 + DEFINE_HWx_IRQDISPATCH(2) 59 + DEFINE_HWx_IRQDISPATCH(3) 60 + DEFINE_HWx_IRQDISPATCH(4) 61 + DEFINE_HWx_IRQDISPATCH(5) 62 + DEFINE_HWx_IRQDISPATCH(6) 63 + DEFINE_HWx_IRQDISPATCH(7) 64 + 65 void __init arch_init_irq(void) 66 { 67 #ifdef CONFIG_BCM47XX_BCMA ··· 64 } 65 #endif 66 mips_cpu_irq_init(); 67 + 68 + if (cpu_has_vint) { 69 + pr_info("Setting up vectored interrupts\n"); 70 + set_vi_handler(2, bcm47xx_hw2_irqdispatch); 71 + set_vi_handler(3, bcm47xx_hw3_irqdispatch); 72 + set_vi_handler(4, bcm47xx_hw4_irqdispatch); 73 + set_vi_handler(5, bcm47xx_hw5_irqdispatch); 74 + set_vi_handler(6, bcm47xx_hw6_irqdispatch); 75 + set_vi_handler(7, bcm47xx_hw7_irqdispatch); 76 + } 77 }
+542
arch/mips/bcm47xx/leds.c
···
··· 1 + #include "bcm47xx_private.h" 2 + 3 + #include <linux/leds.h> 4 + #include <bcm47xx_board.h> 5 + 6 + /************************************************** 7 + * Database 8 + **************************************************/ 9 + 10 + #define BCM47XX_GPIO_LED(_gpio, _color, _function, _active_low, \ 11 + _default_state) \ 12 + { \ 13 + .name = "bcm47xx:" _color ":" _function, \ 14 + .gpio = _gpio, \ 15 + .active_low = _active_low, \ 16 + .default_state = _default_state, \ 17 + } 18 + 19 + #define BCM47XX_GPIO_LED_TRIGGER(_gpio, _color, _function, _active_low, \ 20 + _default_trigger) \ 21 + { \ 22 + .name = "bcm47xx:" _color ":" _function, \ 23 + .gpio = _gpio, \ 24 + .active_low = _active_low, \ 25 + .default_state = LEDS_GPIO_DEFSTATE_OFF, \ 26 + .default_trigger = _default_trigger, \ 27 + } 28 + 29 + /* Asus */ 30 + 31 + static const struct gpio_led 32 + bcm47xx_leds_asus_rtn12[] __initconst = { 33 + BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 34 + BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 35 + }; 36 + 37 + static const struct gpio_led 38 + bcm47xx_leds_asus_rtn16[] __initconst = { 39 + BCM47XX_GPIO_LED(1, "blue", "power", 1, LEDS_GPIO_DEFSTATE_ON), 40 + BCM47XX_GPIO_LED(7, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 41 + }; 42 + 43 + static const struct gpio_led 44 + bcm47xx_leds_asus_rtn66u[] __initconst = { 45 + BCM47XX_GPIO_LED(12, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 46 + BCM47XX_GPIO_LED(15, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF), 47 + }; 48 + 49 + static const struct gpio_led 50 + bcm47xx_leds_asus_wl300g[] __initconst = { 51 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 52 + }; 53 + 54 + static const struct gpio_led 55 + bcm47xx_leds_asus_wl320ge[] __initconst = { 56 + BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 57 + BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 58 + BCM47XX_GPIO_LED(11, "unk", "link", 1, LEDS_GPIO_DEFSTATE_OFF), 59 + }; 60 + 61 + static const struct gpio_led 62 + bcm47xx_leds_asus_wl330ge[] __initconst = { 63 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 64 + }; 65 + 66 + static const struct gpio_led 67 + bcm47xx_leds_asus_wl500gd[] __initconst = { 68 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 69 + }; 70 + 71 + static const struct gpio_led 72 + bcm47xx_leds_asus_wl500gpv1[] __initconst = { 73 + BCM47XX_GPIO_LED(1, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 74 + }; 75 + 76 + static const struct gpio_led 77 + bcm47xx_leds_asus_wl500gpv2[] __initconst = { 78 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 79 + BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 80 + }; 81 + 82 + static const struct gpio_led 83 + bcm47xx_leds_asus_wl500w[] __initconst = { 84 + BCM47XX_GPIO_LED(5, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 85 + }; 86 + 87 + static const struct gpio_led 88 + bcm47xx_leds_asus_wl520gc[] __initconst = { 89 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 90 + BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 91 + }; 92 + 93 + static const struct gpio_led 94 + bcm47xx_leds_asus_wl520gu[] __initconst = { 95 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 96 + BCM47XX_GPIO_LED(1, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 97 + }; 98 + 99 + static const struct gpio_led 100 + bcm47xx_leds_asus_wl700ge[] __initconst = { 101 + BCM47XX_GPIO_LED(1, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), /* Labeled "READY" (there is no "power" LED). Originally ON, flashing on USB activity. */ 102 + }; 103 + 104 + static const struct gpio_led 105 + bcm47xx_leds_asus_wlhdd[] __initconst = { 106 + BCM47XX_GPIO_LED(0, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 107 + BCM47XX_GPIO_LED(2, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF), 108 + }; 109 + 110 + /* Belkin */ 111 + 112 + static const struct gpio_led 113 + bcm47xx_leds_belkin_f7d4301[] __initconst = { 114 + BCM47XX_GPIO_LED(10, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), 115 + BCM47XX_GPIO_LED(11, "amber", "power", 1, LEDS_GPIO_DEFSTATE_OFF), 116 + BCM47XX_GPIO_LED(12, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 117 + BCM47XX_GPIO_LED(13, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 118 + BCM47XX_GPIO_LED(14, "unk", "usb0", 1, LEDS_GPIO_DEFSTATE_OFF), 119 + BCM47XX_GPIO_LED(15, "unk", "usb1", 1, LEDS_GPIO_DEFSTATE_OFF), 120 + }; 121 + 122 + /* Buffalo */ 123 + 124 + static const struct gpio_led 125 + bcm47xx_leds_buffalo_whr2_a54g54[] __initconst = { 126 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 127 + }; 128 + 129 + static const struct gpio_led 130 + bcm47xx_leds_buffalo_whr_g125[] __initconst = { 131 + BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF), 132 + BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 133 + BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF), 134 + BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 135 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 136 + }; 137 + 138 + static const struct gpio_led 139 + bcm47xx_leds_buffalo_whr_g54s[] __initconst = { 140 + BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF), 141 + BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 142 + BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF), 143 + BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 144 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 145 + }; 146 + 147 + static const struct gpio_led 148 + bcm47xx_leds_buffalo_whr_hp_g54[] __initconst = { 149 + BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF), 150 + BCM47XX_GPIO_LED(2, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 151 + BCM47XX_GPIO_LED(3, "unk", "internal", 1, LEDS_GPIO_DEFSTATE_OFF), 152 + BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 153 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 154 + }; 155 + 156 + static const struct gpio_led 157 + bcm47xx_leds_buffalo_wzr_g300n[] __initconst = { 158 + BCM47XX_GPIO_LED(1, "unk", "bridge", 1, LEDS_GPIO_DEFSTATE_OFF), 159 + BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 160 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 161 + }; 162 + 163 + static const struct gpio_led 164 + bcm47xx_leds_buffalo_wzr_rs_g54[] __initconst = { 165 + BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 166 + BCM47XX_GPIO_LED(1, "unk", "vpn", 1, LEDS_GPIO_DEFSTATE_OFF), 167 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 168 + }; 169 + 170 + static const struct gpio_led 171 + bcm47xx_leds_buffalo_wzr_rs_g54hp[] __initconst = { 172 + BCM47XX_GPIO_LED(6, "unk", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 173 + BCM47XX_GPIO_LED(1, "unk", "vpn", 1, LEDS_GPIO_DEFSTATE_OFF), 174 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 175 + }; 176 + 177 + /* Dell */ 178 + 179 + static const struct gpio_led 180 + bcm47xx_leds_dell_tm2300[] __initconst = { 181 + BCM47XX_GPIO_LED(6, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 182 + BCM47XX_GPIO_LED(7, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 183 + }; 184 + 185 + /* D-Link */ 186 + 187 + static const struct gpio_led 188 + bcm47xx_leds_dlink_dir130[] __initconst = { 189 + BCM47XX_GPIO_LED_TRIGGER(0, "green", "status", 1, "timer"), /* Originally blinking when device is ready, separated from "power" LED */ 190 + BCM47XX_GPIO_LED(6, "blue", "unk", 1, LEDS_GPIO_DEFSTATE_OFF), 191 + }; 192 + 193 + static const struct gpio_led 194 + bcm47xx_leds_dlink_dir330[] __initconst = { 195 + BCM47XX_GPIO_LED_TRIGGER(0, "green", "status", 1, "timer"), /* Originally blinking when device is ready, separated from "power" LED */ 196 + BCM47XX_GPIO_LED(4, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF), 197 + BCM47XX_GPIO_LED(6, "blue", "unk", 1, LEDS_GPIO_DEFSTATE_OFF), 198 + }; 199 + 200 + /* Huawei */ 201 + 202 + static const struct gpio_led 203 + bcm47xx_leds_huawei_e970[] __initconst = { 204 + BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 205 + }; 206 + 207 + /* Linksys */ 208 + 209 + static const struct gpio_led 210 + bcm47xx_leds_linksys_e1000v1[] __initconst = { 211 + BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 212 + BCM47XX_GPIO_LED(1, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), 213 + BCM47XX_GPIO_LED(2, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 214 + BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 215 + }; 216 + 217 + static const struct gpio_led 218 + bcm47xx_leds_linksys_e1000v21[] __initconst = { 219 + BCM47XX_GPIO_LED(5, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 220 + BCM47XX_GPIO_LED(6, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON), 221 + BCM47XX_GPIO_LED(7, "amber", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), 222 + BCM47XX_GPIO_LED(8, "blue", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), 223 + }; 224 + 225 + static const struct gpio_led 226 + bcm47xx_leds_linksys_e2000v1[] __initconst = { 227 + BCM47XX_GPIO_LED(1, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 228 + BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), 229 + BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 230 + BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 231 + }; 232 + 233 + static const struct gpio_led 234 + bcm47xx_leds_linksys_e3000v1[] __initconst = { 235 + BCM47XX_GPIO_LED(0, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 236 + BCM47XX_GPIO_LED(1, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 237 + BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 238 + BCM47XX_GPIO_LED(5, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 239 + BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), 240 + }; 241 + 242 + static const struct gpio_led 243 + bcm47xx_leds_linksys_e3200v1[] __initconst = { 244 + BCM47XX_GPIO_LED(3, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), 245 + }; 246 + 247 + static const struct gpio_led 248 + bcm47xx_leds_linksys_e4200v1[] __initconst = { 249 + BCM47XX_GPIO_LED(5, "white", "power", 1, LEDS_GPIO_DEFSTATE_ON), 250 + }; 251 + 252 + static const struct gpio_led 253 + bcm47xx_leds_linksys_wrt150nv1[] __initconst = { 254 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 255 + BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 256 + BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 257 + }; 258 + 259 + static const struct gpio_led 260 + bcm47xx_leds_linksys_wrt150nv11[] __initconst = { 261 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 262 + BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 263 + BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 264 + }; 265 + 266 + static const struct gpio_led 267 + bcm47xx_leds_linksys_wrt160nv1[] __initconst = { 268 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 269 + BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 270 + BCM47XX_GPIO_LED(5, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 271 + }; 272 + 273 + static const struct gpio_led 274 + bcm47xx_leds_linksys_wrt160nv3[] __initconst = { 275 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 276 + BCM47XX_GPIO_LED(2, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 277 + BCM47XX_GPIO_LED(4, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 278 + }; 279 + 280 + static const struct gpio_led 281 + bcm47xx_leds_linksys_wrt300nv11[] __initconst = { 282 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 283 + BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 284 + BCM47XX_GPIO_LED(5, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 285 + }; 286 + 287 + static const struct gpio_led 288 + bcm47xx_leds_linksys_wrt310nv1[] __initconst = { 289 + BCM47XX_GPIO_LED(1, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON), 290 + BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 291 + BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 292 + }; 293 + 294 + static const struct gpio_led 295 + bcm47xx_leds_linksys_wrt610nv1[] __initconst = { 296 + BCM47XX_GPIO_LED(0, "unk", "usb", 1, LEDS_GPIO_DEFSTATE_OFF), 297 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_OFF), 298 + BCM47XX_GPIO_LED(3, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 299 + BCM47XX_GPIO_LED(9, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 300 + }; 301 + 302 + static const struct gpio_led 303 + bcm47xx_leds_linksys_wrt610nv2[] __initconst = { 304 + BCM47XX_GPIO_LED(0, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 305 + BCM47XX_GPIO_LED(1, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 306 + BCM47XX_GPIO_LED(3, "blue", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 307 + BCM47XX_GPIO_LED(5, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 308 + BCM47XX_GPIO_LED(7, "unk", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), 309 + }; 310 + 311 + /* Motorola */ 312 + 313 + static const struct gpio_led 314 + bcm47xx_leds_motorola_we800g[] __initconst = { 315 + BCM47XX_GPIO_LED(1, "amber", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF), 316 + BCM47XX_GPIO_LED(2, "unk", "unk", 1, LEDS_GPIO_DEFSTATE_OFF), /* There are only 3 LEDs: Power, Wireless and Device (ethernet) */ 317 + BCM47XX_GPIO_LED(4, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), 318 + }; 319 + 320 + static const struct gpio_led 321 + bcm47xx_leds_motorola_wr850gp[] __initconst = { 322 + BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 323 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 324 + BCM47XX_GPIO_LED(6, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF), 325 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 326 + }; 327 + 328 + static const struct gpio_led 329 + bcm47xx_leds_motorola_wr850gv2v3[] __initconst = { 330 + BCM47XX_GPIO_LED(0, "unk", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF), 331 + BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON), 332 + BCM47XX_GPIO_LED(7, "unk", "diag", 1, LEDS_GPIO_DEFSTATE_OFF), 333 + }; 334 + 335 + /* Netgear */ 336 + 337 + static const struct gpio_led 338 + bcm47xx_leds_netgear_wndr3400v1[] __initconst = { 339 + BCM47XX_GPIO_LED(2, "green", "usb", 1, LEDS_GPIO_DEFSTATE_OFF), 340 + BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), 341 + BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), 342 + }; 343 + 344 + static const struct gpio_led 345 + bcm47xx_leds_netgear_wndr4500v1[] __initconst = { 346 + BCM47XX_GPIO_LED(1, "green", "wps", 1, LEDS_GPIO_DEFSTATE_OFF), 347 + BCM47XX_GPIO_LED(2, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON), 348 + BCM47XX_GPIO_LED(3, "amber", "power", 1, LEDS_GPIO_DEFSTATE_OFF), 349 + BCM47XX_GPIO_LED(8, "green", "usb1", 1, LEDS_GPIO_DEFSTATE_OFF), 350 + BCM47XX_GPIO_LED(9, "green", "2ghz", 1, LEDS_GPIO_DEFSTATE_OFF), 351 + BCM47XX_GPIO_LED(11, "blue", "5ghz", 1, LEDS_GPIO_DEFSTATE_OFF), 352 + BCM47XX_GPIO_LED(14, "green", "usb2", 1, LEDS_GPIO_DEFSTATE_OFF), 353 + }; 354 + 355 + static const struct gpio_led 356 + bcm47xx_leds_netgear_wnr834bv2[] __initconst = { 357 + BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON), 358 + BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF), 359 + BCM47XX_GPIO_LED(7, "unk", "connected", 0, LEDS_GPIO_DEFSTATE_OFF), 360 + }; 361 + 362 + /* SimpleTech */ 363 + 364 + static const struct gpio_led 365 + bcm47xx_leds_simpletech_simpleshare[] __initconst = { 366 + BCM47XX_GPIO_LED(1, "unk", "status", 1, LEDS_GPIO_DEFSTATE_OFF), /* "Ready" LED */ 367 + }; 368 + 369 + /************************************************** 370 + * Init 371 + **************************************************/ 372 + 373 + static struct gpio_led_platform_data bcm47xx_leds_pdata; 374 + 375 + #define bcm47xx_set_pdata(dev_leds) do { \ 376 + bcm47xx_leds_pdata.leds = dev_leds; \ 377 + bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds); \ 378 + } while (0) 379 + 380 + void __init bcm47xx_leds_register(void) 381 + { 382 + enum bcm47xx_board board = bcm47xx_board_get(); 383 + 384 + switch (board) { 385 + case BCM47XX_BOARD_ASUS_RTN12: 386 + bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12); 387 + break; 388 + case BCM47XX_BOARD_ASUS_RTN16: 389 + bcm47xx_set_pdata(bcm47xx_leds_asus_rtn16); 390 + break; 391 + case BCM47XX_BOARD_ASUS_RTN66U: 392 + bcm47xx_set_pdata(bcm47xx_leds_asus_rtn66u); 393 + break; 394 + case BCM47XX_BOARD_ASUS_WL300G: 395 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl300g); 396 + break; 397 + case BCM47XX_BOARD_ASUS_WL320GE: 398 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl320ge); 399 + break; 400 + case BCM47XX_BOARD_ASUS_WL330GE: 401 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl330ge); 402 + break; 403 + case BCM47XX_BOARD_ASUS_WL500GD: 404 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gd); 405 + break; 406 + case BCM47XX_BOARD_ASUS_WL500GPV1: 407 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gpv1); 408 + break; 409 + case BCM47XX_BOARD_ASUS_WL500GPV2: 410 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl500gpv2); 411 + break; 412 + case BCM47XX_BOARD_ASUS_WL500W: 413 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl500w); 414 + break; 415 + case BCM47XX_BOARD_ASUS_WL520GC: 416 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl520gc); 417 + break; 418 + case BCM47XX_BOARD_ASUS_WL520GU: 419 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl520gu); 420 + break; 421 + case BCM47XX_BOARD_ASUS_WL700GE: 422 + bcm47xx_set_pdata(bcm47xx_leds_asus_wl700ge); 423 + break; 424 + case BCM47XX_BOARD_ASUS_WLHDD: 425 + bcm47xx_set_pdata(bcm47xx_leds_asus_wlhdd); 426 + break; 427 + 428 + case BCM47XX_BOARD_BELKIN_F7D4301: 429 + bcm47xx_set_pdata(bcm47xx_leds_belkin_f7d4301); 430 + break; 431 + 432 + case BCM47XX_BOARD_BUFFALO_WHR2_A54G54: 433 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr2_a54g54); 434 + break; 435 + case BCM47XX_BOARD_BUFFALO_WHR_G125: 436 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_g125); 437 + break; 438 + case BCM47XX_BOARD_BUFFALO_WHR_G54S: 439 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_g54s); 440 + break; 441 + case BCM47XX_BOARD_BUFFALO_WHR_HP_G54: 442 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_whr_hp_g54); 443 + break; 444 + case BCM47XX_BOARD_BUFFALO_WZR_G300N: 445 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_g300n); 446 + break; 447 + case BCM47XX_BOARD_BUFFALO_WZR_RS_G54: 448 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_rs_g54); 449 + break; 450 + case BCM47XX_BOARD_BUFFALO_WZR_RS_G54HP: 451 + bcm47xx_set_pdata(bcm47xx_leds_buffalo_wzr_rs_g54hp); 452 + break; 453 + 454 + case BCM47XX_BOARD_DELL_TM2300: 455 + bcm47xx_set_pdata(bcm47xx_leds_dell_tm2300); 456 + break; 457 + 458 + case BCM47XX_BOARD_DLINK_DIR130: 459 + bcm47xx_set_pdata(bcm47xx_leds_dlink_dir130); 460 + break; 461 + case BCM47XX_BOARD_DLINK_DIR330: 462 + bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330); 463 + break; 464 + 465 + case BCM47XX_BOARD_HUAWEI_E970: 466 + bcm47xx_set_pdata(bcm47xx_leds_huawei_e970); 467 + break; 468 + 469 + case BCM47XX_BOARD_LINKSYS_E1000V1: 470 + bcm47xx_set_pdata(bcm47xx_leds_linksys_e1000v1); 471 + break; 472 + case BCM47XX_BOARD_LINKSYS_E1000V21: 473 + bcm47xx_set_pdata(bcm47xx_leds_linksys_e1000v21); 474 + break; 475 + case BCM47XX_BOARD_LINKSYS_E2000V1: 476 + bcm47xx_set_pdata(bcm47xx_leds_linksys_e2000v1); 477 + break; 478 + case BCM47XX_BOARD_LINKSYS_E3000V1: 479 + bcm47xx_set_pdata(bcm47xx_leds_linksys_e3000v1); 480 + break; 481 + case BCM47XX_BOARD_LINKSYS_E3200V1: 482 + bcm47xx_set_pdata(bcm47xx_leds_linksys_e3200v1); 483 + break; 484 + case BCM47XX_BOARD_LINKSYS_E4200V1: 485 + bcm47xx_set_pdata(bcm47xx_leds_linksys_e4200v1); 486 + break; 487 + case BCM47XX_BOARD_LINKSYS_WRT150NV1: 488 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt150nv1); 489 + break; 490 + case BCM47XX_BOARD_LINKSYS_WRT150NV11: 491 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt150nv11); 492 + break; 493 + case BCM47XX_BOARD_LINKSYS_WRT160NV1: 494 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv1); 495 + break; 496 + case BCM47XX_BOARD_LINKSYS_WRT160NV3: 497 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt160nv3); 498 + break; 499 + case BCM47XX_BOARD_LINKSYS_WRT300NV11: 500 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt300nv11); 501 + break; 502 + case BCM47XX_BOARD_LINKSYS_WRT310NV1: 503 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1); 504 + break; 505 + case BCM47XX_BOARD_LINKSYS_WRT610NV1: 506 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv1); 507 + break; 508 + case BCM47XX_BOARD_LINKSYS_WRT610NV2: 509 + bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt610nv2); 510 + break; 511 + 512 + case BCM47XX_BOARD_MOTOROLA_WE800G: 513 + bcm47xx_set_pdata(bcm47xx_leds_motorola_we800g); 514 + break; 515 + case BCM47XX_BOARD_MOTOROLA_WR850GP: 516 + bcm47xx_set_pdata(bcm47xx_leds_motorola_wr850gp); 517 + break; 518 + case BCM47XX_BOARD_MOTOROLA_WR850GV2V3: 519 + bcm47xx_set_pdata(bcm47xx_leds_motorola_wr850gv2v3); 520 + break; 521 + 522 + case BCM47XX_BOARD_NETGEAR_WNDR3400V1: 523 + bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr3400v1); 524 + break; 525 + case BCM47XX_BOARD_NETGEAR_WNDR4500V1: 526 + bcm47xx_set_pdata(bcm47xx_leds_netgear_wndr4500v1); 527 + break; 528 + case BCM47XX_BOARD_NETGEAR_WNR834BV2: 529 + bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2); 530 + break; 531 + 532 + case BCM47XX_BOARD_SIMPLETECH_SIMPLESHARE: 533 + bcm47xx_set_pdata(bcm47xx_leds_simpletech_simpleshare); 534 + break; 535 + 536 + default: 537 + pr_debug("No LEDs configuration found for this device\n"); 538 + return; 539 + } 540 + 541 + gpio_led_register_device(-1, &bcm47xx_leds_pdata); 542 + }
+1 -2
arch/mips/bcm47xx/nvram.c
··· 11 * option) any later version. 12 */ 13 14 - #include <linux/init.h> 15 #include <linux/types.h> 16 #include <linux/module.h> 17 #include <linux/ssb/ssb.h> ··· 21 #include <asm/mach-bcm47xx/bcm47xx.h> 22 23 static char nvram_buf[NVRAM_SPACE]; 24 25 static u32 find_nvram_size(u32 end) 26 { 27 struct nvram_header *header; 28 - u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000}; 29 int i; 30 31 for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
··· 11 * option) any later version. 12 */ 13 14 #include <linux/types.h> 15 #include <linux/module.h> 16 #include <linux/ssb/ssb.h> ··· 22 #include <asm/mach-bcm47xx/bcm47xx.h> 23 24 static char nvram_buf[NVRAM_SPACE]; 25 + static const u32 nvram_sizes[] = {0x8000, 0xF000, 0x10000}; 26 27 static u32 find_nvram_size(u32 end) 28 { 29 struct nvram_header *header; 30 int i; 31 32 for (i = 0; i < ARRAY_SIZE(nvram_sizes); i++) {
+16 -111
arch/mips/bcm47xx/prom.c
··· 28 #include <linux/types.h> 29 #include <linux/kernel.h> 30 #include <linux/spinlock.h> 31 #include <linux/smp.h> 32 #include <asm/bootinfo.h> 33 - #include <asm/fw/cfe/cfe_api.h> 34 - #include <asm/fw/cfe/cfe_error.h> 35 #include <bcm47xx.h> 36 #include <bcm47xx_board.h> 37 38 - static int cfe_cons_handle; 39 40 - static u16 get_chip_id(void) 41 - { 42 - switch (bcm47xx_bus_type) { 43 - #ifdef CONFIG_BCM47XX_SSB 44 - case BCM47XX_BUS_TYPE_SSB: 45 - return bcm47xx_bus.ssb.chip_id; 46 - #endif 47 - #ifdef CONFIG_BCM47XX_BCMA 48 - case BCM47XX_BUS_TYPE_BCMA: 49 - return bcm47xx_bus.bcma.bus.chipinfo.id; 50 - #endif 51 - } 52 - return 0; 53 - } 54 55 const char *get_system_type(void) 56 { 57 - static char buf[50]; 58 - u16 chip_id = get_chip_id(); 59 - 60 - snprintf(buf, sizeof(buf), 61 - (chip_id > 0x9999) ? "Broadcom BCM%d (%s)" : 62 - "Broadcom BCM%04X (%s)", 63 - chip_id, bcm47xx_board_get_name()); 64 - 65 - return buf; 66 } 67 68 - void prom_putchar(char c) 69 { 70 - while (cfe_write(cfe_cons_handle, &c, 1) == 0) 71 - ; 72 - } 73 - 74 - static __init void prom_init_cfe(void) 75 - { 76 - uint32_t cfe_ept; 77 - uint32_t cfe_handle; 78 - uint32_t cfe_eptseal; 79 - int argc = fw_arg0; 80 - char **envp = (char **) fw_arg2; 81 - int *prom_vec = (int *) fw_arg3; 82 - 83 - /* 84 - * Check if a loader was used; if NOT, the 4 arguments are 85 - * what CFE gives us (handle, 0, EPT and EPTSEAL) 86 - */ 87 - if (argc < 0) { 88 - cfe_handle = (uint32_t)argc; 89 - cfe_ept = (uint32_t)envp; 90 - cfe_eptseal = (uint32_t)prom_vec; 91 - } else { 92 - if ((int)prom_vec < 0) { 93 - /* 94 - * Old loader; all it gives us is the handle, 95 - * so use the "known" entrypoint and assume 96 - * the seal. 97 - */ 98 - cfe_handle = (uint32_t)prom_vec; 99 - cfe_ept = 0xBFC00500; 100 - cfe_eptseal = CFE_EPTSEAL; 101 - } else { 102 - /* 103 - * Newer loaders bundle the handle/ept/eptseal 104 - * Note: prom_vec is in the loader's useg 105 - * which is still alive in the TLB. 106 - */ 107 - cfe_handle = prom_vec[0]; 108 - cfe_ept = prom_vec[2]; 109 - cfe_eptseal = prom_vec[3]; 110 - } 111 - } 112 - 113 - if (cfe_eptseal != CFE_EPTSEAL) { 114 - /* too early for panic to do any good */ 115 - printk(KERN_ERR "CFE's entrypoint seal doesn't match."); 116 - while (1) ; 117 - } 118 - 119 - cfe_init(cfe_handle, cfe_ept); 120 - } 121 - 122 - static __init void prom_init_console(void) 123 - { 124 - /* Initialize CFE console */ 125 - cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); 126 - } 127 - 128 - static __init void prom_init_cmdline(void) 129 - { 130 - static char buf[COMMAND_LINE_SIZE] __initdata; 131 - 132 - /* Get the kernel command line from CFE */ 133 - if (cfe_getenv("LINUX_CMDLINE", buf, COMMAND_LINE_SIZE) >= 0) { 134 - buf[COMMAND_LINE_SIZE - 1] = 0; 135 - strcpy(arcs_cmdline, buf); 136 - } 137 - 138 - /* Force a console handover by adding a console= argument if needed, 139 - * as CFE is not available anymore later in the boot process. */ 140 - if ((strstr(arcs_cmdline, "console=")) == NULL) { 141 - /* Try to read the default serial port used by CFE */ 142 - if ((cfe_getenv("BOOT_CONSOLE", buf, COMMAND_LINE_SIZE) < 0) 143 - || (strncmp("uart", buf, 4))) 144 - /* Default to uart0 */ 145 - strcpy(buf, "uart0"); 146 - 147 - /* Compute the new command line */ 148 - snprintf(arcs_cmdline, COMMAND_LINE_SIZE, "%s console=ttyS%c,115200", 149 - arcs_cmdline, buf[4]); 150 - } 151 } 152 153 static __init void prom_init_mem(void) ··· 96 add_memory_region(0, mem, BOOT_MEM_RAM); 97 } 98 99 void __init prom_init(void) 100 { 101 - prom_init_cfe(); 102 - prom_init_console(); 103 - prom_init_cmdline(); 104 prom_init_mem(); 105 } 106 107 void __init prom_free_prom_memory(void)
··· 28 #include <linux/types.h> 29 #include <linux/kernel.h> 30 #include <linux/spinlock.h> 31 + #include <linux/ssb/ssb_driver_chipcommon.h> 32 + #include <linux/ssb/ssb_regs.h> 33 #include <linux/smp.h> 34 #include <asm/bootinfo.h> 35 #include <bcm47xx.h> 36 #include <bcm47xx_board.h> 37 38 39 + static char bcm47xx_system_type[20] = "Broadcom BCM47XX"; 40 41 const char *get_system_type(void) 42 { 43 + return bcm47xx_system_type; 44 } 45 46 + __init void bcm47xx_set_system_type(u16 chip_id) 47 { 48 + snprintf(bcm47xx_system_type, sizeof(bcm47xx_system_type), 49 + (chip_id > 0x9999) ? "Broadcom BCM%d" : 50 + "Broadcom BCM%04X", 51 + chip_id); 52 } 53 54 static __init void prom_init_mem(void) ··· 195 add_memory_region(0, mem, BOOT_MEM_RAM); 196 } 197 198 + /* 199 + * This is the first serial on the chip common core, it is at this position 200 + * for sb (ssb) and ai (bcma) bus. 201 + */ 202 + #define BCM47XX_SERIAL_ADDR (SSB_ENUM_BASE + SSB_CHIPCO_UART0_DATA) 203 + 204 void __init prom_init(void) 205 { 206 prom_init_mem(); 207 + setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0); 208 } 209 210 void __init prom_free_prom_memory(void)
+4 -2
arch/mips/bcm47xx/serial.c
··· 31 32 memset(&uart8250_data, 0, sizeof(uart8250_data)); 33 34 - for (i = 0; i < mcore->nr_serial_ports; i++) { 35 struct plat_serial8250_port *p = &(uart8250_data[i]); 36 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]); 37 ··· 56 57 memset(&uart8250_data, 0, sizeof(uart8250_data)); 58 59 - for (i = 0; i < cc->nr_serial_ports; i++) { 60 struct plat_serial8250_port *p = &(uart8250_data[i]); 61 struct bcma_serial_port *bcma_port; 62 bcma_port = &(cc->serial_ports[i]);
··· 31 32 memset(&uart8250_data, 0, sizeof(uart8250_data)); 33 34 + for (i = 0; i < mcore->nr_serial_ports && 35 + i < ARRAY_SIZE(uart8250_data) - 1; i++) { 36 struct plat_serial8250_port *p = &(uart8250_data[i]); 37 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]); 38 ··· 55 56 memset(&uart8250_data, 0, sizeof(uart8250_data)); 57 58 + for (i = 0; i < cc->nr_serial_ports && 59 + i < ARRAY_SIZE(uart8250_data) - 1; i++) { 60 struct plat_serial8250_port *p = &(uart8250_data[i]); 61 struct bcma_serial_port *bcma_port; 62 bcma_port = &(cc->serial_ports[i]);
+35
arch/mips/bcm47xx/setup.c
··· 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 29 #include <linux/export.h> 30 #include <linux/types.h> 31 #include <linux/ethtool.h> ··· 37 #include <linux/ssb/ssb_embedded.h> 38 #include <linux/bcma/bcma_soc.h> 39 #include <asm/bootinfo.h> 40 #include <asm/reboot.h> 41 #include <asm/time.h> 42 #include <bcm47xx.h> ··· 217 #ifdef CONFIG_BCM47XX_BCMA 218 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA; 219 bcm47xx_register_bcma(); 220 #endif 221 } else { 222 printk(KERN_INFO "bcm47xx: using ssb bus\n"); 223 #ifdef CONFIG_BCM47XX_SSB 224 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; 225 bcm47xx_register_ssb(); 226 #endif 227 } 228 ··· 232 _machine_halt = bcm47xx_machine_halt; 233 pm_power_off = bcm47xx_machine_halt; 234 bcm47xx_board_detect(); 235 } 236 237 static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = { 238 .link = 1, ··· 280 break; 281 #endif 282 } 283 fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); 284 return 0; 285 }
··· 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 29 + #include "bcm47xx_private.h" 30 + 31 #include <linux/export.h> 32 #include <linux/types.h> 33 #include <linux/ethtool.h> ··· 35 #include <linux/ssb/ssb_embedded.h> 36 #include <linux/bcma/bcma_soc.h> 37 #include <asm/bootinfo.h> 38 + #include <asm/idle.h> 39 + #include <asm/prom.h> 40 #include <asm/reboot.h> 41 #include <asm/time.h> 42 #include <bcm47xx.h> ··· 213 #ifdef CONFIG_BCM47XX_BCMA 214 bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA; 215 bcm47xx_register_bcma(); 216 + bcm47xx_set_system_type(bcm47xx_bus.bcma.bus.chipinfo.id); 217 #endif 218 } else { 219 printk(KERN_INFO "bcm47xx: using ssb bus\n"); 220 #ifdef CONFIG_BCM47XX_SSB 221 bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB; 222 bcm47xx_register_ssb(); 223 + bcm47xx_set_system_type(bcm47xx_bus.ssb.chip_id); 224 #endif 225 } 226 ··· 226 _machine_halt = bcm47xx_machine_halt; 227 pm_power_off = bcm47xx_machine_halt; 228 bcm47xx_board_detect(); 229 + mips_set_machine_name(bcm47xx_board_get_name()); 230 } 231 + 232 + static int __init bcm47xx_cpu_fixes(void) 233 + { 234 + switch (bcm47xx_bus_type) { 235 + #ifdef CONFIG_BCM47XX_SSB 236 + case BCM47XX_BUS_TYPE_SSB: 237 + /* Nothing to do */ 238 + break; 239 + #endif 240 + #ifdef CONFIG_BCM47XX_BCMA 241 + case BCM47XX_BUS_TYPE_BCMA: 242 + /* The BCM4706 has a problem with the CPU wait instruction. 243 + * When r4k_wait or r4k_wait_irqoff is used will just hang and 244 + * not return from a msleep(). Removing the cpu_wait 245 + * functionality is a workaround for this problem. The BCM4716 246 + * does not have this problem. 247 + */ 248 + if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) 249 + cpu_wait = NULL; 250 + break; 251 + #endif 252 + } 253 + return 0; 254 + } 255 + arch_initcall(bcm47xx_cpu_fixes); 256 257 static struct fixed_phy_status bcm47xx_fixed_phy_status __initdata = { 258 .link = 1, ··· 248 break; 249 #endif 250 } 251 + bcm47xx_buttons_register(); 252 + bcm47xx_leds_register(); 253 + 254 fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status); 255 return 0; 256 }
+9 -9
arch/mips/bcm47xx/sprom.c
··· 135 } 136 137 static void nvram_read_macaddr(const char *prefix, const char *name, 138 - u8 (*val)[6], bool fallback) 139 { 140 char buf[100]; 141 int err; ··· 144 if (err < 0) 145 return; 146 147 - bcm47xx_nvram_parse_macaddr(buf, *val); 148 } 149 150 static void nvram_read_alpha2(const char *prefix, const char *name, 151 - char (*val)[2], bool fallback) 152 { 153 char buf[10]; 154 int err; ··· 162 pr_warn("alpha2 is too long %s\n", buf); 163 return; 164 } 165 - memcpy(val, buf, sizeof(val)); 166 } 167 168 static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom, ··· 180 fallback); 181 nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0, 182 fallback); 183 - nvram_read_alpha2(prefix, "ccode", &sprom->alpha2, fallback); 184 } 185 186 static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom, ··· 633 static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, 634 const char *prefix, bool fallback) 635 { 636 - nvram_read_macaddr(prefix, "et0macaddr", &sprom->et0mac, fallback); 637 nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0, 638 fallback); 639 nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0, 640 fallback); 641 642 - nvram_read_macaddr(prefix, "et1macaddr", &sprom->et1mac, fallback); 643 nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0, 644 fallback); 645 nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0, 646 fallback); 647 648 - nvram_read_macaddr(prefix, "macaddr", &sprom->il0mac, fallback); 649 - nvram_read_macaddr(prefix, "il0macaddr", &sprom->il0mac, fallback); 650 } 651 652 static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
··· 135 } 136 137 static void nvram_read_macaddr(const char *prefix, const char *name, 138 + u8 val[6], bool fallback) 139 { 140 char buf[100]; 141 int err; ··· 144 if (err < 0) 145 return; 146 147 + bcm47xx_nvram_parse_macaddr(buf, val); 148 } 149 150 static void nvram_read_alpha2(const char *prefix, const char *name, 151 + char val[2], bool fallback) 152 { 153 char buf[10]; 154 int err; ··· 162 pr_warn("alpha2 is too long %s\n", buf); 163 return; 164 } 165 + memcpy(val, buf, 2); 166 } 167 168 static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom, ··· 180 fallback); 181 nvram_read_s8(prefix, NULL, "ag1", &sprom->antenna_gain.a1, 0, 182 fallback); 183 + nvram_read_alpha2(prefix, "ccode", sprom->alpha2, fallback); 184 } 185 186 static void bcm47xx_fill_sprom_r12389(struct ssb_sprom *sprom, ··· 633 static void bcm47xx_fill_sprom_ethernet(struct ssb_sprom *sprom, 634 const char *prefix, bool fallback) 635 { 636 + nvram_read_macaddr(prefix, "et0macaddr", sprom->et0mac, fallback); 637 nvram_read_u8(prefix, NULL, "et0mdcport", &sprom->et0mdcport, 0, 638 fallback); 639 nvram_read_u8(prefix, NULL, "et0phyaddr", &sprom->et0phyaddr, 0, 640 fallback); 641 642 + nvram_read_macaddr(prefix, "et1macaddr", sprom->et1mac, fallback); 643 nvram_read_u8(prefix, NULL, "et1mdcport", &sprom->et1mdcport, 0, 644 fallback); 645 nvram_read_u8(prefix, NULL, "et1phyaddr", &sprom->et1phyaddr, 0, 646 fallback); 647 648 + nvram_read_macaddr(prefix, "macaddr", sprom->il0mac, fallback); 649 + nvram_read_macaddr(prefix, "il0macaddr", sprom->il0mac, fallback); 650 } 651 652 static void bcm47xx_fill_board_data(struct ssb_sprom *sprom, const char *prefix,
-174
arch/mips/bcm47xx/wgt634u.c
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net> 7 - */ 8 - 9 - #include <linux/platform_device.h> 10 - #include <linux/module.h> 11 - #include <linux/leds.h> 12 - #include <linux/mtd/physmap.h> 13 - #include <linux/ssb/ssb.h> 14 - #include <linux/ssb/ssb_embedded.h> 15 - #include <linux/interrupt.h> 16 - #include <linux/reboot.h> 17 - #include <linux/gpio.h> 18 - #include <asm/mach-bcm47xx/bcm47xx.h> 19 - 20 - /* GPIO definitions for the WGT634U */ 21 - #define WGT634U_GPIO_LED 3 22 - #define WGT634U_GPIO_RESET 2 23 - #define WGT634U_GPIO_TP1 7 24 - #define WGT634U_GPIO_TP2 6 25 - #define WGT634U_GPIO_TP3 5 26 - #define WGT634U_GPIO_TP4 4 27 - #define WGT634U_GPIO_TP5 1 28 - 29 - static struct gpio_led wgt634u_leds[] = { 30 - { 31 - .name = "power", 32 - .gpio = WGT634U_GPIO_LED, 33 - .active_low = 1, 34 - .default_trigger = "heartbeat", 35 - }, 36 - }; 37 - 38 - static struct gpio_led_platform_data wgt634u_led_data = { 39 - .num_leds = ARRAY_SIZE(wgt634u_leds), 40 - .leds = wgt634u_leds, 41 - }; 42 - 43 - static struct platform_device wgt634u_gpio_leds = { 44 - .name = "leds-gpio", 45 - .id = -1, 46 - .dev = { 47 - .platform_data = &wgt634u_led_data, 48 - } 49 - }; 50 - 51 - 52 - /* 8MiB flash. The struct mtd_partition matches original Netgear WGT634U 53 - firmware. */ 54 - static struct mtd_partition wgt634u_partitions[] = { 55 - { 56 - .name = "cfe", 57 - .offset = 0, 58 - .size = 0x60000, /* 384k */ 59 - .mask_flags = MTD_WRITEABLE /* force read-only */ 60 - }, 61 - { 62 - .name = "config", 63 - .offset = 0x60000, 64 - .size = 0x20000 /* 128k */ 65 - }, 66 - { 67 - .name = "linux", 68 - .offset = 0x80000, 69 - .size = 0x140000 /* 1280k */ 70 - }, 71 - { 72 - .name = "jffs", 73 - .offset = 0x1c0000, 74 - .size = 0x620000 /* 6272k */ 75 - }, 76 - { 77 - .name = "nvram", 78 - .offset = 0x7e0000, 79 - .size = 0x20000 /* 128k */ 80 - }, 81 - }; 82 - 83 - static struct physmap_flash_data wgt634u_flash_data = { 84 - .parts = wgt634u_partitions, 85 - .nr_parts = ARRAY_SIZE(wgt634u_partitions) 86 - }; 87 - 88 - static struct resource wgt634u_flash_resource = { 89 - .flags = IORESOURCE_MEM, 90 - }; 91 - 92 - static struct platform_device wgt634u_flash = { 93 - .name = "physmap-flash", 94 - .id = 0, 95 - .dev = { .platform_data = &wgt634u_flash_data, }, 96 - .resource = &wgt634u_flash_resource, 97 - .num_resources = 1, 98 - }; 99 - 100 - /* Platform devices */ 101 - static struct platform_device *wgt634u_devices[] __initdata = { 102 - &wgt634u_flash, 103 - &wgt634u_gpio_leds, 104 - }; 105 - 106 - static irqreturn_t gpio_interrupt(int irq, void *ignored) 107 - { 108 - int state; 109 - 110 - /* Interrupts are shared, check if the current one is 111 - a GPIO interrupt. */ 112 - if (!ssb_chipco_irq_status(&bcm47xx_bus.ssb.chipco, 113 - SSB_CHIPCO_IRQ_GPIO)) 114 - return IRQ_NONE; 115 - 116 - state = gpio_get_value(WGT634U_GPIO_RESET); 117 - 118 - /* Interrupt are level triggered, revert the interrupt polarity 119 - to clear the interrupt. */ 120 - ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << WGT634U_GPIO_RESET, 121 - state ? 1 << WGT634U_GPIO_RESET : 0); 122 - 123 - if (!state) { 124 - printk(KERN_INFO "Reset button pressed"); 125 - ctrl_alt_del(); 126 - } 127 - 128 - return IRQ_HANDLED; 129 - } 130 - 131 - static int __init wgt634u_init(void) 132 - { 133 - /* There is no easy way to detect that we are running on a WGT634U 134 - * machine. Use the MAC address as an heuristic. Netgear Inc. has 135 - * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx. 136 - */ 137 - u8 *et0mac; 138 - 139 - if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB) 140 - return -ENODEV; 141 - 142 - et0mac = bcm47xx_bus.ssb.sprom.et0mac; 143 - 144 - if (et0mac[0] == 0x00 && 145 - ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) || 146 - (et0mac[1] == 0x0f && et0mac[2] == 0xb5))) { 147 - struct ssb_mipscore *mcore = &bcm47xx_bus.ssb.mipscore; 148 - 149 - printk(KERN_INFO "WGT634U machine detected.\n"); 150 - 151 - if (!request_irq(gpio_to_irq(WGT634U_GPIO_RESET), 152 - gpio_interrupt, IRQF_SHARED, 153 - "WGT634U GPIO", &bcm47xx_bus.ssb.chipco)) { 154 - gpio_direction_input(WGT634U_GPIO_RESET); 155 - ssb_gpio_intmask(&bcm47xx_bus.ssb, 156 - 1 << WGT634U_GPIO_RESET, 157 - 1 << WGT634U_GPIO_RESET); 158 - ssb_chipco_irq_mask(&bcm47xx_bus.ssb.chipco, 159 - SSB_CHIPCO_IRQ_GPIO, 160 - SSB_CHIPCO_IRQ_GPIO); 161 - } 162 - 163 - wgt634u_flash_data.width = mcore->pflash.buswidth; 164 - wgt634u_flash_resource.start = mcore->pflash.window; 165 - wgt634u_flash_resource.end = mcore->pflash.window 166 - + mcore->pflash.window_size 167 - - 1; 168 - return platform_add_devices(wgt634u_devices, 169 - ARRAY_SIZE(wgt634u_devices)); 170 - } else 171 - return -ENODEV; 172 - } 173 - 174 - module_init(wgt634u_init);
···
+8
arch/mips/bcm63xx/Kconfig
··· 3 4 config BCM63XX_CPU_3368 5 bool "support 3368 CPU" 6 select HW_HAS_PCI 7 8 config BCM63XX_CPU_6328 9 bool "support 6328 CPU" 10 select HW_HAS_PCI 11 12 config BCM63XX_CPU_6338 13 bool "support 6338 CPU" 14 select HW_HAS_PCI 15 16 config BCM63XX_CPU_6345 17 bool "support 6345 CPU" 18 19 config BCM63XX_CPU_6348 20 bool "support 6348 CPU" 21 select HW_HAS_PCI 22 23 config BCM63XX_CPU_6358 24 bool "support 6358 CPU" 25 select HW_HAS_PCI 26 27 config BCM63XX_CPU_6362 28 bool "support 6362 CPU" 29 select HW_HAS_PCI 30 31 config BCM63XX_CPU_6368 32 bool "support 6368 CPU" 33 select HW_HAS_PCI 34 endmenu 35
··· 3 4 config BCM63XX_CPU_3368 5 bool "support 3368 CPU" 6 + select SYS_HAS_CPU_BMIPS4350 7 select HW_HAS_PCI 8 9 config BCM63XX_CPU_6328 10 bool "support 6328 CPU" 11 + select SYS_HAS_CPU_BMIPS4350 12 select HW_HAS_PCI 13 14 config BCM63XX_CPU_6338 15 bool "support 6338 CPU" 16 + select SYS_HAS_CPU_BMIPS32_3300 17 select HW_HAS_PCI 18 19 config BCM63XX_CPU_6345 20 bool "support 6345 CPU" 21 + select SYS_HAS_CPU_BMIPS32_3300 22 23 config BCM63XX_CPU_6348 24 bool "support 6348 CPU" 25 + select SYS_HAS_CPU_BMIPS32_3300 26 select HW_HAS_PCI 27 28 config BCM63XX_CPU_6358 29 bool "support 6358 CPU" 30 + select SYS_HAS_CPU_BMIPS4350 31 select HW_HAS_PCI 32 33 config BCM63XX_CPU_6362 34 bool "support 6362 CPU" 35 + select SYS_HAS_CPU_BMIPS4350 36 select HW_HAS_PCI 37 38 config BCM63XX_CPU_6368 39 bool "support 6368 CPU" 40 + select SYS_HAS_CPU_BMIPS4350 41 select HW_HAS_PCI 42 endmenu 43
+2 -2
arch/mips/bcm63xx/Makefile
··· 1 obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ 2 setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ 3 - dev-pcmcia.o dev-rng.o dev-spi.o dev-uart.o dev-wdt.o \ 4 - dev-usb-usbd.o 5 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 6 7 obj-y += boards/
··· 1 obj-y += clk.o cpu.o cs.o gpio.o irq.o nvram.o prom.o reset.o \ 2 setup.o timer.o dev-dsp.o dev-enet.o dev-flash.o \ 3 + dev-pcmcia.o dev-rng.o dev-spi.o dev-hsspi.o dev-uart.o \ 4 + dev-wdt.o dev-usb-usbd.o 5 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 6 7 obj-y += boards/
+3
arch/mips/bcm63xx/boards/board_bcm963xx.c
··· 23 #include <bcm63xx_dev_enet.h> 24 #include <bcm63xx_dev_dsp.h> 25 #include <bcm63xx_dev_flash.h> 26 #include <bcm63xx_dev_pcmcia.h> 27 #include <bcm63xx_dev_spi.h> 28 #include <bcm63xx_dev_usb_usbd.h> ··· 915 #endif 916 917 bcm63xx_spi_register(); 918 919 bcm63xx_flash_register(); 920
··· 23 #include <bcm63xx_dev_enet.h> 24 #include <bcm63xx_dev_dsp.h> 25 #include <bcm63xx_dev_flash.h> 26 + #include <bcm63xx_dev_hsspi.h> 27 #include <bcm63xx_dev_pcmcia.h> 28 #include <bcm63xx_dev_spi.h> 29 #include <bcm63xx_dev_usb_usbd.h> ··· 914 #endif 915 916 bcm63xx_spi_register(); 917 + 918 + bcm63xx_hsspi_register(); 919 920 bcm63xx_flash_register(); 921
+42
arch/mips/bcm63xx/clk.c
··· 226 }; 227 228 /* 229 * XTM clock 230 */ 231 static void xtm_set(struct clk *clk, int enable) ··· 368 return &clk_usbd; 369 if (!strcmp(id, "spi")) 370 return &clk_spi; 371 if (!strcmp(id, "xtm")) 372 return &clk_xtm; 373 if (!strcmp(id, "periph")) ··· 390 } 391 392 EXPORT_SYMBOL(clk_put);
··· 226 }; 227 228 /* 229 + * HSSPI clock 230 + */ 231 + static void hsspi_set(struct clk *clk, int enable) 232 + { 233 + u32 mask; 234 + 235 + if (BCMCPU_IS_6328()) 236 + mask = CKCTL_6328_HSSPI_EN; 237 + else if (BCMCPU_IS_6362()) 238 + mask = CKCTL_6362_HSSPI_EN; 239 + else 240 + return; 241 + 242 + bcm_hwclock_set(mask, enable); 243 + } 244 + 245 + static struct clk clk_hsspi = { 246 + .set = hsspi_set, 247 + }; 248 + 249 + 250 + /* 251 * XTM clock 252 */ 253 static void xtm_set(struct clk *clk, int enable) ··· 346 return &clk_usbd; 347 if (!strcmp(id, "spi")) 348 return &clk_spi; 349 + if (!strcmp(id, "hsspi")) 350 + return &clk_hsspi; 351 if (!strcmp(id, "xtm")) 352 return &clk_xtm; 353 if (!strcmp(id, "periph")) ··· 366 } 367 368 EXPORT_SYMBOL(clk_put); 369 + 370 + #define HSSPI_PLL_HZ_6328 133333333 371 + #define HSSPI_PLL_HZ_6362 400000000 372 + 373 + static int __init bcm63xx_clk_init(void) 374 + { 375 + switch (bcm63xx_get_cpu_id()) { 376 + case BCM6328_CPU_ID: 377 + clk_hsspi.rate = HSSPI_PLL_HZ_6328; 378 + break; 379 + case BCM6362_CPU_ID: 380 + clk_hsspi.rate = HSSPI_PLL_HZ_6362; 381 + break; 382 + } 383 + 384 + return 0; 385 + } 386 + arch_initcall(bcm63xx_clk_init);
+4 -2
arch/mips/bcm63xx/cpu.c
··· 123 124 static unsigned int detect_cpu_clock(void) 125 { 126 - switch (bcm63xx_get_cpu_id()) { 127 case BCM3368_CPU_ID: 128 return 300000000; 129 ··· 251 } 252 253 default: 254 - BUG(); 255 } 256 } 257
··· 123 124 static unsigned int detect_cpu_clock(void) 125 { 126 + u16 cpu_id = bcm63xx_get_cpu_id(); 127 + 128 + switch (cpu_id) { 129 case BCM3368_CPU_ID: 130 return 300000000; 131 ··· 249 } 250 251 default: 252 + panic("Failed to detect clock for CPU with id=%04X\n", cpu_id); 253 } 254 } 255
+47
arch/mips/bcm63xx/dev-hsspi.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com> 7 + */ 8 + 9 + #include <linux/init.h> 10 + #include <linux/kernel.h> 11 + #include <linux/platform_device.h> 12 + 13 + #include <bcm63xx_cpu.h> 14 + #include <bcm63xx_dev_hsspi.h> 15 + #include <bcm63xx_regs.h> 16 + 17 + static struct resource spi_resources[] = { 18 + { 19 + .start = -1, /* filled at runtime */ 20 + .end = -1, /* filled at runtime */ 21 + .flags = IORESOURCE_MEM, 22 + }, 23 + { 24 + .start = -1, /* filled at runtime */ 25 + .flags = IORESOURCE_IRQ, 26 + }, 27 + }; 28 + 29 + static struct platform_device bcm63xx_hsspi_device = { 30 + .name = "bcm63xx-hsspi", 31 + .id = 0, 32 + .num_resources = ARRAY_SIZE(spi_resources), 33 + .resource = spi_resources, 34 + }; 35 + 36 + int __init bcm63xx_hsspi_register(void) 37 + { 38 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362()) 39 + return -ENODEV; 40 + 41 + spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI); 42 + spi_resources[0].end = spi_resources[0].start; 43 + spi_resources[0].end += RSET_HSSPI_SIZE - 1; 44 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_HSSPI); 45 + 46 + return platform_device_register(&bcm63xx_hsspi_device); 47 + }
+1 -2
arch/mips/bcm63xx/early_printk.c
··· 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 */ 8 9 - #include <linux/init.h> 10 #include <bcm63xx_io.h> 11 - #include <bcm63xx_regs.h> 12 13 static void wait_xfered(void) 14 {
··· 6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7 */ 8 9 #include <bcm63xx_io.h> 10 + #include <linux/serial_bcm63xx.h> 11 12 static void wait_xfered(void) 13 {
+6 -8
arch/mips/bcm63xx/prom.c
··· 59 /* do low level board init */ 60 board_prom_init(); 61 62 - if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) { 63 - /* set up SMP */ 64 - register_smp_ops(&bmips_smp_ops); 65 - 66 /* 67 - * BCM6328 might not have its second CPU enabled, while BCM6358 68 - * needs special handling for its shared TLB, so disable SMP 69 - * for now. 70 */ 71 if (BCMCPU_IS_6328()) { 72 reg = bcm_readl(BCM_6328_OTP_BASE + ··· 72 73 if (reg & OTP_6328_REG3_TP1_DISABLED) 74 bmips_smp_enabled = 0; 75 - } else if (BCMCPU_IS_6358()) { 76 bmips_smp_enabled = 0; 77 } 78
··· 59 /* do low level board init */ 60 board_prom_init(); 61 62 + /* set up SMP */ 63 + if (!register_bmips_smp_ops()) { 64 /* 65 + * BCM6328 might not have its second CPU enabled, while BCM3368 66 + * and BCM6358 need special handling for their shared TLB, so 67 + * disable SMP for now. 68 */ 69 if (BCMCPU_IS_6328()) { 70 reg = bcm_readl(BCM_6328_OTP_BASE + ··· 74 75 if (reg & OTP_6328_REG3_TP1_DISABLED) 76 bmips_smp_enabled = 0; 77 + } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { 78 bmips_smp_enabled = 0; 79 } 80
+2 -2
arch/mips/boot/compressed/Makefile
··· 27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ 28 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS) 29 30 - targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o 31 32 # decompressor objects (linked with vmlinuz) 33 - vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o 34 35 ifdef CONFIG_DEBUG_ZBOOT 36 vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
··· 27 -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \ 28 -DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS) 29 30 + targets := head.o decompress.o string.o dbg.o uart-16550.o uart-alchemy.o 31 32 # decompressor objects (linked with vmlinuz) 33 + vmlinuzobjs-y := $(obj)/head.o $(obj)/decompress.o $(obj)/string.o $(obj)/dbg.o 34 35 ifdef CONFIG_DEBUG_ZBOOT 36 vmlinuzobjs-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
-1
arch/mips/boot/compressed/dbg.c
··· 6 * need to implement your own putc(). 7 */ 8 #include <linux/compiler.h> 9 - #include <linux/init.h> 10 #include <linux/types.h> 11 12 void __weak putc(char c)
··· 6 * need to implement your own putc(). 7 */ 8 #include <linux/compiler.h> 9 #include <linux/types.h> 10 11 void __weak putc(char c)
-22
arch/mips/boot/compressed/decompress.c
··· 43 /* activate the code for pre-boot environment */ 44 #define STATIC static 45 46 - #if defined(CONFIG_KERNEL_GZIP) || defined(CONFIG_KERNEL_XZ) || \ 47 - defined(CONFIG_KERNEL_LZ4) 48 - void *memcpy(void *dest, const void *src, size_t n) 49 - { 50 - int i; 51 - const char *s = src; 52 - char *d = dest; 53 - 54 - for (i = 0; i < n; i++) 55 - d[i] = s[i]; 56 - return dest; 57 - } 58 - #endif 59 #ifdef CONFIG_KERNEL_GZIP 60 #include "../../../../lib/decompress_inflate.c" 61 #endif 62 63 #ifdef CONFIG_KERNEL_BZIP2 64 - void *memset(void *s, int c, size_t n) 65 - { 66 - int i; 67 - char *ss = s; 68 - 69 - for (i = 0; i < n; i++) 70 - ss[i] = c; 71 - return s; 72 - } 73 #include "../../../../lib/decompress_bunzip2.c" 74 #endif 75
··· 43 /* activate the code for pre-boot environment */ 44 #define STATIC static 45 46 #ifdef CONFIG_KERNEL_GZIP 47 #include "../../../../lib/decompress_inflate.c" 48 #endif 49 50 #ifdef CONFIG_KERNEL_BZIP2 51 #include "../../../../lib/decompress_bunzip2.c" 52 #endif 53
+28
arch/mips/boot/compressed/string.c
···
··· 1 + /* 2 + * arch/mips/boot/compressed/string.c 3 + * 4 + * Very small subset of simple string routines 5 + */ 6 + 7 + #include <linux/types.h> 8 + 9 + void *memcpy(void *dest, const void *src, size_t n) 10 + { 11 + int i; 12 + const char *s = src; 13 + char *d = dest; 14 + 15 + for (i = 0; i < n; i++) 16 + d[i] = s[i]; 17 + return dest; 18 + } 19 + 20 + void *memset(void *s, int c, size_t n) 21 + { 22 + int i; 23 + char *ss = s; 24 + 25 + for (i = 0; i < n; i++) 26 + ss[i] = c; 27 + return s; 28 + }
+2 -3
arch/mips/boot/compressed/uart-16550.c
··· 4 5 #include <linux/types.h> 6 #include <linux/serial_reg.h> 7 - #include <linux/init.h> 8 9 #include <asm/addrspace.h> 10 ··· 18 #endif 19 20 #ifdef CONFIG_MACH_JZ4740 21 - #define UART0_BASE 0xB0030000 22 - #define PORT(offset) (UART0_BASE + (4 * offset)) 23 #endif 24 25 #ifdef CONFIG_CPU_XLR
··· 4 5 #include <linux/types.h> 6 #include <linux/serial_reg.h> 7 8 #include <asm/addrspace.h> 9 ··· 19 #endif 20 21 #ifdef CONFIG_MACH_JZ4740 22 + #include <asm/mach-jz4740/base.h> 23 + #define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset)) 24 #endif 25 26 #ifdef CONFIG_CPU_XLR
+1
arch/mips/cavium-octeon/executive/cvmx-cmd-queue.c
··· 47 * state. It points to a bootmem named block. 48 */ 49 __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; 50 51 /** 52 * Initialize the Global queue state pointer.
··· 47 * state. It points to a bootmem named block. 48 */ 49 __cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; 50 + EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr); 51 52 /** 53 * Initialize the Global queue state pointer.
+27
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
··· 722 } 723 return 0; 724 }
··· 722 } 723 return 0; 724 } 725 + 726 + /** 727 + * Get the clock type used for the USB block based on board type. 728 + * Used by the USB code for auto configuration of clock type. 729 + * 730 + * Return USB clock type enumeration 731 + */ 732 + enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void) 733 + { 734 + switch (cvmx_sysinfo_get()->board_type) { 735 + case CVMX_BOARD_TYPE_BBGW_REF: 736 + case CVMX_BOARD_TYPE_LANAI2_A: 737 + case CVMX_BOARD_TYPE_LANAI2_U: 738 + case CVMX_BOARD_TYPE_LANAI2_G: 739 + case CVMX_BOARD_TYPE_NIC10E_66: 740 + case CVMX_BOARD_TYPE_UBNT_E100: 741 + return USB_CLOCK_TYPE_CRYSTAL_12; 742 + case CVMX_BOARD_TYPE_NIC10E: 743 + return USB_CLOCK_TYPE_REF_12; 744 + default: 745 + break; 746 + } 747 + /* Most boards except NIC10e use a 12MHz crystal */ 748 + if (OCTEON_IS_MODEL(OCTEON_FAM_2)) 749 + return USB_CLOCK_TYPE_CRYSTAL_12; 750 + return USB_CLOCK_TYPE_REF_48; 751 + }
+4
arch/mips/cavium-octeon/executive/cvmx-helper-util.c
··· 251 252 return 0; 253 } 254 255 /** 256 * Setup the common GMX settings that determine the number of ··· 385 } 386 return -1; 387 } 388 389 /** 390 * Returns the interface number for an IPD/PKO port number. ··· 410 411 return -1; 412 } 413 414 /** 415 * Returns the interface index number for an IPD/PKO port ··· 434 435 return -1; 436 }
··· 251 252 return 0; 253 } 254 + EXPORT_SYMBOL_GPL(cvmx_helper_setup_red); 255 256 /** 257 * Setup the common GMX settings that determine the number of ··· 384 } 385 return -1; 386 } 387 + EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port); 388 389 /** 390 * Returns the interface number for an IPD/PKO port number. ··· 408 409 return -1; 410 } 411 + EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num); 412 413 /** 414 * Returns the interface index number for an IPD/PKO port ··· 431 432 return -1; 433 } 434 + EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_index_num);
+9 -1
arch/mips/cavium-octeon/executive/cvmx-helper.c
··· 67 void (*cvmx_override_ipd_port_setup) (int ipd_port); 68 69 /* Port count per interface */ 70 - static int interface_port_count[4] = { 0, 0, 0, 0 }; 71 72 /* Port last configured link info index by IPD/PKO port */ 73 static cvmx_helper_link_info_t ··· 88 else 89 return 3; 90 } 91 92 /** 93 * Return the number of ports on an interface. Depending on the ··· 103 { 104 return interface_port_count[interface]; 105 } 106 107 /** 108 * Get the operating mode of an interface. Depending on the Octeon ··· 181 return CVMX_HELPER_INTERFACE_MODE_RGMII; 182 } 183 } 184 185 /** 186 * Configure the IPD/PIP tagging and QoS options for a specific ··· 828 __cvmx_helper_errata_fix_ipd_ptr_alignment(); 829 return 0; 830 } 831 832 /** 833 * Initialize the PIP, IPD, and PKO hardware to support ··· 907 #endif 908 return result; 909 } 910 911 /** 912 * Does core local initialization for packet io ··· 952 */ 953 return port_link_info[ipd_port]; 954 } 955 956 /** 957 * Return the link state of an IPD/PKO port as returned by ··· 1011 } 1012 return result; 1013 } 1014 1015 /** 1016 * Configure an IPD/PKO port for the specified link state. This ··· 1067 port_link_info[ipd_port].u64 = link_info.u64; 1068 return result; 1069 } 1070 1071 /** 1072 * Configure a port for internal and/or external loopback. Internal loopback
··· 67 void (*cvmx_override_ipd_port_setup) (int ipd_port); 68 69 /* Port count per interface */ 70 + static int interface_port_count[5]; 71 72 /* Port last configured link info index by IPD/PKO port */ 73 static cvmx_helper_link_info_t ··· 88 else 89 return 3; 90 } 91 + EXPORT_SYMBOL_GPL(cvmx_helper_get_number_of_interfaces); 92 93 /** 94 * Return the number of ports on an interface. Depending on the ··· 102 { 103 return interface_port_count[interface]; 104 } 105 + EXPORT_SYMBOL_GPL(cvmx_helper_ports_on_interface); 106 107 /** 108 * Get the operating mode of an interface. Depending on the Octeon ··· 179 return CVMX_HELPER_INTERFACE_MODE_RGMII; 180 } 181 } 182 + EXPORT_SYMBOL_GPL(cvmx_helper_interface_get_mode); 183 184 /** 185 * Configure the IPD/PIP tagging and QoS options for a specific ··· 825 __cvmx_helper_errata_fix_ipd_ptr_alignment(); 826 return 0; 827 } 828 + EXPORT_SYMBOL_GPL(cvmx_helper_ipd_and_packet_input_enable); 829 830 /** 831 * Initialize the PIP, IPD, and PKO hardware to support ··· 903 #endif 904 return result; 905 } 906 + EXPORT_SYMBOL_GPL(cvmx_helper_initialize_packet_io_global); 907 908 /** 909 * Does core local initialization for packet io ··· 947 */ 948 return port_link_info[ipd_port]; 949 } 950 + EXPORT_SYMBOL_GPL(cvmx_helper_link_autoconf); 951 952 /** 953 * Return the link state of an IPD/PKO port as returned by ··· 1005 } 1006 return result; 1007 } 1008 + EXPORT_SYMBOL_GPL(cvmx_helper_link_get); 1009 1010 /** 1011 * Configure an IPD/PKO port for the specified link state. This ··· 1060 port_link_info[ipd_port].u64 = link_info.u64; 1061 return result; 1062 } 1063 + EXPORT_SYMBOL_GPL(cvmx_helper_link_set); 1064 1065 /** 1066 * Configure a port for internal and/or external loopback. Internal loopback
+2 -1
arch/mips/cavium-octeon/executive/cvmx-pko.c
··· 140 pko_reg_flags.s.ena_pko = 0; 141 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); 142 } 143 - 144 145 /** 146 * Reset the packet output. ··· 182 } 183 __cvmx_pko_reset(); 184 } 185 186 /** 187 * Configure a output port and the associated queues for use.
··· 140 pko_reg_flags.s.ena_pko = 0; 141 cvmx_write_csr(CVMX_PKO_REG_FLAGS, pko_reg_flags.u64); 142 } 143 + EXPORT_SYMBOL_GPL(cvmx_pko_disable); 144 145 /** 146 * Reset the packet output. ··· 182 } 183 __cvmx_pko_reset(); 184 } 185 + EXPORT_SYMBOL_GPL(cvmx_pko_shutdown); 186 187 /** 188 * Configure a output port and the associated queues for use.
+1
arch/mips/cavium-octeon/executive/cvmx-spi.c
··· 177 178 return res; 179 } 180 181 /** 182 * Callback to perform SPI4 reset
··· 177 178 return res; 179 } 180 + EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface); 181 182 /** 183 * Callback to perform SPI4 reset
+35 -3
arch/mips/cavium-octeon/octeon-platform.c
··· 171 static struct of_device_id __initdata octeon_ids[] = { 172 { .compatible = "simple-bus", }, 173 { .compatible = "cavium,octeon-6335-uctl", }, 174 { .compatible = "cavium,octeon-3860-bootbus", }, 175 { .compatible = "cavium,mdio-mux", }, 176 { .compatible = "gpio-leds", }, ··· 337 int p; 338 int count = 0; 339 340 - if (cvmx_helper_interface_enumerate(idx) == 0) 341 - count = cvmx_helper_ports_on_interface(idx); 342 - 343 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); 344 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); 345 if (iface < 0) 346 return; 347 348 for (p = 0; p < 16; p++) 349 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); ··· 680 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { 681 /* Missing "refclk-type" defaults to crystal. */ 682 fdt_nop_property(initial_boot_params, uctl, "refclk-type"); 683 } 684 } 685
··· 171 static struct of_device_id __initdata octeon_ids[] = { 172 { .compatible = "simple-bus", }, 173 { .compatible = "cavium,octeon-6335-uctl", }, 174 + { .compatible = "cavium,octeon-5750-usbn", }, 175 { .compatible = "cavium,octeon-3860-bootbus", }, 176 { .compatible = "cavium,mdio-mux", }, 177 { .compatible = "gpio-leds", }, ··· 336 int p; 337 int count = 0; 338 339 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); 340 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); 341 if (iface < 0) 342 return; 343 + 344 + if (cvmx_helper_interface_enumerate(idx) == 0) 345 + count = cvmx_helper_ports_on_interface(idx); 346 347 for (p = 0; p < 16; p++) 348 octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); ··· 679 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { 680 /* Missing "refclk-type" defaults to crystal. */ 681 fdt_nop_property(initial_boot_params, uctl, "refclk-type"); 682 + } 683 + } 684 + 685 + /* DWC2 USB */ 686 + alias_prop = fdt_getprop(initial_boot_params, aliases, 687 + "usbn", NULL); 688 + if (alias_prop) { 689 + int usbn = fdt_path_offset(initial_boot_params, alias_prop); 690 + 691 + if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 || 692 + !octeon_has_feature(OCTEON_FEATURE_USB))) { 693 + pr_debug("Deleting usbn\n"); 694 + fdt_nop_node(initial_boot_params, usbn); 695 + fdt_nop_property(initial_boot_params, aliases, "usbn"); 696 + } else { 697 + __be32 new_f[1]; 698 + enum cvmx_helper_board_usb_clock_types c; 699 + c = __cvmx_helper_board_usb_get_clock_type(); 700 + switch (c) { 701 + case USB_CLOCK_TYPE_REF_48: 702 + new_f[0] = cpu_to_be32(48000000); 703 + fdt_setprop_inplace(initial_boot_params, usbn, 704 + "refclk-frequency", new_f, sizeof(new_f)); 705 + /* Fall through ...*/ 706 + case USB_CLOCK_TYPE_REF_12: 707 + /* Missing "refclk-type" defaults to external. */ 708 + fdt_nop_property(initial_boot_params, usbn, "refclk-type"); 709 + break; 710 + default: 711 + break; 712 + } 713 } 714 } 715
+19
arch/mips/cavium-octeon/octeon_3xxx.dts
··· 550 big-endian-regs; 551 }; 552 }; 553 }; 554 555 aliases { ··· 584 flash0 = &flash0; 585 cf0 = &cf0; 586 uctl = &uctl; 587 led0 = &led0; 588 }; 589 };
··· 550 big-endian-regs; 551 }; 552 }; 553 + 554 + usbn: usbn@1180068000000 { 555 + compatible = "cavium,octeon-5750-usbn"; 556 + reg = <0x11800 0x68000000 0x0 0x1000>; 557 + ranges; /* Direct mapping */ 558 + #address-cells = <2>; 559 + #size-cells = <2>; 560 + /* 12MHz, 24MHz and 48MHz allowed */ 561 + refclk-frequency = <12000000>; 562 + /* Either "crystal" or "external" */ 563 + refclk-type = "crystal"; 564 + 565 + usbc@16f0010000000 { 566 + compatible = "cavium,octeon-5750-usbc"; 567 + reg = <0x16f00 0x10000000 0x0 0x80000>; 568 + interrupts = <0 56>; 569 + }; 570 + }; 571 }; 572 573 aliases { ··· 566 flash0 = &flash0; 567 cf0 = &cf0; 568 uctl = &uctl; 569 + usbn = &usbn; 570 led0 = &led0; 571 }; 572 };
-1
arch/mips/cavium-octeon/smp.c
··· 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 - #include <linux/init.h> 10 #include <linux/delay.h> 11 #include <linux/smp.h> 12 #include <linux/interrupt.h>
··· 6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks 7 */ 8 #include <linux/cpu.h> 9 #include <linux/delay.h> 10 #include <linux/smp.h> 11 #include <linux/interrupt.h>
-1
arch/mips/configs/ar7_defconfig
··· 86 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 87 # CONFIG_FIRMWARE_IN_KERNEL is not set 88 CONFIG_MTD=y 89 - CONFIG_MTD_PARTITIONS=y 90 CONFIG_MTD_CHAR=y 91 CONFIG_MTD_BLOCK=y 92 CONFIG_MTD_CFI=y
··· 86 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 87 # CONFIG_FIRMWARE_IN_KERNEL is not set 88 CONFIG_MTD=y 89 CONFIG_MTD_CHAR=y 90 CONFIG_MTD_BLOCK=y 91 CONFIG_MTD_CFI=y
+43 -580
arch/mips/configs/bcm47xx_defconfig
··· 1 CONFIG_BCM47XX=y 2 - CONFIG_NO_HZ=y 3 - CONFIG_HIGH_RES_TIMERS=y 4 - CONFIG_KEXEC=y 5 - # CONFIG_SECCOMP is not set 6 - CONFIG_EXPERIMENTAL=y 7 - # CONFIG_LOCALVERSION_AUTO is not set 8 CONFIG_SYSVIPC=y 9 - CONFIG_POSIX_MQUEUE=y 10 - CONFIG_BSD_PROCESS_ACCT=y 11 - CONFIG_BSD_PROCESS_ACCT_V3=y 12 - CONFIG_TASKSTATS=y 13 - CONFIG_TASK_DELAY_ACCT=y 14 - CONFIG_TASK_XACCT=y 15 - CONFIG_TASK_IO_ACCOUNTING=y 16 - CONFIG_AUDIT=y 17 - CONFIG_TINY_RCU=y 18 - CONFIG_CGROUPS=y 19 - CONFIG_CGROUP_CPUACCT=y 20 - CONFIG_RELAY=y 21 CONFIG_BLK_DEV_INITRD=y 22 - CONFIG_RD_LZMA=y 23 - CONFIG_EXPERT=y 24 CONFIG_SLAB=y 25 CONFIG_MODULES=y 26 CONFIG_MODULE_UNLOAD=y 27 - CONFIG_MODULE_FORCE_UNLOAD=y 28 - CONFIG_MODVERSIONS=y 29 - # CONFIG_BLK_DEV_BSG is not set 30 CONFIG_PCI=y 31 - CONFIG_BINFMT_MISC=m 32 CONFIG_NET=y 33 CONFIG_PACKET=y 34 CONFIG_UNIX=y 35 - CONFIG_XFRM_USER=m 36 - CONFIG_NET_KEY=m 37 CONFIG_INET=y 38 CONFIG_IP_MULTICAST=y 39 CONFIG_IP_ADVANCED_ROUTER=y 40 CONFIG_IP_MULTIPLE_TABLES=y 41 CONFIG_IP_ROUTE_MULTIPATH=y 42 - CONFIG_IP_ROUTE_VERBOSE=y 43 - CONFIG_NET_IPIP=m 44 - CONFIG_NET_IPGRE=m 45 - CONFIG_NET_IPGRE_BROADCAST=y 46 CONFIG_IP_MROUTE=y 47 - CONFIG_IP_PIMSM_V1=y 48 - CONFIG_IP_PIMSM_V2=y 49 CONFIG_SYN_COOKIES=y 50 - CONFIG_INET_AH=m 51 - CONFIG_INET_ESP=m 52 - CONFIG_INET_IPCOMP=m 53 - CONFIG_INET_XFRM_MODE_TRANSPORT=m 54 - CONFIG_INET_XFRM_MODE_TUNNEL=m 55 - CONFIG_INET_XFRM_MODE_BEET=m 56 - CONFIG_INET_DIAG=m 57 CONFIG_TCP_CONG_ADVANCED=y 58 - CONFIG_TCP_CONG_BIC=y 59 - CONFIG_TCP_CONG_CUBIC=m 60 - CONFIG_TCP_CONG_HSTCP=m 61 - CONFIG_TCP_CONG_HYBLA=m 62 - CONFIG_TCP_CONG_SCALABLE=m 63 - CONFIG_TCP_CONG_LP=m 64 - CONFIG_TCP_CONG_VENO=m 65 - CONFIG_TCP_CONG_YEAH=m 66 - CONFIG_TCP_CONG_ILLINOIS=m 67 CONFIG_IPV6_PRIVACY=y 68 - CONFIG_INET6_AH=m 69 - CONFIG_INET6_ESP=m 70 - CONFIG_INET6_IPCOMP=m 71 - CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m 72 - CONFIG_IPV6_TUNNEL=m 73 CONFIG_IPV6_MULTIPLE_TABLES=y 74 CONFIG_IPV6_SUBTREES=y 75 - CONFIG_NETWORK_SECMARK=y 76 CONFIG_NETFILTER=y 77 - CONFIG_NETFILTER_NETLINK_QUEUE=m 78 - CONFIG_NF_CONNTRACK=m 79 - CONFIG_NF_CONNTRACK_SECMARK=y 80 - CONFIG_NF_CONNTRACK_EVENTS=y 81 - CONFIG_NF_CT_PROTO_UDPLITE=m 82 - CONFIG_NF_CONNTRACK_AMANDA=m 83 - CONFIG_NF_CONNTRACK_FTP=m 84 - CONFIG_NF_CONNTRACK_H323=m 85 - CONFIG_NF_CONNTRACK_IRC=m 86 - CONFIG_NF_CONNTRACK_NETBIOS_NS=m 87 - CONFIG_NF_CONNTRACK_PPTP=m 88 - CONFIG_NF_CONNTRACK_SANE=m 89 - CONFIG_NF_CONNTRACK_SIP=m 90 - CONFIG_NF_CONNTRACK_TFTP=m 91 - CONFIG_NF_CT_NETLINK=m 92 - CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m 93 - CONFIG_NETFILTER_XT_TARGET_CONNMARK=m 94 - CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m 95 - CONFIG_NETFILTER_XT_TARGET_DSCP=m 96 - CONFIG_NETFILTER_XT_TARGET_MARK=m 97 - CONFIG_NETFILTER_XT_TARGET_NFLOG=m 98 - CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m 99 - CONFIG_NETFILTER_XT_TARGET_TRACE=m 100 - CONFIG_NETFILTER_XT_TARGET_SECMARK=m 101 - CONFIG_NETFILTER_XT_TARGET_TCPMSS=m 102 - CONFIG_NETFILTER_XT_MATCH_COMMENT=m 103 - CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m 104 - CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m 105 - CONFIG_NETFILTER_XT_MATCH_CONNMARK=m 106 - CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m 107 - CONFIG_NETFILTER_XT_MATCH_DSCP=m 108 - CONFIG_NETFILTER_XT_MATCH_ESP=m 109 - CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m 110 - CONFIG_NETFILTER_XT_MATCH_HELPER=m 111 - CONFIG_NETFILTER_XT_MATCH_LENGTH=m 112 - CONFIG_NETFILTER_XT_MATCH_LIMIT=m 113 - CONFIG_NETFILTER_XT_MATCH_MAC=m 114 - CONFIG_NETFILTER_XT_MATCH_MARK=m 115 - CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m 116 - CONFIG_NETFILTER_XT_MATCH_POLICY=m 117 - CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m 118 - CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m 119 - CONFIG_NETFILTER_XT_MATCH_QUOTA=m 120 - CONFIG_NETFILTER_XT_MATCH_REALM=m 121 - CONFIG_NETFILTER_XT_MATCH_STATE=m 122 - CONFIG_NETFILTER_XT_MATCH_STATISTIC=m 123 - CONFIG_NETFILTER_XT_MATCH_STRING=m 124 - CONFIG_NETFILTER_XT_MATCH_TCPMSS=m 125 - CONFIG_NETFILTER_XT_MATCH_TIME=m 126 - CONFIG_NETFILTER_XT_MATCH_U32=m 127 - CONFIG_IP_VS=m 128 - CONFIG_IP_VS_PROTO_TCP=y 129 - CONFIG_IP_VS_PROTO_UDP=y 130 - CONFIG_IP_VS_PROTO_ESP=y 131 - CONFIG_IP_VS_PROTO_AH=y 132 - CONFIG_IP_VS_RR=m 133 - CONFIG_IP_VS_WRR=m 134 - CONFIG_IP_VS_LC=m 135 - CONFIG_IP_VS_WLC=m 136 - CONFIG_IP_VS_LBLC=m 137 - CONFIG_IP_VS_LBLCR=m 138 - CONFIG_IP_VS_DH=m 139 - CONFIG_IP_VS_SH=m 140 - CONFIG_IP_VS_SED=m 141 - CONFIG_IP_VS_NQ=m 142 - CONFIG_IP_VS_FTP=m 143 - CONFIG_NF_CONNTRACK_IPV4=m 144 - CONFIG_IP_NF_QUEUE=m 145 - CONFIG_IP_NF_IPTABLES=m 146 - CONFIG_IP_NF_MATCH_ADDRTYPE=m 147 - CONFIG_IP_NF_MATCH_AH=m 148 - CONFIG_IP_NF_MATCH_ECN=m 149 - CONFIG_IP_NF_MATCH_TTL=m 150 - CONFIG_IP_NF_FILTER=m 151 - CONFIG_IP_NF_TARGET_REJECT=m 152 - CONFIG_IP_NF_TARGET_LOG=m 153 - CONFIG_IP_NF_TARGET_ULOG=m 154 - CONFIG_NF_NAT=m 155 - CONFIG_IP_NF_TARGET_MASQUERADE=m 156 - CONFIG_IP_NF_TARGET_NETMAP=m 157 - CONFIG_IP_NF_TARGET_REDIRECT=m 158 - CONFIG_NF_NAT_SNMP_BASIC=m 159 - CONFIG_IP_NF_MANGLE=m 160 - CONFIG_IP_NF_TARGET_CLUSTERIP=m 161 - CONFIG_IP_NF_TARGET_ECN=m 162 - CONFIG_IP_NF_TARGET_TTL=m 163 - CONFIG_IP_NF_RAW=m 164 - CONFIG_IP_NF_ARPTABLES=m 165 - CONFIG_IP_NF_ARPFILTER=m 166 - CONFIG_IP_NF_ARP_MANGLE=m 167 - CONFIG_NF_CONNTRACK_IPV6=m 168 - CONFIG_IP6_NF_QUEUE=m 169 - CONFIG_IP6_NF_IPTABLES=m 170 - CONFIG_IP6_NF_MATCH_AH=m 171 - CONFIG_IP6_NF_MATCH_EUI64=m 172 - CONFIG_IP6_NF_MATCH_FRAG=m 173 - CONFIG_IP6_NF_MATCH_OPTS=m 174 - CONFIG_IP6_NF_MATCH_HL=m 175 - CONFIG_IP6_NF_MATCH_IPV6HEADER=m 176 - CONFIG_IP6_NF_MATCH_MH=m 177 - CONFIG_IP6_NF_MATCH_RT=m 178 - CONFIG_IP6_NF_TARGET_HL=m 179 - CONFIG_IP6_NF_TARGET_LOG=m 180 - CONFIG_IP6_NF_FILTER=m 181 - CONFIG_IP6_NF_TARGET_REJECT=m 182 - CONFIG_IP6_NF_MANGLE=m 183 - CONFIG_IP6_NF_RAW=m 184 - CONFIG_BRIDGE_NF_EBTABLES=m 185 - CONFIG_BRIDGE_EBT_BROUTE=m 186 - CONFIG_BRIDGE_EBT_T_FILTER=m 187 - CONFIG_BRIDGE_EBT_T_NAT=m 188 - CONFIG_BRIDGE_EBT_802_3=m 189 - CONFIG_BRIDGE_EBT_AMONG=m 190 - CONFIG_BRIDGE_EBT_ARP=m 191 - CONFIG_BRIDGE_EBT_IP=m 192 - CONFIG_BRIDGE_EBT_LIMIT=m 193 - CONFIG_BRIDGE_EBT_MARK=m 194 - CONFIG_BRIDGE_EBT_PKTTYPE=m 195 - CONFIG_BRIDGE_EBT_STP=m 196 - CONFIG_BRIDGE_EBT_VLAN=m 197 - CONFIG_BRIDGE_EBT_ARPREPLY=m 198 - CONFIG_BRIDGE_EBT_DNAT=m 199 - CONFIG_BRIDGE_EBT_MARK_T=m 200 - CONFIG_BRIDGE_EBT_REDIRECT=m 201 - CONFIG_BRIDGE_EBT_SNAT=m 202 - CONFIG_BRIDGE_EBT_LOG=m 203 - CONFIG_BRIDGE_EBT_ULOG=m 204 - CONFIG_IP_DCCP=m 205 - CONFIG_TIPC=m 206 - CONFIG_TIPC_ADVANCED=y 207 - CONFIG_ATM=m 208 - CONFIG_ATM_CLIP=m 209 - CONFIG_ATM_LANE=m 210 - CONFIG_ATM_MPOA=m 211 - CONFIG_ATM_BR2684=m 212 - CONFIG_BRIDGE=m 213 - CONFIG_VLAN_8021Q=m 214 CONFIG_NET_SCHED=y 215 - CONFIG_NET_SCH_CBQ=m 216 - CONFIG_NET_SCH_HTB=m 217 - CONFIG_NET_SCH_HFSC=m 218 - CONFIG_NET_SCH_ATM=m 219 - CONFIG_NET_SCH_PRIO=m 220 - CONFIG_NET_SCH_RED=m 221 - CONFIG_NET_SCH_SFQ=m 222 - CONFIG_NET_SCH_TEQL=m 223 - CONFIG_NET_SCH_TBF=m 224 - CONFIG_NET_SCH_GRED=m 225 - CONFIG_NET_SCH_DSMARK=m 226 - CONFIG_NET_SCH_NETEM=m 227 - CONFIG_NET_SCH_INGRESS=m 228 - CONFIG_NET_CLS_BASIC=m 229 - CONFIG_NET_CLS_TCINDEX=m 230 - CONFIG_NET_CLS_ROUTE4=m 231 - CONFIG_NET_CLS_FW=m 232 - CONFIG_NET_CLS_U32=m 233 - CONFIG_CLS_U32_PERF=y 234 - CONFIG_CLS_U32_MARK=y 235 - CONFIG_NET_CLS_RSVP=m 236 - CONFIG_NET_CLS_RSVP6=m 237 - CONFIG_NET_EMATCH=y 238 - CONFIG_NET_EMATCH_CMP=m 239 - CONFIG_NET_EMATCH_NBYTE=m 240 - CONFIG_NET_EMATCH_U32=m 241 - CONFIG_NET_EMATCH_META=m 242 - CONFIG_NET_EMATCH_TEXT=m 243 - CONFIG_NET_CLS_ACT=y 244 - CONFIG_NET_ACT_POLICE=m 245 - CONFIG_NET_ACT_GACT=m 246 - CONFIG_GACT_PROB=y 247 - CONFIG_NET_ACT_MIRRED=m 248 - CONFIG_NET_ACT_IPT=m 249 - CONFIG_NET_ACT_NAT=m 250 - CONFIG_NET_ACT_PEDIT=m 251 - CONFIG_NET_ACT_SIMP=m 252 - CONFIG_NET_CLS_IND=y 253 - CONFIG_NET_PKTGEN=m 254 - CONFIG_BT=m 255 - CONFIG_BT_HCIUART=m 256 - CONFIG_BT_HCIUART_H4=y 257 - CONFIG_BT_HCIUART_BCSP=y 258 - CONFIG_BT_HCIUART_LL=y 259 - CONFIG_BT_HCIBCM203X=m 260 - CONFIG_BT_HCIBPA10X=m 261 - CONFIG_BT_HCIBFUSB=m 262 - CONFIG_BT_HCIVHCI=m 263 - CONFIG_CFG80211=m 264 - CONFIG_MAC80211=m 265 - CONFIG_MAC80211_RC_PID=y 266 - CONFIG_MAC80211_RC_DEFAULT_PID=y 267 - CONFIG_MAC80211_MESH=y 268 - CONFIG_RFKILL=m 269 - CONFIG_RFKILL_INPUT=y 270 - CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 271 - CONFIG_FW_LOADER=m 272 - CONFIG_CONNECTOR=m 273 CONFIG_MTD=y 274 - CONFIG_MTD_CONCAT=y 275 - CONFIG_MTD_PARTITIONS=y 276 - CONFIG_MTD_CHAR=y 277 CONFIG_MTD_BLOCK=y 278 CONFIG_MTD_CFI=y 279 CONFIG_MTD_CFI_INTELEXT=y 280 CONFIG_MTD_CFI_AMDSTD=y 281 - CONFIG_MTD_CFI_STAA=y 282 - CONFIG_MTD_RAM=y 283 - CONFIG_MTD_ROM=y 284 - CONFIG_MTD_ABSENT=y 285 CONFIG_MTD_PHYSMAP=y 286 - CONFIG_BLK_DEV_LOOP=m 287 - CONFIG_BLK_DEV_CRYPTOLOOP=m 288 - CONFIG_BLK_DEV_NBD=m 289 - CONFIG_BLK_DEV_RAM=y 290 - CONFIG_BLK_DEV_RAM_SIZE=16384 291 - CONFIG_ATA_OVER_ETH=m 292 - CONFIG_RAID_ATTRS=m 293 - CONFIG_SCSI=y 294 - CONFIG_SCSI_TGT=m 295 - CONFIG_BLK_DEV_SD=y 296 - CONFIG_CHR_DEV_ST=m 297 - CONFIG_CHR_DEV_OSST=m 298 - CONFIG_BLK_DEV_SR=m 299 - CONFIG_BLK_DEV_SR_VENDOR=y 300 - CONFIG_CHR_DEV_SG=m 301 - CONFIG_CHR_DEV_SCH=m 302 - CONFIG_SCSI_MULTI_LUN=y 303 - CONFIG_SCSI_CONSTANTS=y 304 - CONFIG_SCSI_LOGGING=y 305 - CONFIG_SCSI_SCAN_ASYNC=y 306 - CONFIG_ISCSI_TCP=m 307 CONFIG_NETDEVICES=y 308 - CONFIG_DUMMY=m 309 - CONFIG_EQUALIZER=m 310 - CONFIG_TUN=m 311 - CONFIG_VETH=m 312 - CONFIG_PHYLIB=m 313 - CONFIG_MARVELL_PHY=m 314 - CONFIG_DAVICOM_PHY=m 315 - CONFIG_QSEMI_PHY=m 316 - CONFIG_LXT_PHY=m 317 - CONFIG_CICADA_PHY=m 318 - CONFIG_VITESSE_PHY=m 319 - CONFIG_SMSC_PHY=m 320 - CONFIG_BROADCOM_PHY=m 321 - CONFIG_ICPLUS_PHY=m 322 - CONFIG_MDIO_BITBANG=m 323 - CONFIG_NET_ETHERNET=y 324 - CONFIG_NET_PCI=y 325 CONFIG_B44=y 326 - # CONFIG_NETDEV_1000 is not set 327 - # CONFIG_NETDEV_10000 is not set 328 - CONFIG_ATH_COMMON=m 329 - CONFIG_ATH5K=m 330 - CONFIG_B43=m 331 - CONFIG_B43LEGACY=m 332 - CONFIG_ZD1211RW=m 333 - CONFIG_USB_CATC=m 334 - CONFIG_USB_KAWETH=m 335 - CONFIG_USB_PEGASUS=m 336 - CONFIG_USB_RTL8150=m 337 - CONFIG_USB_USBNET=m 338 - CONFIG_USB_NET_DM9601=m 339 - CONFIG_USB_NET_GL620A=m 340 - CONFIG_USB_NET_PLUSB=m 341 - CONFIG_USB_NET_MCS7830=m 342 - CONFIG_USB_NET_RNDIS_HOST=m 343 - CONFIG_USB_ALI_M5632=y 344 - CONFIG_USB_AN2720=y 345 - CONFIG_USB_EPSON2888=y 346 - CONFIG_USB_KC2190=y 347 - CONFIG_USB_SIERRA_NET=m 348 - CONFIG_ATM_DUMMY=m 349 - CONFIG_ATM_TCP=m 350 - CONFIG_PPP=m 351 - CONFIG_PPP_ASYNC=m 352 - CONFIG_PPP_DEFLATE=m 353 - CONFIG_PPP_BSDCOMP=m 354 - CONFIG_PPP_MPPE=m 355 - CONFIG_PPPOE=m 356 - CONFIG_PPPOATM=m 357 - CONFIG_SLIP=m 358 - CONFIG_INPUT_EVDEV=m 359 - # CONFIG_INPUT_KEYBOARD is not set 360 - # CONFIG_INPUT_MOUSE is not set 361 - # CONFIG_SERIO is not set 362 - # CONFIG_VT is not set 363 CONFIG_SERIAL_8250=y 364 CONFIG_SERIAL_8250_CONSOLE=y 365 # CONFIG_SERIAL_8250_PCI is not set 366 CONFIG_SERIAL_8250_NR_UARTS=2 367 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 368 - # CONFIG_LEGACY_PTYS is not set 369 - # CONFIG_HW_RANDOM is not set 370 - CONFIG_W1=m 371 - CONFIG_W1_MASTER_MATROX=m 372 - CONFIG_W1_MASTER_DS2490=m 373 - CONFIG_W1_SLAVE_THERM=m 374 - CONFIG_W1_SLAVE_SMEM=m 375 - CONFIG_W1_SLAVE_DS2433=m 376 - CONFIG_W1_SLAVE_DS2760=m 377 - # CONFIG_HWMON is not set 378 - CONFIG_THERMAL=y 379 CONFIG_WATCHDOG=y 380 - CONFIG_WATCHDOG_NOWAYOUT=y 381 CONFIG_BCM47XX_WDT=y 382 CONFIG_SSB_DRIVER_GIGE=y 383 - CONFIG_DISPLAY_SUPPORT=m 384 - CONFIG_SOUND=m 385 - CONFIG_SND=m 386 - CONFIG_SND_SEQUENCER=m 387 - CONFIG_SND_SEQ_DUMMY=m 388 - CONFIG_SND_MIXER_OSS=m 389 - CONFIG_SND_PCM_OSS=m 390 - CONFIG_SND_SEQUENCER_OSS=y 391 - CONFIG_SND_DUMMY=m 392 - CONFIG_SND_VIRMIDI=m 393 - CONFIG_SND_USB_AUDIO=m 394 - CONFIG_HID=m 395 - CONFIG_USB_HID=m 396 - CONFIG_USB_HIDDEV=y 397 CONFIG_USB=y 398 - CONFIG_USB_DEVICEFS=y 399 - # CONFIG_USB_DEVICE_CLASS is not set 400 - CONFIG_USB_EHCI_HCD=y 401 - CONFIG_USB_EHCI_ROOT_HUB_TT=y 402 - CONFIG_USB_OHCI_HCD=y 403 - CONFIG_USB_U132_HCD=m 404 - CONFIG_USB_R8A66597_HCD=m 405 - CONFIG_USB_ACM=m 406 - CONFIG_USB_PRINTER=m 407 - CONFIG_USB_STORAGE=y 408 - CONFIG_USB_STORAGE_DATAFAB=y 409 - CONFIG_USB_STORAGE_FREECOM=y 410 - CONFIG_USB_STORAGE_USBAT=y 411 - CONFIG_USB_STORAGE_SDDR09=y 412 - CONFIG_USB_STORAGE_SDDR55=y 413 - CONFIG_USB_STORAGE_JUMPSHOT=y 414 - CONFIG_USB_STORAGE_ALAUDA=y 415 - CONFIG_USB_STORAGE_ONETOUCH=y 416 - CONFIG_USB_STORAGE_KARMA=y 417 - CONFIG_USB_MDC800=m 418 - CONFIG_USB_MICROTEK=m 419 - CONFIG_USB_SERIAL=m 420 - CONFIG_USB_SERIAL_GENERIC=y 421 - CONFIG_USB_SERIAL_AIRCABLE=m 422 - CONFIG_USB_SERIAL_ARK3116=m 423 - CONFIG_USB_SERIAL_BELKIN=m 424 - CONFIG_USB_SERIAL_CH341=m 425 - CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m 426 - CONFIG_USB_SERIAL_CYPRESS_M8=m 427 - CONFIG_USB_SERIAL_EMPEG=m 428 - CONFIG_USB_SERIAL_FTDI_SIO=m 429 - CONFIG_USB_SERIAL_FUNSOFT=m 430 - CONFIG_USB_SERIAL_VISOR=m 431 - CONFIG_USB_SERIAL_IPAQ=m 432 - CONFIG_USB_SERIAL_IR=m 433 - CONFIG_USB_SERIAL_GARMIN=m 434 - CONFIG_USB_SERIAL_IPW=m 435 - CONFIG_USB_SERIAL_KEYSPAN_PDA=m 436 - CONFIG_USB_SERIAL_KLSI=m 437 - CONFIG_USB_SERIAL_KOBIL_SCT=m 438 - CONFIG_USB_SERIAL_MCT_U232=m 439 - CONFIG_USB_SERIAL_MOS7720=m 440 - CONFIG_USB_SERIAL_MOS7840=m 441 - CONFIG_USB_SERIAL_NAVMAN=m 442 - CONFIG_USB_SERIAL_PL2303=m 443 - CONFIG_USB_SERIAL_OTI6858=m 444 - CONFIG_USB_SERIAL_HP4X=m 445 - CONFIG_USB_SERIAL_SAFE=m 446 - CONFIG_USB_SERIAL_SIERRAWIRELESS=m 447 - CONFIG_USB_SERIAL_CYBERJACK=m 448 - CONFIG_USB_SERIAL_XIRCOM=m 449 - CONFIG_USB_SERIAL_OPTION=m 450 - CONFIG_USB_SERIAL_OMNINET=m 451 - CONFIG_USB_SERIAL_DEBUG=m 452 - CONFIG_USB_ADUTUX=m 453 - CONFIG_USB_RIO500=m 454 - CONFIG_USB_LEGOTOWER=m 455 - CONFIG_USB_LCD=m 456 - CONFIG_USB_LED=m 457 - CONFIG_USB_CYPRESS_CY7C63=m 458 - CONFIG_USB_CYTHERM=m 459 - CONFIG_USB_IDMOUSE=m 460 - CONFIG_USB_FTDI_ELAN=m 461 - CONFIG_USB_SISUSBVGA=m 462 - CONFIG_USB_LD=m 463 - CONFIG_USB_TRANCEVIBRATOR=m 464 - CONFIG_USB_IOWARRIOR=m 465 - CONFIG_USB_TEST=m 466 - CONFIG_USB_ATM=m 467 - CONFIG_USB_SPEEDTOUCH=m 468 - CONFIG_USB_CXACRU=m 469 - CONFIG_USB_UEAGLEATM=m 470 - CONFIG_USB_XUSBATM=m 471 - CONFIG_USB_GADGET=m 472 - CONFIG_USB_GADGET_NET2280=y 473 - CONFIG_USB_ZERO=m 474 - CONFIG_USB_ETH=m 475 - CONFIG_USB_GADGETFS=m 476 - CONFIG_USB_MASS_STORAGE=m 477 - CONFIG_USB_G_SERIAL=m 478 - CONFIG_USB_MIDI_GADGET=m 479 - CONFIG_LEDS_CLASS=y 480 - CONFIG_LEDS_GPIO=y 481 CONFIG_LEDS_TRIGGER_TIMER=y 482 - CONFIG_LEDS_TRIGGER_HEARTBEAT=y 483 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 484 - CONFIG_EXT2_FS=y 485 - CONFIG_EXT2_FS_XATTR=y 486 - CONFIG_EXT2_FS_POSIX_ACL=y 487 - CONFIG_EXT2_FS_SECURITY=y 488 - CONFIG_EXT3_FS=y 489 - # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 490 - CONFIG_EXT3_FS_POSIX_ACL=y 491 - CONFIG_EXT3_FS_SECURITY=y 492 - CONFIG_REISERFS_FS=m 493 - CONFIG_REISERFS_FS_XATTR=y 494 - CONFIG_REISERFS_FS_POSIX_ACL=y 495 - CONFIG_REISERFS_FS_SECURITY=y 496 - CONFIG_JFS_FS=m 497 - CONFIG_JFS_POSIX_ACL=y 498 - CONFIG_JFS_SECURITY=y 499 - CONFIG_XFS_FS=m 500 - CONFIG_XFS_QUOTA=y 501 - CONFIG_XFS_POSIX_ACL=y 502 - CONFIG_XFS_RT=y 503 - CONFIG_GFS2_FS=m 504 - CONFIG_QUOTA=y 505 - CONFIG_QUOTA_NETLINK_INTERFACE=y 506 - CONFIG_QFMT_V1=m 507 - CONFIG_QFMT_V2=m 508 - CONFIG_AUTOFS_FS=m 509 - CONFIG_AUTOFS4_FS=m 510 - CONFIG_FUSE_FS=m 511 - CONFIG_ISO9660_FS=m 512 - CONFIG_JOLIET=y 513 - CONFIG_ZISOFS=y 514 - CONFIG_UDF_FS=m 515 - CONFIG_MSDOS_FS=m 516 - CONFIG_VFAT_FS=m 517 - CONFIG_NTFS_FS=m 518 - CONFIG_NTFS_RW=y 519 - CONFIG_PROC_KCORE=y 520 - CONFIG_TMPFS=y 521 - CONFIG_TMPFS_POSIX_ACL=y 522 - CONFIG_ADFS_FS=m 523 - CONFIG_AFFS_FS=m 524 - CONFIG_HFS_FS=m 525 - CONFIG_HFSPLUS_FS=m 526 - CONFIG_BEFS_FS=m 527 - CONFIG_BFS_FS=m 528 - CONFIG_EFS_FS=m 529 - CONFIG_JFFS2_FS=m 530 - CONFIG_JFFS2_FS_XATTR=y 531 - CONFIG_CRAMFS=m 532 - CONFIG_VXFS_FS=m 533 - CONFIG_MINIX_FS=m 534 - CONFIG_HPFS_FS=m 535 - CONFIG_QNX4FS_FS=m 536 - CONFIG_ROMFS_FS=m 537 - CONFIG_SYSV_FS=m 538 - CONFIG_UFS_FS=m 539 - CONFIG_NFS_FS=m 540 - CONFIG_NFS_V3=y 541 - CONFIG_NFS_V3_ACL=y 542 - CONFIG_NFS_V4=y 543 - CONFIG_NFSD=m 544 - CONFIG_NFSD_V3_ACL=y 545 - CONFIG_NFSD_V4=y 546 - CONFIG_RPCSEC_GSS_SPKM3=m 547 - CONFIG_CIFS=m 548 - CONFIG_CIFS_XATTR=y 549 - CONFIG_CIFS_POSIX=y 550 - CONFIG_NCP_FS=m 551 - CONFIG_NCPFS_NFS_NS=y 552 - CONFIG_NCPFS_OS2_NS=y 553 - CONFIG_NCPFS_NLS=y 554 - CONFIG_NCPFS_EXTRAS=y 555 - CONFIG_CODA_FS=m 556 - CONFIG_PARTITION_ADVANCED=y 557 - CONFIG_KARMA_PARTITION=y 558 - CONFIG_NLS_CODEPAGE_437=m 559 - CONFIG_NLS_CODEPAGE_737=m 560 - CONFIG_NLS_CODEPAGE_775=m 561 - CONFIG_NLS_CODEPAGE_850=m 562 - CONFIG_NLS_CODEPAGE_852=m 563 - CONFIG_NLS_CODEPAGE_855=m 564 - CONFIG_NLS_CODEPAGE_857=m 565 - CONFIG_NLS_CODEPAGE_860=m 566 - CONFIG_NLS_CODEPAGE_861=m 567 - CONFIG_NLS_CODEPAGE_862=m 568 - CONFIG_NLS_CODEPAGE_863=m 569 - CONFIG_NLS_CODEPAGE_864=m 570 - CONFIG_NLS_CODEPAGE_865=m 571 - CONFIG_NLS_CODEPAGE_866=m 572 - CONFIG_NLS_CODEPAGE_869=m 573 - CONFIG_NLS_CODEPAGE_936=m 574 - CONFIG_NLS_CODEPAGE_950=m 575 - CONFIG_NLS_CODEPAGE_932=m 576 - CONFIG_NLS_CODEPAGE_949=m 577 - CONFIG_NLS_CODEPAGE_874=m 578 - CONFIG_NLS_ISO8859_8=m 579 - CONFIG_NLS_CODEPAGE_1250=m 580 - CONFIG_NLS_CODEPAGE_1251=m 581 - CONFIG_NLS_ASCII=m 582 - CONFIG_NLS_ISO8859_1=m 583 - CONFIG_NLS_ISO8859_2=m 584 - CONFIG_NLS_ISO8859_3=m 585 - CONFIG_NLS_ISO8859_4=m 586 - CONFIG_NLS_ISO8859_5=m 587 - CONFIG_NLS_ISO8859_6=m 588 - CONFIG_NLS_ISO8859_7=m 589 - CONFIG_NLS_ISO8859_9=m 590 - CONFIG_NLS_ISO8859_13=m 591 - CONFIG_NLS_ISO8859_14=m 592 - CONFIG_NLS_ISO8859_15=m 593 - CONFIG_NLS_KOI8_R=m 594 - CONFIG_NLS_KOI8_U=m 595 - CONFIG_DLM=m 596 - CONFIG_DLM_DEBUG=y 597 CONFIG_DEBUG_FS=y 598 - CONFIG_CRYPTO_NULL=m 599 - CONFIG_CRYPTO_TEST=m 600 - CONFIG_CRYPTO_LRW=m 601 - CONFIG_CRYPTO_PCBC=m 602 - CONFIG_CRYPTO_XTS=m 603 - CONFIG_CRYPTO_HMAC=y 604 - CONFIG_CRYPTO_XCBC=m 605 - CONFIG_CRYPTO_MD4=m 606 - CONFIG_CRYPTO_MD5=y 607 - CONFIG_CRYPTO_MICHAEL_MIC=m 608 - CONFIG_CRYPTO_SHA256=m 609 - CONFIG_CRYPTO_SHA512=m 610 - CONFIG_CRYPTO_TGR192=m 611 - CONFIG_CRYPTO_WP512=m 612 - CONFIG_CRYPTO_ANUBIS=m 613 - CONFIG_CRYPTO_BLOWFISH=m 614 - CONFIG_CRYPTO_CAMELLIA=m 615 - CONFIG_CRYPTO_CAST6=m 616 - CONFIG_CRYPTO_FCRYPT=m 617 - CONFIG_CRYPTO_KHAZAD=m 618 - CONFIG_CRYPTO_SEED=m 619 - CONFIG_CRYPTO_SERPENT=m 620 - CONFIG_CRYPTO_TEA=m 621 - CONFIG_CRYPTO_TWOFISH=m 622 - CONFIG_CRC16=m 623 - CONFIG_CRC7=m
··· 1 CONFIG_BCM47XX=y 2 CONFIG_SYSVIPC=y 3 + CONFIG_HIGH_RES_TIMERS=y 4 + CONFIG_UIDGID_STRICT_TYPE_CHECKS=y 5 CONFIG_BLK_DEV_INITRD=y 6 + CONFIG_CC_OPTIMIZE_FOR_SIZE=y 7 + CONFIG_EMBEDDED=y 8 CONFIG_SLAB=y 9 CONFIG_MODULES=y 10 CONFIG_MODULE_UNLOAD=y 11 + CONFIG_PARTITION_ADVANCED=y 12 CONFIG_PCI=y 13 + # CONFIG_SUSPEND is not set 14 CONFIG_NET=y 15 CONFIG_PACKET=y 16 CONFIG_UNIX=y 17 CONFIG_INET=y 18 CONFIG_IP_MULTICAST=y 19 CONFIG_IP_ADVANCED_ROUTER=y 20 CONFIG_IP_MULTIPLE_TABLES=y 21 CONFIG_IP_ROUTE_MULTIPATH=y 22 CONFIG_IP_MROUTE=y 23 + CONFIG_IP_MROUTE_MULTIPLE_TABLES=y 24 CONFIG_SYN_COOKIES=y 25 CONFIG_TCP_CONG_ADVANCED=y 26 CONFIG_IPV6_PRIVACY=y 27 CONFIG_IPV6_MULTIPLE_TABLES=y 28 CONFIG_IPV6_SUBTREES=y 29 + CONFIG_IPV6_MROUTE=y 30 CONFIG_NETFILTER=y 31 + CONFIG_VLAN_8021Q=y 32 CONFIG_NET_SCHED=y 33 + CONFIG_NET_SCH_FQ_CODEL=y 34 + CONFIG_HAMRADIO=y 35 + CONFIG_CFG80211=y 36 + CONFIG_MAC80211=y 37 CONFIG_MTD=y 38 + CONFIG_MTD_BCM47XX_PARTS=y 39 CONFIG_MTD_BLOCK=y 40 CONFIG_MTD_CFI=y 41 CONFIG_MTD_CFI_INTELEXT=y 42 CONFIG_MTD_CFI_AMDSTD=y 43 + CONFIG_MTD_COMPLEX_MAPPINGS=y 44 CONFIG_MTD_PHYSMAP=y 45 + CONFIG_MTD_BCM47XXSFLASH=y 46 + CONFIG_MTD_NAND=y 47 + CONFIG_MTD_NAND_BCM47XXNFLASH=y 48 CONFIG_NETDEVICES=y 49 CONFIG_B44=y 50 + CONFIG_TIGON3=y 51 + CONFIG_BGMAC=y 52 + CONFIG_ATH_CARDS=y 53 + CONFIG_ATH5K=y 54 + CONFIG_B43=y 55 + CONFIG_B43LEGACY=y 56 + CONFIG_BRCMSMAC=y 57 + CONFIG_ISDN=y 58 CONFIG_SERIAL_8250=y 59 + # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set 60 CONFIG_SERIAL_8250_CONSOLE=y 61 # CONFIG_SERIAL_8250_PCI is not set 62 CONFIG_SERIAL_8250_NR_UARTS=2 63 CONFIG_SERIAL_8250_RUNTIME_UARTS=2 64 + CONFIG_SERIAL_8250_EXTENDED=y 65 + CONFIG_SERIAL_8250_SHARE_IRQ=y 66 + CONFIG_HW_RANDOM=y 67 + CONFIG_GPIO_SYSFS=y 68 CONFIG_WATCHDOG=y 69 CONFIG_BCM47XX_WDT=y 70 + CONFIG_SSB_DEBUG=y 71 CONFIG_SSB_DRIVER_GIGE=y 72 + CONFIG_BCMA_DRIVER_GMAC_CMN=y 73 CONFIG_USB=y 74 + CONFIG_USB_HCD_BCMA=y 75 + CONFIG_USB_HCD_SSB=y 76 CONFIG_LEDS_TRIGGER_TIMER=y 77 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 78 + CONFIG_PRINTK_TIME=y 79 + CONFIG_DEBUG_INFO=y 80 + CONFIG_DEBUG_INFO_REDUCED=y 81 + CONFIG_STRIP_ASM_SYMS=y 82 CONFIG_DEBUG_FS=y 83 + CONFIG_MAGIC_SYSRQ=y 84 + CONFIG_CMDLINE_BOOL=y 85 + CONFIG_CMDLINE="console=ttyS0,115200" 86 + CONFIG_CRC32_SARWATE=y
-1
arch/mips/configs/bcm63xx_defconfig
··· 44 # CONFIG_STANDALONE is not set 45 # CONFIG_PREVENT_FIRMWARE_BUILD is not set 46 CONFIG_MTD=y 47 - CONFIG_MTD_PARTITIONS=y 48 CONFIG_MTD_CFI=y 49 CONFIG_MTD_CFI_INTELEXT=y 50 CONFIG_MTD_CFI_AMDSTD=y
··· 44 # CONFIG_STANDALONE is not set 45 # CONFIG_PREVENT_FIRMWARE_BUILD is not set 46 CONFIG_MTD=y 47 CONFIG_MTD_CFI=y 48 CONFIG_MTD_CFI_INTELEXT=y 49 CONFIG_MTD_CFI_AMDSTD=y
-1
arch/mips/configs/cobalt_defconfig
··· 19 # CONFIG_IPV6 is not set 20 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 21 CONFIG_MTD=y 22 - CONFIG_MTD_PARTITIONS=y 23 CONFIG_MTD_CHAR=y 24 CONFIG_MTD_BLKDEVS=y 25 CONFIG_MTD_JEDECPROBE=y
··· 19 # CONFIG_IPV6 is not set 20 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 21 CONFIG_MTD=y 22 CONFIG_MTD_CHAR=y 23 CONFIG_MTD_BLKDEVS=y 24 CONFIG_MTD_JEDECPROBE=y
-1
arch/mips/configs/gpr_defconfig
··· 165 CONFIG_CFG80211=y 166 CONFIG_MAC80211=y 167 CONFIG_MTD=y 168 - CONFIG_MTD_PARTITIONS=y 169 CONFIG_MTD_CHAR=y 170 CONFIG_MTD_BLOCK=y 171 CONFIG_MTD_CFI=y
··· 165 CONFIG_CFG80211=y 166 CONFIG_MAC80211=y 167 CONFIG_MTD=y 168 CONFIG_MTD_CHAR=y 169 CONFIG_MTD_BLOCK=y 170 CONFIG_MTD_CFI=y
-1
arch/mips/configs/jmr3927_defconfig
··· 22 # CONFIG_INET_DIAG is not set 23 # CONFIG_IPV6 is not set 24 CONFIG_MTD=y 25 - CONFIG_MTD_PARTITIONS=y 26 CONFIG_MTD_CMDLINE_PARTS=y 27 CONFIG_MTD_CHAR=y 28 CONFIG_MTD_CFI=y
··· 22 # CONFIG_INET_DIAG is not set 23 # CONFIG_IPV6 is not set 24 CONFIG_MTD=y 25 CONFIG_MTD_CMDLINE_PARTS=y 26 CONFIG_MTD_CHAR=y 27 CONFIG_MTD_CFI=y
-1
arch/mips/configs/lasat_defconfig
··· 31 # CONFIG_INET_DIAG is not set 32 # CONFIG_IPV6 is not set 33 CONFIG_MTD=y 34 - CONFIG_MTD_PARTITIONS=y 35 CONFIG_MTD_CHAR=y 36 CONFIG_MTD_BLOCK=y 37 CONFIG_MTD_CFI=y
··· 31 # CONFIG_INET_DIAG is not set 32 # CONFIG_IPV6 is not set 33 CONFIG_MTD=y 34 CONFIG_MTD_CHAR=y 35 CONFIG_MTD_BLOCK=y 36 CONFIG_MTD_CFI=y
+1 -2
arch/mips/configs/maltasmvp_defconfig
··· 4 CONFIG_MIPS_MT_SMP=y 5 CONFIG_SCHED_SMT=y 6 CONFIG_MIPS_CMP=y 7 - CONFIG_NR_CPUS=8 8 CONFIG_HZ_100=y 9 CONFIG_LOCALVERSION="cmp" 10 CONFIG_SYSVIPC=y ··· 58 CONFIG_DEV_APPLETALK=m 59 CONFIG_IPDDP=m 60 CONFIG_IPDDP_ENCAP=y 61 - CONFIG_IPDDP_DECAP=y 62 CONFIG_NET_SCHED=y 63 CONFIG_NET_SCH_CBQ=m 64 CONFIG_NET_SCH_HTB=m
··· 4 CONFIG_MIPS_MT_SMP=y 5 CONFIG_SCHED_SMT=y 6 CONFIG_MIPS_CMP=y 7 + CONFIG_NR_CPUS=2 8 CONFIG_HZ_100=y 9 CONFIG_LOCALVERSION="cmp" 10 CONFIG_SYSVIPC=y ··· 58 CONFIG_DEV_APPLETALK=m 59 CONFIG_IPDDP=m 60 CONFIG_IPDDP_ENCAP=y 61 CONFIG_NET_SCHED=y 62 CONFIG_NET_SCH_CBQ=m 63 CONFIG_NET_SCH_HTB=m
-1
arch/mips/configs/markeins_defconfig
··· 124 CONFIG_IP6_NF_RAW=m 125 CONFIG_FW_LOADER=m 126 CONFIG_MTD=y 127 - CONFIG_MTD_PARTITIONS=y 128 CONFIG_MTD_CMDLINE_PARTS=y 129 CONFIG_MTD_CHAR=y 130 CONFIG_MTD_BLOCK=y
··· 124 CONFIG_IP6_NF_RAW=m 125 CONFIG_FW_LOADER=m 126 CONFIG_MTD=y 127 CONFIG_MTD_CMDLINE_PARTS=y 128 CONFIG_MTD_CHAR=y 129 CONFIG_MTD_BLOCK=y
-1
arch/mips/configs/mtx1_defconfig
··· 246 CONFIG_BT_HCIVHCI=m 247 CONFIG_CONNECTOR=m 248 CONFIG_MTD=y 249 - CONFIG_MTD_PARTITIONS=y 250 CONFIG_MTD_CHAR=y 251 CONFIG_MTD_BLOCK=y 252 CONFIG_MTD_CFI=y
··· 246 CONFIG_BT_HCIVHCI=m 247 CONFIG_CONNECTOR=m 248 CONFIG_MTD=y 249 CONFIG_MTD_CHAR=y 250 CONFIG_MTD_BLOCK=y 251 CONFIG_MTD_CFI=y
-1
arch/mips/configs/pnx8335_stb225_defconfig
··· 31 # CONFIG_IPV6 is not set 32 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 33 CONFIG_MTD=y 34 - CONFIG_MTD_PARTITIONS=y 35 CONFIG_MTD_CMDLINE_PARTS=y 36 CONFIG_MTD_CHAR=y 37 CONFIG_MTD_BLOCK=y
··· 31 # CONFIG_IPV6 is not set 32 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 33 CONFIG_MTD=y 34 CONFIG_MTD_CMDLINE_PARTS=y 35 CONFIG_MTD_CHAR=y 36 CONFIG_MTD_BLOCK=y
+188
arch/mips/configs/qi_lb60_defconfig
···
··· 1 + CONFIG_MACH_JZ4740=y 2 + # CONFIG_COMPACTION is not set 3 + # CONFIG_CROSS_MEMORY_ATTACH is not set 4 + CONFIG_HZ_100=y 5 + CONFIG_PREEMPT=y 6 + # CONFIG_SECCOMP is not set 7 + # CONFIG_LOCALVERSION_AUTO is not set 8 + CONFIG_SYSVIPC=y 9 + CONFIG_LOG_BUF_SHIFT=14 10 + CONFIG_SYSCTL_SYSCALL=y 11 + CONFIG_KALLSYMS_ALL=y 12 + CONFIG_EMBEDDED=y 13 + # CONFIG_VM_EVENT_COUNTERS is not set 14 + # CONFIG_COMPAT_BRK is not set 15 + CONFIG_SLAB=y 16 + CONFIG_MODULES=y 17 + CONFIG_MODULE_UNLOAD=y 18 + # CONFIG_BLK_DEV_BSG is not set 19 + CONFIG_PARTITION_ADVANCED=y 20 + # CONFIG_EFI_PARTITION is not set 21 + # CONFIG_IOSCHED_CFQ is not set 22 + # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 23 + CONFIG_NET=y 24 + CONFIG_PACKET=y 25 + CONFIG_UNIX=y 26 + CONFIG_INET=y 27 + CONFIG_IP_MULTICAST=y 28 + CONFIG_IP_ADVANCED_ROUTER=y 29 + CONFIG_IP_MULTIPLE_TABLES=y 30 + CONFIG_IP_ROUTE_MULTIPATH=y 31 + CONFIG_IP_ROUTE_VERBOSE=y 32 + CONFIG_IP_MROUTE=y 33 + CONFIG_IP_MROUTE_MULTIPLE_TABLES=y 34 + # CONFIG_INET_XFRM_MODE_TRANSPORT is not set 35 + # CONFIG_INET_XFRM_MODE_TUNNEL is not set 36 + # CONFIG_INET_XFRM_MODE_BEET is not set 37 + # CONFIG_INET_LRO is not set 38 + # CONFIG_INET_DIAG is not set 39 + CONFIG_TCP_CONG_ADVANCED=y 40 + # CONFIG_TCP_CONG_BIC is not set 41 + # CONFIG_TCP_CONG_CUBIC is not set 42 + CONFIG_TCP_CONG_WESTWOOD=y 43 + # CONFIG_TCP_CONG_HTCP is not set 44 + # CONFIG_IPV6 is not set 45 + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 46 + # CONFIG_FIRMWARE_IN_KERNEL is not set 47 + CONFIG_MTD=y 48 + CONFIG_MTD_BLOCK=y 49 + CONFIG_MTD_NAND=y 50 + CONFIG_MTD_NAND_JZ4740=y 51 + CONFIG_MTD_UBI=y 52 + CONFIG_NETDEVICES=y 53 + # CONFIG_WLAN is not set 54 + # CONFIG_INPUT_MOUSEDEV is not set 55 + CONFIG_INPUT_EVDEV=y 56 + # CONFIG_KEYBOARD_ATKBD is not set 57 + CONFIG_KEYBOARD_GPIO=y 58 + CONFIG_KEYBOARD_MATRIX=y 59 + # CONFIG_INPUT_MOUSE is not set 60 + CONFIG_INPUT_MISC=y 61 + # CONFIG_SERIO is not set 62 + CONFIG_LEGACY_PTY_COUNT=2 63 + # CONFIG_DEVKMEM is not set 64 + CONFIG_SERIAL_8250=y 65 + CONFIG_SERIAL_8250_CONSOLE=y 66 + # CONFIG_SERIAL_8250_DMA is not set 67 + CONFIG_SERIAL_8250_NR_UARTS=2 68 + CONFIG_SERIAL_8250_RUNTIME_UARTS=2 69 + # CONFIG_HW_RANDOM is not set 70 + CONFIG_SPI=y 71 + CONFIG_SPI_GPIO=y 72 + CONFIG_POWER_SUPPLY=y 73 + CONFIG_BATTERY_JZ4740=y 74 + CONFIG_CHARGER_GPIO=y 75 + # CONFIG_HWMON is not set 76 + CONFIG_MFD_JZ4740_ADC=y 77 + CONFIG_REGULATOR=y 78 + CONFIG_REGULATOR_FIXED_VOLTAGE=y 79 + CONFIG_FB=y 80 + CONFIG_FB_JZ4740=y 81 + CONFIG_BACKLIGHT_LCD_SUPPORT=y 82 + CONFIG_LCD_CLASS_DEVICE=y 83 + # CONFIG_BACKLIGHT_CLASS_DEVICE is not set 84 + # CONFIG_VGA_CONSOLE is not set 85 + CONFIG_FRAMEBUFFER_CONSOLE=y 86 + CONFIG_LOGO=y 87 + # CONFIG_LOGO_LINUX_MONO is not set 88 + # CONFIG_LOGO_LINUX_VGA16 is not set 89 + # CONFIG_LOGO_LINUX_CLUT224 is not set 90 + CONFIG_SOUND=y 91 + CONFIG_SND=y 92 + # CONFIG_SND_SUPPORT_OLD_API is not set 93 + # CONFIG_SND_VERBOSE_PROCFS is not set 94 + # CONFIG_SND_DRIVERS is not set 95 + # CONFIG_SND_SPI is not set 96 + # CONFIG_SND_MIPS is not set 97 + CONFIG_SND_SOC=y 98 + CONFIG_SND_JZ4740_SOC=y 99 + CONFIG_SND_JZ4740_SOC_QI_LB60=y 100 + CONFIG_USB=y 101 + CONFIG_USB_OTG_BLACKLIST_HUB=y 102 + CONFIG_USB_MUSB_HDRC=y 103 + CONFIG_USB_MUSB_GADGET=y 104 + CONFIG_USB_MUSB_JZ4740=y 105 + CONFIG_NOP_USB_XCEIV=y 106 + CONFIG_USB_GADGET=y 107 + CONFIG_USB_GADGET_DEBUG=y 108 + CONFIG_USB_ETH=y 109 + # CONFIG_USB_ETH_RNDIS is not set 110 + CONFIG_MMC=y 111 + CONFIG_MMC_UNSAFE_RESUME=y 112 + # CONFIG_MMC_BLOCK_BOUNCE is not set 113 + CONFIG_MMC_JZ4740=y 114 + CONFIG_RTC_CLASS=y 115 + CONFIG_RTC_DRV_JZ4740=y 116 + CONFIG_DMADEVICES=y 117 + CONFIG_DMA_JZ4740=y 118 + CONFIG_PWM=y 119 + CONFIG_PWM_JZ4740=y 120 + CONFIG_EXT2_FS=y 121 + CONFIG_EXT3_FS=y 122 + # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set 123 + # CONFIG_EXT3_FS_XATTR is not set 124 + # CONFIG_DNOTIFY is not set 125 + CONFIG_VFAT_FS=y 126 + CONFIG_PROC_KCORE=y 127 + # CONFIG_PROC_PAGE_MONITOR is not set 128 + CONFIG_TMPFS=y 129 + CONFIG_JFFS2_FS=y 130 + CONFIG_JFFS2_SUMMARY=y 131 + CONFIG_JFFS2_COMPRESSION_OPTIONS=y 132 + # CONFIG_JFFS2_ZLIB is not set 133 + CONFIG_UBIFS_FS=y 134 + CONFIG_UBIFS_FS_ADVANCED_COMPR=y 135 + # CONFIG_NETWORK_FILESYSTEMS is not set 136 + CONFIG_NLS_CODEPAGE_437=y 137 + CONFIG_NLS_CODEPAGE_737=y 138 + CONFIG_NLS_CODEPAGE_775=y 139 + CONFIG_NLS_CODEPAGE_850=y 140 + CONFIG_NLS_CODEPAGE_852=y 141 + CONFIG_NLS_CODEPAGE_855=y 142 + CONFIG_NLS_CODEPAGE_857=y 143 + CONFIG_NLS_CODEPAGE_860=y 144 + CONFIG_NLS_CODEPAGE_861=y 145 + CONFIG_NLS_CODEPAGE_862=y 146 + CONFIG_NLS_CODEPAGE_863=y 147 + CONFIG_NLS_CODEPAGE_864=y 148 + CONFIG_NLS_CODEPAGE_865=y 149 + CONFIG_NLS_CODEPAGE_866=y 150 + CONFIG_NLS_CODEPAGE_869=y 151 + CONFIG_NLS_CODEPAGE_936=y 152 + CONFIG_NLS_CODEPAGE_950=y 153 + CONFIG_NLS_CODEPAGE_932=y 154 + CONFIG_NLS_CODEPAGE_949=y 155 + CONFIG_NLS_CODEPAGE_874=y 156 + CONFIG_NLS_ISO8859_8=y 157 + CONFIG_NLS_CODEPAGE_1250=y 158 + CONFIG_NLS_CODEPAGE_1251=y 159 + CONFIG_NLS_ASCII=y 160 + CONFIG_NLS_ISO8859_1=y 161 + CONFIG_NLS_ISO8859_2=y 162 + CONFIG_NLS_ISO8859_3=y 163 + CONFIG_NLS_ISO8859_4=y 164 + CONFIG_NLS_ISO8859_5=y 165 + CONFIG_NLS_ISO8859_6=y 166 + CONFIG_NLS_ISO8859_7=y 167 + CONFIG_NLS_ISO8859_9=y 168 + CONFIG_NLS_ISO8859_13=y 169 + CONFIG_NLS_ISO8859_14=y 170 + CONFIG_NLS_ISO8859_15=y 171 + CONFIG_NLS_KOI8_R=y 172 + CONFIG_NLS_KOI8_U=y 173 + CONFIG_NLS_UTF8=y 174 + CONFIG_PRINTK_TIME=y 175 + CONFIG_DEBUG_INFO=y 176 + CONFIG_STRIP_ASM_SYMS=y 177 + CONFIG_READABLE_ASM=y 178 + CONFIG_DEBUG_KMEMLEAK=y 179 + CONFIG_DEBUG_MEMORY_INIT=y 180 + CONFIG_DEBUG_STACKOVERFLOW=y 181 + CONFIG_PANIC_ON_OOPS=y 182 + # CONFIG_FTRACE is not set 183 + CONFIG_KGDB=y 184 + CONFIG_RUNTIME_DEBUG=y 185 + CONFIG_CRYPTO_ZLIB=y 186 + # CONFIG_CRYPTO_ANSI_CPRNG is not set 187 + CONFIG_FONTS=y 188 + CONFIG_FONT_SUN8x16=y
-1
arch/mips/configs/rb532_defconfig
··· 114 CONFIG_HAMRADIO=y 115 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 116 CONFIG_MTD=y 117 - CONFIG_MTD_PARTITIONS=y 118 CONFIG_MTD_CHAR=y 119 CONFIG_MTD_BLOCK=y 120 CONFIG_MTD_BLOCK2MTD=y
··· 114 CONFIG_HAMRADIO=y 115 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 116 CONFIG_MTD=y 117 CONFIG_MTD_CHAR=y 118 CONFIG_MTD_BLOCK=y 119 CONFIG_MTD_BLOCK2MTD=y
-1
arch/mips/configs/rbtx49xx_defconfig
··· 35 # CONFIG_IPV6 is not set 36 # CONFIG_WIRELESS is not set 37 CONFIG_MTD=y 38 - CONFIG_MTD_PARTITIONS=y 39 CONFIG_MTD_CMDLINE_PARTS=y 40 CONFIG_MTD_CHAR=y 41 CONFIG_MTD_BLOCK=m
··· 35 # CONFIG_IPV6 is not set 36 # CONFIG_WIRELESS is not set 37 CONFIG_MTD=y 38 CONFIG_MTD_CMDLINE_PARTS=y 39 CONFIG_MTD_CHAR=y 40 CONFIG_MTD_BLOCK=m
-1
arch/mips/fw/arc/file.c
··· 8 * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 - #include <linux/init.h> 12 13 #include <asm/fw/arc/types.h> 14 #include <asm/sgialib.h>
··· 8 * Copyright (C) 1994, 1995, 1996, 1999 Ralf Baechle 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 */ 11 12 #include <asm/fw/arc/types.h> 13 #include <asm/sgialib.h>
+10 -5
arch/mips/include/asm/amon.h
··· 1 /* 2 - * Amon support 3 */ 4 - 5 - int amon_cpu_avail(int); 6 - void amon_cpu_start(int, unsigned long, unsigned long, 7 - unsigned long, unsigned long);
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2013 Imagination Technologies Ltd. 7 + * 8 + * Arbitrary Monitor Support (AMON) 9 */ 10 + int amon_cpu_avail(int cpu); 11 + int amon_cpu_start(int cpu, unsigned long pc, unsigned long sp, 12 + unsigned long gp, unsigned long a0);
-42
arch/mips/include/asm/asmmacro-32.h
··· 12 #include <asm/fpregdef.h> 13 #include <asm/mipsregs.h> 14 15 - .macro fpu_save_double thread status tmp1=t0 16 - cfc1 \tmp1, fcr31 17 - sdc1 $f0, THREAD_FPR0(\thread) 18 - sdc1 $f2, THREAD_FPR2(\thread) 19 - sdc1 $f4, THREAD_FPR4(\thread) 20 - sdc1 $f6, THREAD_FPR6(\thread) 21 - sdc1 $f8, THREAD_FPR8(\thread) 22 - sdc1 $f10, THREAD_FPR10(\thread) 23 - sdc1 $f12, THREAD_FPR12(\thread) 24 - sdc1 $f14, THREAD_FPR14(\thread) 25 - sdc1 $f16, THREAD_FPR16(\thread) 26 - sdc1 $f18, THREAD_FPR18(\thread) 27 - sdc1 $f20, THREAD_FPR20(\thread) 28 - sdc1 $f22, THREAD_FPR22(\thread) 29 - sdc1 $f24, THREAD_FPR24(\thread) 30 - sdc1 $f26, THREAD_FPR26(\thread) 31 - sdc1 $f28, THREAD_FPR28(\thread) 32 - sdc1 $f30, THREAD_FPR30(\thread) 33 - sw \tmp1, THREAD_FCR31(\thread) 34 - .endm 35 - 36 .macro fpu_save_single thread tmp=t0 37 cfc1 \tmp, fcr31 38 swc1 $f0, THREAD_FPR0(\thread) ··· 47 swc1 $f30, THREAD_FPR30(\thread) 48 swc1 $f31, THREAD_FPR31(\thread) 49 sw \tmp, THREAD_FCR31(\thread) 50 - .endm 51 - 52 - .macro fpu_restore_double thread status tmp=t0 53 - lw \tmp, THREAD_FCR31(\thread) 54 - ldc1 $f0, THREAD_FPR0(\thread) 55 - ldc1 $f2, THREAD_FPR2(\thread) 56 - ldc1 $f4, THREAD_FPR4(\thread) 57 - ldc1 $f6, THREAD_FPR6(\thread) 58 - ldc1 $f8, THREAD_FPR8(\thread) 59 - ldc1 $f10, THREAD_FPR10(\thread) 60 - ldc1 $f12, THREAD_FPR12(\thread) 61 - ldc1 $f14, THREAD_FPR14(\thread) 62 - ldc1 $f16, THREAD_FPR16(\thread) 63 - ldc1 $f18, THREAD_FPR18(\thread) 64 - ldc1 $f20, THREAD_FPR20(\thread) 65 - ldc1 $f22, THREAD_FPR22(\thread) 66 - ldc1 $f24, THREAD_FPR24(\thread) 67 - ldc1 $f26, THREAD_FPR26(\thread) 68 - ldc1 $f28, THREAD_FPR28(\thread) 69 - ldc1 $f30, THREAD_FPR30(\thread) 70 - ctc1 \tmp, fcr31 71 .endm 72 73 .macro fpu_restore_single thread tmp=t0
··· 12 #include <asm/fpregdef.h> 13 #include <asm/mipsregs.h> 14 15 .macro fpu_save_single thread tmp=t0 16 cfc1 \tmp, fcr31 17 swc1 $f0, THREAD_FPR0(\thread) ··· 68 swc1 $f30, THREAD_FPR30(\thread) 69 swc1 $f31, THREAD_FPR31(\thread) 70 sw \tmp, THREAD_FCR31(\thread) 71 .endm 72 73 .macro fpu_restore_single thread tmp=t0
-96
arch/mips/include/asm/asmmacro-64.h
··· 13 #include <asm/fpregdef.h> 14 #include <asm/mipsregs.h> 15 16 - .macro fpu_save_16even thread tmp=t0 17 - cfc1 \tmp, fcr31 18 - sdc1 $f0, THREAD_FPR0(\thread) 19 - sdc1 $f2, THREAD_FPR2(\thread) 20 - sdc1 $f4, THREAD_FPR4(\thread) 21 - sdc1 $f6, THREAD_FPR6(\thread) 22 - sdc1 $f8, THREAD_FPR8(\thread) 23 - sdc1 $f10, THREAD_FPR10(\thread) 24 - sdc1 $f12, THREAD_FPR12(\thread) 25 - sdc1 $f14, THREAD_FPR14(\thread) 26 - sdc1 $f16, THREAD_FPR16(\thread) 27 - sdc1 $f18, THREAD_FPR18(\thread) 28 - sdc1 $f20, THREAD_FPR20(\thread) 29 - sdc1 $f22, THREAD_FPR22(\thread) 30 - sdc1 $f24, THREAD_FPR24(\thread) 31 - sdc1 $f26, THREAD_FPR26(\thread) 32 - sdc1 $f28, THREAD_FPR28(\thread) 33 - sdc1 $f30, THREAD_FPR30(\thread) 34 - sw \tmp, THREAD_FCR31(\thread) 35 - .endm 36 - 37 - .macro fpu_save_16odd thread 38 - sdc1 $f1, THREAD_FPR1(\thread) 39 - sdc1 $f3, THREAD_FPR3(\thread) 40 - sdc1 $f5, THREAD_FPR5(\thread) 41 - sdc1 $f7, THREAD_FPR7(\thread) 42 - sdc1 $f9, THREAD_FPR9(\thread) 43 - sdc1 $f11, THREAD_FPR11(\thread) 44 - sdc1 $f13, THREAD_FPR13(\thread) 45 - sdc1 $f15, THREAD_FPR15(\thread) 46 - sdc1 $f17, THREAD_FPR17(\thread) 47 - sdc1 $f19, THREAD_FPR19(\thread) 48 - sdc1 $f21, THREAD_FPR21(\thread) 49 - sdc1 $f23, THREAD_FPR23(\thread) 50 - sdc1 $f25, THREAD_FPR25(\thread) 51 - sdc1 $f27, THREAD_FPR27(\thread) 52 - sdc1 $f29, THREAD_FPR29(\thread) 53 - sdc1 $f31, THREAD_FPR31(\thread) 54 - .endm 55 - 56 - .macro fpu_save_double thread status tmp 57 - sll \tmp, \status, 5 58 - bgez \tmp, 2f 59 - fpu_save_16odd \thread 60 - 2: 61 - fpu_save_16even \thread \tmp 62 - .endm 63 - 64 - .macro fpu_restore_16even thread tmp=t0 65 - lw \tmp, THREAD_FCR31(\thread) 66 - ldc1 $f0, THREAD_FPR0(\thread) 67 - ldc1 $f2, THREAD_FPR2(\thread) 68 - ldc1 $f4, THREAD_FPR4(\thread) 69 - ldc1 $f6, THREAD_FPR6(\thread) 70 - ldc1 $f8, THREAD_FPR8(\thread) 71 - ldc1 $f10, THREAD_FPR10(\thread) 72 - ldc1 $f12, THREAD_FPR12(\thread) 73 - ldc1 $f14, THREAD_FPR14(\thread) 74 - ldc1 $f16, THREAD_FPR16(\thread) 75 - ldc1 $f18, THREAD_FPR18(\thread) 76 - ldc1 $f20, THREAD_FPR20(\thread) 77 - ldc1 $f22, THREAD_FPR22(\thread) 78 - ldc1 $f24, THREAD_FPR24(\thread) 79 - ldc1 $f26, THREAD_FPR26(\thread) 80 - ldc1 $f28, THREAD_FPR28(\thread) 81 - ldc1 $f30, THREAD_FPR30(\thread) 82 - ctc1 \tmp, fcr31 83 - .endm 84 - 85 - .macro fpu_restore_16odd thread 86 - ldc1 $f1, THREAD_FPR1(\thread) 87 - ldc1 $f3, THREAD_FPR3(\thread) 88 - ldc1 $f5, THREAD_FPR5(\thread) 89 - ldc1 $f7, THREAD_FPR7(\thread) 90 - ldc1 $f9, THREAD_FPR9(\thread) 91 - ldc1 $f11, THREAD_FPR11(\thread) 92 - ldc1 $f13, THREAD_FPR13(\thread) 93 - ldc1 $f15, THREAD_FPR15(\thread) 94 - ldc1 $f17, THREAD_FPR17(\thread) 95 - ldc1 $f19, THREAD_FPR19(\thread) 96 - ldc1 $f21, THREAD_FPR21(\thread) 97 - ldc1 $f23, THREAD_FPR23(\thread) 98 - ldc1 $f25, THREAD_FPR25(\thread) 99 - ldc1 $f27, THREAD_FPR27(\thread) 100 - ldc1 $f29, THREAD_FPR29(\thread) 101 - ldc1 $f31, THREAD_FPR31(\thread) 102 - .endm 103 - 104 - .macro fpu_restore_double thread status tmp 105 - sll \tmp, \status, 5 106 - bgez \tmp, 1f # 16 register mode? 107 - 108 - fpu_restore_16odd \thread 109 - 1: fpu_restore_16even \thread \tmp 110 - .endm 111 - 112 .macro cpu_save_nonscratch thread 113 LONG_S s0, THREAD_REG16(\thread) 114 LONG_S s1, THREAD_REG17(\thread)
··· 13 #include <asm/fpregdef.h> 14 #include <asm/mipsregs.h> 15 16 .macro cpu_save_nonscratch thread 17 LONG_S s0, THREAD_REG16(\thread) 18 LONG_S s1, THREAD_REG17(\thread)
+107
arch/mips/include/asm/asmmacro.h
··· 62 .endm 63 #endif /* CONFIG_MIPS_MT_SMTC */ 64 65 /* 66 * Temporary until all gas have MT ASE support 67 */
··· 62 .endm 63 #endif /* CONFIG_MIPS_MT_SMTC */ 64 65 + .macro fpu_save_16even thread tmp=t0 66 + cfc1 \tmp, fcr31 67 + sdc1 $f0, THREAD_FPR0(\thread) 68 + sdc1 $f2, THREAD_FPR2(\thread) 69 + sdc1 $f4, THREAD_FPR4(\thread) 70 + sdc1 $f6, THREAD_FPR6(\thread) 71 + sdc1 $f8, THREAD_FPR8(\thread) 72 + sdc1 $f10, THREAD_FPR10(\thread) 73 + sdc1 $f12, THREAD_FPR12(\thread) 74 + sdc1 $f14, THREAD_FPR14(\thread) 75 + sdc1 $f16, THREAD_FPR16(\thread) 76 + sdc1 $f18, THREAD_FPR18(\thread) 77 + sdc1 $f20, THREAD_FPR20(\thread) 78 + sdc1 $f22, THREAD_FPR22(\thread) 79 + sdc1 $f24, THREAD_FPR24(\thread) 80 + sdc1 $f26, THREAD_FPR26(\thread) 81 + sdc1 $f28, THREAD_FPR28(\thread) 82 + sdc1 $f30, THREAD_FPR30(\thread) 83 + sw \tmp, THREAD_FCR31(\thread) 84 + .endm 85 + 86 + .macro fpu_save_16odd thread 87 + .set push 88 + .set mips64r2 89 + sdc1 $f1, THREAD_FPR1(\thread) 90 + sdc1 $f3, THREAD_FPR3(\thread) 91 + sdc1 $f5, THREAD_FPR5(\thread) 92 + sdc1 $f7, THREAD_FPR7(\thread) 93 + sdc1 $f9, THREAD_FPR9(\thread) 94 + sdc1 $f11, THREAD_FPR11(\thread) 95 + sdc1 $f13, THREAD_FPR13(\thread) 96 + sdc1 $f15, THREAD_FPR15(\thread) 97 + sdc1 $f17, THREAD_FPR17(\thread) 98 + sdc1 $f19, THREAD_FPR19(\thread) 99 + sdc1 $f21, THREAD_FPR21(\thread) 100 + sdc1 $f23, THREAD_FPR23(\thread) 101 + sdc1 $f25, THREAD_FPR25(\thread) 102 + sdc1 $f27, THREAD_FPR27(\thread) 103 + sdc1 $f29, THREAD_FPR29(\thread) 104 + sdc1 $f31, THREAD_FPR31(\thread) 105 + .set pop 106 + .endm 107 + 108 + .macro fpu_save_double thread status tmp 109 + #if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 110 + sll \tmp, \status, 5 111 + bgez \tmp, 10f 112 + fpu_save_16odd \thread 113 + 10: 114 + #endif 115 + fpu_save_16even \thread \tmp 116 + .endm 117 + 118 + .macro fpu_restore_16even thread tmp=t0 119 + lw \tmp, THREAD_FCR31(\thread) 120 + ldc1 $f0, THREAD_FPR0(\thread) 121 + ldc1 $f2, THREAD_FPR2(\thread) 122 + ldc1 $f4, THREAD_FPR4(\thread) 123 + ldc1 $f6, THREAD_FPR6(\thread) 124 + ldc1 $f8, THREAD_FPR8(\thread) 125 + ldc1 $f10, THREAD_FPR10(\thread) 126 + ldc1 $f12, THREAD_FPR12(\thread) 127 + ldc1 $f14, THREAD_FPR14(\thread) 128 + ldc1 $f16, THREAD_FPR16(\thread) 129 + ldc1 $f18, THREAD_FPR18(\thread) 130 + ldc1 $f20, THREAD_FPR20(\thread) 131 + ldc1 $f22, THREAD_FPR22(\thread) 132 + ldc1 $f24, THREAD_FPR24(\thread) 133 + ldc1 $f26, THREAD_FPR26(\thread) 134 + ldc1 $f28, THREAD_FPR28(\thread) 135 + ldc1 $f30, THREAD_FPR30(\thread) 136 + ctc1 \tmp, fcr31 137 + .endm 138 + 139 + .macro fpu_restore_16odd thread 140 + .set push 141 + .set mips64r2 142 + ldc1 $f1, THREAD_FPR1(\thread) 143 + ldc1 $f3, THREAD_FPR3(\thread) 144 + ldc1 $f5, THREAD_FPR5(\thread) 145 + ldc1 $f7, THREAD_FPR7(\thread) 146 + ldc1 $f9, THREAD_FPR9(\thread) 147 + ldc1 $f11, THREAD_FPR11(\thread) 148 + ldc1 $f13, THREAD_FPR13(\thread) 149 + ldc1 $f15, THREAD_FPR15(\thread) 150 + ldc1 $f17, THREAD_FPR17(\thread) 151 + ldc1 $f19, THREAD_FPR19(\thread) 152 + ldc1 $f21, THREAD_FPR21(\thread) 153 + ldc1 $f23, THREAD_FPR23(\thread) 154 + ldc1 $f25, THREAD_FPR25(\thread) 155 + ldc1 $f27, THREAD_FPR27(\thread) 156 + ldc1 $f29, THREAD_FPR29(\thread) 157 + ldc1 $f31, THREAD_FPR31(\thread) 158 + .set pop 159 + .endm 160 + 161 + .macro fpu_restore_double thread status tmp 162 + #if defined(CONFIG_MIPS64) || defined(CONFIG_CPU_MIPS32_R2) 163 + sll \tmp, \status, 5 164 + bgez \tmp, 10f # 16 register mode? 165 + 166 + fpu_restore_16odd \thread 167 + 10: 168 + #endif 169 + fpu_restore_16even \thread \tmp 170 + .endm 171 + 172 /* 173 * Temporary until all gas have MT ASE support 174 */
+28 -1
arch/mips/include/asm/bmips.h
··· 46 47 #include <linux/cpumask.h> 48 #include <asm/r4kcache.h> 49 50 - extern struct plat_smp_ops bmips_smp_ops; 51 extern char bmips_reset_nmi_vec; 52 extern char bmips_reset_nmi_vec_end; 53 extern char bmips_smp_movevec;
··· 46 47 #include <linux/cpumask.h> 48 #include <asm/r4kcache.h> 49 + #include <asm/smp-ops.h> 50 51 + extern struct plat_smp_ops bmips43xx_smp_ops; 52 + extern struct plat_smp_ops bmips5000_smp_ops; 53 + 54 + static inline int register_bmips_smp_ops(void) 55 + { 56 + #if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP) 57 + switch (current_cpu_type()) { 58 + case CPU_BMIPS32: 59 + case CPU_BMIPS3300: 60 + return register_up_smp_ops(); 61 + case CPU_BMIPS4350: 62 + case CPU_BMIPS4380: 63 + register_smp_ops(&bmips43xx_smp_ops); 64 + break; 65 + case CPU_BMIPS5000: 66 + register_smp_ops(&bmips5000_smp_ops); 67 + break; 68 + default: 69 + return -ENODEV; 70 + } 71 + 72 + return 0; 73 + #else 74 + return -ENODEV; 75 + #endif 76 + } 77 + 78 extern char bmips_reset_nmi_vec; 79 extern char bmips_reset_nmi_vec_end; 80 extern char bmips_smp_movevec;
+7
arch/mips/include/asm/cpu-features.h
··· 20 #ifndef cpu_has_tlb 21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 22 #endif 23 24 /* 25 * For the moment we don't consider R6000 and R8000 so we can assume that
··· 20 #ifndef cpu_has_tlb 21 #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) 22 #endif 23 + #ifndef cpu_has_tlbinv 24 + #define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV) 25 + #endif 26 + #ifndef cpu_has_segments 27 + #define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS) 28 + #endif 29 + 30 31 /* 32 * For the moment we don't consider R6000 and R8000 so we can assume that
+3
arch/mips/include/asm/cpu-info.h
··· 52 unsigned int cputype; 53 int isa_level; 54 int tlbsize; 55 struct cache_desc icache; /* Primary I-cache */ 56 struct cache_desc dcache; /* Primary D or combined I/D cache */ 57 struct cache_desc scache; /* Secondary cache */
··· 52 unsigned int cputype; 53 int isa_level; 54 int tlbsize; 55 + int tlbsizevtlb; 56 + int tlbsizeftlbsets; 57 + int tlbsizeftlbways; 58 struct cache_desc icache; /* Primary I-cache */ 59 struct cache_desc dcache; /* Primary D or combined I/D cache */ 60 struct cache_desc scache; /* Secondary cache */
+12 -3
arch/mips/include/asm/cpu-type.h
··· 27 #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 28 case CPU_4KC: 29 case CPU_ALCHEMY: 30 - case CPU_BMIPS3300: 31 - case CPU_BMIPS4350: 32 case CPU_PR4450: 33 - case CPU_BMIPS32: 34 case CPU_JZRISC: 35 #endif 36 ··· 44 case CPU_74K: 45 case CPU_M14KC: 46 case CPU_M14KEC: 47 #endif 48 49 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 ··· 160 case CPU_CAVIUM_OCTEON: 161 case CPU_CAVIUM_OCTEON_PLUS: 162 case CPU_CAVIUM_OCTEON2: 163 #endif 164 165 #ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
··· 27 #ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1 28 case CPU_4KC: 29 case CPU_ALCHEMY: 30 case CPU_PR4450: 31 case CPU_JZRISC: 32 #endif 33 ··· 47 case CPU_74K: 48 case CPU_M14KC: 49 case CPU_M14KEC: 50 + case CPU_INTERAPTIV: 51 + case CPU_PROAPTIV: 52 #endif 53 54 #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1 ··· 161 case CPU_CAVIUM_OCTEON: 162 case CPU_CAVIUM_OCTEON_PLUS: 163 case CPU_CAVIUM_OCTEON2: 164 + #endif 165 + 166 + #if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \ 167 + defined (CONFIG_SYS_HAS_CPU_MIPS32_R1) 168 + case CPU_BMIPS32: 169 + case CPU_BMIPS3300: 170 + #endif 171 + 172 + #ifdef CONFIG_SYS_HAS_CPU_BMIPS4350 173 + case CPU_BMIPS4350: 174 #endif 175 176 #ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
+11 -1
arch/mips/include/asm/cpu.h
··· 111 #define PRID_IMP_1074K 0x9a00 112 #define PRID_IMP_M14KC 0x9c00 113 #define PRID_IMP_M14KEC 0x9e00 114 115 /* 116 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ··· 198 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 199 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 200 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 201 202 /* 203 * Particular Revision values for bits 7:0 of the PRId register. ··· 254 255 #define FPIR_IMP_NONE 0x0000 256 257 enum cpu_type_enum { 258 CPU_UNKNOWN, 259 ··· 296 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 297 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 298 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 299 - CPU_M14KEC, 300 301 /* 302 * MIPS64 class processors ··· 308 CPU_LAST 309 }; 310 311 312 /* 313 * ISA Level encodings ··· 356 #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 357 #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 358 #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 359 360 /* 361 * CPU ASE encodings
··· 111 #define PRID_IMP_1074K 0x9a00 112 #define PRID_IMP_M14KC 0x9c00 113 #define PRID_IMP_M14KEC 0x9e00 114 + #define PRID_IMP_INTERAPTIV_UP 0xa000 115 + #define PRID_IMP_INTERAPTIV_MP 0xa100 116 + #define PRID_IMP_PROAPTIV_UP 0xa200 117 + #define PRID_IMP_PROAPTIV_MP 0xa300 118 119 /* 120 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE ··· 194 #define PRID_IMP_NETLOGIC_XLP8XX 0x1000 195 #define PRID_IMP_NETLOGIC_XLP3XX 0x1100 196 #define PRID_IMP_NETLOGIC_XLP2XX 0x1200 197 + #define PRID_IMP_NETLOGIC_XLP9XX 0x1500 198 199 /* 200 * Particular Revision values for bits 7:0 of the PRId register. ··· 249 250 #define FPIR_IMP_NONE 0x0000 251 252 + #if !defined(__ASSEMBLY__) 253 + 254 enum cpu_type_enum { 255 CPU_UNKNOWN, 256 ··· 289 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 290 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 291 CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC, 292 + CPU_M14KEC, CPU_INTERAPTIV, CPU_PROAPTIV, 293 294 /* 295 * MIPS64 class processors ··· 301 CPU_LAST 302 }; 303 304 + #endif /* !__ASSEMBLY */ 305 306 /* 307 * ISA Level encodings ··· 348 #define MIPS_CPU_PCI 0x00400000 /* CPU has Perf Ctr Int indicator */ 349 #define MIPS_CPU_RIXI 0x00800000 /* CPU has TLB Read/eXec Inhibit */ 350 #define MIPS_CPU_MICROMIPS 0x01000000 /* CPU has microMIPS capability */ 351 + #define MIPS_CPU_TLBINV 0x02000000 /* CPU supports TLBINV/F */ 352 + #define MIPS_CPU_SEGMENTS 0x04000000 /* CPU supports Segmentation Control registers */ 353 354 /* 355 * CPU ASE encodings
+9
arch/mips/include/asm/dma-coherence.h
··· 9 #ifndef __ASM_DMA_COHERENCE_H 10 #define __ASM_DMA_COHERENCE_H 11 12 extern int coherentio; 13 extern int hw_coherentio; 14 15 #endif
··· 9 #ifndef __ASM_DMA_COHERENCE_H 10 #define __ASM_DMA_COHERENCE_H 11 12 + #ifdef CONFIG_DMA_MAYBE_COHERENT 13 extern int coherentio; 14 extern int hw_coherentio; 15 + #else 16 + #ifdef CONFIG_DMA_COHERENT 17 + #define coherentio 1 18 + #else 19 + #define coherentio 0 20 + #endif 21 + #define hw_coherentio 0 22 + #endif /* CONFIG_DMA_MAYBE_COHERENT */ 23 24 #endif
+28 -3
arch/mips/include/asm/elf.h
··· 36 #define EF_MIPS_ABI2 0x00000020 37 #define EF_MIPS_OPTIONS_FIRST 0x00000080 38 #define EF_MIPS_32BITMODE 0x00000100 39 #define EF_MIPS_ABI 0x0000f000 40 #define EF_MIPS_ARCH 0xf0000000 41 ··· 177 #ifdef CONFIG_32BIT 178 179 /* 180 * This is used to ensure we don't load something for the wrong architecture. 181 */ 182 #define elf_check_arch(hdr) \ ··· 204 __res = 0; \ 205 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 206 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 207 __res = 0; \ 208 \ 209 __res; \ ··· 264 265 #define SET_PERSONALITY(ex) \ 266 do { \ 267 if (personality(current->personality) != PER_LINUX) \ 268 set_personality(PER_LINUX); \ 269 \ ··· 291 #endif 292 293 #ifdef CONFIG_MIPS32_O32 294 - #define __SET_PERSONALITY32_O32() \ 295 do { \ 296 set_thread_flag(TIF_32BIT_REGS); \ 297 set_thread_flag(TIF_32BIT_ADDR); \ 298 current->thread.abi = &mips_abi_32; \ 299 } while (0) 300 #else 301 - #define __SET_PERSONALITY32_O32() \ 302 do { } while (0) 303 #endif 304 ··· 313 ((ex).e_flags & EF_MIPS_ABI) == 0) \ 314 __SET_PERSONALITY32_N32(); \ 315 else \ 316 - __SET_PERSONALITY32_O32(); \ 317 } while (0) 318 #else 319 #define __SET_PERSONALITY32(ex) do { } while (0) ··· 324 unsigned int p; \ 325 \ 326 clear_thread_flag(TIF_32BIT_REGS); \ 327 clear_thread_flag(TIF_32BIT_ADDR); \ 328 \ 329 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
··· 36 #define EF_MIPS_ABI2 0x00000020 37 #define EF_MIPS_OPTIONS_FIRST 0x00000080 38 #define EF_MIPS_32BITMODE 0x00000100 39 + #define EF_MIPS_FP64 0x00000200 40 #define EF_MIPS_ABI 0x0000f000 41 #define EF_MIPS_ARCH 0xf0000000 42 ··· 176 #ifdef CONFIG_32BIT 177 178 /* 179 + * In order to be sure that we don't attempt to execute an O32 binary which 180 + * requires 64 bit FP (FR=1) on a system which does not support it we refuse 181 + * to execute any binary which has bits specified by the following macro set 182 + * in its ELF header flags. 183 + */ 184 + #ifdef CONFIG_MIPS_O32_FP64_SUPPORT 185 + # define __MIPS_O32_FP64_MUST_BE_ZERO 0 186 + #else 187 + # define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64 188 + #endif 189 + 190 + /* 191 * This is used to ensure we don't load something for the wrong architecture. 192 */ 193 #define elf_check_arch(hdr) \ ··· 191 __res = 0; \ 192 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 193 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 194 + __res = 0; \ 195 + if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \ 196 __res = 0; \ 197 \ 198 __res; \ ··· 249 250 #define SET_PERSONALITY(ex) \ 251 do { \ 252 + if ((ex).e_flags & EF_MIPS_FP64) \ 253 + clear_thread_flag(TIF_32BIT_FPREGS); \ 254 + else \ 255 + set_thread_flag(TIF_32BIT_FPREGS); \ 256 + \ 257 if (personality(current->personality) != PER_LINUX) \ 258 set_personality(PER_LINUX); \ 259 \ ··· 271 #endif 272 273 #ifdef CONFIG_MIPS32_O32 274 + #define __SET_PERSONALITY32_O32(ex) \ 275 do { \ 276 set_thread_flag(TIF_32BIT_REGS); \ 277 set_thread_flag(TIF_32BIT_ADDR); \ 278 + \ 279 + if (!((ex).e_flags & EF_MIPS_FP64)) \ 280 + set_thread_flag(TIF_32BIT_FPREGS); \ 281 + \ 282 current->thread.abi = &mips_abi_32; \ 283 } while (0) 284 #else 285 + #define __SET_PERSONALITY32_O32(ex) \ 286 do { } while (0) 287 #endif 288 ··· 289 ((ex).e_flags & EF_MIPS_ABI) == 0) \ 290 __SET_PERSONALITY32_N32(); \ 291 else \ 292 + __SET_PERSONALITY32_O32(ex); \ 293 } while (0) 294 #else 295 #define __SET_PERSONALITY32(ex) do { } while (0) ··· 300 unsigned int p; \ 301 \ 302 clear_thread_flag(TIF_32BIT_REGS); \ 303 + clear_thread_flag(TIF_32BIT_FPREGS); \ 304 clear_thread_flag(TIF_32BIT_ADDR); \ 305 \ 306 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
+76 -28
arch/mips/include/asm/fpu.h
··· 33 extern void _save_fp(struct task_struct *); 34 extern void _restore_fp(struct task_struct *); 35 36 - #define __enable_fpu() \ 37 - do { \ 38 - set_c0_status(ST0_CU1); \ 39 - enable_fpu_hazard(); \ 40 - } while (0) 41 42 #define __disable_fpu() \ 43 do { \ 44 clear_c0_status(ST0_CU1); \ 45 disable_fpu_hazard(); \ 46 } while (0) 47 - 48 - #define enable_fpu() \ 49 - do { \ 50 - if (cpu_has_fpu) \ 51 - __enable_fpu(); \ 52 - } while (0) 53 - 54 - #define disable_fpu() \ 55 - do { \ 56 - if (cpu_has_fpu) \ 57 - __disable_fpu(); \ 58 - } while (0) 59 - 60 61 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) 62 ··· 94 return cpu_has_fpu && __is_fpu_owner(); 95 } 96 97 - static inline void __own_fpu(void) 98 { 99 - __enable_fpu(); 100 KSTK_STATUS(current) |= ST0_CU1; 101 set_thread_flag(TIF_USEDFPU); 102 } 103 104 - static inline void own_fpu_inatomic(int restore) 105 { 106 if (cpu_has_fpu && !__is_fpu_owner()) { 107 - __own_fpu(); 108 - if (restore) 109 _restore_fp(current); 110 } 111 } 112 113 - static inline void own_fpu(int restore) 114 { 115 preempt_disable(); 116 - own_fpu_inatomic(restore); 117 preempt_enable(); 118 } 119 120 static inline void lose_fpu(int save) ··· 149 preempt_enable(); 150 } 151 152 - static inline void init_fpu(void) 153 { 154 preempt_disable(); 155 if (cpu_has_fpu) { 156 - __own_fpu(); 157 - _init_fpu(); 158 } else { 159 fpu_emulator_init_fpu(); 160 } 161 preempt_enable(); 162 } 163 164 static inline void save_fp(struct task_struct *tsk)
··· 33 extern void _save_fp(struct task_struct *); 34 extern void _restore_fp(struct task_struct *); 35 36 + /* 37 + * This enum specifies a mode in which we want the FPU to operate, for cores 38 + * which implement the Status.FR bit. Note that FPU_32BIT & FPU_64BIT 39 + * purposefully have the values 0 & 1 respectively, so that an integer value 40 + * of Status.FR can be trivially casted to the corresponding enum fpu_mode. 41 + */ 42 + enum fpu_mode { 43 + FPU_32BIT = 0, /* FR = 0 */ 44 + FPU_64BIT, /* FR = 1 */ 45 + FPU_AS_IS, 46 + }; 47 + 48 + static inline int __enable_fpu(enum fpu_mode mode) 49 + { 50 + int fr; 51 + 52 + switch (mode) { 53 + case FPU_AS_IS: 54 + /* just enable the FPU in its current mode */ 55 + set_c0_status(ST0_CU1); 56 + enable_fpu_hazard(); 57 + return 0; 58 + 59 + case FPU_64BIT: 60 + #if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_MIPS64)) 61 + /* we only have a 32-bit FPU */ 62 + return SIGFPE; 63 + #endif 64 + /* fall through */ 65 + case FPU_32BIT: 66 + /* set CU1 & change FR appropriately */ 67 + fr = (int)mode; 68 + change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0)); 69 + enable_fpu_hazard(); 70 + 71 + /* check FR has the desired value */ 72 + return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE; 73 + 74 + default: 75 + BUG(); 76 + } 77 + } 78 79 #define __disable_fpu() \ 80 do { \ 81 clear_c0_status(ST0_CU1); \ 82 disable_fpu_hazard(); \ 83 } while (0) 84 85 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) 86 ··· 70 return cpu_has_fpu && __is_fpu_owner(); 71 } 72 73 + static inline int __own_fpu(void) 74 { 75 + enum fpu_mode mode; 76 + int ret; 77 + 78 + mode = !test_thread_flag(TIF_32BIT_FPREGS); 79 + ret = __enable_fpu(mode); 80 + if (ret) 81 + return ret; 82 + 83 KSTK_STATUS(current) |= ST0_CU1; 84 + if (mode == FPU_64BIT) 85 + KSTK_STATUS(current) |= ST0_FR; 86 + else /* mode == FPU_32BIT */ 87 + KSTK_STATUS(current) &= ~ST0_FR; 88 + 89 set_thread_flag(TIF_USEDFPU); 90 + return 0; 91 } 92 93 + static inline int own_fpu_inatomic(int restore) 94 { 95 + int ret = 0; 96 + 97 if (cpu_has_fpu && !__is_fpu_owner()) { 98 + ret = __own_fpu(); 99 + if (restore && !ret) 100 _restore_fp(current); 101 } 102 + return ret; 103 } 104 105 + static inline int own_fpu(int restore) 106 { 107 + int ret; 108 + 109 preempt_disable(); 110 + ret = own_fpu_inatomic(restore); 111 preempt_enable(); 112 + return ret; 113 } 114 115 static inline void lose_fpu(int save) ··· 106 preempt_enable(); 107 } 108 109 + static inline int init_fpu(void) 110 { 111 + int ret = 0; 112 + 113 preempt_disable(); 114 if (cpu_has_fpu) { 115 + ret = __own_fpu(); 116 + if (!ret) 117 + _init_fpu(); 118 } else { 119 fpu_emulator_init_fpu(); 120 } 121 + 122 preempt_enable(); 123 + return ret; 124 } 125 126 static inline void save_fp(struct task_struct *tsk)
-1
arch/mips/include/asm/highmem.h
··· 19 20 #ifdef __KERNEL__ 21 22 - #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/uaccess.h> 25 #include <asm/kmap_types.h>
··· 19 20 #ifdef __KERNEL__ 21 22 #include <linux/interrupt.h> 23 #include <linux/uaccess.h> 24 #include <asm/kmap_types.h>
-7
arch/mips/include/asm/kvm_host.h
··· 391 uint32_t guest_kernel_asid[NR_CPUS]; 392 struct mm_struct guest_kernel_mm, guest_user_mm; 393 394 - struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE]; 395 - 396 - 397 struct hrtimer comparecount_timer; 398 399 int last_sched_cpu; ··· 526 527 extern void kvm_mips_dump_host_tlbs(void); 528 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 529 - extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu); 530 extern void kvm_mips_flush_host_tlb(int skip_kseg0); 531 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 532 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); ··· 537 unsigned long gva); 538 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, 539 struct kvm_vcpu *vcpu); 540 - extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu); 541 - extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu); 542 extern void kvm_local_flush_tlb_all(void); 543 - extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu); 544 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); 545 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 546 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
··· 391 uint32_t guest_kernel_asid[NR_CPUS]; 392 struct mm_struct guest_kernel_mm, guest_user_mm; 393 394 struct hrtimer comparecount_timer; 395 396 int last_sched_cpu; ··· 529 530 extern void kvm_mips_dump_host_tlbs(void); 531 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu); 532 extern void kvm_mips_flush_host_tlb(int skip_kseg0); 533 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi); 534 extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index); ··· 541 unsigned long gva); 542 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu, 543 struct kvm_vcpu *vcpu); 544 extern void kvm_local_flush_tlb_all(void); 545 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu); 546 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 547 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
-1
arch/mips/include/asm/mach-ath79/ar71xx_regs.h
··· 16 #define __ASM_MACH_AR71XX_REGS_H 17 18 #include <linux/types.h> 19 - #include <linux/init.h> 20 #include <linux/io.h> 21 #include <linux/bitops.h> 22
··· 16 #define __ASM_MACH_AR71XX_REGS_H 17 18 #include <linux/types.h> 19 #include <linux/io.h> 20 #include <linux/bitops.h> 21
+2
arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
··· 56 const char *prefix); 57 #endif 58 59 #endif /* __ASM_BCM47XX_H */
··· 56 const char *prefix); 57 #endif 58 59 + void bcm47xx_set_system_type(u16 chip_id); 60 + 61 #endif /* __ASM_BCM47XX_H */
+1
arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
··· 66 BCM47XX_BOARD_LINKSYS_WRT310NV1, 67 BCM47XX_BOARD_LINKSYS_WRT310NV2, 68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2, 69 BCM47XX_BOARD_LINKSYS_WRT610NV1, 70 BCM47XX_BOARD_LINKSYS_WRT610NV2, 71 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
··· 66 BCM47XX_BOARD_LINKSYS_WRT310NV1, 67 BCM47XX_BOARD_LINKSYS_WRT310NV2, 68 BCM47XX_BOARD_LINKSYS_WRT54G3GV2, 69 + BCM47XX_BOARD_LINKSYS_WRT54GSV1, 70 BCM47XX_BOARD_LINKSYS_WRT610NV1, 71 BCM47XX_BOARD_LINKSYS_WRT610NV2, 72 BCM47XX_BOARD_LINKSYS_WRTSL54GS,
+82
arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
···
··· 1 + #ifndef __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H 2 + #define __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H 3 + 4 + #define cpu_has_tlb 1 5 + #define cpu_has_4kex 1 6 + #define cpu_has_3k_cache 0 7 + #define cpu_has_4k_cache 1 8 + #define cpu_has_tx39_cache 0 9 + #define cpu_has_fpu 0 10 + #define cpu_has_32fpr 0 11 + #define cpu_has_counter 1 12 + #if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) 13 + #define cpu_has_watch 1 14 + #elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) 15 + #define cpu_has_watch 0 16 + #endif 17 + #define cpu_has_divec 1 18 + #define cpu_has_vce 0 19 + #define cpu_has_cache_cdex_p 0 20 + #define cpu_has_cache_cdex_s 0 21 + #define cpu_has_prefetch 1 22 + #define cpu_has_mcheck 1 23 + #define cpu_has_ejtag 1 24 + #define cpu_has_llsc 1 25 + 26 + /* cpu_has_mips16 */ 27 + #define cpu_has_mdmx 0 28 + #define cpu_has_mips3d 0 29 + #define cpu_has_rixi 0 30 + #define cpu_has_mmips 0 31 + #define cpu_has_smartmips 0 32 + #define cpu_has_vtag_icache 0 33 + /* cpu_has_dc_aliases */ 34 + #define cpu_has_ic_fills_f_dc 0 35 + #define cpu_has_pindexed_dcache 0 36 + #define cpu_icache_snoops_remote_store 0 37 + 38 + #define cpu_has_mips_2 1 39 + #define cpu_has_mips_3 0 40 + #define cpu_has_mips32r1 1 41 + #if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) 42 + #define cpu_has_mips32r2 1 43 + #elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) 44 + #define cpu_has_mips32r2 0 45 + #endif 46 + #define cpu_has_mips64r1 0 47 + #define cpu_has_mips64r2 0 48 + 49 + #if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) 50 + #define cpu_has_dsp 1 51 + #define cpu_has_dsp2 1 52 + #elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) 53 + #define cpu_has_dsp 0 54 + #define cpu_has_dsp2 0 55 + #endif 56 + #define cpu_has_mipsmt 0 57 + /* cpu_has_userlocal */ 58 + 59 + #define cpu_has_nofpuex 0 60 + #define cpu_has_64bits 0 61 + #define cpu_has_64bit_zero_reg 0 62 + #if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) 63 + #define cpu_has_vint 1 64 + #elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) 65 + #define cpu_has_vint 0 66 + #endif 67 + #define cpu_has_veic 0 68 + #define cpu_has_inclusive_pcaches 0 69 + 70 + #if defined(CONFIG_BCM47XX_BCMA) && !defined(CONFIG_BCM47XX_SSB) 71 + #define cpu_dcache_line_size() 32 72 + #define cpu_icache_line_size() 32 73 + #define cpu_has_perf_cntr_intr_bit 1 74 + #elif defined(CONFIG_BCM47XX_SSB) && !defined(CONFIG_BCM47XX_BCMA) 75 + #define cpu_dcache_line_size() 16 76 + #define cpu_icache_line_size() 16 77 + #define cpu_has_perf_cntr_intr_bit 0 78 + #endif 79 + #define cpu_scache_line_size() 0 80 + #define cpu_has_vz 0 81 + 82 + #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+18
arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
··· 145 RSET_UART1, 146 RSET_GPIO, 147 RSET_SPI, 148 RSET_UDC0, 149 RSET_OHCI0, 150 RSET_OHCI_PRIV, ··· 194 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 195 #define RSET_ENETSW_SIZE 65536 196 #define RSET_UART_SIZE 24 197 #define RSET_UDC_SIZE 256 198 #define RSET_OHCI_SIZE 256 199 #define RSET_EHCI_SIZE 256 ··· 267 #define BCM_6328_UART1_BASE (0xb0000120) 268 #define BCM_6328_GPIO_BASE (0xb0000080) 269 #define BCM_6328_SPI_BASE (0xdeadbeef) 270 #define BCM_6328_UDC0_BASE (0xdeadbeef) 271 #define BCM_6328_USBDMA_BASE (0xb000c000) 272 #define BCM_6328_OHCI0_BASE (0xb0002600) ··· 316 #define BCM_6338_UART1_BASE (0xdeadbeef) 317 #define BCM_6338_GPIO_BASE (0xfffe0400) 318 #define BCM_6338_SPI_BASE (0xfffe0c00) 319 #define BCM_6338_UDC0_BASE (0xdeadbeef) 320 #define BCM_6338_USBDMA_BASE (0xfffe2400) 321 #define BCM_6338_OHCI0_BASE (0xdeadbeef) ··· 364 #define BCM_6345_UART1_BASE (0xdeadbeef) 365 #define BCM_6345_GPIO_BASE (0xfffe0400) 366 #define BCM_6345_SPI_BASE (0xdeadbeef) 367 #define BCM_6345_UDC0_BASE (0xdeadbeef) 368 #define BCM_6345_USBDMA_BASE (0xfffe2800) 369 #define BCM_6345_ENET0_BASE (0xfffe1800) ··· 411 #define BCM_6348_UART1_BASE (0xdeadbeef) 412 #define BCM_6348_GPIO_BASE (0xfffe0400) 413 #define BCM_6348_SPI_BASE (0xfffe0c00) 414 #define BCM_6348_UDC0_BASE (0xfffe1000) 415 #define BCM_6348_USBDMA_BASE (0xdeadbeef) 416 #define BCM_6348_OHCI0_BASE (0xfffe1b00) ··· 457 #define BCM_6358_UART1_BASE (0xfffe0120) 458 #define BCM_6358_GPIO_BASE (0xfffe0080) 459 #define BCM_6358_SPI_BASE (0xfffe0800) 460 #define BCM_6358_UDC0_BASE (0xfffe0800) 461 #define BCM_6358_USBDMA_BASE (0xdeadbeef) 462 #define BCM_6358_OHCI0_BASE (0xfffe1400) ··· 560 #define BCM_6368_UART1_BASE (0xb0000120) 561 #define BCM_6368_GPIO_BASE (0xb0000080) 562 #define BCM_6368_SPI_BASE (0xb0000800) 563 #define BCM_6368_UDC0_BASE (0xdeadbeef) 564 #define BCM_6368_USBDMA_BASE (0xb0004800) 565 #define BCM_6368_OHCI0_BASE (0xb0001600) ··· 612 __GEN_RSET_BASE(__cpu, UART1) \ 613 __GEN_RSET_BASE(__cpu, GPIO) \ 614 __GEN_RSET_BASE(__cpu, SPI) \ 615 __GEN_RSET_BASE(__cpu, UDC0) \ 616 __GEN_RSET_BASE(__cpu, OHCI0) \ 617 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ ··· 656 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 657 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 658 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 659 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 660 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 661 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ ··· 737 IRQ_ENET0, 738 IRQ_ENET1, 739 IRQ_ENET_PHY, 740 IRQ_OHCI0, 741 IRQ_EHCI0, 742 IRQ_USBD, ··· 826 #define BCM_6328_ENET0_IRQ 0 827 #define BCM_6328_ENET1_IRQ 0 828 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 829 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 830 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 831 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) ··· 872 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 873 #define BCM_6338_ENET1_IRQ 0 874 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 875 #define BCM_6338_OHCI0_IRQ 0 876 #define BCM_6338_EHCI0_IRQ 0 877 #define BCM_6338_USBD_IRQ 0 ··· 911 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 912 #define BCM_6345_ENET1_IRQ 0 913 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 914 #define BCM_6345_OHCI0_IRQ 0 915 #define BCM_6345_EHCI0_IRQ 0 916 #define BCM_6345_USBD_IRQ 0 ··· 950 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 951 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 952 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 953 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 954 #define BCM_6348_EHCI0_IRQ 0 955 #define BCM_6348_USBD_IRQ 0 ··· 989 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 990 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 991 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 992 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 993 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 994 #define BCM_6358_USBD_IRQ 0 ··· 1102 #define BCM_6368_ENET0_IRQ 0 1103 #define BCM_6368_ENET1_IRQ 0 1104 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 1105 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 1106 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 1107 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) ··· 1150 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1151 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1152 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1153 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1154 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1155 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
··· 145 RSET_UART1, 146 RSET_GPIO, 147 RSET_SPI, 148 + RSET_HSSPI, 149 RSET_UDC0, 150 RSET_OHCI0, 151 RSET_OHCI_PRIV, ··· 193 #define RSET_ENETDMAS_SIZE(chans) (16 * (chans)) 194 #define RSET_ENETSW_SIZE 65536 195 #define RSET_UART_SIZE 24 196 + #define RSET_HSSPI_SIZE 1536 197 #define RSET_UDC_SIZE 256 198 #define RSET_OHCI_SIZE 256 199 #define RSET_EHCI_SIZE 256 ··· 265 #define BCM_6328_UART1_BASE (0xb0000120) 266 #define BCM_6328_GPIO_BASE (0xb0000080) 267 #define BCM_6328_SPI_BASE (0xdeadbeef) 268 + #define BCM_6328_HSSPI_BASE (0xb0001000) 269 #define BCM_6328_UDC0_BASE (0xdeadbeef) 270 #define BCM_6328_USBDMA_BASE (0xb000c000) 271 #define BCM_6328_OHCI0_BASE (0xb0002600) ··· 313 #define BCM_6338_UART1_BASE (0xdeadbeef) 314 #define BCM_6338_GPIO_BASE (0xfffe0400) 315 #define BCM_6338_SPI_BASE (0xfffe0c00) 316 + #define BCM_6338_HSSPI_BASE (0xdeadbeef) 317 #define BCM_6338_UDC0_BASE (0xdeadbeef) 318 #define BCM_6338_USBDMA_BASE (0xfffe2400) 319 #define BCM_6338_OHCI0_BASE (0xdeadbeef) ··· 360 #define BCM_6345_UART1_BASE (0xdeadbeef) 361 #define BCM_6345_GPIO_BASE (0xfffe0400) 362 #define BCM_6345_SPI_BASE (0xdeadbeef) 363 + #define BCM_6345_HSSPI_BASE (0xdeadbeef) 364 #define BCM_6345_UDC0_BASE (0xdeadbeef) 365 #define BCM_6345_USBDMA_BASE (0xfffe2800) 366 #define BCM_6345_ENET0_BASE (0xfffe1800) ··· 406 #define BCM_6348_UART1_BASE (0xdeadbeef) 407 #define BCM_6348_GPIO_BASE (0xfffe0400) 408 #define BCM_6348_SPI_BASE (0xfffe0c00) 409 + #define BCM_6348_HSSPI_BASE (0xdeadbeef) 410 #define BCM_6348_UDC0_BASE (0xfffe1000) 411 #define BCM_6348_USBDMA_BASE (0xdeadbeef) 412 #define BCM_6348_OHCI0_BASE (0xfffe1b00) ··· 451 #define BCM_6358_UART1_BASE (0xfffe0120) 452 #define BCM_6358_GPIO_BASE (0xfffe0080) 453 #define BCM_6358_SPI_BASE (0xfffe0800) 454 + #define BCM_6358_HSSPI_BASE (0xdeadbeef) 455 #define BCM_6358_UDC0_BASE (0xfffe0800) 456 #define BCM_6358_USBDMA_BASE (0xdeadbeef) 457 #define BCM_6358_OHCI0_BASE (0xfffe1400) ··· 553 #define BCM_6368_UART1_BASE (0xb0000120) 554 #define BCM_6368_GPIO_BASE (0xb0000080) 555 #define BCM_6368_SPI_BASE (0xb0000800) 556 + #define BCM_6368_HSSPI_BASE (0xdeadbeef) 557 #define BCM_6368_UDC0_BASE (0xdeadbeef) 558 #define BCM_6368_USBDMA_BASE (0xb0004800) 559 #define BCM_6368_OHCI0_BASE (0xb0001600) ··· 604 __GEN_RSET_BASE(__cpu, UART1) \ 605 __GEN_RSET_BASE(__cpu, GPIO) \ 606 __GEN_RSET_BASE(__cpu, SPI) \ 607 + __GEN_RSET_BASE(__cpu, HSSPI) \ 608 __GEN_RSET_BASE(__cpu, UDC0) \ 609 __GEN_RSET_BASE(__cpu, OHCI0) \ 610 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ ··· 647 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ 648 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ 649 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ 650 + [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \ 651 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ 652 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ 653 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ ··· 727 IRQ_ENET0, 728 IRQ_ENET1, 729 IRQ_ENET_PHY, 730 + IRQ_HSSPI, 731 IRQ_OHCI0, 732 IRQ_EHCI0, 733 IRQ_USBD, ··· 815 #define BCM_6328_ENET0_IRQ 0 816 #define BCM_6328_ENET1_IRQ 0 817 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 818 + #define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29) 819 #define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9) 820 #define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10) 821 #define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4) ··· 860 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 861 #define BCM_6338_ENET1_IRQ 0 862 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 863 + #define BCM_6338_HSSPI_IRQ 0 864 #define BCM_6338_OHCI0_IRQ 0 865 #define BCM_6338_EHCI0_IRQ 0 866 #define BCM_6338_USBD_IRQ 0 ··· 898 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 899 #define BCM_6345_ENET1_IRQ 0 900 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 901 + #define BCM_6345_HSSPI_IRQ 0 902 #define BCM_6345_OHCI0_IRQ 0 903 #define BCM_6345_EHCI0_IRQ 0 904 #define BCM_6345_USBD_IRQ 0 ··· 936 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 937 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 938 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 939 + #define BCM_6348_HSSPI_IRQ 0 940 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 941 #define BCM_6348_EHCI0_IRQ 0 942 #define BCM_6348_USBD_IRQ 0 ··· 974 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 975 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 976 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 977 + #define BCM_6358_HSSPI_IRQ 0 978 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 979 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 980 #define BCM_6358_USBD_IRQ 0 ··· 1086 #define BCM_6368_ENET0_IRQ 0 1087 #define BCM_6368_ENET1_IRQ 0 1088 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15) 1089 + #define BCM_6368_HSSPI_IRQ 0 1090 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 1091 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7) 1092 #define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8) ··· 1133 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \ 1134 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \ 1135 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \ 1136 + [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \ 1137 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \ 1138 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \ 1139 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
+8
arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_hsspi.h
···
··· 1 + #ifndef BCM63XX_DEV_HSSPI_H 2 + #define BCM63XX_DEV_HSSPI_H 3 + 4 + #include <linux/types.h> 5 + 6 + int bcm63xx_hsspi_register(void); 7 + 8 + #endif /* BCM63XX_DEV_HSSPI_H */
-120
arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
··· 463 #define WDT_SOFTRESET_REG 0xc 464 465 /************************************************************************* 466 - * _REG relative to RSET_UARTx 467 - *************************************************************************/ 468 - 469 - /* UART Control Register */ 470 - #define UART_CTL_REG 0x0 471 - #define UART_CTL_RXTMOUTCNT_SHIFT 0 472 - #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 473 - #define UART_CTL_RSTTXDN_SHIFT 5 474 - #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 475 - #define UART_CTL_RSTRXFIFO_SHIFT 6 476 - #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 477 - #define UART_CTL_RSTTXFIFO_SHIFT 7 478 - #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 479 - #define UART_CTL_STOPBITS_SHIFT 8 480 - #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 481 - #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 482 - #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 483 - #define UART_CTL_BITSPERSYM_SHIFT 12 484 - #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 485 - #define UART_CTL_XMITBRK_SHIFT 14 486 - #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 487 - #define UART_CTL_RSVD_SHIFT 15 488 - #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 489 - #define UART_CTL_RXPAREVEN_SHIFT 16 490 - #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 491 - #define UART_CTL_RXPAREN_SHIFT 17 492 - #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 493 - #define UART_CTL_TXPAREVEN_SHIFT 18 494 - #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 495 - #define UART_CTL_TXPAREN_SHIFT 18 496 - #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 497 - #define UART_CTL_LOOPBACK_SHIFT 20 498 - #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 499 - #define UART_CTL_RXEN_SHIFT 21 500 - #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 501 - #define UART_CTL_TXEN_SHIFT 22 502 - #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 503 - #define UART_CTL_BRGEN_SHIFT 23 504 - #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 505 - 506 - /* UART Baudword register */ 507 - #define UART_BAUD_REG 0x4 508 - 509 - /* UART Misc Control register */ 510 - #define UART_MCTL_REG 0x8 511 - #define UART_MCTL_DTR_SHIFT 0 512 - #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 513 - #define UART_MCTL_RTS_SHIFT 1 514 - #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 515 - #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 516 - #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 517 - #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 518 - #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 519 - #define UART_MCTL_RXFIFOFILL_SHIFT 16 520 - #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 521 - #define UART_MCTL_TXFIFOFILL_SHIFT 24 522 - #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 523 - 524 - /* UART External Input Configuration register */ 525 - #define UART_EXTINP_REG 0xc 526 - #define UART_EXTINP_RI_SHIFT 0 527 - #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 528 - #define UART_EXTINP_CTS_SHIFT 1 529 - #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 530 - #define UART_EXTINP_DCD_SHIFT 2 531 - #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 532 - #define UART_EXTINP_DSR_SHIFT 3 533 - #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 534 - #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 535 - #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 536 - #define UART_EXTINP_IR_RI 0 537 - #define UART_EXTINP_IR_CTS 1 538 - #define UART_EXTINP_IR_DCD 2 539 - #define UART_EXTINP_IR_DSR 3 540 - #define UART_EXTINP_RI_NOSENSE_SHIFT 16 541 - #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 542 - #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 543 - #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 544 - #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 545 - #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 546 - #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 547 - #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 548 - 549 - /* UART Interrupt register */ 550 - #define UART_IR_REG 0x10 551 - #define UART_IR_MASK(x) (1 << (x + 16)) 552 - #define UART_IR_STAT(x) (1 << (x)) 553 - #define UART_IR_EXTIP 0 554 - #define UART_IR_TXUNDER 1 555 - #define UART_IR_TXOVER 2 556 - #define UART_IR_TXTRESH 3 557 - #define UART_IR_TXRDLATCH 4 558 - #define UART_IR_TXEMPTY 5 559 - #define UART_IR_RXUNDER 6 560 - #define UART_IR_RXOVER 7 561 - #define UART_IR_RXTIMEOUT 8 562 - #define UART_IR_RXFULL 9 563 - #define UART_IR_RXTHRESH 10 564 - #define UART_IR_RXNOTEMPTY 11 565 - #define UART_IR_RXFRAMEERR 12 566 - #define UART_IR_RXPARERR 13 567 - #define UART_IR_RXBRK 14 568 - #define UART_IR_TXDONE 15 569 - 570 - /* UART Fifo register */ 571 - #define UART_FIFO_REG 0x14 572 - #define UART_FIFO_VALID_SHIFT 0 573 - #define UART_FIFO_VALID_MASK 0xff 574 - #define UART_FIFO_FRAMEERR_SHIFT 8 575 - #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 576 - #define UART_FIFO_PARERR_SHIFT 9 577 - #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 578 - #define UART_FIFO_BRKDET_SHIFT 10 579 - #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 580 - #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 581 - UART_FIFO_PARERR_MASK | \ 582 - UART_FIFO_BRKDET_MASK) 583 - 584 - 585 - /************************************************************************* 586 * _REG relative to RSET_GPIO 587 *************************************************************************/ 588
··· 463 #define WDT_SOFTRESET_REG 0xc 464 465 /************************************************************************* 466 * _REG relative to RSET_GPIO 467 *************************************************************************/ 468
-4
arch/mips/include/asm/mach-generic/dma-coherence.h
··· 49 50 static inline int plat_device_is_coherent(struct device *dev) 51 { 52 - #ifdef CONFIG_DMA_COHERENT 53 - return 1; 54 - #else 55 return coherentio; 56 - #endif 57 } 58 59 #ifdef CONFIG_SWIOTLB
··· 49 50 static inline int plat_device_is_coherent(struct device *dev) 51 { 52 return coherentio; 53 } 54 55 #ifdef CONFIG_SWIOTLB
-1
arch/mips/include/asm/mach-generic/floppy.h
··· 9 #define __ASM_MACH_GENERIC_FLOPPY_H 10 11 #include <linux/delay.h> 12 - #include <linux/init.h> 13 #include <linux/ioport.h> 14 #include <linux/sched.h> 15 #include <linux/linkage.h>
··· 9 #define __ASM_MACH_GENERIC_FLOPPY_H 10 11 #include <linux/delay.h> 12 #include <linux/ioport.h> 13 #include <linux/sched.h> 14 #include <linux/linkage.h>
+3 -3
arch/mips/include/asm/mach-generic/ide.h
··· 23 static inline void __ide_flush_prologue(void) 24 { 25 #ifdef CONFIG_SMP 26 - if (cpu_has_dc_aliases) 27 preempt_disable(); 28 #endif 29 } ··· 31 static inline void __ide_flush_epilogue(void) 32 { 33 #ifdef CONFIG_SMP 34 - if (cpu_has_dc_aliases) 35 preempt_enable(); 36 #endif 37 } 38 39 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) 40 { 41 - if (cpu_has_dc_aliases) { 42 unsigned long end = addr + size; 43 44 while (addr < end) {
··· 23 static inline void __ide_flush_prologue(void) 24 { 25 #ifdef CONFIG_SMP 26 + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 27 preempt_disable(); 28 #endif 29 } ··· 31 static inline void __ide_flush_epilogue(void) 32 { 33 #ifdef CONFIG_SMP 34 + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 35 preempt_enable(); 36 #endif 37 } 38 39 static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size) 40 { 41 + if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { 42 unsigned long end = addr + size; 43 44 while (addr < end) {
-1
arch/mips/include/asm/mach-jazz/floppy.h
··· 9 #define __ASM_MACH_JAZZ_FLOPPY_H 10 11 #include <linux/delay.h> 12 - #include <linux/init.h> 13 #include <linux/linkage.h> 14 #include <linux/types.h> 15 #include <linux/mm.h>
··· 9 #define __ASM_MACH_JAZZ_FLOPPY_H 10 11 #include <linux/delay.h> 12 #include <linux/linkage.h> 13 #include <linux/types.h> 14 #include <linux/mm.h>
+1
arch/mips/include/asm/mach-jz4740/platform.h
··· 21 22 extern struct platform_device jz4740_usb_ohci_device; 23 extern struct platform_device jz4740_udc_device; 24 extern struct platform_device jz4740_mmc_device; 25 extern struct platform_device jz4740_rtc_device; 26 extern struct platform_device jz4740_i2c_device;
··· 21 22 extern struct platform_device jz4740_usb_ohci_device; 23 extern struct platform_device jz4740_udc_device; 24 + extern struct platform_device jz4740_udc_xceiv_device; 25 extern struct platform_device jz4740_mmc_device; 26 extern struct platform_device jz4740_rtc_device; 27 extern struct platform_device jz4740_i2c_device;
+2 -1
arch/mips/include/asm/mach-netlogic/irq.h
··· 9 #define __ASM_NETLOGIC_IRQ_H 10 11 #include <asm/mach-netlogic/multi-node.h> 12 - #define NR_IRQS (64 * NLM_NR_NODES) 13 14 #define MIPS_CPU_IRQ_BASE 0 15
··· 9 #define __ASM_NETLOGIC_IRQ_H 10 11 #include <asm/mach-netlogic/multi-node.h> 12 + #define NLM_IRQS_PER_NODE 1024 13 + #define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES) 14 15 #define MIPS_CPU_IRQ_BASE 0 16
+31 -2
arch/mips/include/asm/mach-netlogic/multi-node.h
··· 47 #endif 48 #endif 49 50 - #define NLM_CORES_PER_NODE 8 51 #define NLM_THREADS_PER_CORE 4 52 - #define NLM_CPUS_PER_NODE (NLM_CORES_PER_NODE * NLM_THREADS_PER_CORE) 53 54 #endif
··· 47 #endif 48 #endif 49 50 #define NLM_THREADS_PER_CORE 4 51 + #ifdef CONFIG_CPU_XLR 52 + #define nlm_cores_per_node() 8 53 + #else 54 + extern unsigned int xlp_cores_per_node; 55 + #define nlm_cores_per_node() xlp_cores_per_node 56 + #endif 57 + 58 + #define nlm_threads_per_node() (nlm_cores_per_node() * NLM_THREADS_PER_CORE) 59 + #define nlm_cpuid_to_node(c) ((c) / nlm_threads_per_node()) 60 + 61 + struct nlm_soc_info { 62 + unsigned long coremask; /* cores enabled on the soc */ 63 + unsigned long ebase; /* not used now */ 64 + uint64_t irqmask; /* EIMR for the node */ 65 + uint64_t sysbase; /* only for XLP - sys block base */ 66 + uint64_t picbase; /* PIC block base */ 67 + spinlock_t piclock; /* lock for PIC access */ 68 + cpumask_t cpumask; /* logical cpu mask for node */ 69 + unsigned int socbus; 70 + }; 71 + 72 + extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 73 + #define nlm_get_node(i) (&nlm_nodes[i]) 74 + #define nlm_node_present(n) ((n) >= 0 && (n) < NLM_NR_NODES && \ 75 + nlm_get_node(n)->coremask != 0) 76 + #ifdef CONFIG_CPU_XLR 77 + #define nlm_current_node() (&nlm_nodes[0]) 78 + #else 79 + #define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) 80 + #endif 81 + void nlm_node_init(int node); 82 83 #endif
+20
arch/mips/include/asm/mach-netlogic/topology.h
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2013 Broadcom Corporation 7 + */ 8 + #ifndef _ASM_MACH_NETLOGIC_TOPOLOGY_H 9 + #define _ASM_MACH_NETLOGIC_TOPOLOGY_H 10 + 11 + #include <asm/mach-netlogic/multi-node.h> 12 + 13 + #define topology_physical_package_id(cpu) cpu_to_node(cpu) 14 + #define topology_core_id(cpu) (cpu_logical_map(cpu) / NLM_THREADS_PER_CORE) 15 + #define topology_thread_cpumask(cpu) (&cpu_sibling_map[cpu]) 16 + #define topology_core_cpumask(cpu) cpumask_of_node(cpu_to_node(cpu)) 17 + 18 + #include <asm-generic/topology.h> 19 + 20 + #endif /* _ASM_MACH_NETLOGIC_TOPOLOGY_H */
+7
arch/mips/include/asm/mips-boards/piix4.h
··· 26 #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 27 #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 28 #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 29 /* Top Of Memory */ 30 #define PIIX4_FUNC0_TOM 0x69 31 #define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 ··· 38 #define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 39 #define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 40 #define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 41 42 /* IDE Timing */ 43 #define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
··· 26 #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 27 #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 28 #define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 29 + /* SERIRQ Control */ 30 + #define PIIX4_FUNC0_SERIRQC 0x64 31 + #define PIIX4_FUNC0_SERIRQC_EN (1 << 7) 32 + #define PIIX4_FUNC0_SERIRQC_CONT (1 << 6) 33 /* Top Of Memory */ 34 #define PIIX4_FUNC0_TOM 0x69 35 #define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 ··· 34 #define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 35 #define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 36 #define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 37 + /* General Configuration */ 38 + #define PIIX4_FUNC0_GENCFG 0xb0 39 + #define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16) 40 41 /* IDE Timing */ 42 #define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40
+82 -1
arch/mips/include/asm/mipsregs.h
··· 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 #include <asm/hazards.h> 18 #include <asm/war.h> 19 ··· 574 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 575 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 576 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 577 - #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 578 579 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 580 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) ··· 590 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 591 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 592 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 593 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 594 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 595 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 596 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 597 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 598 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 599 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 600 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 601 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 602 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 603 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 604 605 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 606 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 607 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 608 609 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 610 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) ··· 646 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 647 648 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 649 650 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 651 652 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 653 654 655 /* 656 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. ··· 666 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 667 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 668 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 669 670 #ifndef __ASSEMBLY__ 671 ··· 706 707 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 708 } 709 710 /* 711 * Functions to access the R10000 performance counters. These are basically ··· 1174 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1175 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1176 1177 1178 /* Cavium OCTEON (cnMIPS) */ 1179 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
··· 14 #define _ASM_MIPSREGS_H 15 16 #include <linux/linkage.h> 17 + #include <linux/types.h> 18 #include <asm/hazards.h> 19 #include <asm/war.h> 20 ··· 573 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 574 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 575 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 576 + #define MIPS_CONF1_TLBS_SHIFT (25) 577 + #define MIPS_CONF1_TLBS_SIZE (6) 578 + #define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT) 579 580 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 581 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) ··· 587 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 588 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 589 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 590 + #define MIPS_CONF3_CDMM (_ULCAST_(1) << 3) 591 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 592 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 593 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 594 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 595 + #define MIPS_CONF3_ITL (_ULCAST_(1) << 8) 596 + #define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9) 597 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 598 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 599 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 600 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 601 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 602 #define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16) 603 + #define MIPS_CONF3_MCU (_ULCAST_(1) << 17) 604 + #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18) 605 + #define MIPS_CONF3_IPLW (_ULCAST_(3) << 21) 606 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 607 + #define MIPS_CONF3_PW (_ULCAST_(1) << 24) 608 + #define MIPS_CONF3_SC (_ULCAST_(1) << 25) 609 + #define MIPS_CONF3_BI (_ULCAST_(1) << 26) 610 + #define MIPS_CONF3_BP (_ULCAST_(1) << 27) 611 + #define MIPS_CONF3_MSA (_ULCAST_(1) << 28) 612 + #define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29) 613 + #define MIPS_CONF3_BPG (_ULCAST_(1) << 30) 614 615 + #define MIPS_CONF4_MMUSIZEEXT_SHIFT (0) 616 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 617 + #define MIPS_CONF4_FTLBSETS_SHIFT (0) 618 + #define MIPS_CONF4_FTLBSETS_SHIFT (0) 619 + #define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT) 620 + #define MIPS_CONF4_FTLBWAYS_SHIFT (4) 621 + #define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT) 622 + #define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8) 623 + /* bits 10:8 in FTLB-only configurations */ 624 + #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 625 + /* bits 12:8 in VTLB-FTLB only configurations */ 626 + #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT) 627 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 628 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 629 + #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14) 630 + #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14) 631 + #define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16) 632 + #define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24) 633 + #define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT) 634 + #define MIPS_CONF4_AE (_ULCAST_(1) << 28) 635 + #define MIPS_CONF4_IE (_ULCAST_(3) << 29) 636 + #define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29) 637 638 #define MIPS_CONF5_NF (_ULCAST_(1) << 0) 639 #define MIPS_CONF5_UFR (_ULCAST_(1) << 2) ··· 611 #define MIPS_CONF5_K (_ULCAST_(1) << 30) 612 613 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 614 + /* proAptiv FTLB on/off bit */ 615 + #define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15) 616 617 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 618 619 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 620 621 + /* EntryHI bit definition */ 622 + #define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10) 623 624 /* 625 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. ··· 627 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 628 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 629 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 630 + 631 + /* 632 + * Bits in the MIPS32 Memory Segmentation registers. 633 + */ 634 + #define MIPS_SEGCFG_PA_SHIFT 9 635 + #define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT) 636 + #define MIPS_SEGCFG_AM_SHIFT 4 637 + #define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT) 638 + #define MIPS_SEGCFG_EU_SHIFT 3 639 + #define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT) 640 + #define MIPS_SEGCFG_C_SHIFT 0 641 + #define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT) 642 + 643 + #define MIPS_SEGCFG_UUSK _ULCAST_(7) 644 + #define MIPS_SEGCFG_USK _ULCAST_(5) 645 + #define MIPS_SEGCFG_MUSUK _ULCAST_(4) 646 + #define MIPS_SEGCFG_MUSK _ULCAST_(3) 647 + #define MIPS_SEGCFG_MSK _ULCAST_(2) 648 + #define MIPS_SEGCFG_MK _ULCAST_(1) 649 + #define MIPS_SEGCFG_UK _ULCAST_(0) 650 651 #ifndef __ASSEMBLY__ 652 ··· 647 648 return (opcode >= 1 && opcode <= 3) ? 1 : 0; 649 } 650 + 651 + /* 652 + * TLB Invalidate Flush 653 + */ 654 + static inline void tlbinvf(void) 655 + { 656 + __asm__ __volatile__( 657 + ".set push\n\t" 658 + ".set noreorder\n\t" 659 + ".word 0x42000004\n\t" /* tlbinvf */ 660 + ".set pop"); 661 + } 662 + 663 664 /* 665 * Functions to access the R10000 performance counters. These are basically ··· 1102 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1103 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1104 1105 + /* MIPSR3 */ 1106 + #define read_c0_segctl0() __read_32bit_c0_register($5, 2) 1107 + #define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val) 1108 + 1109 + #define read_c0_segctl1() __read_32bit_c0_register($5, 3) 1110 + #define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val) 1111 + 1112 + #define read_c0_segctl2() __read_32bit_c0_register($5, 4) 1113 + #define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val) 1114 1115 /* Cavium OCTEON (cnMIPS) */ 1116 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
+6 -18
arch/mips/include/asm/netlogic/common.h
··· 84 */ 85 void nlm_init_boot_cpu(void); 86 unsigned int nlm_get_cpu_frequency(void); 87 - void nlm_node_init(int node); 88 extern struct plat_smp_ops nlm_smp_ops; 89 extern char nlm_reset_entry[], nlm_reset_entry_end[]; 90 ··· 93 extern unsigned int nlm_threads_per_core; 94 extern cpumask_t nlm_cpumask; 95 96 - struct nlm_soc_info { 97 - unsigned long coremask; /* cores enabled on the soc */ 98 - unsigned long ebase; 99 - uint64_t irqmask; 100 - uint64_t sysbase; /* only for XLP */ 101 - uint64_t picbase; 102 - spinlock_t piclock; 103 - }; 104 - 105 - #define nlm_get_node(i) (&nlm_nodes[i]) 106 - #ifdef CONFIG_CPU_XLR 107 - #define nlm_current_node() (&nlm_nodes[0]) 108 - #else 109 - #define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) 110 - #endif 111 - 112 struct irq_data; 113 uint64_t nlm_pci_irqmask(int node); 114 void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); 115 116 /* 117 * The NR_IRQs is divided between nodes, each of them has a separate irq space ··· 111 return node * NR_IRQS / NLM_NR_NODES + irq; 112 } 113 114 - extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 115 extern int nlm_cpu_ready[]; 116 #endif 117 #endif /* _NETLOGIC_COMMON_H_ */
··· 84 */ 85 void nlm_init_boot_cpu(void); 86 unsigned int nlm_get_cpu_frequency(void); 87 extern struct plat_smp_ops nlm_smp_ops; 88 extern char nlm_reset_entry[], nlm_reset_entry_end[]; 89 ··· 94 extern unsigned int nlm_threads_per_core; 95 extern cpumask_t nlm_cpumask; 96 97 struct irq_data; 98 uint64_t nlm_pci_irqmask(int node); 99 + void nlm_setup_pic_irq(int node, int picirq, int irq, int irt); 100 void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); 101 + 102 + #ifdef CONFIG_PCI_MSI 103 + void nlm_dispatch_msi(int node, int lirq); 104 + void nlm_dispatch_msix(int node, int msixirq); 105 + #endif 106 107 /* 108 * The NR_IRQs is divided between nodes, each of them has a separate irq space ··· 122 return node * NR_IRQS / NLM_NR_NODES + irq; 123 } 124 125 extern int nlm_cpu_ready[]; 126 #endif 127 #endif /* _NETLOGIC_COMMON_H_ */
+6 -1
arch/mips/include/asm/netlogic/mips-extns.h
··· 146 147 static inline int nlm_nodeid(void) 148 { 149 - return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; 150 } 151 152 static inline unsigned int nlm_core_id(void)
··· 146 147 static inline int nlm_nodeid(void) 148 { 149 + uint32_t prid = read_c0_prid(); 150 + 151 + if ((prid & 0xff00) == PRID_IMP_NETLOGIC_XLP9XX) 152 + return (__read_32bit_c0_register($15, 1) >> 7) & 0x7; 153 + else 154 + return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; 155 } 156 157 static inline unsigned int nlm_core_id(void)
+32 -37
arch/mips/include/asm/netlogic/xlp-hal/bridge.h
··· 69 #define BRIDGE_FLASH_LIMIT3 0x13 70 71 #define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 72 - #define BRIDGE_DRAM_BAR0 0x14 73 - #define BRIDGE_DRAM_BAR1 0x15 74 - #define BRIDGE_DRAM_BAR2 0x16 75 - #define BRIDGE_DRAM_BAR3 0x17 76 - #define BRIDGE_DRAM_BAR4 0x18 77 - #define BRIDGE_DRAM_BAR5 0x19 78 - #define BRIDGE_DRAM_BAR6 0x1a 79 - #define BRIDGE_DRAM_BAR7 0x1b 80 - 81 #define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 82 - #define BRIDGE_DRAM_LIMIT0 0x1c 83 - #define BRIDGE_DRAM_LIMIT1 0x1d 84 - #define BRIDGE_DRAM_LIMIT2 0x1e 85 - #define BRIDGE_DRAM_LIMIT3 0x1f 86 - #define BRIDGE_DRAM_LIMIT4 0x20 87 - #define BRIDGE_DRAM_LIMIT5 0x21 88 - #define BRIDGE_DRAM_LIMIT6 0x22 89 - #define BRIDGE_DRAM_LIMIT7 0x23 90 - 91 #define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) 92 - #define BRIDGE_DRAM_NODE_TRANSLN0 0x24 93 - #define BRIDGE_DRAM_NODE_TRANSLN1 0x25 94 - #define BRIDGE_DRAM_NODE_TRANSLN2 0x26 95 - #define BRIDGE_DRAM_NODE_TRANSLN3 0x27 96 - #define BRIDGE_DRAM_NODE_TRANSLN4 0x28 97 - #define BRIDGE_DRAM_NODE_TRANSLN5 0x29 98 - #define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 99 - #define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 100 - 101 #define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) 102 - #define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 103 - #define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 104 - #define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 105 - #define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f 106 - #define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 107 - #define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 108 - #define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 109 - #define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 110 111 #define BRIDGE_PCIEMEM_BASE0 0x34 112 #define BRIDGE_PCIEMEM_BASE1 0x35 ··· 143 #define BRIDGE_GIO_WEIGHT 0x2cb 144 #define BRIDGE_FLASH_WEIGHT 0x2cc 145 146 #ifndef __ASSEMBLY__ 147 148 #define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 149 #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 150 - #define nlm_get_bridge_pcibase(node) \ 151 - nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) 152 #define nlm_get_bridge_regbase(node) \ 153 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 154
··· 69 #define BRIDGE_FLASH_LIMIT3 0x13 70 71 #define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 72 #define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 73 #define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i)) 74 #define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i)) 75 76 #define BRIDGE_PCIEMEM_BASE0 0x34 77 #define BRIDGE_PCIEMEM_BASE1 0x35 ··· 178 #define BRIDGE_GIO_WEIGHT 0x2cb 179 #define BRIDGE_FLASH_WEIGHT 0x2cc 180 181 + /* FIXME verify */ 182 + #define BRIDGE_9XX_FLASH_BAR(i) (0x11 + (i)) 183 + #define BRIDGE_9XX_FLASH_BAR_LIMIT(i) (0x15 + (i)) 184 + 185 + #define BRIDGE_9XX_DRAM_BAR(i) (0x19 + (i)) 186 + #define BRIDGE_9XX_DRAM_LIMIT(i) (0x29 + (i)) 187 + #define BRIDGE_9XX_DRAM_NODE_TRANSLN(i) (0x39 + (i)) 188 + #define BRIDGE_9XX_DRAM_CHNL_TRANSLN(i) (0x49 + (i)) 189 + 190 + #define BRIDGE_9XX_ADDRESS_ERROR0 0x9d 191 + #define BRIDGE_9XX_ADDRESS_ERROR1 0x9e 192 + #define BRIDGE_9XX_ADDRESS_ERROR2 0x9f 193 + 194 + #define BRIDGE_9XX_PCIEMEM_BASE0 0x59 195 + #define BRIDGE_9XX_PCIEMEM_BASE1 0x5a 196 + #define BRIDGE_9XX_PCIEMEM_BASE2 0x5b 197 + #define BRIDGE_9XX_PCIEMEM_BASE3 0x5c 198 + #define BRIDGE_9XX_PCIEMEM_LIMIT0 0x5d 199 + #define BRIDGE_9XX_PCIEMEM_LIMIT1 0x5e 200 + #define BRIDGE_9XX_PCIEMEM_LIMIT2 0x5f 201 + #define BRIDGE_9XX_PCIEMEM_LIMIT3 0x60 202 + #define BRIDGE_9XX_PCIEIO_BASE0 0x61 203 + #define BRIDGE_9XX_PCIEIO_BASE1 0x62 204 + #define BRIDGE_9XX_PCIEIO_BASE2 0x63 205 + #define BRIDGE_9XX_PCIEIO_BASE3 0x64 206 + #define BRIDGE_9XX_PCIEIO_LIMIT0 0x65 207 + #define BRIDGE_9XX_PCIEIO_LIMIT1 0x66 208 + #define BRIDGE_9XX_PCIEIO_LIMIT2 0x67 209 + #define BRIDGE_9XX_PCIEIO_LIMIT3 0x68 210 + 211 #ifndef __ASSEMBLY__ 212 213 #define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 214 #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) 215 + #define nlm_get_bridge_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ 216 + XLP9XX_IO_BRIDGE_OFFSET(node) : XLP_IO_BRIDGE_OFFSET(node)) 217 #define nlm_get_bridge_regbase(node) \ 218 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) 219
+46 -2
arch/mips/include/asm/netlogic/xlp-hal/iomap.h
··· 48 #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 49 #define XLP_IO_PCI_HDRSZ 0x100 50 #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 51 - #define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ 52 - ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 53 54 #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) 55 /* coherent inter chip */ ··· 111 #define XLP_IO_MMC_OFFSET(node, slot) \ 112 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 113 114 /* PCI config header register id's */ 115 #define XLP_PCI_CFGREG0 0x00 116 #define XLP_PCI_CFGREG1 0x01 ··· 188 #define PCI_DEVICE_ID_NLM_MMC 0x1018 189 #define PCI_DEVICE_ID_NLM_XHCI 0x101d 190 191 #ifndef __ASSEMBLY__ 192 193 #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 194 #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) 195 196 #endif /* !__ASSEMBLY */ 197 198 #endif /* __NLM_HAL_IOMAP_H__ */
··· 48 #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 49 #define XLP_IO_PCI_HDRSZ 0x100 50 #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 51 + #define XLP_IO_PCI_OFFSET(b, d, f) (((b) << 20) | ((d) << 15) | ((f) << 12)) 52 + 53 + #define XLP_HDR_OFFSET(node, bus, dev, fn) \ 54 + XLP_IO_PCI_OFFSET(bus, XLP_IO_DEV(node, dev), fn) 55 56 #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) 57 /* coherent inter chip */ ··· 109 #define XLP_IO_MMC_OFFSET(node, slot) \ 110 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) 111 112 + /* Things have changed drastically in XLP 9XX */ 113 + #define XLP9XX_HDR_OFFSET(n, d, f) \ 114 + XLP_IO_PCI_OFFSET(xlp9xx_get_socbus(n), d, f) 115 + 116 + #define XLP9XX_IO_BRIDGE_OFFSET(node) XLP_IO_PCI_OFFSET(0, 0, node) 117 + #define XLP9XX_IO_PIC_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 0) 118 + #define XLP9XX_IO_UART_OFFSET(node) XLP9XX_HDR_OFFSET(node, 2, 2) 119 + #define XLP9XX_IO_SYS_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 0) 120 + #define XLP9XX_IO_FUSE_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 1) 121 + #define XLP9XX_IO_JTAG_OFFSET(node) XLP9XX_HDR_OFFSET(node, 6, 4) 122 + 123 + #define XLP9XX_IO_PCIE_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 1, i) 124 + #define XLP9XX_IO_PCIE0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 0) 125 + #define XLP9XX_IO_PCIE2_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 2) 126 + #define XLP9XX_IO_PCIE3_OFFSET(node) XLP9XX_HDR_OFFSET(node, 1, 3) 127 + 128 + /* XLP9xx USB block */ 129 + #define XLP9XX_IO_USB_OFFSET(node, i) XLP9XX_HDR_OFFSET(node, 4, i) 130 + #define XLP9XX_IO_USB_XHCI0_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 1) 131 + #define XLP9XX_IO_USB_XHCI1_OFFSET(node) XLP9XX_HDR_OFFSET(node, 4, 2) 132 + 133 + /* XLP9XX on-chip SATA controller */ 134 + #define XLP9XX_IO_SATA_OFFSET(node) XLP9XX_HDR_OFFSET(node, 3, 2) 135 + 136 + #define XLP9XX_IO_NOR_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 0) 137 + #define XLP9XX_IO_NAND_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 1) 138 + #define XLP9XX_IO_SPI_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 2) 139 + /* SD flash */ 140 + #define XLP9XX_IO_MMCSD_OFFSET(node) XLP9XX_HDR_OFFSET(node, 7, 3) 141 + 142 /* PCI config header register id's */ 143 #define XLP_PCI_CFGREG0 0x00 144 #define XLP_PCI_CFGREG1 0x01 ··· 156 #define PCI_DEVICE_ID_NLM_MMC 0x1018 157 #define PCI_DEVICE_ID_NLM_XHCI 0x101d 158 159 + #define PCI_DEVICE_ID_XLP9XX_SATA 0x901A 160 + #define PCI_DEVICE_ID_XLP9XX_XHCI 0x901D 161 + 162 #ifndef __ASSEMBLY__ 163 164 #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 165 #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) 166 167 + static inline int xlp9xx_get_socbus(int node) 168 + { 169 + uint64_t socbridge; 170 + 171 + if (node == 0) 172 + return 1; 173 + socbridge = nlm_pcicfg_base(XLP9XX_IO_BRIDGE_OFFSET(node)); 174 + return (nlm_read_pci_reg(socbridge, 0x6) >> 8) & 0xff; 175 + } 176 #endif /* !__ASSEMBLY */ 177 178 #endif /* __NLM_HAL_IOMAP_H__ */
+32 -9
arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
··· 52 #define PCIE_BYTE_SWAP_MEM_LIM 0x248 53 #define PCIE_BYTE_SWAP_IO_BASE 0x249 54 #define PCIE_BYTE_SWAP_IO_LIM 0x24A 55 #define PCIE_MSI_STATUS 0x25A 56 #define PCIE_MSI_EN 0x25B 57 #define PCIE_INT_EN0 0x261 58 59 - /* PCIE_MSI_EN */ 60 - #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF 61 62 - /* PCIE_INT_EN0 */ 63 - #define PCIE_MSI_INT_EN (1 << 9) 64 65 #ifndef __ASSEMBLY__ 66 67 #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) 68 #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) 69 - #define nlm_get_pcie_base(node, inst) \ 70 - nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) 71 - #define nlm_get_pcie_regbase(node, inst) \ 72 - (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) 73 74 - int xlp_pcie_link_irt(int link); 75 #endif 76 #endif /* __NLM_HAL_PCIBUS_H__ */
··· 52 #define PCIE_BYTE_SWAP_MEM_LIM 0x248 53 #define PCIE_BYTE_SWAP_IO_BASE 0x249 54 #define PCIE_BYTE_SWAP_IO_LIM 0x24A 55 + 56 + #define PCIE_BRIDGE_MSIX_ADDR_BASE 0x24F 57 + #define PCIE_BRIDGE_MSIX_ADDR_LIMIT 0x250 58 #define PCIE_MSI_STATUS 0x25A 59 #define PCIE_MSI_EN 0x25B 60 + #define PCIE_MSIX_STATUS 0x25D 61 + #define PCIE_INT_STATUS0 0x25F 62 + #define PCIE_INT_STATUS1 0x260 63 #define PCIE_INT_EN0 0x261 64 + #define PCIE_INT_EN1 0x262 65 66 + /* XLP9XX has basic changes */ 67 + #define PCIE_9XX_BYTE_SWAP_MEM_BASE 0x25c 68 + #define PCIE_9XX_BYTE_SWAP_MEM_LIM 0x25d 69 + #define PCIE_9XX_BYTE_SWAP_IO_BASE 0x25e 70 + #define PCIE_9XX_BYTE_SWAP_IO_LIM 0x25f 71 72 + /* other */ 73 + #define PCIE_NLINKS 4 74 75 + /* MSI addresses */ 76 + #define MSI_ADDR_BASE 0xfffee00000ULL 77 + #define MSI_ADDR_SZ 0x10000 78 + #define MSI_LINK_ADDR(n, l) (MSI_ADDR_BASE + \ 79 + (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ) 80 + #define MSIX_ADDR_BASE 0xfffef00000ULL 81 + #define MSIX_LINK_ADDR(n, l) (MSIX_ADDR_BASE + \ 82 + (PCIE_NLINKS * (n) + (l)) * MSI_ADDR_SZ) 83 #ifndef __ASSEMBLY__ 84 85 #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) 86 #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) 87 + #define nlm_get_pcie_base(node, inst) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ 88 + XLP9XX_IO_PCIE_OFFSET(node, inst) : XLP_IO_PCIE_OFFSET(node, inst)) 89 90 + #ifdef CONFIG_PCI_MSI 91 + void xlp_init_node_msi_irqs(int node, int link); 92 + #else 93 + static inline void xlp_init_node_msi_irqs(int node, int link) {} 94 + #endif 95 + 96 + struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev); 97 + 98 #endif 99 #endif /* __NLM_HAL_PCIBUS_H__ */
+48 -29
arch/mips/include/asm/netlogic/xlp-hal/pic.h
··· 150 #define PIC_IRT0 0x74 151 #define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 152 153 - #define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 154 155 /* 156 * IRT Map 157 */ 158 #define PIC_NUM_IRTS 160 159 160 #define PIC_IRT_WD_0_INDEX 0 161 #define PIC_IRT_WD_1_INDEX 1 ··· 200 #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 201 202 #define PIC_CLOCK_TIMER 7 203 - #define PIC_IRQ_BASE 8 204 205 #if !defined(LOCORE) && !defined(__ASSEMBLY__) 206 - 207 - #define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) 208 - #define PIC_IRT_LAST_IRQ 63 209 - #define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) 210 211 /* 212 * Misc ··· 212 213 #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 214 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 215 - #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 216 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 217 218 /* We use PIC on node 0 as a timer */ 219 #define pic_timer_freq() nlm_get_pic_frequency(0) 220 221 /* IRT and h/w interrupt routines */ 222 - static inline int 223 - nlm_pic_read_irt(uint64_t base, int irt_index) 224 - { 225 - return nlm_read_pic_reg(base, PIC_IRT(irt_index)); 226 - } 227 - 228 static inline void 229 - nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 230 { 231 uint64_t val; 232 233 - val = nlm_read_pic_reg(base, PIC_IRT(irt)); 234 - /* clear cpuset and mask */ 235 - val &= ~((0x7ull << 16) | 0xffff); 236 - /* set DB, cpuset and cpumask */ 237 - val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf)); 238 - nlm_write_pic_reg(base, PIC_IRT(irt), val); 239 } 240 241 static inline void ··· 252 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 253 int sch, int vec, int cpu) 254 { 255 - nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 256 - (cpu >> 4), /* thread group */ 257 - 1 << (cpu & 0xf)); /* thread mask */ 258 } 259 260 static inline uint64_t ··· 300 { 301 uint64_t reg; 302 303 - reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 304 - nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); 305 } 306 307 static inline void ··· 314 { 315 uint64_t reg; 316 317 - reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 318 - nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); 319 } 320 321 static inline void ··· 330 { 331 uint64_t ipi; 332 333 - ipi = ((uint64_t)nmi << 31) | (irq << 20); 334 - ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ 335 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 336 } 337
··· 150 #define PIC_IRT0 0x74 151 #define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 152 153 + #define PIC_9XX_PENDING_0 0x6 154 + #define PIC_9XX_PENDING_1 0x8 155 + #define PIC_9XX_PENDING_2 0xa 156 + #define PIC_9XX_PENDING_3 0xc 157 + 158 + #define PIC_9XX_IRT0 0x1c0 159 + #define PIC_9XX_IRT(i) (PIC_9XX_IRT0 + ((i) * 2)) 160 161 /* 162 * IRT Map 163 */ 164 #define PIC_NUM_IRTS 160 165 + #define PIC_9XX_NUM_IRTS 256 166 167 #define PIC_IRT_WD_0_INDEX 0 168 #define PIC_IRT_WD_1_INDEX 1 ··· 193 #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 194 195 #define PIC_CLOCK_TIMER 7 196 197 #if !defined(LOCORE) && !defined(__ASSEMBLY__) 198 199 /* 200 * Misc ··· 210 211 #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 212 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 213 + #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ 214 + XLP9XX_IO_PIC_OFFSET(node) : XLP_IO_PIC_OFFSET(node)) 215 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 216 217 /* We use PIC on node 0 as a timer */ 218 #define pic_timer_freq() nlm_get_pic_frequency(0) 219 220 /* IRT and h/w interrupt routines */ 221 static inline void 222 + nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, 223 + int sch, int vec, int dt, int db, int cpu) 224 { 225 uint64_t val; 226 227 + val = (((uint64_t)en & 0x1) << 22) | ((nmi & 0x1) << 23) | 228 + ((0 /*mc*/) << 20) | ((vec & 0x3f) << 24) | 229 + ((dt & 0x1) << 21) | (0 /*ptr*/ << 16) | 230 + (cpu & 0x3ff); 231 + 232 + nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); 233 } 234 235 static inline void ··· 254 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 255 int sch, int vec, int cpu) 256 { 257 + if (cpu_is_xlp9xx()) 258 + nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, 259 + 1, 0, cpu); 260 + else 261 + nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 262 + (cpu >> 4), /* thread group */ 263 + 1 << (cpu & 0xf)); /* thread mask */ 264 } 265 266 static inline uint64_t ··· 298 { 299 uint64_t reg; 300 301 + if (cpu_is_xlp9xx()) { 302 + reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); 303 + nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg | (1 << 22)); 304 + } else { 305 + reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 306 + nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); 307 + } 308 } 309 310 static inline void ··· 307 { 308 uint64_t reg; 309 310 + if (cpu_is_xlp9xx()) { 311 + reg = nlm_read_pic_reg(base, PIC_9XX_IRT(irt)); 312 + reg &= ~((uint64_t)1 << 22); 313 + nlm_write_pic_reg(base, PIC_9XX_IRT(irt), reg); 314 + } else { 315 + reg = nlm_read_pic_reg(base, PIC_IRT(irt)); 316 + reg &= ~((uint64_t)1 << 31); 317 + nlm_write_pic_reg(base, PIC_IRT(irt), reg); 318 + } 319 } 320 321 static inline void ··· 316 { 317 uint64_t ipi; 318 319 + if (cpu_is_xlp9xx()) 320 + ipi = (nmi << 23) | (irq << 24) | 321 + (0/*mcm*/ << 20) | (0/*ptr*/ << 16) | hwt; 322 + else 323 + ipi = ((uint64_t)nmi << 31) | (irq << 20) | 324 + ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); 325 + 326 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 327 } 328
+17 -1
arch/mips/include/asm/netlogic/xlp-hal/sys.h
··· 147 #define SYS_SYS_PLL_MEM_REQ 0x2a3 148 #define SYS_PLL_MEM_STAT 0x2a4 149 150 #ifndef __ASSEMBLY__ 151 152 #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 153 #define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 154 - #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 155 #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 156 157 unsigned int nlm_get_pic_frequency(int node); 158 #endif
··· 147 #define SYS_SYS_PLL_MEM_REQ 0x2a3 148 #define SYS_PLL_MEM_STAT 0x2a4 149 150 + /* Registers changed on 9XX */ 151 + #define SYS_9XX_POWER_ON_RESET_CFG 0x00 152 + #define SYS_9XX_CHIP_RESET 0x01 153 + #define SYS_9XX_CPU_RESET 0x02 154 + #define SYS_9XX_CPU_NONCOHERENT_MODE 0x03 155 + 156 + /* XLP 9XX fuse block registers */ 157 + #define FUSE_9XX_DEVCFG6 0xc6 158 + 159 #ifndef __ASSEMBLY__ 160 161 #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 162 #define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 163 + #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(cpu_is_xlp9xx() ? \ 164 + XLP9XX_IO_SYS_OFFSET(node) : XLP_IO_SYS_OFFSET(node)) 165 #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 166 + 167 + /* XLP9XX fuse block */ 168 + #define nlm_get_fuse_pcibase(node) \ 169 + nlm_pcicfg_base(XLP9XX_IO_FUSE_OFFSET(node)) 170 + #define nlm_get_fuse_regbase(node) \ 171 + (nlm_get_fuse_pcibase(node) + XLP_IO_PCI_HDRSZ) 172 173 unsigned int nlm_get_pic_frequency(int node); 174 #endif
+2 -1
arch/mips/include/asm/netlogic/xlp-hal/uart.h
··· 94 #define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) 95 #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) 96 #define nlm_get_uart_pcibase(node, inst) \ 97 - nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) 98 #define nlm_get_uart_regbase(node, inst) \ 99 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 100
··· 94 #define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) 95 #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) 96 #define nlm_get_uart_pcibase(node, inst) \ 97 + nlm_pcicfg_base(cpu_is_xlp9xx() ? XLP9XX_IO_UART_OFFSET(node) : \ 98 + XLP_IO_UART_OFFSET(node, inst)) 99 #define nlm_get_uart_regbase(node, inst) \ 100 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 101
+33 -5
arch/mips/include/asm/netlogic/xlp-hal/xlp.h
··· 37 38 #define PIC_UART_0_IRQ 17 39 #define PIC_UART_1_IRQ 18 40 - #define PIC_PCIE_LINK_0_IRQ 19 41 - #define PIC_PCIE_LINK_1_IRQ 20 42 - #define PIC_PCIE_LINK_2_IRQ 21 43 - #define PIC_PCIE_LINK_3_IRQ 22 44 45 #define PIC_EHCI_0_IRQ 23 46 #define PIC_EHCI_1_IRQ 24 ··· 50 #define PIC_2XX_XHCI_0_IRQ 23 51 #define PIC_2XX_XHCI_1_IRQ 24 52 #define PIC_2XX_XHCI_2_IRQ 25 53 54 #define PIC_MMC_IRQ 29 55 #define PIC_I2C_0_IRQ 30 56 #define PIC_I2C_1_IRQ 31 57 #define PIC_I2C_2_IRQ 32 58 #define PIC_I2C_3_IRQ 33 59 60 #ifndef __ASSEMBLY__ 61 ··· 86 void nlm_hal_init(void); 87 int xlp_get_dram_map(int n, uint64_t *dram_map); 88 89 /* Device tree related */ 90 void xlp_early_init_devtree(void); 91 void *xlp_dt_init(void *fdtp); ··· 97 { 98 int chip = read_c0_prid() & 0xff00; 99 100 - return chip == PRID_IMP_NETLOGIC_XLP2XX; 101 } 102 103 #endif /* !__ASSEMBLY__ */ 104 #endif /* _ASM_NLM_XLP_H */
··· 37 38 #define PIC_UART_0_IRQ 17 39 #define PIC_UART_1_IRQ 18 40 + 41 + #define PIC_PCIE_LINK_LEGACY_IRQ_BASE 19 42 + #define PIC_PCIE_LINK_LEGACY_IRQ(i) (19 + (i)) 43 44 #define PIC_EHCI_0_IRQ 23 45 #define PIC_EHCI_1_IRQ 24 ··· 51 #define PIC_2XX_XHCI_0_IRQ 23 52 #define PIC_2XX_XHCI_1_IRQ 24 53 #define PIC_2XX_XHCI_2_IRQ 25 54 + #define PIC_9XX_XHCI_0_IRQ 23 55 + #define PIC_9XX_XHCI_1_IRQ 24 56 57 #define PIC_MMC_IRQ 29 58 #define PIC_I2C_0_IRQ 30 59 #define PIC_I2C_1_IRQ 31 60 #define PIC_I2C_2_IRQ 32 61 #define PIC_I2C_3_IRQ 33 62 + 63 + #define PIC_PCIE_LINK_MSI_IRQ_BASE 44 /* 44 - 47 MSI IRQ */ 64 + #define PIC_PCIE_LINK_MSI_IRQ(i) (44 + (i)) 65 + 66 + /* MSI-X with second link-level dispatch */ 67 + #define PIC_PCIE_MSIX_IRQ_BASE 48 /* 48 - 51 MSI-X IRQ */ 68 + #define PIC_PCIE_MSIX_IRQ(i) (48 + (i)) 69 + 70 + #define NLM_MSIX_VEC_BASE 96 /* 96 - 127 - MSIX mapped */ 71 + #define NLM_MSI_VEC_BASE 128 /* 128 -255 - MSI mapped */ 72 + 73 + #define NLM_PIC_INDIRECT_VEC_BASE 512 74 + #define NLM_GPIO_VEC_BASE 768 75 + 76 + #define PIC_IRQ_BASE 8 77 + #define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE 78 + #define PIC_IRT_LAST_IRQ 63 79 80 #ifndef __ASSEMBLY__ 81 ··· 68 void nlm_hal_init(void); 69 int xlp_get_dram_map(int n, uint64_t *dram_map); 70 71 + struct pci_dev; 72 + int xlp_socdev_to_node(const struct pci_dev *dev); 73 + 74 /* Device tree related */ 75 void xlp_early_init_devtree(void); 76 void *xlp_dt_init(void *fdtp); ··· 76 { 77 int chip = read_c0_prid() & 0xff00; 78 79 + return chip == PRID_IMP_NETLOGIC_XLP2XX || 80 + chip == PRID_IMP_NETLOGIC_XLP9XX; 81 } 82 83 + static inline int cpu_is_xlp9xx(void) 84 + { 85 + int chip = read_c0_prid() & 0xff00; 86 + 87 + return chip == PRID_IMP_NETLOGIC_XLP9XX; 88 + } 89 #endif /* !__ASSEMBLY__ */ 90 #endif /* _ASM_NLM_XLP_H */
-5
arch/mips/include/asm/netlogic/xlr/xlr.h
··· 35 #ifndef _ASM_NLM_XLR_H 36 #define _ASM_NLM_XLR_H 37 38 - /* Platform UART functions */ 39 - struct uart_port; 40 - unsigned int nlm_xlr_uart_in(struct uart_port *, int); 41 - void nlm_xlr_uart_out(struct uart_port *, int, int); 42 - 43 /* SMP helpers */ 44 void xlr_wakeup_secondary_cpus(void); 45
··· 35 #ifndef _ASM_NLM_XLR_H 36 #define _ASM_NLM_XLR_H 37 38 /* SMP helpers */ 39 void xlr_wakeup_secondary_cpus(void); 40
+9
arch/mips/include/asm/octeon/cvmx-helper-board.h
··· 36 37 #include <asm/octeon/cvmx-helper.h> 38 39 typedef enum { 40 set_phy_link_flags_autoneg = 0x1, 41 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, ··· 160 * Returns Zero on success, negative on failure 161 */ 162 extern int __cvmx_helper_board_hardware_enable(int interface); 163 164 #endif /* __CVMX_HELPER_BOARD_H__ */
··· 36 37 #include <asm/octeon/cvmx-helper.h> 38 39 + enum cvmx_helper_board_usb_clock_types { 40 + USB_CLOCK_TYPE_REF_12, 41 + USB_CLOCK_TYPE_REF_24, 42 + USB_CLOCK_TYPE_REF_48, 43 + USB_CLOCK_TYPE_CRYSTAL_12, 44 + }; 45 + 46 typedef enum { 47 set_phy_link_flags_autoneg = 0x1, 48 set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, ··· 153 * Returns Zero on success, negative on failure 154 */ 155 extern int __cvmx_helper_board_hardware_enable(int interface); 156 + 157 + enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(void); 158 159 #endif /* __CVMX_HELPER_BOARD_H__ */
+25
arch/mips/include/asm/page.h
··· 11 12 #include <spaces.h> 13 #include <linux/const.h> 14 15 /* 16 * PAGE_SHIFT determines the page size ··· 34 #endif 35 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 36 #define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 37 38 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 39 #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
··· 11 12 #include <spaces.h> 13 #include <linux/const.h> 14 + #include <linux/kernel.h> 15 + #include <asm/mipsregs.h> 16 17 /* 18 * PAGE_SHIFT determines the page size ··· 32 #endif 33 #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) 34 #define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 35 + 36 + /* 37 + * This is used for calculating the real page sizes 38 + * for FTLB or VTLB + FTLB confugrations. 39 + */ 40 + static inline unsigned int page_size_ftlb(unsigned int mmuextdef) 41 + { 42 + switch (mmuextdef) { 43 + case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 44 + if (PAGE_SIZE == (1 << 30)) 45 + return 5; 46 + if (PAGE_SIZE == (1llu << 32)) 47 + return 6; 48 + if (PAGE_SIZE > (256 << 10)) 49 + return 7; /* reserved */ 50 + /* fall through */ 51 + case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 52 + return (PAGE_SHIFT - 10) / 2; 53 + default: 54 + panic("Invalid FTLB configuration with Conf4_mmuextdef=%d value\n", 55 + mmuextdef >> 14); 56 + } 57 + } 58 59 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 60 #define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
+36 -13
arch/mips/include/asm/rtlx.h
··· 1 /* 2 - * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 3 * 4 */ 5 - 6 #ifndef __ASM_RTLX_H_ 7 #define __ASM_RTLX_H_ 8 9 #include <irq.h> 10 11 #define LX_NODE_BASE 10 12 ··· 20 #define RTLX_VERSION 2 21 #define RTLX_xID 0x12345600 22 #define RTLX_ID (RTLX_xID | RTLX_VERSION) 23 #define RTLX_CHANNELS 8 24 25 #define RTLX_CHANNEL_STDIO 0 26 #define RTLX_CHANNEL_DBG 1 27 #define RTLX_CHANNEL_SYSIO 2 28 29 - extern int rtlx_open(int index, int can_sleep); 30 - extern int rtlx_release(int index); 31 - extern ssize_t rtlx_read(int index, void __user *buff, size_t count); 32 - extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count); 33 - extern unsigned int rtlx_read_poll(int index, int can_sleep); 34 - extern unsigned int rtlx_write_poll(int index); 35 36 enum rtlx_state { 37 RTLX_STATE_UNUSED = 0, ··· 53 RTLX_STATE_OPENED 54 }; 55 56 - #define RTLX_BUFFER_SIZE 2048 57 58 /* each channel supports read and write. 59 - linux (vpe0) reads lx_buffer and writes rt_buffer 60 SP (vpe1) reads rt_buffer and writes lx_buffer 61 */ 62 struct rtlx_channel { ··· 78 char *lx_buffer; 79 }; 80 81 - struct rtlx_info { 82 unsigned long id; 83 enum rtlx_state state; 84 85 struct rtlx_channel channel[RTLX_CHANNELS]; 86 - }; 87 - 88 #endif /* __ASM_RTLX_H_ */
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 * 6 + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 */ 9 #ifndef __ASM_RTLX_H_ 10 #define __ASM_RTLX_H_ 11 12 #include <irq.h> 13 + 14 + #define RTLX_MODULE_NAME "rtlx" 15 16 #define LX_NODE_BASE 10 17 ··· 15 #define RTLX_VERSION 2 16 #define RTLX_xID 0x12345600 17 #define RTLX_ID (RTLX_xID | RTLX_VERSION) 18 + #define RTLX_BUFFER_SIZE 2048 19 #define RTLX_CHANNELS 8 20 21 #define RTLX_CHANNEL_STDIO 0 22 #define RTLX_CHANNEL_DBG 1 23 #define RTLX_CHANNEL_SYSIO 2 24 25 + void rtlx_starting(int vpe); 26 + void rtlx_stopping(int vpe); 27 + 28 + int rtlx_open(int index, int can_sleep); 29 + int rtlx_release(int index); 30 + ssize_t rtlx_read(int index, void __user *buff, size_t count); 31 + ssize_t rtlx_write(int index, const void __user *buffer, size_t count); 32 + unsigned int rtlx_read_poll(int index, int can_sleep); 33 + unsigned int rtlx_write_poll(int index); 34 + 35 + int __init rtlx_module_init(void); 36 + void __exit rtlx_module_exit(void); 37 + 38 + void _interrupt_sp(void); 39 + 40 + extern struct vpe_notifications rtlx_notify; 41 + extern const struct file_operations rtlx_fops; 42 + extern void (*aprp_hook)(void); 43 44 enum rtlx_state { 45 RTLX_STATE_UNUSED = 0, ··· 35 RTLX_STATE_OPENED 36 }; 37 38 + extern struct chan_waitqueues { 39 + wait_queue_head_t rt_queue; 40 + wait_queue_head_t lx_queue; 41 + atomic_t in_open; 42 + struct mutex mutex; 43 + } channel_wqs[RTLX_CHANNELS]; 44 45 /* each channel supports read and write. 46 + linux (vpe0) reads lx_buffer and writes rt_buffer 47 SP (vpe1) reads rt_buffer and writes lx_buffer 48 */ 49 struct rtlx_channel { ··· 55 char *lx_buffer; 56 }; 57 58 + extern struct rtlx_info { 59 unsigned long id; 60 enum rtlx_state state; 61 + int ap_int_pending; /* Status of 0 or 1 for CONFIG_MIPS_CMP only */ 62 63 struct rtlx_channel channel[RTLX_CHANNELS]; 64 + } *rtlx; 65 #endif /* __ASM_RTLX_H_ */
+12 -4
arch/mips/include/asm/switch_to.h
··· 19 20 struct task_struct; 21 22 - /* 23 - * switch_to(n) should switch tasks to task nr n, first 24 - * checking that n isn't the current task, in which case it does nothing. 25 */ 26 - extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); 27 28 extern unsigned int ll_bit; 29 extern struct task_struct *ll_task;
··· 19 20 struct task_struct; 21 22 + /** 23 + * resume - resume execution of a task 24 + * @prev: The task previously executed. 25 + * @next: The task to begin executing. 26 + * @next_ti: task_thread_info(next). 27 + * @usedfpu: Non-zero if prev's FP context should be saved. 28 + * 29 + * This function is used whilst scheduling to save the context of prev & load 30 + * the context of next. Returns prev. 31 */ 32 + extern asmlinkage struct task_struct *resume(struct task_struct *prev, 33 + struct task_struct *next, struct thread_info *next_ti, 34 + u32 usedfpu); 35 36 extern unsigned int ll_bit; 37 extern struct task_struct *ll_task;
+1 -1
arch/mips/include/asm/syscall.h
··· 29 static inline unsigned long mips_get_syscall_arg(unsigned long *arg, 30 struct task_struct *task, struct pt_regs *regs, unsigned int n) 31 { 32 - unsigned long usp = regs->regs[29]; 33 34 switch (n) { 35 case 0: case 1: case 2: case 3:
··· 29 static inline unsigned long mips_get_syscall_arg(unsigned long *arg, 30 struct task_struct *task, struct pt_regs *regs, unsigned int n) 31 { 32 + unsigned long usp __maybe_unused = regs->regs[29]; 33 34 switch (n) { 35 case 0: case 1: case 2: case 3:
+3 -1
arch/mips/include/asm/thread_info.h
··· 110 #define TIF_NOHZ 19 /* in adaptive nohz mode */ 111 #define TIF_FIXADE 20 /* Fix address errors in software */ 112 #define TIF_LOGADE 21 /* Log address errors to syslog */ 113 - #define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */ 114 #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 115 #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 116 #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 117 #define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ 118 #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 119 120 #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) ··· 132 #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 133 #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 134 #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 135 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) 136 137 #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
··· 110 #define TIF_NOHZ 19 /* in adaptive nohz mode */ 111 #define TIF_FIXADE 20 /* Fix address errors in software */ 112 #define TIF_LOGADE 21 /* Log address errors to syslog */ 113 + #define TIF_32BIT_REGS 22 /* 32-bit general purpose registers */ 114 #define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */ 115 #define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */ 116 #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ 117 #define TIF_SYSCALL_TRACEPOINT 26 /* syscall tracepoint instrumentation */ 118 + #define TIF_32BIT_FPREGS 27 /* 32-bit floating point registers */ 119 #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ 120 121 #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) ··· 131 #define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR) 132 #define _TIF_FPUBOUND (1<<TIF_FPUBOUND) 133 #define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH) 134 + #define _TIF_32BIT_FPREGS (1<<TIF_32BIT_FPREGS) 135 #define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT) 136 137 #define _TIF_WORK_SYSCALL_ENTRY (_TIF_NOHZ | _TIF_SYSCALL_TRACE | \
+4
arch/mips/include/asm/tlb.h
··· 18 */ 19 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 20 21 #include <asm-generic/tlb.h> 22 23 #endif /* __ASM_TLB_H */
··· 18 */ 19 #define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) 20 21 + #define UNIQUE_ENTRYHI(idx) \ 22 + ((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \ 23 + (cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0)) 24 + 25 #include <asm-generic/tlb.h> 26 27 #endif /* __ASM_TLB_H */
+113 -18
arch/mips/include/asm/vpe.h
··· 1 /* 2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 3 - * 4 - * This program is free software; you can distribute it and/or modify it 5 - * under the terms of the GNU General Public License (Version 2) as 6 - * published by the Free Software Foundation. 7 - * 8 - * This program is distributed in the hope it will be useful, but WITHOUT 9 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 - * for more details. 12 - * 13 - * You should have received a copy of the GNU General Public License along 14 - * with this program; if not, write to the Free Software Foundation, Inc., 15 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 - * 17 */ 18 - 19 #ifndef _ASM_VPE_H 20 #define _ASM_VPE_H 21 22 struct vpe_notifications { 23 void (*start)(int vpe); ··· 97 struct list_head list; 98 }; 99 100 101 - extern int vpe_notify(int index, struct vpe_notifications *notify); 102 103 - extern void *vpe_get_shared(int index); 104 - extern char *vpe_getcwd(int index); 105 106 #endif /* _ASM_VPE_H */
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 */ 9 #ifndef _ASM_VPE_H 10 #define _ASM_VPE_H 11 + 12 + #include <linux/init.h> 13 + #include <linux/list.h> 14 + #include <linux/smp.h> 15 + #include <linux/spinlock.h> 16 + 17 + #define VPE_MODULE_NAME "vpe" 18 + #define VPE_MODULE_MINOR 1 19 + 20 + /* grab the likely amount of memory we will need. */ 21 + #ifdef CONFIG_MIPS_VPE_LOADER_TOM 22 + #define P_SIZE (2 * 1024 * 1024) 23 + #else 24 + /* add an overhead to the max kmalloc size for non-striped symbols/etc */ 25 + #define P_SIZE (256 * 1024) 26 + #endif 27 + 28 + #define MAX_VPES 16 29 + #define VPE_PATH_MAX 256 30 + 31 + static inline int aprp_cpu_index(void) 32 + { 33 + #ifdef CONFIG_MIPS_CMP 34 + return setup_max_cpus; 35 + #else 36 + extern int tclimit; 37 + return tclimit; 38 + #endif 39 + } 40 + 41 + enum vpe_state { 42 + VPE_STATE_UNUSED = 0, 43 + VPE_STATE_INUSE, 44 + VPE_STATE_RUNNING 45 + }; 46 + 47 + enum tc_state { 48 + TC_STATE_UNUSED = 0, 49 + TC_STATE_INUSE, 50 + TC_STATE_RUNNING, 51 + TC_STATE_DYNAMIC 52 + }; 53 + 54 + struct vpe { 55 + enum vpe_state state; 56 + 57 + /* (device) minor associated with this vpe */ 58 + int minor; 59 + 60 + /* elfloader stuff */ 61 + void *load_addr; 62 + unsigned long len; 63 + char *pbuffer; 64 + unsigned long plen; 65 + char cwd[VPE_PATH_MAX]; 66 + 67 + unsigned long __start; 68 + 69 + /* tc's associated with this vpe */ 70 + struct list_head tc; 71 + 72 + /* The list of vpe's */ 73 + struct list_head list; 74 + 75 + /* shared symbol address */ 76 + void *shared_ptr; 77 + 78 + /* the list of who wants to know when something major happens */ 79 + struct list_head notify; 80 + 81 + unsigned int ntcs; 82 + }; 83 + 84 + struct tc { 85 + enum tc_state state; 86 + int index; 87 + 88 + struct vpe *pvpe; /* parent VPE */ 89 + struct list_head tc; /* The list of TC's with this VPE */ 90 + struct list_head list; /* The global list of tc's */ 91 + }; 92 93 struct vpe_notifications { 94 void (*start)(int vpe); ··· 26 struct list_head list; 27 }; 28 29 + struct vpe_control { 30 + spinlock_t vpe_list_lock; 31 + struct list_head vpe_list; /* Virtual processing elements */ 32 + spinlock_t tc_list_lock; 33 + struct list_head tc_list; /* Thread contexts */ 34 + }; 35 36 + extern unsigned long physical_memsize; 37 + extern struct vpe_control vpecontrol; 38 + extern const struct file_operations vpe_fops; 39 40 + int vpe_notify(int index, struct vpe_notifications *notify); 41 42 + void *vpe_get_shared(int index); 43 + char *vpe_getcwd(int index); 44 + 45 + struct vpe *get_vpe(int minor); 46 + struct tc *get_tc(int index); 47 + struct vpe *alloc_vpe(int minor); 48 + struct tc *alloc_tc(int index); 49 + void release_vpe(struct vpe *v); 50 + 51 + void *alloc_progmem(unsigned long len); 52 + void release_progmem(void *ptr); 53 + 54 + int __weak vpe_run(struct vpe *v); 55 + void cleanup_tc(struct tc *tc); 56 + 57 + int __init vpe_module_init(void); 58 + void __exit vpe_module_exit(void); 59 #endif /* _ASM_VPE_H */
+5 -2
arch/mips/include/uapi/asm/inst.h
··· 98 */ 99 enum cop_op { 100 mfc_op = 0x00, dmfc_op = 0x01, 101 - cfc_op = 0x02, mtc_op = 0x04, 102 - dmtc_op = 0x05, ctc_op = 0x06, 103 bc_op = 0x08, cop_op = 0x10, 104 copm_op = 0x18 105 }; ··· 398 mm_movt1_op = 0xa5, 399 mm_ftruncw_op = 0xac, 400 mm_fneg1_op = 0xad, 401 mm_froundl_op = 0xcc, 402 mm_fcvtd1_op = 0xcd, 403 mm_froundw_op = 0xec, 404 mm_fcvts1_op = 0xed, 405 };
··· 98 */ 99 enum cop_op { 100 mfc_op = 0x00, dmfc_op = 0x01, 101 + cfc_op = 0x02, mfhc_op = 0x03, 102 + mtc_op = 0x04, dmtc_op = 0x05, 103 + ctc_op = 0x06, mthc_op = 0x07, 104 bc_op = 0x08, cop_op = 0x10, 105 copm_op = 0x18 106 }; ··· 397 mm_movt1_op = 0xa5, 398 mm_ftruncw_op = 0xac, 399 mm_fneg1_op = 0xad, 400 + mm_mfhc1_op = 0xc0, 401 mm_froundl_op = 0xcc, 402 mm_fcvtd1_op = 0xcd, 403 + mm_mthc1_op = 0xe0, 404 mm_froundw_op = 0xec, 405 mm_fcvts1_op = 0xed, 406 };
+1
arch/mips/jz4740/board-qi_lb60.c
··· 427 428 static struct platform_device *jz_platform_devices[] __initdata = { 429 &jz4740_udc_device, 430 &jz4740_mmc_device, 431 &jz4740_nand_device, 432 &qi_lb60_keypad,
··· 427 428 static struct platform_device *jz_platform_devices[] __initdata = { 429 &jz4740_udc_device, 430 + &jz4740_udc_xceiv_device, 431 &jz4740_mmc_device, 432 &jz4740_nand_device, 433 &qi_lb60_keypad,
+24 -17
arch/mips/jz4740/platform.c
··· 14 */ 15 16 #include <linux/device.h> 17 - #include <linux/init.h> 18 #include <linux/kernel.h> 19 #include <linux/platform_device.h> 20 #include <linux/resource.h> 21 22 #include <linux/dma-mapping.h> 23 24 #include <asm/mach-jz4740/platform.h> 25 #include <asm/mach-jz4740/base.h> ··· 57 .resource = jz4740_usb_ohci_resources, 58 }; 59 60 - /* UDC (USB gadget controller) */ 61 - static struct resource jz4740_usb_gdt_resources[] = { 62 - { 63 - .start = JZ4740_UDC_BASE_ADDR, 64 - .end = JZ4740_UDC_BASE_ADDR + 0x1000 - 1, 65 - .flags = IORESOURCE_MEM, 66 }, 67 - { 68 - .start = JZ4740_IRQ_UDC, 69 - .end = JZ4740_IRQ_UDC, 70 - .flags = IORESOURCE_IRQ, 71 }, 72 }; 73 74 struct platform_device jz4740_udc_device = { 75 - .name = "jz-udc", 76 - .id = -1, 77 - .dev = { 78 - .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, 79 .coherent_dma_mask = DMA_BIT_MASK(32), 80 }, 81 - .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources), 82 - .resource = jz4740_usb_gdt_resources, 83 }; 84 85 /* MMC/SD controller */
··· 14 */ 15 16 #include <linux/device.h> 17 #include <linux/kernel.h> 18 #include <linux/platform_device.h> 19 #include <linux/resource.h> 20 21 #include <linux/dma-mapping.h> 22 + 23 + #include <linux/usb/musb.h> 24 25 #include <asm/mach-jz4740/platform.h> 26 #include <asm/mach-jz4740/base.h> ··· 56 .resource = jz4740_usb_ohci_resources, 57 }; 58 59 + /* USB Device Controller */ 60 + struct platform_device jz4740_udc_xceiv_device = { 61 + .name = "usb_phy_gen_xceiv", 62 + .id = 0, 63 + }; 64 + 65 + static struct resource jz4740_udc_resources[] = { 66 + [0] = { 67 + .start = JZ4740_UDC_BASE_ADDR, 68 + .end = JZ4740_UDC_BASE_ADDR + 0x10000 - 1, 69 + .flags = IORESOURCE_MEM, 70 }, 71 + [1] = { 72 + .start = JZ4740_IRQ_UDC, 73 + .end = JZ4740_IRQ_UDC, 74 + .flags = IORESOURCE_IRQ, 75 + .name = "mc", 76 }, 77 }; 78 79 struct platform_device jz4740_udc_device = { 80 + .name = "musb-jz4740", 81 + .id = -1, 82 + .dev = { 83 + .dma_mask = &jz4740_udc_device.dev.coherent_dma_mask, 84 .coherent_dma_mask = DMA_BIT_MASK(32), 85 }, 86 + .num_resources = ARRAY_SIZE(jz4740_udc_resources), 87 + .resource = jz4740_udc_resources, 88 }; 89 90 /* MMC/SD controller */
+5
arch/mips/kernel/Makefile
··· 30 obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 31 obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 32 33 obj-$(CONFIG_STACKTRACE) += stacktrace.o 34 obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 35 obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o ··· 56 obj-$(CONFIG_CPU_MIPSR2) += spram.o 57 58 obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 59 obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 60 61 obj-$(CONFIG_I8259) += i8259.o 62 obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
··· 30 obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 31 obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 32 33 + obj-$(CONFIG_DEBUG_FS) += segment.o 34 obj-$(CONFIG_STACKTRACE) += stacktrace.o 35 obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 36 obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o ··· 55 obj-$(CONFIG_CPU_MIPSR2) += spram.o 56 57 obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 58 + obj-$(CONFIG_MIPS_VPE_LOADER_CMP) += vpe-cmp.o 59 + obj-$(CONFIG_MIPS_VPE_LOADER_MT) += vpe-mt.o 60 obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 61 + obj-$(CONFIG_MIPS_VPE_APSP_API_CMP) += rtlx-cmp.o 62 + obj-$(CONFIG_MIPS_VPE_APSP_API_MT) += rtlx-mt.o 63 64 obj-$(CONFIG_I8259) += i8259.o 65 obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
+14
arch/mips/kernel/binfmt_elfo32.c
··· 28 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; 29 30 /* 31 * This is used to ensure we don't load something for the wrong architecture. 32 */ 33 #define elf_check_arch(hdr) \ ··· 55 __res = 0; \ 56 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 57 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 58 __res = 0; \ 59 \ 60 __res; \
··· 28 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; 29 30 /* 31 + * In order to be sure that we don't attempt to execute an O32 binary which 32 + * requires 64 bit FP (FR=1) on a system which does not support it we refuse 33 + * to execute any binary which has bits specified by the following macro set 34 + * in its ELF header flags. 35 + */ 36 + #ifdef CONFIG_MIPS_O32_FP64_SUPPORT 37 + # define __MIPS_O32_FP64_MUST_BE_ZERO 0 38 + #else 39 + # define __MIPS_O32_FP64_MUST_BE_ZERO EF_MIPS_FP64 40 + #endif 41 + 42 + /* 43 * This is used to ensure we don't load something for the wrong architecture. 44 */ 45 #define elf_check_arch(hdr) \ ··· 43 __res = 0; \ 44 if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ 45 ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ 46 + __res = 0; \ 47 + if (__h->e_flags & __MIPS_O32_FP64_MUST_BE_ZERO) \ 48 __res = 0; \ 49 \ 50 __res; \
+43 -13
arch/mips/kernel/bmips_vec.S
··· 8 * Reset/NMI/re-entry vectors for BMIPS processors 9 */ 10 11 - #include <linux/init.h> 12 13 #include <asm/asm.h> 14 #include <asm/asmmacro.h> 15 #include <asm/cacheops.h> 16 #include <asm/regdef.h> 17 #include <asm/mipsregs.h> 18 #include <asm/stackframe.h> ··· 91 beqz k0, bmips_smp_entry 92 93 #if defined(CONFIG_CPU_BMIPS5000) 94 /* if we're not on core 0, this must be the SMP boot signal */ 95 li k1, (3 << 25) 96 mfc0 k0, $22 97 and k0, k1 98 bnez k0, bmips_smp_entry 99 - #endif 100 #endif /* CONFIG_SMP */ 101 102 /* nope, it's just a regular NMI */ ··· 145 xori k0, 0x04 146 mtc0 k0, CP0_CONFIG 147 148 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 149 /* initialize CPU1's local I-cache */ 150 li k0, 0x80000000 151 li k1, 0x80010000 ··· 161 1: cache Index_Store_Tag_I, 0(k0) 162 addiu k0, 16 163 bne k0, k1, 1b 164 - #elif defined(CONFIG_CPU_BMIPS5000) 165 /* set exception vector base */ 166 la k0, ebase 167 lw k0, 0(k0) 168 mtc0 k0, $15, 1 169 BARRIER 170 - #endif 171 - 172 /* jump back to kseg0 in case we need to remap the kseg1 area */ 173 la k0, 1f 174 jr k0 ··· 239 LEAF(bmips_enable_xks01) 240 241 #if defined(CONFIG_XKS01) 242 - 243 #if defined(CONFIG_CPU_BMIPS4380) 244 mfc0 t0, $22, 3 245 li t1, 0x1ff0 246 li t2, (1 << 12) | (1 << 9) ··· 259 or t0, t2 260 mtc0 t0, $22, 3 261 BARRIER 262 - #elif defined(CONFIG_CPU_BMIPS5000) 263 mfc0 t0, $22, 5 264 li t1, 0x01ff 265 li t2, (1 << 8) | (1 << 5) ··· 274 or t0, t2 275 mtc0 t0, $22, 5 276 BARRIER 277 - #else 278 - 279 - #error Missing XKS01 setup 280 - 281 - #endif 282 - 283 #endif /* defined(CONFIG_XKS01) */ 284 285 jr ra
··· 8 * Reset/NMI/re-entry vectors for BMIPS processors 9 */ 10 11 12 #include <asm/asm.h> 13 #include <asm/asmmacro.h> 14 #include <asm/cacheops.h> 15 + #include <asm/cpu.h> 16 #include <asm/regdef.h> 17 #include <asm/mipsregs.h> 18 #include <asm/stackframe.h> ··· 91 beqz k0, bmips_smp_entry 92 93 #if defined(CONFIG_CPU_BMIPS5000) 94 + mfc0 k0, CP0_PRID 95 + li k1, PRID_IMP_BMIPS5000 96 + andi k0, 0xff00 97 + bne k0, k1, 1f 98 + 99 /* if we're not on core 0, this must be the SMP boot signal */ 100 li k1, (3 << 25) 101 mfc0 k0, $22 102 and k0, k1 103 bnez k0, bmips_smp_entry 104 + 1: 105 + #endif /* CONFIG_CPU_BMIPS5000 */ 106 #endif /* CONFIG_SMP */ 107 108 /* nope, it's just a regular NMI */ ··· 139 xori k0, 0x04 140 mtc0 k0, CP0_CONFIG 141 142 + mfc0 k0, CP0_PRID 143 + andi k0, 0xff00 144 #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 145 + li k1, PRID_IMP_BMIPS43XX 146 + bne k0, k1, 2f 147 + 148 /* initialize CPU1's local I-cache */ 149 li k0, 0x80000000 150 li k1, 0x80010000 ··· 150 1: cache Index_Store_Tag_I, 0(k0) 151 addiu k0, 16 152 bne k0, k1, 1b 153 + 154 + b 3f 155 + 2: 156 + #endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */ 157 + #if defined(CONFIG_CPU_BMIPS5000) 158 /* set exception vector base */ 159 + li k1, PRID_IMP_BMIPS5000 160 + bne k0, k1, 3f 161 + 162 la k0, ebase 163 lw k0, 0(k0) 164 mtc0 k0, $15, 1 165 BARRIER 166 + #endif /* CONFIG_CPU_BMIPS5000 */ 167 + 3: 168 /* jump back to kseg0 in case we need to remap the kseg1 area */ 169 la k0, 1f 170 jr k0 ··· 221 LEAF(bmips_enable_xks01) 222 223 #if defined(CONFIG_XKS01) 224 + mfc0 t0, CP0_PRID 225 + andi t2, t0, 0xff00 226 #if defined(CONFIG_CPU_BMIPS4380) 227 + li t1, PRID_IMP_BMIPS43XX 228 + bne t2, t1, 1f 229 + 230 + andi t0, 0xff 231 + addiu t1, t0, -PRID_REV_BMIPS4380_HI 232 + bgtz t1, 2f 233 + addiu t0, -PRID_REV_BMIPS4380_LO 234 + bltz t0, 2f 235 + 236 mfc0 t0, $22, 3 237 li t1, 0x1ff0 238 li t2, (1 << 12) | (1 << 9) ··· 231 or t0, t2 232 mtc0 t0, $22, 3 233 BARRIER 234 + b 2f 235 + 1: 236 + #endif /* CONFIG_CPU_BMIPS4380 */ 237 + #if defined(CONFIG_CPU_BMIPS5000) 238 + li t1, PRID_IMP_BMIPS5000 239 + bne t2, t1, 2f 240 + 241 mfc0 t0, $22, 5 242 li t1, 0x01ff 243 li t2, (1 << 8) | (1 << 5) ··· 240 or t0, t2 241 mtc0 t0, $22, 5 242 BARRIER 243 + #endif /* CONFIG_CPU_BMIPS5000 */ 244 + 2: 245 #endif /* defined(CONFIG_XKS01) */ 246 247 jr ra
+96 -7
arch/mips/kernel/cpu-probe.c
··· 112 unsigned long tmp, fpu_id; 113 114 tmp = read_c0_status(); 115 - __enable_fpu(); 116 fpu_id = read_32bit_cp1_register(CP1_REVISION); 117 write_c0_status(tmp); 118 return fpu_id; ··· 163 static char unknown_isa[] = KERN_ERR \ 164 "Unsupported ISA type, c0.config0: %d."; 165 166 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 167 { 168 unsigned int config0; ··· 189 190 config0 = read_c0_config(); 191 192 - if (((config0 & MIPS_CONF_MT) >> 7) == 1) 193 c->options |= MIPS_CPU_TLB; 194 isa = (config0 & MIPS_CONF_AT) >> 13; 195 switch (isa) { 196 case 0: ··· 250 c->options |= MIPS_CPU_FPU; 251 c->options |= MIPS_CPU_32FPR; 252 } 253 - if (cpu_has_tlb) 254 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 255 256 return config1 & MIPS_CONF_M; 257 } ··· 299 c->options |= MIPS_CPU_MICROMIPS; 300 if (config3 & MIPS_CONF3_VZ) 301 c->ases |= MIPS_ASE_VZ; 302 303 return config3 & MIPS_CONF_M; 304 } ··· 308 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 309 { 310 unsigned int config4; 311 312 config4 = read_c0_config4(); 313 314 - if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT 315 - && cpu_has_tlb) 316 - c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 317 318 c->kscratch_mask = (config4 >> 16) & 0xff; 319 ··· 379 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 380 381 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 382 383 ok = decode_config0(c); /* Read Config registers. */ 384 BUG_ON(!ok); /* Arch spec violation! */ ··· 746 747 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 748 { 749 - decode_configs(c); 750 switch (c->processor_id & PRID_IMP_MASK) { 751 case PRID_IMP_4KC: 752 c->cputype = CPU_4KC; ··· 809 c->cputype = CPU_74K; 810 __cpu_name[cpu] = "MIPS 1074Kc"; 811 break; 812 } 813 814 spram_config(); 815 } ··· 1031 1032 switch (c->processor_id & PRID_IMP_MASK) { 1033 case PRID_IMP_NETLOGIC_XLP2XX: 1034 c->cputype = CPU_XLP; 1035 __cpu_name[cpu] = "Broadcom XLPII"; 1036 break;
··· 112 unsigned long tmp, fpu_id; 113 114 tmp = read_c0_status(); 115 + __enable_fpu(FPU_AS_IS); 116 fpu_id = read_32bit_cp1_register(CP1_REVISION); 117 write_c0_status(tmp); 118 return fpu_id; ··· 163 static char unknown_isa[] = KERN_ERR \ 164 "Unsupported ISA type, c0.config0: %d."; 165 166 + static void set_ftlb_enable(struct cpuinfo_mips *c, int enable) 167 + { 168 + unsigned int config6; 169 + /* 170 + * Config6 is implementation dependent and it's currently only 171 + * used by proAptiv 172 + */ 173 + if (c->cputype == CPU_PROAPTIV) { 174 + config6 = read_c0_config6(); 175 + if (enable) 176 + /* Enable FTLB */ 177 + write_c0_config6(config6 | MIPS_CONF6_FTLBEN); 178 + else 179 + /* Disable FTLB */ 180 + write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN); 181 + back_to_back_c0_hazard(); 182 + } 183 + } 184 + 185 static inline unsigned int decode_config0(struct cpuinfo_mips *c) 186 { 187 unsigned int config0; ··· 170 171 config0 = read_c0_config(); 172 173 + /* 174 + * Look for Standard TLB or Dual VTLB and FTLB 175 + */ 176 + if ((((config0 & MIPS_CONF_MT) >> 7) == 1) || 177 + (((config0 & MIPS_CONF_MT) >> 7) == 4)) 178 c->options |= MIPS_CPU_TLB; 179 + 180 isa = (config0 & MIPS_CONF_AT) >> 13; 181 switch (isa) { 182 case 0: ··· 226 c->options |= MIPS_CPU_FPU; 227 c->options |= MIPS_CPU_32FPR; 228 } 229 + if (cpu_has_tlb) { 230 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; 231 + c->tlbsizevtlb = c->tlbsize; 232 + c->tlbsizeftlbsets = 0; 233 + } 234 235 return config1 & MIPS_CONF_M; 236 } ··· 272 c->options |= MIPS_CPU_MICROMIPS; 273 if (config3 & MIPS_CONF3_VZ) 274 c->ases |= MIPS_ASE_VZ; 275 + if (config3 & MIPS_CONF3_SC) 276 + c->options |= MIPS_CPU_SEGMENTS; 277 278 return config3 & MIPS_CONF_M; 279 } ··· 279 static inline unsigned int decode_config4(struct cpuinfo_mips *c) 280 { 281 unsigned int config4; 282 + unsigned int newcf4; 283 + unsigned int mmuextdef; 284 + unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE; 285 286 config4 = read_c0_config4(); 287 288 + if (cpu_has_tlb) { 289 + if (((config4 & MIPS_CONF4_IE) >> 29) == 2) 290 + c->options |= MIPS_CPU_TLBINV; 291 + mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF; 292 + switch (mmuextdef) { 293 + case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT: 294 + c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; 295 + c->tlbsizevtlb = c->tlbsize; 296 + break; 297 + case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT: 298 + c->tlbsizevtlb += 299 + ((config4 & MIPS_CONF4_VTLBSIZEEXT) >> 300 + MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40; 301 + c->tlbsize = c->tlbsizevtlb; 302 + ftlb_page = MIPS_CONF4_VFTLBPAGESIZE; 303 + /* fall through */ 304 + case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT: 305 + newcf4 = (config4 & ~ftlb_page) | 306 + (page_size_ftlb(mmuextdef) << 307 + MIPS_CONF4_FTLBPAGESIZE_SHIFT); 308 + write_c0_config4(newcf4); 309 + back_to_back_c0_hazard(); 310 + config4 = read_c0_config4(); 311 + if (config4 != newcf4) { 312 + pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n", 313 + PAGE_SIZE, config4); 314 + /* Switch FTLB off */ 315 + set_ftlb_enable(c, 0); 316 + break; 317 + } 318 + c->tlbsizeftlbsets = 1 << 319 + ((config4 & MIPS_CONF4_FTLBSETS) >> 320 + MIPS_CONF4_FTLBSETS_SHIFT); 321 + c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >> 322 + MIPS_CONF4_FTLBWAYS_SHIFT) + 2; 323 + c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets; 324 + break; 325 + } 326 + } 327 328 c->kscratch_mask = (config4 >> 16) & 0xff; 329 ··· 311 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; 312 313 c->scache.flags = MIPS_CACHE_NOT_PRESENT; 314 + 315 + /* Enable FTLB if present */ 316 + set_ftlb_enable(c, 1); 317 318 ok = decode_config0(c); /* Read Config registers. */ 319 BUG_ON(!ok); /* Arch spec violation! */ ··· 675 676 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 677 { 678 switch (c->processor_id & PRID_IMP_MASK) { 679 case PRID_IMP_4KC: 680 c->cputype = CPU_4KC; ··· 739 c->cputype = CPU_74K; 740 __cpu_name[cpu] = "MIPS 1074Kc"; 741 break; 742 + case PRID_IMP_INTERAPTIV_UP: 743 + c->cputype = CPU_INTERAPTIV; 744 + __cpu_name[cpu] = "MIPS interAptiv"; 745 + break; 746 + case PRID_IMP_INTERAPTIV_MP: 747 + c->cputype = CPU_INTERAPTIV; 748 + __cpu_name[cpu] = "MIPS interAptiv (multi)"; 749 + break; 750 + case PRID_IMP_PROAPTIV_UP: 751 + c->cputype = CPU_PROAPTIV; 752 + __cpu_name[cpu] = "MIPS proAptiv"; 753 + break; 754 + case PRID_IMP_PROAPTIV_MP: 755 + c->cputype = CPU_PROAPTIV; 756 + __cpu_name[cpu] = "MIPS proAptiv (multi)"; 757 + break; 758 } 759 + 760 + decode_configs(c); 761 762 spram_config(); 763 } ··· 943 944 switch (c->processor_id & PRID_IMP_MASK) { 945 case PRID_IMP_NETLOGIC_XLP2XX: 946 + case PRID_IMP_NETLOGIC_XLP9XX: 947 c->cputype = CPU_XLP; 948 __cpu_name[cpu] = "Broadcom XLPII"; 949 break;
-1
arch/mips/kernel/crash.c
··· 5 #include <linux/bootmem.h> 6 #include <linux/crash_dump.h> 7 #include <linux/delay.h> 8 - #include <linux/init.h> 9 #include <linux/irq.h> 10 #include <linux/types.h> 11 #include <linux/sched.h>
··· 5 #include <linux/bootmem.h> 6 #include <linux/crash_dump.h> 7 #include <linux/delay.h> 8 #include <linux/irq.h> 9 #include <linux/types.h> 10 #include <linux/sched.h>
+1
arch/mips/kernel/genex.S
··· 476 BUILD_HANDLER ov ov sti silent /* #12 */ 477 BUILD_HANDLER tr tr sti silent /* #13 */ 478 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 479 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 480 #ifdef CONFIG_HARDWARE_WATCHPOINTS 481 /*
··· 476 BUILD_HANDLER ov ov sti silent /* #12 */ 477 BUILD_HANDLER tr tr sti silent /* #13 */ 478 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 479 + BUILD_HANDLER ftlb ftlb none silent /* #16 */ 480 BUILD_HANDLER mdmx mdmx sti silent /* #22 */ 481 #ifdef CONFIG_HARDWARE_WATCHPOINTS 482 /*
+2
arch/mips/kernel/idle.c
··· 184 case CPU_24K: 185 case CPU_34K: 186 case CPU_1004K: 187 cpu_wait = r4k_wait; 188 if (read_c0_config7() & MIPS_CONF7_WII) 189 cpu_wait = r4k_wait_irqoff;
··· 184 case CPU_24K: 185 case CPU_34K: 186 case CPU_1004K: 187 + case CPU_INTERAPTIV: 188 + case CPU_PROAPTIV: 189 cpu_wait = r4k_wait; 190 if (read_c0_config7() & MIPS_CONF7_WII) 191 cpu_wait = r4k_wait_irqoff;
+27 -21
arch/mips/kernel/proc.c
··· 65 cpu_data[n].watch_reg_masks[i]); 66 seq_printf(m, "]\n"); 67 } 68 - if (cpu_has_mips_r) { 69 - seq_printf(m, "isa\t\t\t: mips1"); 70 - if (cpu_has_mips_2) 71 - seq_printf(m, "%s", " mips2"); 72 - if (cpu_has_mips_3) 73 - seq_printf(m, "%s", " mips3"); 74 - if (cpu_has_mips_4) 75 - seq_printf(m, "%s", " mips4"); 76 - if (cpu_has_mips_5) 77 - seq_printf(m, "%s", " mips5"); 78 - if (cpu_has_mips32r1) 79 - seq_printf(m, "%s", " mips32r1"); 80 - if (cpu_has_mips32r2) 81 - seq_printf(m, "%s", " mips32r2"); 82 - if (cpu_has_mips64r1) 83 - seq_printf(m, "%s", " mips64r1"); 84 - if (cpu_has_mips64r2) 85 - seq_printf(m, "%s", " mips64r2"); 86 - seq_printf(m, "\n"); 87 - } 88 89 seq_printf(m, "ASEs implemented\t:"); 90 if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); ··· 106 seq_printf(m, "kscratch registers\t: %d\n", 107 hweight8(cpu_data[n].kscratch_mask)); 108 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); 109 - 110 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 111 cpu_has_vce ? "%u" : "not available"); 112 seq_printf(m, fmt, 'D', vced_count);
··· 65 cpu_data[n].watch_reg_masks[i]); 66 seq_printf(m, "]\n"); 67 } 68 + 69 + seq_printf(m, "isa\t\t\t: mips1"); 70 + if (cpu_has_mips_2) 71 + seq_printf(m, "%s", " mips2"); 72 + if (cpu_has_mips_3) 73 + seq_printf(m, "%s", " mips3"); 74 + if (cpu_has_mips_4) 75 + seq_printf(m, "%s", " mips4"); 76 + if (cpu_has_mips_5) 77 + seq_printf(m, "%s", " mips5"); 78 + if (cpu_has_mips32r1) 79 + seq_printf(m, "%s", " mips32r1"); 80 + if (cpu_has_mips32r2) 81 + seq_printf(m, "%s", " mips32r2"); 82 + if (cpu_has_mips64r1) 83 + seq_printf(m, "%s", " mips64r1"); 84 + if (cpu_has_mips64r2) 85 + seq_printf(m, "%s", " mips64r2"); 86 + seq_printf(m, "\n"); 87 88 seq_printf(m, "ASEs implemented\t:"); 89 if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); ··· 107 seq_printf(m, "kscratch registers\t: %d\n", 108 hweight8(cpu_data[n].kscratch_mask)); 109 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core); 110 + #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) 111 + if (cpu_has_mipsmt) { 112 + seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id); 113 + #if defined(CONFIG_MIPS_MT_SMTC) 114 + seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id); 115 + #endif 116 + } 117 + #endif 118 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", 119 cpu_has_vce ? "%u" : "not available"); 120 seq_printf(m, fmt, 'D', vced_count);
+1 -5
arch/mips/kernel/process.c
··· 60 61 /* New thread loses kernel privileges. */ 62 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); 63 - #ifdef CONFIG_64BIT 64 - status |= test_thread_flag(TIF_32BIT_REGS) ? 0 : ST0_FR; 65 - #endif 66 status |= KU_USER; 67 regs->cp0_status = status; 68 clear_used_math(); 69 clear_fpu_owner(); 70 - if (cpu_has_dsp) 71 - __init_dsp(); 72 regs->cp0_epc = pc; 73 regs->regs[29] = sp; 74 }
··· 60 61 /* New thread loses kernel privileges. */ 62 status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_FR|KU_MASK); 63 status |= KU_USER; 64 regs->cp0_status = status; 65 clear_used_math(); 66 clear_fpu_owner(); 67 + init_dsp(); 68 regs->cp0_epc = pc; 69 regs->regs[29] = sp; 70 }
+33 -27
arch/mips/kernel/ptrace.c
··· 137 if (cpu_has_mipsmt) { 138 unsigned int vpflags = dvpe(); 139 flags = read_c0_status(); 140 - __enable_fpu(); 141 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 142 write_c0_status(flags); 143 evpe(vpflags); 144 } else { 145 flags = read_c0_status(); 146 - __enable_fpu(); 147 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 148 write_c0_status(flags); 149 } ··· 408 /* Read the word at location addr in the USER area. */ 409 case PTRACE_PEEKUSR: { 410 struct pt_regs *regs; 411 unsigned long tmp = 0; 412 413 regs = task_pt_regs(child); ··· 419 tmp = regs->regs[addr]; 420 break; 421 case FPR_BASE ... FPR_BASE + 31: 422 - if (tsk_used_math(child)) { 423 - fpureg_t *fregs = get_fpu_regs(child); 424 425 #ifdef CONFIG_32BIT 426 /* 427 * The odd registers are actually the high 428 * order bits of the values stored in the even 429 * registers - unless we're using r2k_switch.S. 430 */ 431 if (addr & 1) 432 - tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); 433 else 434 - tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); 435 - #endif 436 - #ifdef CONFIG_64BIT 437 - tmp = fregs[addr - FPR_BASE]; 438 - #endif 439 - } else { 440 - tmp = -1; /* FP not yet used */ 441 } 442 break; 443 case PC: 444 tmp = regs->cp0_epc; ··· 486 if (cpu_has_mipsmt) { 487 unsigned int vpflags = dvpe(); 488 flags = read_c0_status(); 489 - __enable_fpu(); 490 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 491 write_c0_status(flags); 492 evpe(vpflags); 493 } else { 494 flags = read_c0_status(); 495 - __enable_fpu(); 496 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 497 write_c0_status(flags); 498 } ··· 557 child->thread.fpu.fcr31 = 0; 558 } 559 #ifdef CONFIG_32BIT 560 - /* 561 - * The odd registers are actually the high order bits 562 - * of the values stored in the even registers - unless 563 - * we're using r2k_switch.S. 564 - */ 565 - if (addr & 1) { 566 - fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; 567 - fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; 568 - } else { 569 - fregs[addr - FPR_BASE] &= ~0xffffffffLL; 570 - fregs[addr - FPR_BASE] |= data; 571 } 572 #endif 573 - #ifdef CONFIG_64BIT 574 fregs[addr - FPR_BASE] = data; 575 - #endif 576 break; 577 } 578 case PC:
··· 137 if (cpu_has_mipsmt) { 138 unsigned int vpflags = dvpe(); 139 flags = read_c0_status(); 140 + __enable_fpu(FPU_AS_IS); 141 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 142 write_c0_status(flags); 143 evpe(vpflags); 144 } else { 145 flags = read_c0_status(); 146 + __enable_fpu(FPU_AS_IS); 147 __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); 148 write_c0_status(flags); 149 } ··· 408 /* Read the word at location addr in the USER area. */ 409 case PTRACE_PEEKUSR: { 410 struct pt_regs *regs; 411 + fpureg_t *fregs; 412 unsigned long tmp = 0; 413 414 regs = task_pt_regs(child); ··· 418 tmp = regs->regs[addr]; 419 break; 420 case FPR_BASE ... FPR_BASE + 31: 421 + if (!tsk_used_math(child)) { 422 + /* FP not yet used */ 423 + tmp = -1; 424 + break; 425 + } 426 + fregs = get_fpu_regs(child); 427 428 #ifdef CONFIG_32BIT 429 + if (test_thread_flag(TIF_32BIT_FPREGS)) { 430 /* 431 * The odd registers are actually the high 432 * order bits of the values stored in the even 433 * registers - unless we're using r2k_switch.S. 434 */ 435 if (addr & 1) 436 + tmp = fregs[(addr & ~1) - 32] >> 32; 437 else 438 + tmp = fregs[addr - 32]; 439 + break; 440 } 441 + #endif 442 + tmp = fregs[addr - FPR_BASE]; 443 break; 444 case PC: 445 tmp = regs->cp0_epc; ··· 483 if (cpu_has_mipsmt) { 484 unsigned int vpflags = dvpe(); 485 flags = read_c0_status(); 486 + __enable_fpu(FPU_AS_IS); 487 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 488 write_c0_status(flags); 489 evpe(vpflags); 490 } else { 491 flags = read_c0_status(); 492 + __enable_fpu(FPU_AS_IS); 493 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 494 write_c0_status(flags); 495 } ··· 554 child->thread.fpu.fcr31 = 0; 555 } 556 #ifdef CONFIG_32BIT 557 + if (test_thread_flag(TIF_32BIT_FPREGS)) { 558 + /* 559 + * The odd registers are actually the high 560 + * order bits of the values stored in the even 561 + * registers - unless we're using r2k_switch.S. 562 + */ 563 + if (addr & 1) { 564 + fregs[(addr & ~1) - FPR_BASE] &= 565 + 0xffffffff; 566 + fregs[(addr & ~1) - FPR_BASE] |= 567 + ((u64)data) << 32; 568 + } else { 569 + fregs[addr - FPR_BASE] &= ~0xffffffffLL; 570 + fregs[addr - FPR_BASE] |= data; 571 + } 572 + break; 573 } 574 #endif 575 fregs[addr - FPR_BASE] = data; 576 break; 577 } 578 case PC:
+31 -22
arch/mips/kernel/ptrace32.c
··· 80 /* Read the word at location addr in the USER area. */ 81 case PTRACE_PEEKUSR: { 82 struct pt_regs *regs; 83 unsigned int tmp; 84 85 regs = task_pt_regs(child); ··· 91 tmp = regs->regs[addr]; 92 break; 93 case FPR_BASE ... FPR_BASE + 31: 94 - if (tsk_used_math(child)) { 95 - fpureg_t *fregs = get_fpu_regs(child); 96 - 97 /* 98 * The odd registers are actually the high 99 * order bits of the values stored in the even 100 * registers - unless we're using r2k_switch.S. 101 */ 102 if (addr & 1) 103 - tmp = (unsigned long) (fregs[((addr & ~1) - 32)] >> 32); 104 else 105 - tmp = (unsigned long) (fregs[(addr - 32)] & 0xffffffff); 106 - } else { 107 - tmp = -1; /* FP not yet used */ 108 } 109 break; 110 case PC: 111 tmp = regs->cp0_epc; ··· 152 if (cpu_has_mipsmt) { 153 unsigned int vpflags = dvpe(); 154 flags = read_c0_status(); 155 - __enable_fpu(); 156 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 157 write_c0_status(flags); 158 evpe(vpflags); 159 } else { 160 flags = read_c0_status(); 161 - __enable_fpu(); 162 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 163 write_c0_status(flags); 164 } ··· 241 sizeof(child->thread.fpu)); 242 child->thread.fpu.fcr31 = 0; 243 } 244 - /* 245 - * The odd registers are actually the high order bits 246 - * of the values stored in the even registers - unless 247 - * we're using r2k_switch.S. 248 - */ 249 - if (addr & 1) { 250 - fregs[(addr & ~1) - FPR_BASE] &= 0xffffffff; 251 - fregs[(addr & ~1) - FPR_BASE] |= ((unsigned long long) data) << 32; 252 - } else { 253 - fregs[addr - FPR_BASE] &= ~0xffffffffLL; 254 - /* Must cast, lest sign extension fill upper 255 - bits! */ 256 - fregs[addr - FPR_BASE] |= (unsigned int)data; 257 } 258 break; 259 } 260 case PC:
··· 80 /* Read the word at location addr in the USER area. */ 81 case PTRACE_PEEKUSR: { 82 struct pt_regs *regs; 83 + fpureg_t *fregs; 84 unsigned int tmp; 85 86 regs = task_pt_regs(child); ··· 90 tmp = regs->regs[addr]; 91 break; 92 case FPR_BASE ... FPR_BASE + 31: 93 + if (!tsk_used_math(child)) { 94 + /* FP not yet used */ 95 + tmp = -1; 96 + break; 97 + } 98 + fregs = get_fpu_regs(child); 99 + if (test_thread_flag(TIF_32BIT_FPREGS)) { 100 /* 101 * The odd registers are actually the high 102 * order bits of the values stored in the even 103 * registers - unless we're using r2k_switch.S. 104 */ 105 if (addr & 1) 106 + tmp = fregs[(addr & ~1) - 32] >> 32; 107 else 108 + tmp = fregs[addr - 32]; 109 + break; 110 } 111 + tmp = fregs[addr - FPR_BASE]; 112 break; 113 case PC: 114 tmp = regs->cp0_epc; ··· 147 if (cpu_has_mipsmt) { 148 unsigned int vpflags = dvpe(); 149 flags = read_c0_status(); 150 + __enable_fpu(FPU_AS_IS); 151 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 152 write_c0_status(flags); 153 evpe(vpflags); 154 } else { 155 flags = read_c0_status(); 156 + __enable_fpu(FPU_AS_IS); 157 __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); 158 write_c0_status(flags); 159 } ··· 236 sizeof(child->thread.fpu)); 237 child->thread.fpu.fcr31 = 0; 238 } 239 + if (test_thread_flag(TIF_32BIT_FPREGS)) { 240 + /* 241 + * The odd registers are actually the high 242 + * order bits of the values stored in the even 243 + * registers - unless we're using r2k_switch.S. 244 + */ 245 + if (addr & 1) { 246 + fregs[(addr & ~1) - FPR_BASE] &= 247 + 0xffffffff; 248 + fregs[(addr & ~1) - FPR_BASE] |= 249 + ((u64)data) << 32; 250 + } else { 251 + fregs[addr - FPR_BASE] &= ~0xffffffffLL; 252 + fregs[addr - FPR_BASE] |= data; 253 + } 254 + break; 255 } 256 + fregs[addr - FPR_BASE] = data; 257 break; 258 } 259 case PC:
+70 -4
arch/mips/kernel/r4k_fpu.S
··· 35 LEAF(_save_fp_context) 36 cfc1 t1, fcr31 37 38 - #ifdef CONFIG_64BIT 39 /* Store the 16 odd double precision registers */ 40 EX sdc1 $f1, SC_FPREGS+8(a0) 41 EX sdc1 $f3, SC_FPREGS+24(a0) ··· 61 EX sdc1 $f27, SC_FPREGS+216(a0) 62 EX sdc1 $f29, SC_FPREGS+232(a0) 63 EX sdc1 $f31, SC_FPREGS+248(a0) 64 #endif 65 66 /* Store the 16 even double precision registers */ ··· 91 LEAF(_save_fp_context32) 92 cfc1 t1, fcr31 93 94 - EX sdc1 $f0, SC32_FPREGS+0(a0) 95 EX sdc1 $f2, SC32_FPREGS+16(a0) 96 EX sdc1 $f4, SC32_FPREGS+32(a0) 97 EX sdc1 $f6, SC32_FPREGS+48(a0) ··· 147 */ 148 LEAF(_restore_fp_context) 149 EX lw t0, SC_FPC_CSR(a0) 150 - #ifdef CONFIG_64BIT 151 EX ldc1 $f1, SC_FPREGS+8(a0) 152 EX ldc1 $f3, SC_FPREGS+24(a0) 153 EX ldc1 $f5, SC_FPREGS+40(a0) ··· 173 EX ldc1 $f27, SC_FPREGS+216(a0) 174 EX ldc1 $f29, SC_FPREGS+232(a0) 175 EX ldc1 $f31, SC_FPREGS+248(a0) 176 #endif 177 EX ldc1 $f0, SC_FPREGS+0(a0) 178 EX ldc1 $f2, SC_FPREGS+16(a0) ··· 200 LEAF(_restore_fp_context32) 201 /* Restore an o32 sigcontext. */ 202 EX lw t0, SC32_FPC_CSR(a0) 203 - EX ldc1 $f0, SC32_FPREGS+0(a0) 204 EX ldc1 $f2, SC32_FPREGS+16(a0) 205 EX ldc1 $f4, SC32_FPREGS+32(a0) 206 EX ldc1 $f6, SC32_FPREGS+48(a0)
··· 35 LEAF(_save_fp_context) 36 cfc1 t1, fcr31 37 38 + #if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) 39 + .set push 40 + #ifdef CONFIG_MIPS32_R2 41 + .set mips64r2 42 + mfc0 t0, CP0_STATUS 43 + sll t0, t0, 5 44 + bgez t0, 1f # skip storing odd if FR=0 45 + nop 46 + #endif 47 /* Store the 16 odd double precision registers */ 48 EX sdc1 $f1, SC_FPREGS+8(a0) 49 EX sdc1 $f3, SC_FPREGS+24(a0) ··· 53 EX sdc1 $f27, SC_FPREGS+216(a0) 54 EX sdc1 $f29, SC_FPREGS+232(a0) 55 EX sdc1 $f31, SC_FPREGS+248(a0) 56 + 1: .set pop 57 #endif 58 59 /* Store the 16 even double precision registers */ ··· 82 LEAF(_save_fp_context32) 83 cfc1 t1, fcr31 84 85 + mfc0 t0, CP0_STATUS 86 + sll t0, t0, 5 87 + bgez t0, 1f # skip storing odd if FR=0 88 + nop 89 + 90 + /* Store the 16 odd double precision registers */ 91 + EX sdc1 $f1, SC32_FPREGS+8(a0) 92 + EX sdc1 $f3, SC32_FPREGS+24(a0) 93 + EX sdc1 $f5, SC32_FPREGS+40(a0) 94 + EX sdc1 $f7, SC32_FPREGS+56(a0) 95 + EX sdc1 $f9, SC32_FPREGS+72(a0) 96 + EX sdc1 $f11, SC32_FPREGS+88(a0) 97 + EX sdc1 $f13, SC32_FPREGS+104(a0) 98 + EX sdc1 $f15, SC32_FPREGS+120(a0) 99 + EX sdc1 $f17, SC32_FPREGS+136(a0) 100 + EX sdc1 $f19, SC32_FPREGS+152(a0) 101 + EX sdc1 $f21, SC32_FPREGS+168(a0) 102 + EX sdc1 $f23, SC32_FPREGS+184(a0) 103 + EX sdc1 $f25, SC32_FPREGS+200(a0) 104 + EX sdc1 $f27, SC32_FPREGS+216(a0) 105 + EX sdc1 $f29, SC32_FPREGS+232(a0) 106 + EX sdc1 $f31, SC32_FPREGS+248(a0) 107 + 108 + /* Store the 16 even double precision registers */ 109 + 1: EX sdc1 $f0, SC32_FPREGS+0(a0) 110 EX sdc1 $f2, SC32_FPREGS+16(a0) 111 EX sdc1 $f4, SC32_FPREGS+32(a0) 112 EX sdc1 $f6, SC32_FPREGS+48(a0) ··· 114 */ 115 LEAF(_restore_fp_context) 116 EX lw t0, SC_FPC_CSR(a0) 117 + 118 + #if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) 119 + .set push 120 + #ifdef CONFIG_MIPS32_R2 121 + .set mips64r2 122 + mfc0 t0, CP0_STATUS 123 + sll t0, t0, 5 124 + bgez t0, 1f # skip loading odd if FR=0 125 + nop 126 + #endif 127 EX ldc1 $f1, SC_FPREGS+8(a0) 128 EX ldc1 $f3, SC_FPREGS+24(a0) 129 EX ldc1 $f5, SC_FPREGS+40(a0) ··· 131 EX ldc1 $f27, SC_FPREGS+216(a0) 132 EX ldc1 $f29, SC_FPREGS+232(a0) 133 EX ldc1 $f31, SC_FPREGS+248(a0) 134 + 1: .set pop 135 #endif 136 EX ldc1 $f0, SC_FPREGS+0(a0) 137 EX ldc1 $f2, SC_FPREGS+16(a0) ··· 157 LEAF(_restore_fp_context32) 158 /* Restore an o32 sigcontext. */ 159 EX lw t0, SC32_FPC_CSR(a0) 160 + 161 + mfc0 t0, CP0_STATUS 162 + sll t0, t0, 5 163 + bgez t0, 1f # skip loading odd if FR=0 164 + nop 165 + 166 + EX ldc1 $f1, SC32_FPREGS+8(a0) 167 + EX ldc1 $f3, SC32_FPREGS+24(a0) 168 + EX ldc1 $f5, SC32_FPREGS+40(a0) 169 + EX ldc1 $f7, SC32_FPREGS+56(a0) 170 + EX ldc1 $f9, SC32_FPREGS+72(a0) 171 + EX ldc1 $f11, SC32_FPREGS+88(a0) 172 + EX ldc1 $f13, SC32_FPREGS+104(a0) 173 + EX ldc1 $f15, SC32_FPREGS+120(a0) 174 + EX ldc1 $f17, SC32_FPREGS+136(a0) 175 + EX ldc1 $f19, SC32_FPREGS+152(a0) 176 + EX ldc1 $f21, SC32_FPREGS+168(a0) 177 + EX ldc1 $f23, SC32_FPREGS+184(a0) 178 + EX ldc1 $f25, SC32_FPREGS+200(a0) 179 + EX ldc1 $f27, SC32_FPREGS+216(a0) 180 + EX ldc1 $f29, SC32_FPREGS+232(a0) 181 + EX ldc1 $f31, SC32_FPREGS+248(a0) 182 + 183 + 1: EX ldc1 $f0, SC32_FPREGS+0(a0) 184 EX ldc1 $f2, SC32_FPREGS+16(a0) 185 EX ldc1 $f4, SC32_FPREGS+32(a0) 186 EX ldc1 $f6, SC32_FPREGS+48(a0)
+43 -2
arch/mips/kernel/r4k_switch.S
··· 123 * Save a thread's fp context. 124 */ 125 LEAF(_save_fp) 126 - #ifdef CONFIG_64BIT 127 mfc0 t0, CP0_STATUS 128 #endif 129 fpu_save_double a0 t0 t1 # clobbers t1 ··· 134 * Restore a thread's fp context. 135 */ 136 LEAF(_restore_fp) 137 - #ifdef CONFIG_64BIT 138 mfc0 t0, CP0_STATUS 139 #endif 140 fpu_restore_double a0 t0 t1 # clobbers t1 ··· 228 mtc1 t1, $f29 229 mtc1 t1, $f30 230 mtc1 t1, $f31 231 #else 232 .set mips3 233 dmtc1 t1, $f0
··· 123 * Save a thread's fp context. 124 */ 125 LEAF(_save_fp) 126 + #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 127 mfc0 t0, CP0_STATUS 128 #endif 129 fpu_save_double a0 t0 t1 # clobbers t1 ··· 134 * Restore a thread's fp context. 135 */ 136 LEAF(_restore_fp) 137 + #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) 138 mfc0 t0, CP0_STATUS 139 #endif 140 fpu_restore_double a0 t0 t1 # clobbers t1 ··· 228 mtc1 t1, $f29 229 mtc1 t1, $f30 230 mtc1 t1, $f31 231 + 232 + #ifdef CONFIG_CPU_MIPS32_R2 233 + .set push 234 + .set mips64r2 235 + sll t0, t0, 5 # is Status.FR set? 236 + bgez t0, 1f # no: skip setting upper 32b 237 + 238 + mthc1 t1, $f0 239 + mthc1 t1, $f1 240 + mthc1 t1, $f2 241 + mthc1 t1, $f3 242 + mthc1 t1, $f4 243 + mthc1 t1, $f5 244 + mthc1 t1, $f6 245 + mthc1 t1, $f7 246 + mthc1 t1, $f8 247 + mthc1 t1, $f9 248 + mthc1 t1, $f10 249 + mthc1 t1, $f11 250 + mthc1 t1, $f12 251 + mthc1 t1, $f13 252 + mthc1 t1, $f14 253 + mthc1 t1, $f15 254 + mthc1 t1, $f16 255 + mthc1 t1, $f17 256 + mthc1 t1, $f18 257 + mthc1 t1, $f19 258 + mthc1 t1, $f20 259 + mthc1 t1, $f21 260 + mthc1 t1, $f22 261 + mthc1 t1, $f23 262 + mthc1 t1, $f24 263 + mthc1 t1, $f25 264 + mthc1 t1, $f26 265 + mthc1 t1, $f27 266 + mthc1 t1, $f28 267 + mthc1 t1, $f29 268 + mthc1 t1, $f30 269 + mthc1 t1, $f31 270 + 1: .set pop 271 + #endif /* CONFIG_CPU_MIPS32_R2 */ 272 #else 273 .set mips3 274 dmtc1 t1, $f0
+116
arch/mips/kernel/rtlx-cmp.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 + */ 9 + #include <linux/device.h> 10 + #include <linux/fs.h> 11 + #include <linux/err.h> 12 + #include <linux/wait.h> 13 + #include <linux/sched.h> 14 + #include <linux/smp.h> 15 + 16 + #include <asm/mips_mt.h> 17 + #include <asm/vpe.h> 18 + #include <asm/rtlx.h> 19 + 20 + static int major; 21 + 22 + static void rtlx_interrupt(void) 23 + { 24 + int i; 25 + struct rtlx_info *info; 26 + struct rtlx_info **p = vpe_get_shared(aprp_cpu_index()); 27 + 28 + if (p == NULL || *p == NULL) 29 + return; 30 + 31 + info = *p; 32 + 33 + if (info->ap_int_pending == 1 && smp_processor_id() == 0) { 34 + for (i = 0; i < RTLX_CHANNELS; i++) { 35 + wake_up(&channel_wqs[i].lx_queue); 36 + wake_up(&channel_wqs[i].rt_queue); 37 + } 38 + info->ap_int_pending = 0; 39 + } 40 + } 41 + 42 + void _interrupt_sp(void) 43 + { 44 + smp_send_reschedule(aprp_cpu_index()); 45 + } 46 + 47 + int __init rtlx_module_init(void) 48 + { 49 + struct device *dev; 50 + int i, err; 51 + 52 + if (!cpu_has_mipsmt) { 53 + pr_warn("VPE loader: not a MIPS MT capable processor\n"); 54 + return -ENODEV; 55 + } 56 + 57 + if (num_possible_cpus() - aprp_cpu_index() < 1) { 58 + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" 59 + "Pass maxcpus=<n> argument as kernel argument\n"); 60 + 61 + return -ENODEV; 62 + } 63 + 64 + major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); 65 + if (major < 0) { 66 + pr_err("rtlx_module_init: unable to register device\n"); 67 + return major; 68 + } 69 + 70 + /* initialise the wait queues */ 71 + for (i = 0; i < RTLX_CHANNELS; i++) { 72 + init_waitqueue_head(&channel_wqs[i].rt_queue); 73 + init_waitqueue_head(&channel_wqs[i].lx_queue); 74 + atomic_set(&channel_wqs[i].in_open, 0); 75 + mutex_init(&channel_wqs[i].mutex); 76 + 77 + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, 78 + "%s%d", RTLX_MODULE_NAME, i); 79 + if (IS_ERR(dev)) { 80 + err = PTR_ERR(dev); 81 + goto out_chrdev; 82 + } 83 + } 84 + 85 + /* set up notifiers */ 86 + rtlx_notify.start = rtlx_starting; 87 + rtlx_notify.stop = rtlx_stopping; 88 + vpe_notify(aprp_cpu_index(), &rtlx_notify); 89 + 90 + if (cpu_has_vint) { 91 + aprp_hook = rtlx_interrupt; 92 + } else { 93 + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); 94 + err = -ENODEV; 95 + goto out_class; 96 + } 97 + 98 + return 0; 99 + 100 + out_class: 101 + for (i = 0; i < RTLX_CHANNELS; i++) 102 + device_destroy(mt_class, MKDEV(major, i)); 103 + out_chrdev: 104 + unregister_chrdev(major, RTLX_MODULE_NAME); 105 + 106 + return err; 107 + } 108 + 109 + void __exit rtlx_module_exit(void) 110 + { 111 + int i; 112 + 113 + for (i = 0; i < RTLX_CHANNELS; i++) 114 + device_destroy(mt_class, MKDEV(major, i)); 115 + unregister_chrdev(major, RTLX_MODULE_NAME); 116 + }
+148
arch/mips/kernel/rtlx-mt.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 + */ 9 + #include <linux/device.h> 10 + #include <linux/fs.h> 11 + #include <linux/err.h> 12 + #include <linux/wait.h> 13 + #include <linux/sched.h> 14 + #include <linux/interrupt.h> 15 + #include <linux/irq.h> 16 + 17 + #include <asm/mips_mt.h> 18 + #include <asm/vpe.h> 19 + #include <asm/rtlx.h> 20 + 21 + static int major; 22 + 23 + static void rtlx_dispatch(void) 24 + { 25 + if (read_c0_cause() & read_c0_status() & C_SW0) 26 + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); 27 + } 28 + 29 + /* 30 + * Interrupt handler may be called before rtlx_init has otherwise had 31 + * a chance to run. 32 + */ 33 + static irqreturn_t rtlx_interrupt(int irq, void *dev_id) 34 + { 35 + unsigned int vpeflags; 36 + unsigned long flags; 37 + int i; 38 + 39 + /* Ought not to be strictly necessary for SMTC builds */ 40 + local_irq_save(flags); 41 + vpeflags = dvpe(); 42 + set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ); 43 + irq_enable_hazard(); 44 + evpe(vpeflags); 45 + local_irq_restore(flags); 46 + 47 + for (i = 0; i < RTLX_CHANNELS; i++) { 48 + wake_up(&channel_wqs[i].lx_queue); 49 + wake_up(&channel_wqs[i].rt_queue); 50 + } 51 + 52 + return IRQ_HANDLED; 53 + } 54 + 55 + static struct irqaction rtlx_irq = { 56 + .handler = rtlx_interrupt, 57 + .name = "RTLX", 58 + }; 59 + 60 + static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; 61 + 62 + void _interrupt_sp(void) 63 + { 64 + unsigned long flags; 65 + 66 + local_irq_save(flags); 67 + dvpe(); 68 + settc(1); 69 + write_vpe_c0_cause(read_vpe_c0_cause() | C_SW0); 70 + evpe(EVPE_ENABLE); 71 + local_irq_restore(flags); 72 + } 73 + 74 + int __init rtlx_module_init(void) 75 + { 76 + struct device *dev; 77 + int i, err; 78 + 79 + if (!cpu_has_mipsmt) { 80 + pr_warn("VPE loader: not a MIPS MT capable processor\n"); 81 + return -ENODEV; 82 + } 83 + 84 + if (aprp_cpu_index() == 0) { 85 + pr_warn("No TCs reserved for AP/SP, not initializing RTLX.\n" 86 + "Pass maxtcs=<n> argument as kernel argument\n"); 87 + 88 + return -ENODEV; 89 + } 90 + 91 + major = register_chrdev(0, RTLX_MODULE_NAME, &rtlx_fops); 92 + if (major < 0) { 93 + pr_err("rtlx_module_init: unable to register device\n"); 94 + return major; 95 + } 96 + 97 + /* initialise the wait queues */ 98 + for (i = 0; i < RTLX_CHANNELS; i++) { 99 + init_waitqueue_head(&channel_wqs[i].rt_queue); 100 + init_waitqueue_head(&channel_wqs[i].lx_queue); 101 + atomic_set(&channel_wqs[i].in_open, 0); 102 + mutex_init(&channel_wqs[i].mutex); 103 + 104 + dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, 105 + "%s%d", RTLX_MODULE_NAME, i); 106 + if (IS_ERR(dev)) { 107 + err = PTR_ERR(dev); 108 + goto out_chrdev; 109 + } 110 + } 111 + 112 + /* set up notifiers */ 113 + rtlx_notify.start = rtlx_starting; 114 + rtlx_notify.stop = rtlx_stopping; 115 + vpe_notify(aprp_cpu_index(), &rtlx_notify); 116 + 117 + if (cpu_has_vint) { 118 + aprp_hook = rtlx_dispatch; 119 + } else { 120 + pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); 121 + err = -ENODEV; 122 + goto out_class; 123 + } 124 + 125 + rtlx_irq.dev_id = rtlx; 126 + err = setup_irq(rtlx_irq_num, &rtlx_irq); 127 + if (err) 128 + goto out_class; 129 + 130 + return 0; 131 + 132 + out_class: 133 + for (i = 0; i < RTLX_CHANNELS; i++) 134 + device_destroy(mt_class, MKDEV(major, i)); 135 + out_chrdev: 136 + unregister_chrdev(major, RTLX_MODULE_NAME); 137 + 138 + return err; 139 + } 140 + 141 + void __exit rtlx_module_exit(void) 142 + { 143 + int i; 144 + 145 + for (i = 0; i < RTLX_CHANNELS; i++) 146 + device_destroy(mt_class, MKDEV(major, i)); 147 + unregister_chrdev(major, RTLX_MODULE_NAME); 148 + }
+62 -211
arch/mips/kernel/rtlx.c
··· 1 /* 2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org) 4 - * 5 - * This program is free software; you can distribute it and/or modify it 6 - * under the terms of the GNU General Public License (Version 2) as 7 - * published by the Free Software Foundation. 8 - * 9 - * This program is distributed in the hope it will be useful, but WITHOUT 10 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 - * for more details. 13 - * 14 - * You should have received a copy of the GNU General Public License along 15 - * with this program; if not, write to the Free Software Foundation, Inc., 16 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 - * 18 */ 19 - 20 - #include <linux/device.h> 21 #include <linux/kernel.h> 22 #include <linux/fs.h> 23 - #include <linux/init.h> 24 - #include <asm/uaccess.h> 25 - #include <linux/list.h> 26 - #include <linux/vmalloc.h> 27 - #include <linux/elf.h> 28 - #include <linux/seq_file.h> 29 #include <linux/syscalls.h> 30 #include <linux/moduleloader.h> 31 - #include <linux/interrupt.h> 32 - #include <linux/poll.h> 33 - #include <linux/sched.h> 34 - #include <linux/wait.h> 35 #include <asm/mipsmtregs.h> 36 #include <asm/mips_mt.h> 37 - #include <asm/cacheflush.h> 38 - #include <linux/atomic.h> 39 - #include <asm/cpu.h> 40 #include <asm/processor.h> 41 - #include <asm/vpe.h> 42 #include <asm/rtlx.h> 43 #include <asm/setup.h> 44 45 - static struct rtlx_info *rtlx; 46 - static int major; 47 - static char module_name[] = "rtlx"; 48 - 49 - static struct chan_waitqueues { 50 - wait_queue_head_t rt_queue; 51 - wait_queue_head_t lx_queue; 52 - atomic_t in_open; 53 - struct mutex mutex; 54 - } channel_wqs[RTLX_CHANNELS]; 55 - 56 - static struct vpe_notifications notify; 57 static int sp_stopping; 58 - 59 - extern void *vpe_get_shared(int index); 60 - 61 - static void rtlx_dispatch(void) 62 - { 63 - do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ); 64 - } 65 - 66 - 67 - /* Interrupt handler may be called before rtlx_init has otherwise had 68 - a chance to run. 69 - */ 70 - static irqreturn_t rtlx_interrupt(int irq, void *dev_id) 71 - { 72 - unsigned int vpeflags; 73 - unsigned long flags; 74 - int i; 75 - 76 - /* Ought not to be strictly necessary for SMTC builds */ 77 - local_irq_save(flags); 78 - vpeflags = dvpe(); 79 - set_c0_status(0x100 << MIPS_CPU_RTLX_IRQ); 80 - irq_enable_hazard(); 81 - evpe(vpeflags); 82 - local_irq_restore(flags); 83 - 84 - for (i = 0; i < RTLX_CHANNELS; i++) { 85 - wake_up(&channel_wqs[i].lx_queue); 86 - wake_up(&channel_wqs[i].rt_queue); 87 - } 88 - 89 - return IRQ_HANDLED; 90 - } 91 92 static void __used dump_rtlx(void) 93 { 94 int i; 95 96 - printk("id 0x%lx state %d\n", rtlx->id, rtlx->state); 97 98 for (i = 0; i < RTLX_CHANNELS; i++) { 99 struct rtlx_channel *chan = &rtlx->channel[i]; 100 101 - printk(" rt_state %d lx_state %d buffer_size %d\n", 102 - chan->rt_state, chan->lx_state, chan->buffer_size); 103 104 - printk(" rt_read %d rt_write %d\n", 105 - chan->rt_read, chan->rt_write); 106 107 - printk(" lx_read %d lx_write %d\n", 108 - chan->lx_read, chan->lx_write); 109 110 - printk(" rt_buffer <%s>\n", chan->rt_buffer); 111 - printk(" lx_buffer <%s>\n", chan->lx_buffer); 112 } 113 } 114 ··· 53 static int rtlx_init(struct rtlx_info *rtlxi) 54 { 55 if (rtlxi->id != RTLX_ID) { 56 - printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", 57 - rtlxi, rtlxi->id); 58 return -ENOEXEC; 59 } 60 ··· 63 } 64 65 /* notifications */ 66 - static void starting(int vpe) 67 { 68 int i; 69 sp_stopping = 0; 70 71 /* force a reload of rtlx */ 72 - rtlx=NULL; 73 74 /* wake up any sleeping rtlx_open's */ 75 for (i = 0; i < RTLX_CHANNELS; i++) 76 wake_up_interruptible(&channel_wqs[i].lx_queue); 77 } 78 79 - static void stopping(int vpe) 80 { 81 int i; 82 ··· 94 int ret = 0; 95 96 if (index >= RTLX_CHANNELS) { 97 - printk(KERN_DEBUG "rtlx_open index out of range\n"); 98 return -ENOSYS; 99 } 100 101 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { 102 - printk(KERN_DEBUG "rtlx_open channel %d already opened\n", 103 - index); 104 ret = -EBUSY; 105 goto out_fail; 106 } 107 108 if (rtlx == NULL) { 109 - if( (p = vpe_get_shared(tclimit)) == NULL) { 110 - if (can_sleep) { 111 - ret = __wait_event_interruptible( 112 channel_wqs[index].lx_queue, 113 - (p = vpe_get_shared(tclimit))); 114 - if (ret) 115 goto out_fail; 116 - } else { 117 - printk(KERN_DEBUG "No SP program loaded, and device " 118 - "opened with O_NONBLOCK\n"); 119 - ret = -ENOSYS; 120 - goto out_fail; 121 - } 122 } 123 124 smp_rmb(); ··· 139 ret = -ERESTARTSYS; 140 goto out_fail; 141 } 142 - finish_wait(&channel_wqs[index].lx_queue, &wait); 143 } else { 144 - pr_err(" *vpe_get_shared is NULL. " 145 - "Has an SP program been loaded?\n"); 146 ret = -ENOSYS; 147 goto out_fail; 148 } 149 } 150 151 if ((unsigned int)*p < KSEG0) { 152 - printk(KERN_WARNING "vpe_get_shared returned an " 153 - "invalid pointer maybe an error code %d\n", 154 - (int)*p); 155 ret = -ENOSYS; 156 goto out_fail; 157 } 158 159 - if ((ret = rtlx_init(*p)) < 0) 160 goto out_ret; 161 } 162 ··· 287 size_t fl; 288 289 if (rtlx == NULL) 290 - return(-ENOSYS); 291 292 rt = &rtlx->channel[index]; 293 ··· 296 rt_read = rt->rt_read; 297 298 /* total number of bytes to copy */ 299 - count = min(count, (size_t)write_spacefree(rt_read, rt->rt_write, 300 - rt->buffer_size)); 301 302 /* first bit from write pointer to the end of the buffer, or count */ 303 fl = min(count, (size_t) rt->buffer_size - rt->rt_write); ··· 307 goto out; 308 309 /* if there's any left copy to the beginning of the buffer */ 310 - if (count - fl) { 311 failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl); 312 - } 313 314 out: 315 count -= failed; ··· 317 rt->rt_write = (rt->rt_write + count) % rt->buffer_size; 318 smp_wmb(); 319 mutex_unlock(&channel_wqs[index].mutex); 320 321 return count; 322 } ··· 334 return rtlx_release(iminor(inode)); 335 } 336 337 - static unsigned int file_poll(struct file *file, poll_table * wait) 338 { 339 int minor = iminor(file_inode(file)); 340 unsigned int mask = 0; ··· 356 return mask; 357 } 358 359 - static ssize_t file_read(struct file *file, char __user * buffer, size_t count, 360 - loff_t * ppos) 361 { 362 int minor = iminor(file_inode(file)); 363 364 /* data available? */ 365 - if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) { 366 - return 0; // -EAGAIN makes cat whinge 367 - } 368 369 return rtlx_read(minor, buffer, count); 370 } 371 372 - static ssize_t file_write(struct file *file, const char __user * buffer, 373 - size_t count, loff_t * ppos) 374 { 375 int minor = iminor(file_inode(file)); 376 ··· 389 return rtlx_write(minor, buffer, count); 390 } 391 392 - static const struct file_operations rtlx_fops = { 393 .owner = THIS_MODULE, 394 - .open = file_open, 395 .release = file_release, 396 .write = file_write, 397 - .read = file_read, 398 - .poll = file_poll, 399 .llseek = noop_llseek, 400 }; 401 - 402 - static struct irqaction rtlx_irq = { 403 - .handler = rtlx_interrupt, 404 - .name = "RTLX", 405 - }; 406 - 407 - static int rtlx_irq_num = MIPS_CPU_IRQ_BASE + MIPS_CPU_RTLX_IRQ; 408 - 409 - static char register_chrdev_failed[] __initdata = 410 - KERN_ERR "rtlx_module_init: unable to register device\n"; 411 - 412 - static int __init rtlx_module_init(void) 413 - { 414 - struct device *dev; 415 - int i, err; 416 - 417 - if (!cpu_has_mipsmt) { 418 - printk("VPE loader: not a MIPS MT capable processor\n"); 419 - return -ENODEV; 420 - } 421 - 422 - if (tclimit == 0) { 423 - printk(KERN_WARNING "No TCs reserved for AP/SP, not " 424 - "initializing RTLX.\nPass maxtcs=<n> argument as kernel " 425 - "argument\n"); 426 - 427 - return -ENODEV; 428 - } 429 - 430 - major = register_chrdev(0, module_name, &rtlx_fops); 431 - if (major < 0) { 432 - printk(register_chrdev_failed); 433 - return major; 434 - } 435 - 436 - /* initialise the wait queues */ 437 - for (i = 0; i < RTLX_CHANNELS; i++) { 438 - init_waitqueue_head(&channel_wqs[i].rt_queue); 439 - init_waitqueue_head(&channel_wqs[i].lx_queue); 440 - atomic_set(&channel_wqs[i].in_open, 0); 441 - mutex_init(&channel_wqs[i].mutex); 442 - 443 - dev = device_create(mt_class, NULL, MKDEV(major, i), NULL, 444 - "%s%d", module_name, i); 445 - if (IS_ERR(dev)) { 446 - err = PTR_ERR(dev); 447 - goto out_chrdev; 448 - } 449 - } 450 - 451 - /* set up notifiers */ 452 - notify.start = starting; 453 - notify.stop = stopping; 454 - vpe_notify(tclimit, &notify); 455 - 456 - if (cpu_has_vint) 457 - set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch); 458 - else { 459 - pr_err("APRP RTLX init on non-vectored-interrupt processor\n"); 460 - err = -ENODEV; 461 - goto out_chrdev; 462 - } 463 - 464 - rtlx_irq.dev_id = rtlx; 465 - setup_irq(rtlx_irq_num, &rtlx_irq); 466 - 467 - return 0; 468 - 469 - out_chrdev: 470 - for (i = 0; i < RTLX_CHANNELS; i++) 471 - device_destroy(mt_class, MKDEV(major, i)); 472 - 473 - return err; 474 - } 475 - 476 - static void __exit rtlx_module_exit(void) 477 - { 478 - int i; 479 - 480 - for (i = 0; i < RTLX_CHANNELS; i++) 481 - device_destroy(mt_class, MKDEV(major, i)); 482 - 483 - unregister_chrdev(major, module_name); 484 - } 485 486 module_init(rtlx_module_init); 487 module_exit(rtlx_module_exit);
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 7 * Copyright (C) 2005, 06 Ralf Baechle (ralf@linux-mips.org) 8 + * Copyright (C) 2013 Imagination Technologies Ltd. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/fs.h> 12 #include <linux/syscalls.h> 13 #include <linux/moduleloader.h> 14 + #include <linux/atomic.h> 15 #include <asm/mipsmtregs.h> 16 #include <asm/mips_mt.h> 17 #include <asm/processor.h> 18 #include <asm/rtlx.h> 19 #include <asm/setup.h> 20 + #include <asm/vpe.h> 21 22 static int sp_stopping; 23 + struct rtlx_info *rtlx; 24 + struct chan_waitqueues channel_wqs[RTLX_CHANNELS]; 25 + struct vpe_notifications rtlx_notify; 26 + void (*aprp_hook)(void) = NULL; 27 + EXPORT_SYMBOL(aprp_hook); 28 29 static void __used dump_rtlx(void) 30 { 31 int i; 32 33 + pr_info("id 0x%lx state %d\n", rtlx->id, rtlx->state); 34 35 for (i = 0; i < RTLX_CHANNELS; i++) { 36 struct rtlx_channel *chan = &rtlx->channel[i]; 37 38 + pr_info(" rt_state %d lx_state %d buffer_size %d\n", 39 + chan->rt_state, chan->lx_state, chan->buffer_size); 40 41 + pr_info(" rt_read %d rt_write %d\n", 42 + chan->rt_read, chan->rt_write); 43 44 + pr_info(" lx_read %d lx_write %d\n", 45 + chan->lx_read, chan->lx_write); 46 47 + pr_info(" rt_buffer <%s>\n", chan->rt_buffer); 48 + pr_info(" lx_buffer <%s>\n", chan->lx_buffer); 49 } 50 } 51 ··· 116 static int rtlx_init(struct rtlx_info *rtlxi) 117 { 118 if (rtlxi->id != RTLX_ID) { 119 + pr_err("no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id); 120 return -ENOEXEC; 121 } 122 ··· 127 } 128 129 /* notifications */ 130 + void rtlx_starting(int vpe) 131 { 132 int i; 133 sp_stopping = 0; 134 135 /* force a reload of rtlx */ 136 + rtlx = NULL; 137 138 /* wake up any sleeping rtlx_open's */ 139 for (i = 0; i < RTLX_CHANNELS; i++) 140 wake_up_interruptible(&channel_wqs[i].lx_queue); 141 } 142 143 + void rtlx_stopping(int vpe) 144 { 145 int i; 146 ··· 158 int ret = 0; 159 160 if (index >= RTLX_CHANNELS) { 161 + pr_debug(KERN_DEBUG "rtlx_open index out of range\n"); 162 return -ENOSYS; 163 } 164 165 if (atomic_inc_return(&channel_wqs[index].in_open) > 1) { 166 + pr_debug(KERN_DEBUG "rtlx_open channel %d already opened\n", index); 167 ret = -EBUSY; 168 goto out_fail; 169 } 170 171 if (rtlx == NULL) { 172 + p = vpe_get_shared(aprp_cpu_index()); 173 + if (p == NULL) { 174 + if (can_sleep) { 175 + ret = __wait_event_interruptible( 176 channel_wqs[index].lx_queue, 177 + (p = vpe_get_shared(aprp_cpu_index()))); 178 + if (ret) 179 + goto out_fail; 180 + } else { 181 + pr_debug("No SP program loaded, and device opened with O_NONBLOCK\n"); 182 + ret = -ENOSYS; 183 goto out_fail; 184 + } 185 } 186 187 smp_rmb(); ··· 204 ret = -ERESTARTSYS; 205 goto out_fail; 206 } 207 + finish_wait(&channel_wqs[index].lx_queue, 208 + &wait); 209 } else { 210 + pr_err(" *vpe_get_shared is NULL. Has an SP program been loaded?\n"); 211 ret = -ENOSYS; 212 goto out_fail; 213 } 214 } 215 216 if ((unsigned int)*p < KSEG0) { 217 + pr_warn("vpe_get_shared returned an invalid pointer maybe an error code %d\n", 218 + (int)*p); 219 ret = -ENOSYS; 220 goto out_fail; 221 } 222 223 + ret = rtlx_init(*p); 224 + if (ret < 0) 225 goto out_ret; 226 } 227 ··· 352 size_t fl; 353 354 if (rtlx == NULL) 355 + return -ENOSYS; 356 357 rt = &rtlx->channel[index]; 358 ··· 361 rt_read = rt->rt_read; 362 363 /* total number of bytes to copy */ 364 + count = min_t(size_t, count, write_spacefree(rt_read, rt->rt_write, 365 + rt->buffer_size)); 366 367 /* first bit from write pointer to the end of the buffer, or count */ 368 fl = min(count, (size_t) rt->buffer_size - rt->rt_write); ··· 372 goto out; 373 374 /* if there's any left copy to the beginning of the buffer */ 375 + if (count - fl) 376 failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl); 377 378 out: 379 count -= failed; ··· 383 rt->rt_write = (rt->rt_write + count) % rt->buffer_size; 384 smp_wmb(); 385 mutex_unlock(&channel_wqs[index].mutex); 386 + 387 + _interrupt_sp(); 388 389 return count; 390 } ··· 398 return rtlx_release(iminor(inode)); 399 } 400 401 + static unsigned int file_poll(struct file *file, poll_table *wait) 402 { 403 int minor = iminor(file_inode(file)); 404 unsigned int mask = 0; ··· 420 return mask; 421 } 422 423 + static ssize_t file_read(struct file *file, char __user *buffer, size_t count, 424 + loff_t *ppos) 425 { 426 int minor = iminor(file_inode(file)); 427 428 /* data available? */ 429 + if (!rtlx_read_poll(minor, (file->f_flags & O_NONBLOCK) ? 0 : 1)) 430 + return 0; /* -EAGAIN makes 'cat' whine */ 431 432 return rtlx_read(minor, buffer, count); 433 } 434 435 + static ssize_t file_write(struct file *file, const char __user *buffer, 436 + size_t count, loff_t *ppos) 437 { 438 int minor = iminor(file_inode(file)); 439 ··· 454 return rtlx_write(minor, buffer, count); 455 } 456 457 + const struct file_operations rtlx_fops = { 458 .owner = THIS_MODULE, 459 + .open = file_open, 460 .release = file_release, 461 .write = file_write, 462 + .read = file_read, 463 + .poll = file_poll, 464 .llseek = noop_llseek, 465 }; 466 467 module_init(rtlx_module_init); 468 module_exit(rtlx_module_exit);
+110
arch/mips/kernel/segment.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2013 Imagination Technologies Ltd. 7 + */ 8 + 9 + #include <linux/kernel.h> 10 + #include <linux/debugfs.h> 11 + #include <linux/seq_file.h> 12 + #include <asm/cpu.h> 13 + #include <asm/mipsregs.h> 14 + 15 + static void build_segment_config(char *str, unsigned int cfg) 16 + { 17 + unsigned int am; 18 + static const char * const am_str[] = { 19 + "UK", "MK", "MSK", "MUSK", "MUSUK", "USK", 20 + "RSRVD", "UUSK"}; 21 + 22 + /* Segment access mode. */ 23 + am = (cfg & MIPS_SEGCFG_AM) >> MIPS_SEGCFG_AM_SHIFT; 24 + str += sprintf(str, "%-5s", am_str[am]); 25 + 26 + /* 27 + * Access modes MK, MSK and MUSK are mapped segments. Therefore 28 + * there is no direct physical address mapping. 29 + */ 30 + if ((am == 0) || (am > 3)) { 31 + str += sprintf(str, " %03lx", 32 + ((cfg & MIPS_SEGCFG_PA) >> MIPS_SEGCFG_PA_SHIFT)); 33 + str += sprintf(str, " %01ld", 34 + ((cfg & MIPS_SEGCFG_C) >> MIPS_SEGCFG_C_SHIFT)); 35 + } else { 36 + str += sprintf(str, " UND"); 37 + str += sprintf(str, " U"); 38 + } 39 + 40 + /* Exception configuration. */ 41 + str += sprintf(str, " %01ld\n", 42 + ((cfg & MIPS_SEGCFG_EU) >> MIPS_SEGCFG_EU_SHIFT)); 43 + } 44 + 45 + static int show_segments(struct seq_file *m, void *v) 46 + { 47 + unsigned int segcfg; 48 + char str[42]; 49 + 50 + seq_puts(m, "Segment Virtual Size Access Mode Physical Caching EU\n"); 51 + seq_puts(m, "------- ------- ---- ----------- -------- ------- --\n"); 52 + 53 + segcfg = read_c0_segctl0(); 54 + build_segment_config(str, segcfg); 55 + seq_printf(m, " 0 e0000000 512M %s", str); 56 + 57 + segcfg >>= 16; 58 + build_segment_config(str, segcfg); 59 + seq_printf(m, " 1 c0000000 512M %s", str); 60 + 61 + segcfg = read_c0_segctl1(); 62 + build_segment_config(str, segcfg); 63 + seq_printf(m, " 2 a0000000 512M %s", str); 64 + 65 + segcfg >>= 16; 66 + build_segment_config(str, segcfg); 67 + seq_printf(m, " 3 80000000 512M %s", str); 68 + 69 + segcfg = read_c0_segctl2(); 70 + build_segment_config(str, segcfg); 71 + seq_printf(m, " 4 40000000 1G %s", str); 72 + 73 + segcfg >>= 16; 74 + build_segment_config(str, segcfg); 75 + seq_printf(m, " 5 00000000 1G %s\n", str); 76 + 77 + return 0; 78 + } 79 + 80 + static int segments_open(struct inode *inode, struct file *file) 81 + { 82 + return single_open(file, show_segments, NULL); 83 + } 84 + 85 + static const struct file_operations segments_fops = { 86 + .open = segments_open, 87 + .read = seq_read, 88 + .llseek = seq_lseek, 89 + .release = single_release, 90 + }; 91 + 92 + static int __init segments_info(void) 93 + { 94 + extern struct dentry *mips_debugfs_dir; 95 + struct dentry *segments; 96 + 97 + if (cpu_has_segments) { 98 + if (!mips_debugfs_dir) 99 + return -ENODEV; 100 + 101 + segments = debugfs_create_file("segments", S_IRUGO, 102 + mips_debugfs_dir, NULL, 103 + &segments_fops); 104 + if (!segments) 105 + return -ENOMEM; 106 + } 107 + return 0; 108 + } 109 + 110 + device_initcall(segments_info);
+6 -4
arch/mips/kernel/signal.c
··· 71 int err; 72 while (1) { 73 lock_fpu_owner(); 74 - own_fpu_inatomic(1); 75 - err = save_fp_context(sc); /* this might fail */ 76 unlock_fpu_owner(); 77 if (likely(!err)) 78 break; ··· 92 int err, tmp __maybe_unused; 93 while (1) { 94 lock_fpu_owner(); 95 - own_fpu_inatomic(0); 96 - err = restore_fp_context(sc); /* this might fail */ 97 unlock_fpu_owner(); 98 if (likely(!err)) 99 break;
··· 71 int err; 72 while (1) { 73 lock_fpu_owner(); 74 + err = own_fpu_inatomic(1); 75 + if (!err) 76 + err = save_fp_context(sc); /* this might fail */ 77 unlock_fpu_owner(); 78 if (likely(!err)) 79 break; ··· 91 int err, tmp __maybe_unused; 92 while (1) { 93 lock_fpu_owner(); 94 + err = own_fpu_inatomic(0); 95 + if (!err) 96 + err = restore_fp_context(sc); /* this might fail */ 97 unlock_fpu_owner(); 98 if (likely(!err)) 99 break;
+6 -4
arch/mips/kernel/signal32.c
··· 85 int err; 86 while (1) { 87 lock_fpu_owner(); 88 - own_fpu_inatomic(1); 89 - err = save_fp_context32(sc); /* this might fail */ 90 unlock_fpu_owner(); 91 if (likely(!err)) 92 break; ··· 106 int err, tmp __maybe_unused; 107 while (1) { 108 lock_fpu_owner(); 109 - own_fpu_inatomic(0); 110 - err = restore_fp_context32(sc); /* this might fail */ 111 unlock_fpu_owner(); 112 if (likely(!err)) 113 break;
··· 85 int err; 86 while (1) { 87 lock_fpu_owner(); 88 + err = own_fpu_inatomic(1); 89 + if (!err) 90 + err = save_fp_context32(sc); /* this might fail */ 91 unlock_fpu_owner(); 92 if (likely(!err)) 93 break; ··· 105 int err, tmp __maybe_unused; 106 while (1) { 107 lock_fpu_owner(); 108 + err = own_fpu_inatomic(0); 109 + if (!err) 110 + err = restore_fp_context32(sc); /* this might fail */ 111 unlock_fpu_owner(); 112 if (likely(!err)) 113 break;
+183 -117
arch/mips/kernel/smp-bmips.c
··· 49 unsigned long bmips_smp_boot_sp; 50 unsigned long bmips_smp_boot_gp; 51 52 - static void bmips_send_ipi_single(int cpu, unsigned int action); 53 - static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id); 54 55 /* SW interrupts 0,1 are used for interprocessor signaling */ 56 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) ··· 66 static void __init bmips_smp_setup(void) 67 { 68 int i, cpu = 1, boot_cpu = 0; 69 - 70 - #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 71 int cpu_hw_intr; 72 73 - /* arbitration priority */ 74 - clear_c0_brcm_cmt_ctrl(0x30); 75 76 - /* NBK and weak order flags */ 77 - set_c0_brcm_config_0(0x30000); 78 79 - /* Find out if we are running on TP0 or TP1 */ 80 - boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 81 82 - /* 83 - * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread 84 - * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 85 - * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 86 - */ 87 - if (boot_cpu == 0) 88 - cpu_hw_intr = 0x02; 89 - else 90 - cpu_hw_intr = 0x1d; 91 92 - change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15)); 93 94 - /* single core, 2 threads (2 pipelines) */ 95 - max_cpus = 2; 96 - #elif defined(CONFIG_CPU_BMIPS5000) 97 - /* enable raceless SW interrupts */ 98 - set_c0_brcm_config(0x03 << 22); 99 100 - /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 101 - change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 102 103 - /* N cores, 2 threads per core */ 104 - max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 105 106 - /* clear any pending SW interrupts */ 107 - for (i = 0; i < max_cpus; i++) { 108 - write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 109 - write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 110 } 111 - #endif 112 113 if (!bmips_smp_enabled) 114 max_cpus = 1; ··· 145 */ 146 static void bmips_prepare_cpus(unsigned int max_cpus) 147 { 148 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 149 "smp_ipi0", NULL)) 150 panic("Can't request IPI0 interrupt"); ··· 193 194 pr_info("SMP: Booting CPU%d...\n", cpu); 195 196 - if (cpumask_test_cpu(cpu, &bmips_booted_mask)) 197 - bmips_send_ipi_single(cpu, 0); 198 - else { 199 - #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 200 - /* Reset slave TP1 if booting from TP0 */ 201 - if (cpu_logical_map(cpu) == 1) 202 - set_c0_brcm_cmt_ctrl(0x01); 203 - #elif defined(CONFIG_CPU_BMIPS5000) 204 - if (cpu & 0x01) 205 - write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 206 - else { 207 - /* 208 - * core N thread 0 was already booted; just 209 - * pulse the NMI line 210 - */ 211 - bmips_write_zscm_reg(0x210, 0xc0000000); 212 - udelay(10); 213 - bmips_write_zscm_reg(0x210, 0x00); 214 } 215 - #endif 216 cpumask_set_cpu(cpu, &bmips_booted_mask); 217 } 218 } ··· 237 { 238 /* move NMI vector to kseg0, in case XKS01 is enabled */ 239 240 - #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380) 241 - void __iomem *cbr = BMIPS_GET_CBR(); 242 unsigned long old_vec; 243 unsigned long relo_vector; 244 int boot_cpu; 245 246 - boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 247 - relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : 248 - BMIPS_RELO_VECTOR_CONTROL_1; 249 250 - old_vec = __raw_readl(cbr + relo_vector); 251 - __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); 252 253 - clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 254 - #elif defined(CONFIG_CPU_BMIPS5000) 255 - write_c0_brcm_bootvec(read_c0_brcm_bootvec() & 256 - (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); 257 258 - write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 259 - #endif 260 } 261 262 /* ··· 287 { 288 } 289 290 - #if defined(CONFIG_CPU_BMIPS5000) 291 - 292 /* 293 * BMIPS5000 raceless IPIs 294 * ··· 295 * IPI1 is used for SMP_CALL_FUNCTION 296 */ 297 298 - static void bmips_send_ipi_single(int cpu, unsigned int action) 299 { 300 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 301 } 302 303 - static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) 304 { 305 int action = irq - IPI0_IRQ; 306 ··· 314 return IRQ_HANDLED; 315 } 316 317 - #else 318 319 /* 320 * BMIPS43xx racey IPIs ··· 336 static DEFINE_SPINLOCK(ipi_lock); 337 static DEFINE_PER_CPU(int, ipi_action_mask); 338 339 - static void bmips_send_ipi_single(int cpu, unsigned int action) 340 { 341 unsigned long flags; 342 ··· 347 spin_unlock_irqrestore(&ipi_lock, flags); 348 } 349 350 - static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id) 351 { 352 unsigned long flags; 353 int action, cpu = irq - IPI0_IRQ; ··· 366 return IRQ_HANDLED; 367 } 368 369 - #endif /* BMIPS type */ 370 - 371 - static void bmips_send_ipi_mask(const struct cpumask *mask, 372 unsigned int action) 373 { 374 unsigned int i; 375 376 for_each_cpu(i, mask) 377 - bmips_send_ipi_single(i, action); 378 } 379 380 #ifdef CONFIG_HOTPLUG_CPU ··· 428 429 #endif /* CONFIG_HOTPLUG_CPU */ 430 431 - struct plat_smp_ops bmips_smp_ops = { 432 .smp_setup = bmips_smp_setup, 433 .prepare_cpus = bmips_prepare_cpus, 434 .boot_secondary = bmips_boot_secondary, 435 .smp_finish = bmips_smp_finish, 436 .init_secondary = bmips_init_secondary, 437 .cpus_done = bmips_cpus_done, 438 - .send_ipi_single = bmips_send_ipi_single, 439 - .send_ipi_mask = bmips_send_ipi_mask, 440 #ifdef CONFIG_HOTPLUG_CPU 441 .cpu_disable = bmips_cpu_disable, 442 .cpu_die = bmips_cpu_die, ··· 489 490 BUG_ON(ebase != CKSEG0); 491 492 - #if defined(CONFIG_CPU_BMIPS4350) 493 - /* 494 - * BMIPS4350 cannot relocate the normal vectors, but it 495 - * can relocate the BEV=1 vectors. So CPU1 starts up at 496 - * the relocated BEV=1, IV=0 general exception vector @ 497 - * 0xa000_0380. 498 - * 499 - * set_uncached_handler() is used here because: 500 - * - CPU1 will run this from uncached space 501 - * - None of the cacheflush functions are set up yet 502 - */ 503 - set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 504 - &bmips_smp_int_vec, 0x80); 505 - __sync(); 506 - return; 507 - #elif defined(CONFIG_CPU_BMIPS4380) 508 - /* 509 - * 0x8000_0000: reset/NMI (initially in kseg1) 510 - * 0x8000_0400: normal vectors 511 - */ 512 - new_ebase = 0x80000400; 513 - cbr = BMIPS_GET_CBR(); 514 - __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 515 - __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 516 - #elif defined(CONFIG_CPU_BMIPS5000) 517 - /* 518 - * 0x8000_0000: reset/NMI (initially in kseg1) 519 - * 0x8000_1000: normal vectors 520 - */ 521 - new_ebase = 0x80001000; 522 - write_c0_brcm_bootvec(0xa0088008); 523 - write_c0_ebase(new_ebase); 524 - if (max_cpus > 2) 525 - bmips_write_zscm_reg(0xa0, 0xa008a008); 526 - #else 527 - return; 528 - #endif 529 board_nmi_handler_setup = &bmips_nmi_handler_setup; 530 ebase = new_ebase; 531 }
··· 49 unsigned long bmips_smp_boot_sp; 50 unsigned long bmips_smp_boot_gp; 51 52 + static void bmips43xx_send_ipi_single(int cpu, unsigned int action); 53 + static void bmips5000_send_ipi_single(int cpu, unsigned int action); 54 + static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id); 55 + static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id); 56 57 /* SW interrupts 0,1 are used for interprocessor signaling */ 58 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0) ··· 64 static void __init bmips_smp_setup(void) 65 { 66 int i, cpu = 1, boot_cpu = 0; 67 int cpu_hw_intr; 68 69 + switch (current_cpu_type()) { 70 + case CPU_BMIPS4350: 71 + case CPU_BMIPS4380: 72 + /* arbitration priority */ 73 + clear_c0_brcm_cmt_ctrl(0x30); 74 75 + /* NBK and weak order flags */ 76 + set_c0_brcm_config_0(0x30000); 77 78 + /* Find out if we are running on TP0 or TP1 */ 79 + boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 80 81 + /* 82 + * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other 83 + * thread 84 + * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output 85 + * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output 86 + */ 87 + if (boot_cpu == 0) 88 + cpu_hw_intr = 0x02; 89 + else 90 + cpu_hw_intr = 0x1d; 91 92 + change_c0_brcm_cmt_intr(0xf8018000, 93 + (cpu_hw_intr << 27) | (0x03 << 15)); 94 95 + /* single core, 2 threads (2 pipelines) */ 96 + max_cpus = 2; 97 98 + break; 99 + case CPU_BMIPS5000: 100 + /* enable raceless SW interrupts */ 101 + set_c0_brcm_config(0x03 << 22); 102 103 + /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */ 104 + change_c0_brcm_mode(0x1f << 27, 0x02 << 27); 105 106 + /* N cores, 2 threads per core */ 107 + max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1; 108 + 109 + /* clear any pending SW interrupts */ 110 + for (i = 0; i < max_cpus; i++) { 111 + write_c0_brcm_action(ACTION_CLR_IPI(i, 0)); 112 + write_c0_brcm_action(ACTION_CLR_IPI(i, 1)); 113 + } 114 + 115 + break; 116 + default: 117 + max_cpus = 1; 118 } 119 120 if (!bmips_smp_enabled) 121 max_cpus = 1; ··· 134 */ 135 static void bmips_prepare_cpus(unsigned int max_cpus) 136 { 137 + irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id); 138 + 139 + switch (current_cpu_type()) { 140 + case CPU_BMIPS4350: 141 + case CPU_BMIPS4380: 142 + bmips_ipi_interrupt = bmips43xx_ipi_interrupt; 143 + break; 144 + case CPU_BMIPS5000: 145 + bmips_ipi_interrupt = bmips5000_ipi_interrupt; 146 + break; 147 + default: 148 + return; 149 + } 150 + 151 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU, 152 "smp_ipi0", NULL)) 153 panic("Can't request IPI0 interrupt"); ··· 168 169 pr_info("SMP: Booting CPU%d...\n", cpu); 170 171 + if (cpumask_test_cpu(cpu, &bmips_booted_mask)) { 172 + switch (current_cpu_type()) { 173 + case CPU_BMIPS4350: 174 + case CPU_BMIPS4380: 175 + bmips43xx_send_ipi_single(cpu, 0); 176 + break; 177 + case CPU_BMIPS5000: 178 + bmips5000_send_ipi_single(cpu, 0); 179 + break; 180 } 181 + } 182 + else { 183 + switch (current_cpu_type()) { 184 + case CPU_BMIPS4350: 185 + case CPU_BMIPS4380: 186 + /* Reset slave TP1 if booting from TP0 */ 187 + if (cpu_logical_map(cpu) == 1) 188 + set_c0_brcm_cmt_ctrl(0x01); 189 + break; 190 + case CPU_BMIPS5000: 191 + if (cpu & 0x01) 192 + write_c0_brcm_action(ACTION_BOOT_THREAD(cpu)); 193 + else { 194 + /* 195 + * core N thread 0 was already booted; just 196 + * pulse the NMI line 197 + */ 198 + bmips_write_zscm_reg(0x210, 0xc0000000); 199 + udelay(10); 200 + bmips_write_zscm_reg(0x210, 0x00); 201 + } 202 + break; 203 + } 204 cpumask_set_cpu(cpu, &bmips_booted_mask); 205 } 206 } ··· 199 { 200 /* move NMI vector to kseg0, in case XKS01 is enabled */ 201 202 + void __iomem *cbr; 203 unsigned long old_vec; 204 unsigned long relo_vector; 205 int boot_cpu; 206 207 + switch (current_cpu_type()) { 208 + case CPU_BMIPS4350: 209 + case CPU_BMIPS4380: 210 + cbr = BMIPS_GET_CBR(); 211 212 + boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31)); 213 + relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 : 214 + BMIPS_RELO_VECTOR_CONTROL_1; 215 216 + old_vec = __raw_readl(cbr + relo_vector); 217 + __raw_writel(old_vec & ~0x20000000, cbr + relo_vector); 218 219 + clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0); 220 + break; 221 + case CPU_BMIPS5000: 222 + write_c0_brcm_bootvec(read_c0_brcm_bootvec() & 223 + (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000)); 224 + 225 + write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); 226 + break; 227 + } 228 } 229 230 /* ··· 243 { 244 } 245 246 /* 247 * BMIPS5000 raceless IPIs 248 * ··· 253 * IPI1 is used for SMP_CALL_FUNCTION 254 */ 255 256 + static void bmips5000_send_ipi_single(int cpu, unsigned int action) 257 { 258 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION)); 259 } 260 261 + static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id) 262 { 263 int action = irq - IPI0_IRQ; 264 ··· 272 return IRQ_HANDLED; 273 } 274 275 + static void bmips5000_send_ipi_mask(const struct cpumask *mask, 276 + unsigned int action) 277 + { 278 + unsigned int i; 279 + 280 + for_each_cpu(i, mask) 281 + bmips5000_send_ipi_single(i, action); 282 + } 283 284 /* 285 * BMIPS43xx racey IPIs ··· 287 static DEFINE_SPINLOCK(ipi_lock); 288 static DEFINE_PER_CPU(int, ipi_action_mask); 289 290 + static void bmips43xx_send_ipi_single(int cpu, unsigned int action) 291 { 292 unsigned long flags; 293 ··· 298 spin_unlock_irqrestore(&ipi_lock, flags); 299 } 300 301 + static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id) 302 { 303 unsigned long flags; 304 int action, cpu = irq - IPI0_IRQ; ··· 317 return IRQ_HANDLED; 318 } 319 320 + static void bmips43xx_send_ipi_mask(const struct cpumask *mask, 321 unsigned int action) 322 { 323 unsigned int i; 324 325 for_each_cpu(i, mask) 326 + bmips43xx_send_ipi_single(i, action); 327 } 328 329 #ifdef CONFIG_HOTPLUG_CPU ··· 381 382 #endif /* CONFIG_HOTPLUG_CPU */ 383 384 + struct plat_smp_ops bmips43xx_smp_ops = { 385 .smp_setup = bmips_smp_setup, 386 .prepare_cpus = bmips_prepare_cpus, 387 .boot_secondary = bmips_boot_secondary, 388 .smp_finish = bmips_smp_finish, 389 .init_secondary = bmips_init_secondary, 390 .cpus_done = bmips_cpus_done, 391 + .send_ipi_single = bmips43xx_send_ipi_single, 392 + .send_ipi_mask = bmips43xx_send_ipi_mask, 393 + #ifdef CONFIG_HOTPLUG_CPU 394 + .cpu_disable = bmips_cpu_disable, 395 + .cpu_die = bmips_cpu_die, 396 + #endif 397 + }; 398 + 399 + struct plat_smp_ops bmips5000_smp_ops = { 400 + .smp_setup = bmips_smp_setup, 401 + .prepare_cpus = bmips_prepare_cpus, 402 + .boot_secondary = bmips_boot_secondary, 403 + .smp_finish = bmips_smp_finish, 404 + .init_secondary = bmips_init_secondary, 405 + .cpus_done = bmips_cpus_done, 406 + .send_ipi_single = bmips5000_send_ipi_single, 407 + .send_ipi_mask = bmips5000_send_ipi_mask, 408 #ifdef CONFIG_HOTPLUG_CPU 409 .cpu_disable = bmips_cpu_disable, 410 .cpu_die = bmips_cpu_die, ··· 427 428 BUG_ON(ebase != CKSEG0); 429 430 + switch (current_cpu_type()) { 431 + case CPU_BMIPS4350: 432 + /* 433 + * BMIPS4350 cannot relocate the normal vectors, but it 434 + * can relocate the BEV=1 vectors. So CPU1 starts up at 435 + * the relocated BEV=1, IV=0 general exception vector @ 436 + * 0xa000_0380. 437 + * 438 + * set_uncached_handler() is used here because: 439 + * - CPU1 will run this from uncached space 440 + * - None of the cacheflush functions are set up yet 441 + */ 442 + set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0, 443 + &bmips_smp_int_vec, 0x80); 444 + __sync(); 445 + return; 446 + case CPU_BMIPS4380: 447 + /* 448 + * 0x8000_0000: reset/NMI (initially in kseg1) 449 + * 0x8000_0400: normal vectors 450 + */ 451 + new_ebase = 0x80000400; 452 + cbr = BMIPS_GET_CBR(); 453 + __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0); 454 + __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1); 455 + break; 456 + case CPU_BMIPS5000: 457 + /* 458 + * 0x8000_0000: reset/NMI (initially in kseg1) 459 + * 0x8000_1000: normal vectors 460 + */ 461 + new_ebase = 0x80001000; 462 + write_c0_brcm_bootvec(0xa0088008); 463 + write_c0_ebase(new_ebase); 464 + if (max_cpus > 2) 465 + bmips_write_zscm_reg(0xa0, 0xa008a008); 466 + break; 467 + default: 468 + return; 469 + } 470 + 471 board_nmi_handler_setup = &bmips_nmi_handler_setup; 472 ebase = new_ebase; 473 }
+3
arch/mips/kernel/smp-cmp.c
··· 199 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n", 200 smp_processor_id(), __func__, max_cpus); 201 202 /* 203 * FIXME: some of these options are per-system, some per-core and 204 * some per-cpu 205 */ 206 mips_mt_set_cpuoptions(); 207 } 208 209 struct plat_smp_ops cmp_smp_ops = {
··· 199 pr_debug("SMPCMP: CPU%d: %s max_cpus=%d\n", 200 smp_processor_id(), __func__, max_cpus); 201 202 + #ifdef CONFIG_MIPS_MT 203 /* 204 * FIXME: some of these options are per-system, some per-core and 205 * some per-cpu 206 */ 207 mips_mt_set_cpuoptions(); 208 + #endif 209 + 210 } 211 212 struct plat_smp_ops cmp_smp_ops = {
+28
arch/mips/kernel/smp-mt.c
··· 71 72 /* Record this as available CPU */ 73 set_cpu_possible(tc, true); 74 __cpu_number_map[tc] = ++ncpu; 75 __cpu_logical_map[ncpu] = tc; 76 } ··· 113 write_tc_c0_tchalt(TCHALT_H); 114 } 115 116 static void vsmp_send_ipi_single(int cpu, unsigned int action) 117 { 118 int i; 119 unsigned long flags; 120 int vpflags; 121 122 local_irq_save(flags); 123 124 vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
··· 71 72 /* Record this as available CPU */ 73 set_cpu_possible(tc, true); 74 + set_cpu_present(tc, true); 75 __cpu_number_map[tc] = ++ncpu; 76 __cpu_logical_map[ncpu] = tc; 77 } ··· 112 write_tc_c0_tchalt(TCHALT_H); 113 } 114 115 + #ifdef CONFIG_IRQ_GIC 116 + static void mp_send_ipi_single(int cpu, unsigned int action) 117 + { 118 + unsigned long flags; 119 + 120 + local_irq_save(flags); 121 + 122 + switch (action) { 123 + case SMP_CALL_FUNCTION: 124 + gic_send_ipi(plat_ipi_call_int_xlate(cpu)); 125 + break; 126 + 127 + case SMP_RESCHEDULE_YOURSELF: 128 + gic_send_ipi(plat_ipi_resched_int_xlate(cpu)); 129 + break; 130 + } 131 + 132 + local_irq_restore(flags); 133 + } 134 + #endif 135 + 136 static void vsmp_send_ipi_single(int cpu, unsigned int action) 137 { 138 int i; 139 unsigned long flags; 140 int vpflags; 141 142 + #ifdef CONFIG_IRQ_GIC 143 + if (gic_present) { 144 + mp_send_ipi_single(cpu, action); 145 + return; 146 + } 147 + #endif 148 local_irq_save(flags); 149 150 vpflags = dvpe(); /* can't access the other CPU's registers whilst MVPE enabled */
+2 -1
arch/mips/kernel/spram.c
··· 8 * 9 * Copyright (C) 2007, 2008 MIPS Technologies, Inc. 10 */ 11 - #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/ptrace.h> 14 #include <linux/stddef.h> ··· 205 case CPU_34K: 206 case CPU_74K: 207 case CPU_1004K: 208 config0 = read_c0_config(); 209 /* FIXME: addresses are Malta specific */ 210 if (config0 & (1<<24)) {
··· 8 * 9 * Copyright (C) 2007, 2008 MIPS Technologies, Inc. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/ptrace.h> 13 #include <linux/stddef.h> ··· 206 case CPU_34K: 207 case CPU_74K: 208 case CPU_1004K: 209 + case CPU_INTERAPTIV: 210 + case CPU_PROAPTIV: 211 config0 = read_c0_config(); 212 /* FIXME: addresses are Malta specific */ 213 if (config0 & (1<<24)) {
-1
arch/mips/kernel/sync-r4k.c
··· 11 */ 12 13 #include <linux/kernel.h> 14 - #include <linux/init.h> 15 #include <linux/irqflags.h> 16 #include <linux/cpumask.h> 17
··· 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/irqflags.h> 15 #include <linux/cpumask.h> 16
+58 -13
arch/mips/kernel/traps.c
··· 78 extern asmlinkage void handle_ov(void); 79 extern asmlinkage void handle_tr(void); 80 extern asmlinkage void handle_fpe(void); 81 extern asmlinkage void handle_mdmx(void); 82 extern asmlinkage void handle_watch(void); 83 extern asmlinkage void handle_mt(void); ··· 1081 unsigned long old_epc, old31; 1082 unsigned int opcode; 1083 unsigned int cpid; 1084 - int status; 1085 unsigned long __maybe_unused flags; 1086 1087 prev_state = exception_enter(); ··· 1154 1155 case 1: 1156 if (used_math()) /* Using the FPU again. */ 1157 - own_fpu(1); 1158 else { /* First time FPU user. */ 1159 - init_fpu(); 1160 set_used_math(); 1161 } 1162 1163 - if (!raw_cpu_has_fpu) { 1164 int sig; 1165 void __user *fault_addr = NULL; 1166 sig = fpu_emulator_cop1Handler(regs, 1167 &current->thread.fpu, 1168 0, &fault_addr); 1169 - if (!process_fpemu_return(sig, fault_addr)) 1170 mt_ase_fp_affinity(); 1171 } 1172 ··· 1337 case CPU_34K: 1338 case CPU_74K: 1339 case CPU_1004K: 1340 { 1341 #define ERRCTL_PE 0x80000000 1342 #define ERRCTL_L2P 0x00800000 ··· 1428 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1429 reg_val & (1<<30) ? "secondary" : "primary", 1430 reg_val & (1<<31) ? "data" : "insn"); 1431 - printk("Error bits: %s%s%s%s%s%s%s\n", 1432 - reg_val & (1<<29) ? "ED " : "", 1433 - reg_val & (1<<28) ? "ET " : "", 1434 - reg_val & (1<<26) ? "EE " : "", 1435 - reg_val & (1<<25) ? "EB " : "", 1436 - reg_val & (1<<24) ? "EI " : "", 1437 - reg_val & (1<<23) ? "E1 " : "", 1438 - reg_val & (1<<22) ? "E0 " : ""); 1439 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1440 1441 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) ··· 1460 #endif 1461 1462 panic("Can't handle the cache error!"); 1463 } 1464 1465 /* ··· 2039 if (cpu_has_fpu && !cpu_has_nofpuex) 2040 set_except_vector(15, handle_fpe); 2041 2042 set_except_vector(22, handle_mdmx); 2043 2044 if (cpu_has_mcheck)
··· 78 extern asmlinkage void handle_ov(void); 79 extern asmlinkage void handle_tr(void); 80 extern asmlinkage void handle_fpe(void); 81 + extern asmlinkage void handle_ftlb(void); 82 extern asmlinkage void handle_mdmx(void); 83 extern asmlinkage void handle_watch(void); 84 extern asmlinkage void handle_mt(void); ··· 1080 unsigned long old_epc, old31; 1081 unsigned int opcode; 1082 unsigned int cpid; 1083 + int status, err; 1084 unsigned long __maybe_unused flags; 1085 1086 prev_state = exception_enter(); ··· 1153 1154 case 1: 1155 if (used_math()) /* Using the FPU again. */ 1156 + err = own_fpu(1); 1157 else { /* First time FPU user. */ 1158 + err = init_fpu(); 1159 set_used_math(); 1160 } 1161 1162 + if (!raw_cpu_has_fpu || err) { 1163 int sig; 1164 void __user *fault_addr = NULL; 1165 sig = fpu_emulator_cop1Handler(regs, 1166 &current->thread.fpu, 1167 0, &fault_addr); 1168 + if (!process_fpemu_return(sig, fault_addr) && !err) 1169 mt_ase_fp_affinity(); 1170 } 1171 ··· 1336 case CPU_34K: 1337 case CPU_74K: 1338 case CPU_1004K: 1339 + case CPU_INTERAPTIV: 1340 + case CPU_PROAPTIV: 1341 { 1342 #define ERRCTL_PE 0x80000000 1343 #define ERRCTL_L2P 0x00800000 ··· 1425 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1426 reg_val & (1<<30) ? "secondary" : "primary", 1427 reg_val & (1<<31) ? "data" : "insn"); 1428 + if (cpu_has_mips_r2 && 1429 + ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1430 + pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1431 + reg_val & (1<<29) ? "ED " : "", 1432 + reg_val & (1<<28) ? "ET " : "", 1433 + reg_val & (1<<27) ? "ES " : "", 1434 + reg_val & (1<<26) ? "EE " : "", 1435 + reg_val & (1<<25) ? "EB " : "", 1436 + reg_val & (1<<24) ? "EI " : "", 1437 + reg_val & (1<<23) ? "E1 " : "", 1438 + reg_val & (1<<22) ? "E0 " : ""); 1439 + } else { 1440 + pr_err("Error bits: %s%s%s%s%s%s%s\n", 1441 + reg_val & (1<<29) ? "ED " : "", 1442 + reg_val & (1<<28) ? "ET " : "", 1443 + reg_val & (1<<26) ? "EE " : "", 1444 + reg_val & (1<<25) ? "EB " : "", 1445 + reg_val & (1<<24) ? "EI " : "", 1446 + reg_val & (1<<23) ? "E1 " : "", 1447 + reg_val & (1<<22) ? "E0 " : ""); 1448 + } 1449 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1450 1451 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) ··· 1444 #endif 1445 1446 panic("Can't handle the cache error!"); 1447 + } 1448 + 1449 + asmlinkage void do_ftlb(void) 1450 + { 1451 + const int field = 2 * sizeof(unsigned long); 1452 + unsigned int reg_val; 1453 + 1454 + /* For the moment, report the problem and hang. */ 1455 + if (cpu_has_mips_r2 && 1456 + ((current_cpu_data.processor_id && 0xff0000) == PRID_COMP_MIPS)) { 1457 + pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1458 + read_c0_ecc()); 1459 + pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1460 + reg_val = read_c0_cacheerr(); 1461 + pr_err("c0_cacheerr == %08x\n", reg_val); 1462 + 1463 + if ((reg_val & 0xc0000000) == 0xc0000000) { 1464 + pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1465 + } else { 1466 + pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1467 + reg_val & (1<<30) ? "secondary" : "primary", 1468 + reg_val & (1<<31) ? "data" : "insn"); 1469 + } 1470 + } else { 1471 + pr_err("FTLB error exception\n"); 1472 + } 1473 + /* Just print the cacheerr bits for now */ 1474 + cache_parity_error(); 1475 } 1476 1477 /* ··· 1995 if (cpu_has_fpu && !cpu_has_nofpuex) 1996 set_except_vector(15, handle_fpe); 1997 1998 + set_except_vector(16, handle_ftlb); 1999 set_except_vector(22, handle_mdmx); 2000 2001 if (cpu_has_mcheck)
+180
arch/mips/kernel/vpe-cmp.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 + */ 9 + #include <linux/kernel.h> 10 + #include <linux/device.h> 11 + #include <linux/fs.h> 12 + #include <linux/slab.h> 13 + #include <linux/export.h> 14 + 15 + #include <asm/vpe.h> 16 + 17 + static int major; 18 + 19 + void cleanup_tc(struct tc *tc) 20 + { 21 + 22 + } 23 + 24 + static ssize_t store_kill(struct device *dev, struct device_attribute *attr, 25 + const char *buf, size_t len) 26 + { 27 + struct vpe *vpe = get_vpe(aprp_cpu_index()); 28 + struct vpe_notifications *notifier; 29 + 30 + list_for_each_entry(notifier, &vpe->notify, list) 31 + notifier->stop(aprp_cpu_index()); 32 + 33 + release_progmem(vpe->load_addr); 34 + vpe->state = VPE_STATE_UNUSED; 35 + 36 + return len; 37 + } 38 + static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill); 39 + 40 + static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr, 41 + char *buf) 42 + { 43 + struct vpe *vpe = get_vpe(aprp_cpu_index()); 44 + 45 + return sprintf(buf, "%d\n", vpe->ntcs); 46 + } 47 + 48 + static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr, 49 + const char *buf, size_t len) 50 + { 51 + struct vpe *vpe = get_vpe(aprp_cpu_index()); 52 + unsigned long new; 53 + int ret; 54 + 55 + ret = kstrtoul(buf, 0, &new); 56 + if (ret < 0) 57 + return ret; 58 + 59 + /* APRP can only reserve one TC in a VPE and no more. */ 60 + if (new != 1) 61 + return -EINVAL; 62 + 63 + vpe->ntcs = new; 64 + 65 + return len; 66 + } 67 + static DEVICE_ATTR_RW(ntcs); 68 + 69 + static struct attribute *vpe_attrs[] = { 70 + &dev_attr_kill.attr, 71 + &dev_attr_ntcs.attr, 72 + NULL, 73 + }; 74 + ATTRIBUTE_GROUPS(vpe); 75 + 76 + static void vpe_device_release(struct device *cd) 77 + { 78 + kfree(cd); 79 + } 80 + 81 + static struct class vpe_class = { 82 + .name = "vpe", 83 + .owner = THIS_MODULE, 84 + .dev_release = vpe_device_release, 85 + .dev_groups = vpe_groups, 86 + }; 87 + 88 + static struct device vpe_device; 89 + 90 + int __init vpe_module_init(void) 91 + { 92 + struct vpe *v = NULL; 93 + struct tc *t; 94 + int err; 95 + 96 + if (!cpu_has_mipsmt) { 97 + pr_warn("VPE loader: not a MIPS MT capable processor\n"); 98 + return -ENODEV; 99 + } 100 + 101 + if (num_possible_cpus() - aprp_cpu_index() < 1) { 102 + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" 103 + "Pass maxcpus=<n> argument as kernel argument\n"); 104 + return -ENODEV; 105 + } 106 + 107 + major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); 108 + if (major < 0) { 109 + pr_warn("VPE loader: unable to register character device\n"); 110 + return major; 111 + } 112 + 113 + err = class_register(&vpe_class); 114 + if (err) { 115 + pr_err("vpe_class registration failed\n"); 116 + goto out_chrdev; 117 + } 118 + 119 + device_initialize(&vpe_device); 120 + vpe_device.class = &vpe_class, 121 + vpe_device.parent = NULL, 122 + dev_set_name(&vpe_device, "vpe_sp"); 123 + vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); 124 + err = device_add(&vpe_device); 125 + if (err) { 126 + pr_err("Adding vpe_device failed\n"); 127 + goto out_class; 128 + } 129 + 130 + t = alloc_tc(aprp_cpu_index()); 131 + if (!t) { 132 + pr_warn("VPE: unable to allocate TC\n"); 133 + err = -ENOMEM; 134 + goto out_dev; 135 + } 136 + 137 + /* VPE */ 138 + v = alloc_vpe(aprp_cpu_index()); 139 + if (v == NULL) { 140 + pr_warn("VPE: unable to allocate VPE\n"); 141 + kfree(t); 142 + err = -ENOMEM; 143 + goto out_dev; 144 + } 145 + 146 + v->ntcs = 1; 147 + 148 + /* add the tc to the list of this vpe's tc's. */ 149 + list_add(&t->tc, &v->tc); 150 + 151 + /* TC */ 152 + t->pvpe = v; /* set the parent vpe */ 153 + 154 + return 0; 155 + 156 + out_dev: 157 + device_del(&vpe_device); 158 + 159 + out_class: 160 + class_unregister(&vpe_class); 161 + 162 + out_chrdev: 163 + unregister_chrdev(major, VPE_MODULE_NAME); 164 + 165 + return err; 166 + } 167 + 168 + void __exit vpe_module_exit(void) 169 + { 170 + struct vpe *v, *n; 171 + 172 + device_del(&vpe_device); 173 + class_unregister(&vpe_class); 174 + unregister_chrdev(major, VPE_MODULE_NAME); 175 + 176 + /* No locking needed here */ 177 + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) 178 + if (v->state != VPE_STATE_UNUSED) 179 + release_vpe(v); 180 + }
+523
arch/mips/kernel/vpe-mt.c
···
··· 1 + /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 + * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 + */ 9 + #include <linux/kernel.h> 10 + #include <linux/device.h> 11 + #include <linux/fs.h> 12 + #include <linux/slab.h> 13 + #include <linux/export.h> 14 + 15 + #include <asm/mipsregs.h> 16 + #include <asm/mipsmtregs.h> 17 + #include <asm/mips_mt.h> 18 + #include <asm/vpe.h> 19 + 20 + static int major; 21 + 22 + /* The number of TCs and VPEs physically available on the core */ 23 + static int hw_tcs, hw_vpes; 24 + 25 + /* We are prepared so configure and start the VPE... */ 26 + int vpe_run(struct vpe *v) 27 + { 28 + unsigned long flags, val, dmt_flag; 29 + struct vpe_notifications *notifier; 30 + unsigned int vpeflags; 31 + struct tc *t; 32 + 33 + /* check we are the Master VPE */ 34 + local_irq_save(flags); 35 + val = read_c0_vpeconf0(); 36 + if (!(val & VPECONF0_MVP)) { 37 + pr_warn("VPE loader: only Master VPE's are able to config MT\n"); 38 + local_irq_restore(flags); 39 + 40 + return -1; 41 + } 42 + 43 + dmt_flag = dmt(); 44 + vpeflags = dvpe(); 45 + 46 + if (list_empty(&v->tc)) { 47 + evpe(vpeflags); 48 + emt(dmt_flag); 49 + local_irq_restore(flags); 50 + 51 + pr_warn("VPE loader: No TC's associated with VPE %d\n", 52 + v->minor); 53 + 54 + return -ENOEXEC; 55 + } 56 + 57 + t = list_first_entry(&v->tc, struct tc, tc); 58 + 59 + /* Put MVPE's into 'configuration state' */ 60 + set_c0_mvpcontrol(MVPCONTROL_VPC); 61 + 62 + settc(t->index); 63 + 64 + /* should check it is halted, and not activated */ 65 + if ((read_tc_c0_tcstatus() & TCSTATUS_A) || 66 + !(read_tc_c0_tchalt() & TCHALT_H)) { 67 + evpe(vpeflags); 68 + emt(dmt_flag); 69 + local_irq_restore(flags); 70 + 71 + pr_warn("VPE loader: TC %d is already active!\n", 72 + t->index); 73 + 74 + return -ENOEXEC; 75 + } 76 + 77 + /* 78 + * Write the address we want it to start running from in the TCPC 79 + * register. 80 + */ 81 + write_tc_c0_tcrestart((unsigned long)v->__start); 82 + write_tc_c0_tccontext((unsigned long)0); 83 + 84 + /* 85 + * Mark the TC as activated, not interrupt exempt and not dynamically 86 + * allocatable 87 + */ 88 + val = read_tc_c0_tcstatus(); 89 + val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; 90 + write_tc_c0_tcstatus(val); 91 + 92 + write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); 93 + 94 + /* 95 + * The sde-kit passes 'memsize' to __start in $a3, so set something 96 + * here... Or set $a3 to zero and define DFLT_STACK_SIZE and 97 + * DFLT_HEAP_SIZE when you compile your program 98 + */ 99 + mttgpr(6, v->ntcs); 100 + mttgpr(7, physical_memsize); 101 + 102 + /* set up VPE1 */ 103 + /* 104 + * bind the TC to VPE 1 as late as possible so we only have the final 105 + * VPE registers to set up, and so an EJTAG probe can trigger on it 106 + */ 107 + write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); 108 + 109 + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); 110 + 111 + back_to_back_c0_hazard(); 112 + 113 + /* Set up the XTC bit in vpeconf0 to point at our tc */ 114 + write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) 115 + | (t->index << VPECONF0_XTC_SHIFT)); 116 + 117 + back_to_back_c0_hazard(); 118 + 119 + /* enable this VPE */ 120 + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); 121 + 122 + /* clear out any left overs from a previous program */ 123 + write_vpe_c0_status(0); 124 + write_vpe_c0_cause(0); 125 + 126 + /* take system out of configuration state */ 127 + clear_c0_mvpcontrol(MVPCONTROL_VPC); 128 + 129 + /* 130 + * SMTC/SMVP kernels manage VPE enable independently, 131 + * but uniprocessor kernels need to turn it on, even 132 + * if that wasn't the pre-dvpe() state. 133 + */ 134 + #ifdef CONFIG_SMP 135 + evpe(vpeflags); 136 + #else 137 + evpe(EVPE_ENABLE); 138 + #endif 139 + emt(dmt_flag); 140 + local_irq_restore(flags); 141 + 142 + list_for_each_entry(notifier, &v->notify, list) 143 + notifier->start(VPE_MODULE_MINOR); 144 + 145 + return 0; 146 + } 147 + 148 + void cleanup_tc(struct tc *tc) 149 + { 150 + unsigned long flags; 151 + unsigned int mtflags, vpflags; 152 + int tmp; 153 + 154 + local_irq_save(flags); 155 + mtflags = dmt(); 156 + vpflags = dvpe(); 157 + /* Put MVPE's into 'configuration state' */ 158 + set_c0_mvpcontrol(MVPCONTROL_VPC); 159 + 160 + settc(tc->index); 161 + tmp = read_tc_c0_tcstatus(); 162 + 163 + /* mark not allocated and not dynamically allocatable */ 164 + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 165 + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 166 + write_tc_c0_tcstatus(tmp); 167 + 168 + write_tc_c0_tchalt(TCHALT_H); 169 + mips_ihb(); 170 + 171 + clear_c0_mvpcontrol(MVPCONTROL_VPC); 172 + evpe(vpflags); 173 + emt(mtflags); 174 + local_irq_restore(flags); 175 + } 176 + 177 + /* module wrapper entry points */ 178 + /* give me a vpe */ 179 + void *vpe_alloc(void) 180 + { 181 + int i; 182 + struct vpe *v; 183 + 184 + /* find a vpe */ 185 + for (i = 1; i < MAX_VPES; i++) { 186 + v = get_vpe(i); 187 + if (v != NULL) { 188 + v->state = VPE_STATE_INUSE; 189 + return v; 190 + } 191 + } 192 + return NULL; 193 + } 194 + EXPORT_SYMBOL(vpe_alloc); 195 + 196 + /* start running from here */ 197 + int vpe_start(void *vpe, unsigned long start) 198 + { 199 + struct vpe *v = vpe; 200 + 201 + v->__start = start; 202 + return vpe_run(v); 203 + } 204 + EXPORT_SYMBOL(vpe_start); 205 + 206 + /* halt it for now */ 207 + int vpe_stop(void *vpe) 208 + { 209 + struct vpe *v = vpe; 210 + struct tc *t; 211 + unsigned int evpe_flags; 212 + 213 + evpe_flags = dvpe(); 214 + 215 + t = list_entry(v->tc.next, struct tc, tc); 216 + if (t != NULL) { 217 + settc(t->index); 218 + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); 219 + } 220 + 221 + evpe(evpe_flags); 222 + 223 + return 0; 224 + } 225 + EXPORT_SYMBOL(vpe_stop); 226 + 227 + /* I've done with it thank you */ 228 + int vpe_free(void *vpe) 229 + { 230 + struct vpe *v = vpe; 231 + struct tc *t; 232 + unsigned int evpe_flags; 233 + 234 + t = list_entry(v->tc.next, struct tc, tc); 235 + if (t == NULL) 236 + return -ENOEXEC; 237 + 238 + evpe_flags = dvpe(); 239 + 240 + /* Put MVPE's into 'configuration state' */ 241 + set_c0_mvpcontrol(MVPCONTROL_VPC); 242 + 243 + settc(t->index); 244 + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); 245 + 246 + /* halt the TC */ 247 + write_tc_c0_tchalt(TCHALT_H); 248 + mips_ihb(); 249 + 250 + /* mark the TC unallocated */ 251 + write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); 252 + 253 + v->state = VPE_STATE_UNUSED; 254 + 255 + clear_c0_mvpcontrol(MVPCONTROL_VPC); 256 + evpe(evpe_flags); 257 + 258 + return 0; 259 + } 260 + EXPORT_SYMBOL(vpe_free); 261 + 262 + static ssize_t store_kill(struct device *dev, struct device_attribute *attr, 263 + const char *buf, size_t len) 264 + { 265 + struct vpe *vpe = get_vpe(aprp_cpu_index()); 266 + struct vpe_notifications *notifier; 267 + 268 + list_for_each_entry(notifier, &vpe->notify, list) 269 + notifier->stop(aprp_cpu_index()); 270 + 271 + release_progmem(vpe->load_addr); 272 + cleanup_tc(get_tc(aprp_cpu_index())); 273 + vpe_stop(vpe); 274 + vpe_free(vpe); 275 + 276 + return len; 277 + } 278 + static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill); 279 + 280 + static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr, 281 + char *buf) 282 + { 283 + struct vpe *vpe = get_vpe(aprp_cpu_index()); 284 + 285 + return sprintf(buf, "%d\n", vpe->ntcs); 286 + } 287 + 288 + static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr, 289 + const char *buf, size_t len) 290 + { 291 + struct vpe *vpe = get_vpe(aprp_cpu_index()); 292 + unsigned long new; 293 + int ret; 294 + 295 + ret = kstrtoul(buf, 0, &new); 296 + if (ret < 0) 297 + return ret; 298 + 299 + if (new == 0 || new > (hw_tcs - aprp_cpu_index())) 300 + return -EINVAL; 301 + 302 + vpe->ntcs = new; 303 + 304 + return len; 305 + } 306 + static DEVICE_ATTR_RW(ntcs); 307 + 308 + static struct attribute *vpe_attrs[] = { 309 + &dev_attr_kill.attr, 310 + &dev_attr_ntcs.attr, 311 + NULL, 312 + }; 313 + ATTRIBUTE_GROUPS(vpe); 314 + 315 + static void vpe_device_release(struct device *cd) 316 + { 317 + kfree(cd); 318 + } 319 + 320 + static struct class vpe_class = { 321 + .name = "vpe", 322 + .owner = THIS_MODULE, 323 + .dev_release = vpe_device_release, 324 + .dev_groups = vpe_groups, 325 + }; 326 + 327 + static struct device vpe_device; 328 + 329 + int __init vpe_module_init(void) 330 + { 331 + unsigned int mtflags, vpflags; 332 + unsigned long flags, val; 333 + struct vpe *v = NULL; 334 + struct tc *t; 335 + int tc, err; 336 + 337 + if (!cpu_has_mipsmt) { 338 + pr_warn("VPE loader: not a MIPS MT capable processor\n"); 339 + return -ENODEV; 340 + } 341 + 342 + if (vpelimit == 0) { 343 + pr_warn("No VPEs reserved for AP/SP, not initialize VPE loader\n" 344 + "Pass maxvpes=<n> argument as kernel argument\n"); 345 + 346 + return -ENODEV; 347 + } 348 + 349 + if (aprp_cpu_index() == 0) { 350 + pr_warn("No TCs reserved for AP/SP, not initialize VPE loader\n" 351 + "Pass maxtcs=<n> argument as kernel argument\n"); 352 + 353 + return -ENODEV; 354 + } 355 + 356 + major = register_chrdev(0, VPE_MODULE_NAME, &vpe_fops); 357 + if (major < 0) { 358 + pr_warn("VPE loader: unable to register character device\n"); 359 + return major; 360 + } 361 + 362 + err = class_register(&vpe_class); 363 + if (err) { 364 + pr_err("vpe_class registration failed\n"); 365 + goto out_chrdev; 366 + } 367 + 368 + device_initialize(&vpe_device); 369 + vpe_device.class = &vpe_class, 370 + vpe_device.parent = NULL, 371 + dev_set_name(&vpe_device, "vpe1"); 372 + vpe_device.devt = MKDEV(major, VPE_MODULE_MINOR); 373 + err = device_add(&vpe_device); 374 + if (err) { 375 + pr_err("Adding vpe_device failed\n"); 376 + goto out_class; 377 + } 378 + 379 + local_irq_save(flags); 380 + mtflags = dmt(); 381 + vpflags = dvpe(); 382 + 383 + /* Put MVPE's into 'configuration state' */ 384 + set_c0_mvpcontrol(MVPCONTROL_VPC); 385 + 386 + val = read_c0_mvpconf0(); 387 + hw_tcs = (val & MVPCONF0_PTC) + 1; 388 + hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 389 + 390 + for (tc = aprp_cpu_index(); tc < hw_tcs; tc++) { 391 + /* 392 + * Must re-enable multithreading temporarily or in case we 393 + * reschedule send IPIs or similar we might hang. 394 + */ 395 + clear_c0_mvpcontrol(MVPCONTROL_VPC); 396 + evpe(vpflags); 397 + emt(mtflags); 398 + local_irq_restore(flags); 399 + t = alloc_tc(tc); 400 + if (!t) { 401 + err = -ENOMEM; 402 + goto out_dev; 403 + } 404 + 405 + local_irq_save(flags); 406 + mtflags = dmt(); 407 + vpflags = dvpe(); 408 + set_c0_mvpcontrol(MVPCONTROL_VPC); 409 + 410 + /* VPE's */ 411 + if (tc < hw_tcs) { 412 + settc(tc); 413 + 414 + v = alloc_vpe(tc); 415 + if (v == NULL) { 416 + pr_warn("VPE: unable to allocate VPE\n"); 417 + goto out_reenable; 418 + } 419 + 420 + v->ntcs = hw_tcs - aprp_cpu_index(); 421 + 422 + /* add the tc to the list of this vpe's tc's. */ 423 + list_add(&t->tc, &v->tc); 424 + 425 + /* deactivate all but vpe0 */ 426 + if (tc >= aprp_cpu_index()) { 427 + unsigned long tmp = read_vpe_c0_vpeconf0(); 428 + 429 + tmp &= ~VPECONF0_VPA; 430 + 431 + /* master VPE */ 432 + tmp |= VPECONF0_MVP; 433 + write_vpe_c0_vpeconf0(tmp); 434 + } 435 + 436 + /* disable multi-threading with TC's */ 437 + write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & 438 + ~VPECONTROL_TE); 439 + 440 + if (tc >= vpelimit) { 441 + /* 442 + * Set config to be the same as vpe0, 443 + * particularly kseg0 coherency alg 444 + */ 445 + write_vpe_c0_config(read_c0_config()); 446 + } 447 + } 448 + 449 + /* TC's */ 450 + t->pvpe = v; /* set the parent vpe */ 451 + 452 + if (tc >= aprp_cpu_index()) { 453 + unsigned long tmp; 454 + 455 + settc(tc); 456 + 457 + /* Any TC that is bound to VPE0 gets left as is - in 458 + * case we are running SMTC on VPE0. A TC that is bound 459 + * to any other VPE gets bound to VPE0, ideally I'd like 460 + * to make it homeless but it doesn't appear to let me 461 + * bind a TC to a non-existent VPE. Which is perfectly 462 + * reasonable. 463 + * 464 + * The (un)bound state is visible to an EJTAG probe so 465 + * may notify GDB... 466 + */ 467 + tmp = read_tc_c0_tcbind(); 468 + if (tmp & TCBIND_CURVPE) { 469 + /* tc is bound >vpe0 */ 470 + write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); 471 + 472 + t->pvpe = get_vpe(0); /* set the parent vpe */ 473 + } 474 + 475 + /* halt the TC */ 476 + write_tc_c0_tchalt(TCHALT_H); 477 + mips_ihb(); 478 + 479 + tmp = read_tc_c0_tcstatus(); 480 + 481 + /* mark not activated and not dynamically allocatable */ 482 + tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 483 + tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 484 + write_tc_c0_tcstatus(tmp); 485 + } 486 + } 487 + 488 + out_reenable: 489 + /* release config state */ 490 + clear_c0_mvpcontrol(MVPCONTROL_VPC); 491 + 492 + evpe(vpflags); 493 + emt(mtflags); 494 + local_irq_restore(flags); 495 + 496 + return 0; 497 + 498 + out_dev: 499 + device_del(&vpe_device); 500 + 501 + out_class: 502 + class_unregister(&vpe_class); 503 + 504 + out_chrdev: 505 + unregister_chrdev(major, VPE_MODULE_NAME); 506 + 507 + return err; 508 + } 509 + 510 + void __exit vpe_module_exit(void) 511 + { 512 + struct vpe *v, *n; 513 + 514 + device_del(&vpe_device); 515 + class_unregister(&vpe_class); 516 + unregister_chrdev(major, VPE_MODULE_NAME); 517 + 518 + /* No locking needed here */ 519 + list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { 520 + if (v->state != VPE_STATE_UNUSED) 521 + release_vpe(v); 522 + } 523 + }
+124 -758
arch/mips/kernel/vpe.c
··· 1 /* 2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 3 * 4 - * This program is free software; you can distribute it and/or modify it 5 - * under the terms of the GNU General Public License (Version 2) as 6 - * published by the Free Software Foundation. 7 - * 8 - * This program is distributed in the hope it will be useful, but WITHOUT 9 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 - * for more details. 12 - * 13 - * You should have received a copy of the GNU General Public License along 14 - * with this program; if not, write to the Free Software Foundation, Inc., 15 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 16 - */ 17 - 18 - /* 19 - * VPE support module 20 - * 21 - * Provides support for loading a MIPS SP program on VPE1. 22 - * The SP environment is rather simple, no tlb's. It needs to be relocatable 23 - * (or partially linked). You should initialise your stack in the startup 24 - * code. This loader looks for the symbol __start and sets up 25 - * execution to resume from there. The MIPS SDE kit contains suitable examples. 26 - * 27 - * To load and run, simply cat a SP 'program file' to /dev/vpe1. 28 - * i.e cat spapp >/dev/vpe1. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/device.h> 32 #include <linux/fs.h> 33 #include <linux/init.h> 34 - #include <asm/uaccess.h> 35 #include <linux/slab.h> 36 #include <linux/list.h> 37 #include <linux/vmalloc.h> ··· 31 #include <asm/mipsmtregs.h> 32 #include <asm/cacheflush.h> 33 #include <linux/atomic.h> 34 - #include <asm/cpu.h> 35 #include <asm/mips_mt.h> 36 #include <asm/processor.h> 37 #include <asm/vpe.h> 38 - 39 - typedef void *vpe_handle; 40 41 #ifndef ARCH_SHF_SMALL 42 #define ARCH_SHF_SMALL 0 ··· 42 /* If this is set, the section belongs in the init part of the module */ 43 #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) 44 45 - /* 46 - * The number of TCs and VPEs physically available on the core 47 - */ 48 - static int hw_tcs, hw_vpes; 49 - static char module_name[] = "vpe"; 50 - static int major; 51 - static const int minor = 1; /* fixed for now */ 52 - 53 - /* grab the likely amount of memory we will need. */ 54 - #ifdef CONFIG_MIPS_VPE_LOADER_TOM 55 - #define P_SIZE (2 * 1024 * 1024) 56 - #else 57 - /* add an overhead to the max kmalloc size for non-striped symbols/etc */ 58 - #define P_SIZE (256 * 1024) 59 - #endif 60 - 61 - extern unsigned long physical_memsize; 62 - 63 - #define MAX_VPES 16 64 - #define VPE_PATH_MAX 256 65 - 66 - enum vpe_state { 67 - VPE_STATE_UNUSED = 0, 68 - VPE_STATE_INUSE, 69 - VPE_STATE_RUNNING 70 - }; 71 - 72 - enum tc_state { 73 - TC_STATE_UNUSED = 0, 74 - TC_STATE_INUSE, 75 - TC_STATE_RUNNING, 76 - TC_STATE_DYNAMIC 77 - }; 78 - 79 - struct vpe { 80 - enum vpe_state state; 81 - 82 - /* (device) minor associated with this vpe */ 83 - int minor; 84 - 85 - /* elfloader stuff */ 86 - void *load_addr; 87 - unsigned long len; 88 - char *pbuffer; 89 - unsigned long plen; 90 - char cwd[VPE_PATH_MAX]; 91 - 92 - unsigned long __start; 93 - 94 - /* tc's associated with this vpe */ 95 - struct list_head tc; 96 - 97 - /* The list of vpe's */ 98 - struct list_head list; 99 - 100 - /* shared symbol address */ 101 - void *shared_ptr; 102 - 103 - /* the list of who wants to know when something major happens */ 104 - struct list_head notify; 105 - 106 - unsigned int ntcs; 107 - }; 108 - 109 - struct tc { 110 - enum tc_state state; 111 - int index; 112 - 113 - struct vpe *pvpe; /* parent VPE */ 114 - struct list_head tc; /* The list of TC's with this VPE */ 115 - struct list_head list; /* The global list of tc's */ 116 - }; 117 - 118 - struct { 119 - spinlock_t vpe_list_lock; 120 - struct list_head vpe_list; /* Virtual processing elements */ 121 - spinlock_t tc_list_lock; 122 - struct list_head tc_list; /* Thread contexts */ 123 - } vpecontrol = { 124 .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), 125 .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), 126 .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), 127 .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) 128 }; 129 130 - static void release_progmem(void *ptr); 131 - 132 /* get the vpe associated with this minor */ 133 - static struct vpe *get_vpe(int minor) 134 { 135 struct vpe *res, *v; 136 ··· 60 res = NULL; 61 spin_lock(&vpecontrol.vpe_list_lock); 62 list_for_each_entry(v, &vpecontrol.vpe_list, list) { 63 - if (v->minor == minor) { 64 res = v; 65 break; 66 } ··· 71 } 72 73 /* get the vpe associated with this minor */ 74 - static struct tc *get_tc(int index) 75 { 76 struct tc *res, *t; 77 ··· 89 } 90 91 /* allocate a vpe and associate it with this minor (or index) */ 92 - static struct vpe *alloc_vpe(int minor) 93 { 94 struct vpe *v; 95 96 - if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) 97 - return NULL; 98 99 INIT_LIST_HEAD(&v->tc); 100 spin_lock(&vpecontrol.vpe_list_lock); ··· 103 spin_unlock(&vpecontrol.vpe_list_lock); 104 105 INIT_LIST_HEAD(&v->notify); 106 - v->minor = minor; 107 108 return v; 109 } 110 111 /* allocate a tc. At startup only tc0 is running, all other can be halted. */ 112 - static struct tc *alloc_tc(int index) 113 { 114 struct tc *tc; 115 116 - if ((tc = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) 117 goto out; 118 119 INIT_LIST_HEAD(&tc->tc); ··· 130 } 131 132 /* clean up and free everything */ 133 - static void release_vpe(struct vpe *v) 134 { 135 list_del(&v->list); 136 if (v->load_addr) ··· 138 kfree(v); 139 } 140 141 - static void __maybe_unused dump_mtregs(void) 142 - { 143 - unsigned long val; 144 - 145 - val = read_c0_config3(); 146 - printk("config3 0x%lx MT %ld\n", val, 147 - (val & CONFIG3_MT) >> CONFIG3_MT_SHIFT); 148 - 149 - val = read_c0_mvpcontrol(); 150 - printk("MVPControl 0x%lx, STLB %ld VPC %ld EVP %ld\n", val, 151 - (val & MVPCONTROL_STLB) >> MVPCONTROL_STLB_SHIFT, 152 - (val & MVPCONTROL_VPC) >> MVPCONTROL_VPC_SHIFT, 153 - (val & MVPCONTROL_EVP)); 154 - 155 - val = read_c0_mvpconf0(); 156 - printk("mvpconf0 0x%lx, PVPE %ld PTC %ld M %ld\n", val, 157 - (val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT, 158 - val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT); 159 - } 160 - 161 - /* Find some VPE program space */ 162 - static void *alloc_progmem(unsigned long len) 163 { 164 void *addr; 165 ··· 158 return addr; 159 } 160 161 - static void release_progmem(void *ptr) 162 { 163 #ifndef CONFIG_MIPS_VPE_LOADER_TOM 164 kfree(ptr); ··· 166 } 167 168 /* Update size with this section: return offset. */ 169 - static long get_offset(unsigned long *size, Elf_Shdr * sechdr) 170 { 171 long ret; 172 ··· 179 might -- code, read-only data, read-write data, small data. Tally 180 sizes, and place the offsets into sh_entsize fields: high bit means it 181 belongs in init. */ 182 - static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, 183 - Elf_Shdr * sechdrs, const char *secstrings) 184 { 185 static unsigned long const masks[][2] = { 186 /* NOTE: all executable code must be the first section ··· 200 for (i = 0; i < hdr->e_shnum; ++i) { 201 Elf_Shdr *s = &sechdrs[i]; 202 203 - // || strncmp(secstrings + s->sh_name, ".init", 5) == 0) 204 if ((s->sh_flags & masks[m][0]) != masks[m][0] 205 || (s->sh_flags & masks[m][1]) 206 || s->sh_entsize != ~0UL) ··· 213 214 } 215 } 216 - 217 218 /* from module-elf32.c, but subverted a little */ 219 ··· 236 { 237 int rel; 238 239 - if( !(*location & 0xffff) ) { 240 rel = (int)v - gp_addr; 241 - } 242 - else { 243 /* .sbss + gp(relative) + offset */ 244 /* kludge! */ 245 rel = (int)(short)((int)v + gp_offs + 246 (int)(short)(*location & 0xffff) - gp_addr); 247 } 248 249 - if( (rel > 32768) || (rel < -32768) ) { 250 - printk(KERN_DEBUG "VPE loader: apply_r_mips_gprel16: " 251 - "relative address 0x%x out of range of gp register\n", 252 - rel); 253 return -ENOEXEC; 254 } 255 ··· 261 { 262 int rel; 263 rel = (((unsigned int)v - (unsigned int)location)); 264 - rel >>= 2; // because the offset is in _instructions_ not bytes. 265 - rel -= 1; // and one instruction less due to the branch delay slot. 266 267 - if( (rel > 32768) || (rel < -32768) ) { 268 - printk(KERN_DEBUG "VPE loader: " 269 - "apply_r_mips_pc16: relative address out of range 0x%x\n", rel); 270 return -ENOEXEC; 271 } 272 ··· 287 Elf32_Addr v) 288 { 289 if (v % 4) { 290 - printk(KERN_DEBUG "VPE loader: apply_r_mips_26 " 291 - " unaligned relocation\n"); 292 return -ENOEXEC; 293 } 294 ··· 318 * the carry we need to add. Save the information, and let LO16 do the 319 * actual relocation. 320 */ 321 - n = kmalloc(sizeof *n, GFP_KERNEL); 322 if (!n) 323 return -ENOMEM; 324 ··· 350 * The value for the HI16 had best be the same. 351 */ 352 if (v != l->value) { 353 - printk(KERN_DEBUG "VPE loader: " 354 - "apply_r_mips_lo16/hi16: \t" 355 - "inconsistent value information\n"); 356 goto out_free; 357 } 358 ··· 446 + ELF32_R_SYM(r_info); 447 448 if (!sym->st_value) { 449 - printk(KERN_DEBUG "%s: undefined weak symbol %s\n", 450 - me->name, strtab + sym->st_name); 451 /* just print the warning, dont barf */ 452 } 453 454 v = sym->st_value; 455 456 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); 457 - if( res ) { 458 char *r = rstrs[ELF32_R_TYPE(r_info)]; 459 - printk(KERN_WARNING "VPE loader: .text+0x%x " 460 - "relocation type %s for symbol \"%s\" failed\n", 461 - rel[i].r_offset, r ? r : "UNKNOWN", 462 - strtab + sym->st_name); 463 return res; 464 } 465 } ··· 473 } 474 /* end module-elf32.c */ 475 476 - 477 - 478 /* Change all symbols so that sh_value encodes the pointer directly. */ 479 - static void simplify_symbols(Elf_Shdr * sechdrs, 480 unsigned int symindex, 481 const char *strtab, 482 const char *secstrings, ··· 515 break; 516 517 case SHN_MIPS_SCOMMON: 518 - printk(KERN_DEBUG "simplify_symbols: ignoring SHN_MIPS_SCOMMON " 519 - "symbol <%s> st_shndx %d\n", strtab + sym[i].st_name, 520 - sym[i].st_shndx); 521 - // .sbss section 522 break; 523 524 default: 525 secbase = sechdrs[sym[i].st_shndx].sh_addr; 526 527 - if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0) { 528 save_gp_address(secbase, sym[i].st_value); 529 - } 530 531 sym[i].st_value += secbase; 532 break; ··· 533 } 534 535 #ifdef DEBUG_ELFLOADER 536 - static void dump_elfsymbols(Elf_Shdr * sechdrs, unsigned int symindex, 537 const char *strtab, struct module *mod) 538 { 539 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; 540 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); 541 542 - printk(KERN_DEBUG "dump_elfsymbols: n %d\n", n); 543 for (i = 1; i < n; i++) { 544 - printk(KERN_DEBUG " i %d name <%s> 0x%x\n", i, 545 - strtab + sym[i].st_name, sym[i].st_value); 546 } 547 } 548 #endif 549 550 - /* We are prepared so configure and start the VPE... */ 551 - static int vpe_run(struct vpe * v) 552 - { 553 - unsigned long flags, val, dmt_flag; 554 - struct vpe_notifications *n; 555 - unsigned int vpeflags; 556 - struct tc *t; 557 - 558 - /* check we are the Master VPE */ 559 - local_irq_save(flags); 560 - val = read_c0_vpeconf0(); 561 - if (!(val & VPECONF0_MVP)) { 562 - printk(KERN_WARNING 563 - "VPE loader: only Master VPE's are allowed to configure MT\n"); 564 - local_irq_restore(flags); 565 - 566 - return -1; 567 - } 568 - 569 - dmt_flag = dmt(); 570 - vpeflags = dvpe(); 571 - 572 - if (list_empty(&v->tc)) { 573 - evpe(vpeflags); 574 - emt(dmt_flag); 575 - local_irq_restore(flags); 576 - 577 - printk(KERN_WARNING 578 - "VPE loader: No TC's associated with VPE %d\n", 579 - v->minor); 580 - 581 - return -ENOEXEC; 582 - } 583 - 584 - t = list_first_entry(&v->tc, struct tc, tc); 585 - 586 - /* Put MVPE's into 'configuration state' */ 587 - set_c0_mvpcontrol(MVPCONTROL_VPC); 588 - 589 - settc(t->index); 590 - 591 - /* should check it is halted, and not activated */ 592 - if ((read_tc_c0_tcstatus() & TCSTATUS_A) || !(read_tc_c0_tchalt() & TCHALT_H)) { 593 - evpe(vpeflags); 594 - emt(dmt_flag); 595 - local_irq_restore(flags); 596 - 597 - printk(KERN_WARNING "VPE loader: TC %d is already active!\n", 598 - t->index); 599 - 600 - return -ENOEXEC; 601 - } 602 - 603 - /* Write the address we want it to start running from in the TCPC register. */ 604 - write_tc_c0_tcrestart((unsigned long)v->__start); 605 - write_tc_c0_tccontext((unsigned long)0); 606 - 607 - /* 608 - * Mark the TC as activated, not interrupt exempt and not dynamically 609 - * allocatable 610 - */ 611 - val = read_tc_c0_tcstatus(); 612 - val = (val & ~(TCSTATUS_DA | TCSTATUS_IXMT)) | TCSTATUS_A; 613 - write_tc_c0_tcstatus(val); 614 - 615 - write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); 616 - 617 - /* 618 - * The sde-kit passes 'memsize' to __start in $a3, so set something 619 - * here... Or set $a3 to zero and define DFLT_STACK_SIZE and 620 - * DFLT_HEAP_SIZE when you compile your program 621 - */ 622 - mttgpr(6, v->ntcs); 623 - mttgpr(7, physical_memsize); 624 - 625 - /* set up VPE1 */ 626 - /* 627 - * bind the TC to VPE 1 as late as possible so we only have the final 628 - * VPE registers to set up, and so an EJTAG probe can trigger on it 629 - */ 630 - write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); 631 - 632 - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~(VPECONF0_VPA)); 633 - 634 - back_to_back_c0_hazard(); 635 - 636 - /* Set up the XTC bit in vpeconf0 to point at our tc */ 637 - write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC)) 638 - | (t->index << VPECONF0_XTC_SHIFT)); 639 - 640 - back_to_back_c0_hazard(); 641 - 642 - /* enable this VPE */ 643 - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); 644 - 645 - /* clear out any left overs from a previous program */ 646 - write_vpe_c0_status(0); 647 - write_vpe_c0_cause(0); 648 - 649 - /* take system out of configuration state */ 650 - clear_c0_mvpcontrol(MVPCONTROL_VPC); 651 - 652 - /* 653 - * SMTC/SMVP kernels manage VPE enable independently, 654 - * but uniprocessor kernels need to turn it on, even 655 - * if that wasn't the pre-dvpe() state. 656 - */ 657 - #ifdef CONFIG_SMP 658 - evpe(vpeflags); 659 - #else 660 - evpe(EVPE_ENABLE); 661 - #endif 662 - emt(dmt_flag); 663 - local_irq_restore(flags); 664 - 665 - list_for_each_entry(n, &v->notify, list) 666 - n->start(minor); 667 - 668 - return 0; 669 - } 670 - 671 - static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, 672 unsigned int symindex, const char *strtab, 673 struct module *mod) 674 { ··· 555 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); 556 557 for (i = 1; i < n; i++) { 558 - if (strcmp(strtab + sym[i].st_name, "__start") == 0) { 559 v->__start = sym[i].st_value; 560 - } 561 562 - if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) { 563 v->shared_ptr = (void *)sym[i].st_value; 564 - } 565 } 566 567 - if ( (v->__start == 0) || (v->shared_ptr == NULL)) 568 return -1; 569 570 return 0; ··· 573 * contents of the program (p)buffer performing relocatations/etc, free's it 574 * when finished. 575 */ 576 - static int vpe_elfload(struct vpe * v) 577 { 578 Elf_Ehdr *hdr; 579 Elf_Shdr *sechdrs; 580 long err = 0; 581 char *secstrings, *strtab = NULL; 582 unsigned int len, i, symindex = 0, strindex = 0, relocate = 0; 583 - struct module mod; // so we can re-use the relocations code 584 585 memset(&mod, 0, sizeof(struct module)); 586 strcpy(mod.name, "VPE loader"); ··· 594 || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) 595 || !elf_check_arch(hdr) 596 || hdr->e_shentsize != sizeof(*sechdrs)) { 597 - printk(KERN_WARNING 598 - "VPE loader: program wrong arch or weird elf version\n"); 599 600 return -ENOEXEC; 601 } ··· 603 relocate = 1; 604 605 if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { 606 - printk(KERN_ERR "VPE loader: program length %u truncated\n", 607 - len); 608 609 return -ENOEXEC; 610 } ··· 618 619 if (relocate) { 620 for (i = 1; i < hdr->e_shnum; i++) { 621 - if (sechdrs[i].sh_type != SHT_NOBITS 622 - && len < sechdrs[i].sh_offset + sechdrs[i].sh_size) { 623 - printk(KERN_ERR "VPE program length %u truncated\n", 624 len); 625 return -ENOEXEC; 626 } 627 628 /* Mark all sections sh_addr with their address in the 629 temporary image. */ 630 - sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 631 632 /* Internal symbols and strings. */ 633 if (sechdrs[i].sh_type == SHT_SYMTAB) { 634 symindex = i; 635 strindex = sechdrs[i].sh_link; 636 - strtab = (char *)hdr + sechdrs[strindex].sh_offset; 637 } 638 } 639 layout_sections(&mod, hdr, sechdrs, secstrings); ··· 662 /* Update sh_addr to point to copy in image. */ 663 sechdrs[i].sh_addr = (unsigned long)dest; 664 665 - printk(KERN_DEBUG " section sh_name %s sh_addr 0x%x\n", 666 - secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr); 667 } 668 669 /* Fix up syms, so that st_value is a pointer to location. */ ··· 685 continue; 686 687 if (sechdrs[i].sh_type == SHT_REL) 688 - err = apply_relocations(sechdrs, strtab, symindex, i, 689 - &mod); 690 else if (sechdrs[i].sh_type == SHT_RELA) 691 - err = apply_relocate_add(sechdrs, strtab, symindex, i, 692 - &mod); 693 if (err < 0) 694 return err; 695 696 } 697 } else { 698 - struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff); 699 700 for (i = 0; i < hdr->e_phnum; i++) { 701 if (phdr->p_type == PT_LOAD) { ··· 714 if (sechdrs[i].sh_type == SHT_SYMTAB) { 715 symindex = i; 716 strindex = sechdrs[i].sh_link; 717 - strtab = (char *)hdr + sechdrs[strindex].sh_offset; 718 719 - /* mark the symtab's address for when we try to find the 720 - magic symbols */ 721 - sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 722 } 723 } 724 } ··· 733 734 if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { 735 if (v->__start == 0) { 736 - printk(KERN_WARNING "VPE loader: program does not contain " 737 - "a __start symbol\n"); 738 return -ENOEXEC; 739 } 740 741 if (v->shared_ptr == NULL) 742 - printk(KERN_WARNING "VPE loader: " 743 - "program does not contain vpe_shared symbol.\n" 744 - " Unable to use AMVP (AP/SP) facilities.\n"); 745 } 746 747 - printk(" elf loaded\n"); 748 return 0; 749 - } 750 - 751 - static void cleanup_tc(struct tc *tc) 752 - { 753 - unsigned long flags; 754 - unsigned int mtflags, vpflags; 755 - int tmp; 756 - 757 - local_irq_save(flags); 758 - mtflags = dmt(); 759 - vpflags = dvpe(); 760 - /* Put MVPE's into 'configuration state' */ 761 - set_c0_mvpcontrol(MVPCONTROL_VPC); 762 - 763 - settc(tc->index); 764 - tmp = read_tc_c0_tcstatus(); 765 - 766 - /* mark not allocated and not dynamically allocatable */ 767 - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 768 - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 769 - write_tc_c0_tcstatus(tmp); 770 - 771 - write_tc_c0_tchalt(TCHALT_H); 772 - mips_ihb(); 773 - 774 - /* bind it to anything other than VPE1 */ 775 - // write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE 776 - 777 - clear_c0_mvpcontrol(MVPCONTROL_VPC); 778 - evpe(vpflags); 779 - emt(mtflags); 780 - local_irq_restore(flags); 781 } 782 783 static int getcwd(char *buff, int size) ··· 765 static int vpe_open(struct inode *inode, struct file *filp) 766 { 767 enum vpe_state state; 768 - struct vpe_notifications *not; 769 struct vpe *v; 770 int ret; 771 772 - if (minor != iminor(inode)) { 773 /* assume only 1 device at the moment. */ 774 - pr_warning("VPE loader: only vpe1 is supported\n"); 775 776 return -ENODEV; 777 } 778 779 - if ((v = get_vpe(tclimit)) == NULL) { 780 - pr_warning("VPE loader: unable to get vpe\n"); 781 782 return -ENODEV; 783 } 784 785 state = xchg(&v->state, VPE_STATE_INUSE); 786 if (state != VPE_STATE_UNUSED) { 787 - printk(KERN_DEBUG "VPE loader: tc in use dumping regs\n"); 788 789 - list_for_each_entry(not, &v->notify, list) { 790 - not->stop(tclimit); 791 - } 792 793 release_progmem(v->load_addr); 794 - cleanup_tc(get_tc(tclimit)); 795 } 796 797 /* this of-course trashes what was there before... */ 798 v->pbuffer = vmalloc(P_SIZE); 799 if (!v->pbuffer) { 800 - pr_warning("VPE loader: unable to allocate memory\n"); 801 return -ENOMEM; 802 } 803 v->plen = P_SIZE; ··· 807 v->cwd[0] = 0; 808 ret = getcwd(v->cwd, VPE_PATH_MAX); 809 if (ret < 0) 810 - printk(KERN_WARNING "VPE loader: open, getcwd returned %d\n", ret); 811 812 v->shared_ptr = NULL; 813 v->__start = 0; ··· 821 Elf_Ehdr *hdr; 822 int ret = 0; 823 824 - v = get_vpe(tclimit); 825 if (v == NULL) 826 return -ENODEV; 827 828 hdr = (Elf_Ehdr *) v->pbuffer; 829 if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { 830 - if (vpe_elfload(v) >= 0) { 831 vpe_run(v); 832 } else { 833 - printk(KERN_WARNING "VPE loader: ELF load failed.\n"); 834 ret = -ENOEXEC; 835 } 836 } else { 837 - printk(KERN_WARNING "VPE loader: only elf files are supported\n"); 838 ret = -ENOEXEC; 839 } 840 ··· 852 return ret; 853 } 854 855 - static ssize_t vpe_write(struct file *file, const char __user * buffer, 856 - size_t count, loff_t * ppos) 857 { 858 size_t ret = count; 859 struct vpe *v; 860 861 - if (iminor(file_inode(file)) != minor) 862 return -ENODEV; 863 864 - v = get_vpe(tclimit); 865 if (v == NULL) 866 return -ENODEV; 867 868 if ((count + v->len) > v->plen) { 869 - printk(KERN_WARNING 870 - "VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); 871 return -ENOMEM; 872 } 873 ··· 879 return ret; 880 } 881 882 - static const struct file_operations vpe_fops = { 883 .owner = THIS_MODULE, 884 .open = vpe_open, 885 .release = vpe_release, ··· 887 .llseek = noop_llseek, 888 }; 889 890 - /* module wrapper entry points */ 891 - /* give me a vpe */ 892 - vpe_handle vpe_alloc(void) 893 - { 894 - int i; 895 - struct vpe *v; 896 - 897 - /* find a vpe */ 898 - for (i = 1; i < MAX_VPES; i++) { 899 - if ((v = get_vpe(i)) != NULL) { 900 - v->state = VPE_STATE_INUSE; 901 - return v; 902 - } 903 - } 904 - return NULL; 905 - } 906 - 907 - EXPORT_SYMBOL(vpe_alloc); 908 - 909 - /* start running from here */ 910 - int vpe_start(vpe_handle vpe, unsigned long start) 911 - { 912 - struct vpe *v = vpe; 913 - 914 - v->__start = start; 915 - return vpe_run(v); 916 - } 917 - 918 - EXPORT_SYMBOL(vpe_start); 919 - 920 - /* halt it for now */ 921 - int vpe_stop(vpe_handle vpe) 922 - { 923 - struct vpe *v = vpe; 924 - struct tc *t; 925 - unsigned int evpe_flags; 926 - 927 - evpe_flags = dvpe(); 928 - 929 - if ((t = list_entry(v->tc.next, struct tc, tc)) != NULL) { 930 - 931 - settc(t->index); 932 - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); 933 - } 934 - 935 - evpe(evpe_flags); 936 - 937 - return 0; 938 - } 939 - 940 - EXPORT_SYMBOL(vpe_stop); 941 - 942 - /* I've done with it thank you */ 943 - int vpe_free(vpe_handle vpe) 944 - { 945 - struct vpe *v = vpe; 946 - struct tc *t; 947 - unsigned int evpe_flags; 948 - 949 - if ((t = list_entry(v->tc.next, struct tc, tc)) == NULL) { 950 - return -ENOEXEC; 951 - } 952 - 953 - evpe_flags = dvpe(); 954 - 955 - /* Put MVPE's into 'configuration state' */ 956 - set_c0_mvpcontrol(MVPCONTROL_VPC); 957 - 958 - settc(t->index); 959 - write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA); 960 - 961 - /* halt the TC */ 962 - write_tc_c0_tchalt(TCHALT_H); 963 - mips_ihb(); 964 - 965 - /* mark the TC unallocated */ 966 - write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A); 967 - 968 - v->state = VPE_STATE_UNUSED; 969 - 970 - clear_c0_mvpcontrol(MVPCONTROL_VPC); 971 - evpe(evpe_flags); 972 - 973 - return 0; 974 - } 975 - 976 - EXPORT_SYMBOL(vpe_free); 977 - 978 void *vpe_get_shared(int index) 979 { 980 - struct vpe *v; 981 982 - if ((v = get_vpe(index)) == NULL) 983 return NULL; 984 985 return v->shared_ptr; 986 } 987 - 988 EXPORT_SYMBOL(vpe_get_shared); 989 990 int vpe_notify(int index, struct vpe_notifications *notify) 991 { 992 - struct vpe *v; 993 994 - if ((v = get_vpe(index)) == NULL) 995 return -1; 996 997 list_add(&notify->list, &v->notify); 998 return 0; 999 } 1000 - 1001 EXPORT_SYMBOL(vpe_notify); 1002 1003 char *vpe_getcwd(int index) 1004 { 1005 - struct vpe *v; 1006 1007 - if ((v = get_vpe(index)) == NULL) 1008 return NULL; 1009 1010 return v->cwd; 1011 } 1012 - 1013 EXPORT_SYMBOL(vpe_getcwd); 1014 - 1015 - static ssize_t store_kill(struct device *dev, struct device_attribute *attr, 1016 - const char *buf, size_t len) 1017 - { 1018 - struct vpe *vpe = get_vpe(tclimit); 1019 - struct vpe_notifications *not; 1020 - 1021 - list_for_each_entry(not, &vpe->notify, list) { 1022 - not->stop(tclimit); 1023 - } 1024 - 1025 - release_progmem(vpe->load_addr); 1026 - cleanup_tc(get_tc(tclimit)); 1027 - vpe_stop(vpe); 1028 - vpe_free(vpe); 1029 - 1030 - return len; 1031 - } 1032 - static DEVICE_ATTR(kill, S_IWUSR, NULL, store_kill); 1033 - 1034 - static ssize_t ntcs_show(struct device *cd, struct device_attribute *attr, 1035 - char *buf) 1036 - { 1037 - struct vpe *vpe = get_vpe(tclimit); 1038 - 1039 - return sprintf(buf, "%d\n", vpe->ntcs); 1040 - } 1041 - 1042 - static ssize_t ntcs_store(struct device *dev, struct device_attribute *attr, 1043 - const char *buf, size_t len) 1044 - { 1045 - struct vpe *vpe = get_vpe(tclimit); 1046 - unsigned long new; 1047 - char *endp; 1048 - 1049 - new = simple_strtoul(buf, &endp, 0); 1050 - if (endp == buf) 1051 - goto out_einval; 1052 - 1053 - if (new == 0 || new > (hw_tcs - tclimit)) 1054 - goto out_einval; 1055 - 1056 - vpe->ntcs = new; 1057 - 1058 - return len; 1059 - 1060 - out_einval: 1061 - return -EINVAL; 1062 - } 1063 - static DEVICE_ATTR_RW(ntcs); 1064 - 1065 - static struct attribute *vpe_attrs[] = { 1066 - &dev_attr_kill.attr, 1067 - &dev_attr_ntcs.attr, 1068 - NULL, 1069 - }; 1070 - ATTRIBUTE_GROUPS(vpe); 1071 - 1072 - static void vpe_device_release(struct device *cd) 1073 - { 1074 - kfree(cd); 1075 - } 1076 - 1077 - struct class vpe_class = { 1078 - .name = "vpe", 1079 - .owner = THIS_MODULE, 1080 - .dev_release = vpe_device_release, 1081 - .dev_groups = vpe_groups, 1082 - }; 1083 - 1084 - struct device vpe_device; 1085 - 1086 - static int __init vpe_module_init(void) 1087 - { 1088 - unsigned int mtflags, vpflags; 1089 - unsigned long flags, val; 1090 - struct vpe *v = NULL; 1091 - struct tc *t; 1092 - int tc, err; 1093 - 1094 - if (!cpu_has_mipsmt) { 1095 - printk("VPE loader: not a MIPS MT capable processor\n"); 1096 - return -ENODEV; 1097 - } 1098 - 1099 - if (vpelimit == 0) { 1100 - printk(KERN_WARNING "No VPEs reserved for AP/SP, not " 1101 - "initializing VPE loader.\nPass maxvpes=<n> argument as " 1102 - "kernel argument\n"); 1103 - 1104 - return -ENODEV; 1105 - } 1106 - 1107 - if (tclimit == 0) { 1108 - printk(KERN_WARNING "No TCs reserved for AP/SP, not " 1109 - "initializing VPE loader.\nPass maxtcs=<n> argument as " 1110 - "kernel argument\n"); 1111 - 1112 - return -ENODEV; 1113 - } 1114 - 1115 - major = register_chrdev(0, module_name, &vpe_fops); 1116 - if (major < 0) { 1117 - printk("VPE loader: unable to register character device\n"); 1118 - return major; 1119 - } 1120 - 1121 - err = class_register(&vpe_class); 1122 - if (err) { 1123 - printk(KERN_ERR "vpe_class registration failed\n"); 1124 - goto out_chrdev; 1125 - } 1126 - 1127 - device_initialize(&vpe_device); 1128 - vpe_device.class = &vpe_class, 1129 - vpe_device.parent = NULL, 1130 - dev_set_name(&vpe_device, "vpe1"); 1131 - vpe_device.devt = MKDEV(major, minor); 1132 - err = device_add(&vpe_device); 1133 - if (err) { 1134 - printk(KERN_ERR "Adding vpe_device failed\n"); 1135 - goto out_class; 1136 - } 1137 - 1138 - local_irq_save(flags); 1139 - mtflags = dmt(); 1140 - vpflags = dvpe(); 1141 - 1142 - /* Put MVPE's into 'configuration state' */ 1143 - set_c0_mvpcontrol(MVPCONTROL_VPC); 1144 - 1145 - /* dump_mtregs(); */ 1146 - 1147 - val = read_c0_mvpconf0(); 1148 - hw_tcs = (val & MVPCONF0_PTC) + 1; 1149 - hw_vpes = ((val & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; 1150 - 1151 - for (tc = tclimit; tc < hw_tcs; tc++) { 1152 - /* 1153 - * Must re-enable multithreading temporarily or in case we 1154 - * reschedule send IPIs or similar we might hang. 1155 - */ 1156 - clear_c0_mvpcontrol(MVPCONTROL_VPC); 1157 - evpe(vpflags); 1158 - emt(mtflags); 1159 - local_irq_restore(flags); 1160 - t = alloc_tc(tc); 1161 - if (!t) { 1162 - err = -ENOMEM; 1163 - goto out; 1164 - } 1165 - 1166 - local_irq_save(flags); 1167 - mtflags = dmt(); 1168 - vpflags = dvpe(); 1169 - set_c0_mvpcontrol(MVPCONTROL_VPC); 1170 - 1171 - /* VPE's */ 1172 - if (tc < hw_tcs) { 1173 - settc(tc); 1174 - 1175 - if ((v = alloc_vpe(tc)) == NULL) { 1176 - printk(KERN_WARNING "VPE: unable to allocate VPE\n"); 1177 - 1178 - goto out_reenable; 1179 - } 1180 - 1181 - v->ntcs = hw_tcs - tclimit; 1182 - 1183 - /* add the tc to the list of this vpe's tc's. */ 1184 - list_add(&t->tc, &v->tc); 1185 - 1186 - /* deactivate all but vpe0 */ 1187 - if (tc >= tclimit) { 1188 - unsigned long tmp = read_vpe_c0_vpeconf0(); 1189 - 1190 - tmp &= ~VPECONF0_VPA; 1191 - 1192 - /* master VPE */ 1193 - tmp |= VPECONF0_MVP; 1194 - write_vpe_c0_vpeconf0(tmp); 1195 - } 1196 - 1197 - /* disable multi-threading with TC's */ 1198 - write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE); 1199 - 1200 - if (tc >= vpelimit) { 1201 - /* 1202 - * Set config to be the same as vpe0, 1203 - * particularly kseg0 coherency alg 1204 - */ 1205 - write_vpe_c0_config(read_c0_config()); 1206 - } 1207 - } 1208 - 1209 - /* TC's */ 1210 - t->pvpe = v; /* set the parent vpe */ 1211 - 1212 - if (tc >= tclimit) { 1213 - unsigned long tmp; 1214 - 1215 - settc(tc); 1216 - 1217 - /* Any TC that is bound to VPE0 gets left as is - in case 1218 - we are running SMTC on VPE0. A TC that is bound to any 1219 - other VPE gets bound to VPE0, ideally I'd like to make 1220 - it homeless but it doesn't appear to let me bind a TC 1221 - to a non-existent VPE. Which is perfectly reasonable. 1222 - 1223 - The (un)bound state is visible to an EJTAG probe so may 1224 - notify GDB... 1225 - */ 1226 - 1227 - if (((tmp = read_tc_c0_tcbind()) & TCBIND_CURVPE)) { 1228 - /* tc is bound >vpe0 */ 1229 - write_tc_c0_tcbind(tmp & ~TCBIND_CURVPE); 1230 - 1231 - t->pvpe = get_vpe(0); /* set the parent vpe */ 1232 - } 1233 - 1234 - /* halt the TC */ 1235 - write_tc_c0_tchalt(TCHALT_H); 1236 - mips_ihb(); 1237 - 1238 - tmp = read_tc_c0_tcstatus(); 1239 - 1240 - /* mark not activated and not dynamically allocatable */ 1241 - tmp &= ~(TCSTATUS_A | TCSTATUS_DA); 1242 - tmp |= TCSTATUS_IXMT; /* interrupt exempt */ 1243 - write_tc_c0_tcstatus(tmp); 1244 - } 1245 - } 1246 - 1247 - out_reenable: 1248 - /* release config state */ 1249 - clear_c0_mvpcontrol(MVPCONTROL_VPC); 1250 - 1251 - evpe(vpflags); 1252 - emt(mtflags); 1253 - local_irq_restore(flags); 1254 - 1255 - return 0; 1256 - 1257 - out_class: 1258 - class_unregister(&vpe_class); 1259 - out_chrdev: 1260 - unregister_chrdev(major, module_name); 1261 - 1262 - out: 1263 - return err; 1264 - } 1265 - 1266 - static void __exit vpe_module_exit(void) 1267 - { 1268 - struct vpe *v, *n; 1269 - 1270 - device_del(&vpe_device); 1271 - unregister_chrdev(major, module_name); 1272 - 1273 - /* No locking needed here */ 1274 - list_for_each_entry_safe(v, n, &vpecontrol.vpe_list, list) { 1275 - if (v->state != VPE_STATE_UNUSED) 1276 - release_vpe(v); 1277 - } 1278 - } 1279 1280 module_init(vpe_module_init); 1281 module_exit(vpe_module_exit);
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 * 9 + * VPE spport module for loading a MIPS SP program into VPE1. The SP 10 + * environment is rather simple since there are no TLBs. It needs 11 + * to be relocatable (or partiall linked). Initialize your stack in 12 + * the startup-code. The loader looks for the symbol __start and sets 13 + * up the execution to resume from there. To load and run, simply do 14 + * a cat SP 'binary' to the /dev/vpe1 device. 15 */ 16 #include <linux/kernel.h> 17 #include <linux/device.h> 18 #include <linux/fs.h> 19 #include <linux/init.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/vmalloc.h> ··· 46 #include <asm/mipsmtregs.h> 47 #include <asm/cacheflush.h> 48 #include <linux/atomic.h> 49 #include <asm/mips_mt.h> 50 #include <asm/processor.h> 51 #include <asm/vpe.h> 52 53 #ifndef ARCH_SHF_SMALL 54 #define ARCH_SHF_SMALL 0 ··· 60 /* If this is set, the section belongs in the init part of the module */ 61 #define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1)) 62 63 + struct vpe_control vpecontrol = { 64 .vpe_list_lock = __SPIN_LOCK_UNLOCKED(vpe_list_lock), 65 .vpe_list = LIST_HEAD_INIT(vpecontrol.vpe_list), 66 .tc_list_lock = __SPIN_LOCK_UNLOCKED(tc_list_lock), 67 .tc_list = LIST_HEAD_INIT(vpecontrol.tc_list) 68 }; 69 70 /* get the vpe associated with this minor */ 71 + struct vpe *get_vpe(int minor) 72 { 73 struct vpe *res, *v; 74 ··· 158 res = NULL; 159 spin_lock(&vpecontrol.vpe_list_lock); 160 list_for_each_entry(v, &vpecontrol.vpe_list, list) { 161 + if (v->minor == VPE_MODULE_MINOR) { 162 res = v; 163 break; 164 } ··· 169 } 170 171 /* get the vpe associated with this minor */ 172 + struct tc *get_tc(int index) 173 { 174 struct tc *res, *t; 175 ··· 187 } 188 189 /* allocate a vpe and associate it with this minor (or index) */ 190 + struct vpe *alloc_vpe(int minor) 191 { 192 struct vpe *v; 193 194 + v = kzalloc(sizeof(struct vpe), GFP_KERNEL); 195 + if (v == NULL) 196 + goto out; 197 198 INIT_LIST_HEAD(&v->tc); 199 spin_lock(&vpecontrol.vpe_list_lock); ··· 200 spin_unlock(&vpecontrol.vpe_list_lock); 201 202 INIT_LIST_HEAD(&v->notify); 203 + v->minor = VPE_MODULE_MINOR; 204 205 + out: 206 return v; 207 } 208 209 /* allocate a tc. At startup only tc0 is running, all other can be halted. */ 210 + struct tc *alloc_tc(int index) 211 { 212 struct tc *tc; 213 214 + tc = kzalloc(sizeof(struct tc), GFP_KERNEL); 215 + if (tc == NULL) 216 goto out; 217 218 INIT_LIST_HEAD(&tc->tc); ··· 225 } 226 227 /* clean up and free everything */ 228 + void release_vpe(struct vpe *v) 229 { 230 list_del(&v->list); 231 if (v->load_addr) ··· 233 kfree(v); 234 } 235 236 + /* Find some VPE program space */ 237 + void *alloc_progmem(unsigned long len) 238 { 239 void *addr; 240 ··· 273 return addr; 274 } 275 276 + void release_progmem(void *ptr) 277 { 278 #ifndef CONFIG_MIPS_VPE_LOADER_TOM 279 kfree(ptr); ··· 281 } 282 283 /* Update size with this section: return offset. */ 284 + static long get_offset(unsigned long *size, Elf_Shdr *sechdr) 285 { 286 long ret; 287 ··· 294 might -- code, read-only data, read-write data, small data. Tally 295 sizes, and place the offsets into sh_entsize fields: high bit means it 296 belongs in init. */ 297 + static void layout_sections(struct module *mod, const Elf_Ehdr *hdr, 298 + Elf_Shdr *sechdrs, const char *secstrings) 299 { 300 static unsigned long const masks[][2] = { 301 /* NOTE: all executable code must be the first section ··· 315 for (i = 0; i < hdr->e_shnum; ++i) { 316 Elf_Shdr *s = &sechdrs[i]; 317 318 if ((s->sh_flags & masks[m][0]) != masks[m][0] 319 || (s->sh_flags & masks[m][1]) 320 || s->sh_entsize != ~0UL) ··· 329 330 } 331 } 332 333 /* from module-elf32.c, but subverted a little */ 334 ··· 353 { 354 int rel; 355 356 + if (!(*location & 0xffff)) { 357 rel = (int)v - gp_addr; 358 + } else { 359 /* .sbss + gp(relative) + offset */ 360 /* kludge! */ 361 rel = (int)(short)((int)v + gp_offs + 362 (int)(short)(*location & 0xffff) - gp_addr); 363 } 364 365 + if ((rel > 32768) || (rel < -32768)) { 366 + pr_debug("VPE loader: apply_r_mips_gprel16: relative address 0x%x out of range of gp register\n", 367 + rel); 368 return -ENOEXEC; 369 } 370 ··· 380 { 381 int rel; 382 rel = (((unsigned int)v - (unsigned int)location)); 383 + rel >>= 2; /* because the offset is in _instructions_ not bytes. */ 384 + rel -= 1; /* and one instruction less due to the branch delay slot. */ 385 386 + if ((rel > 32768) || (rel < -32768)) { 387 + pr_debug("VPE loader: apply_r_mips_pc16: relative address out of range 0x%x\n", 388 + rel); 389 return -ENOEXEC; 390 } 391 ··· 406 Elf32_Addr v) 407 { 408 if (v % 4) { 409 + pr_debug("VPE loader: apply_r_mips_26: unaligned relocation\n"); 410 return -ENOEXEC; 411 } 412 ··· 438 * the carry we need to add. Save the information, and let LO16 do the 439 * actual relocation. 440 */ 441 + n = kmalloc(sizeof(*n), GFP_KERNEL); 442 if (!n) 443 return -ENOMEM; 444 ··· 470 * The value for the HI16 had best be the same. 471 */ 472 if (v != l->value) { 473 + pr_debug("VPE loader: apply_r_mips_lo16/hi16: inconsistent value information\n"); 474 goto out_free; 475 } 476 ··· 568 + ELF32_R_SYM(r_info); 569 570 if (!sym->st_value) { 571 + pr_debug("%s: undefined weak symbol %s\n", 572 + me->name, strtab + sym->st_name); 573 /* just print the warning, dont barf */ 574 } 575 576 v = sym->st_value; 577 578 res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v); 579 + if (res) { 580 char *r = rstrs[ELF32_R_TYPE(r_info)]; 581 + pr_warn("VPE loader: .text+0x%x relocation type %s for symbol \"%s\" failed\n", 582 + rel[i].r_offset, r ? r : "UNKNOWN", 583 + strtab + sym->st_name); 584 return res; 585 } 586 } ··· 596 } 597 /* end module-elf32.c */ 598 599 /* Change all symbols so that sh_value encodes the pointer directly. */ 600 + static void simplify_symbols(Elf_Shdr *sechdrs, 601 unsigned int symindex, 602 const char *strtab, 603 const char *secstrings, ··· 640 break; 641 642 case SHN_MIPS_SCOMMON: 643 + pr_debug("simplify_symbols: ignoring SHN_MIPS_SCOMMON symbol <%s> st_shndx %d\n", 644 + strtab + sym[i].st_name, sym[i].st_shndx); 645 + /* .sbss section */ 646 break; 647 648 default: 649 secbase = sechdrs[sym[i].st_shndx].sh_addr; 650 651 + if (strncmp(strtab + sym[i].st_name, "_gp", 3) == 0) 652 save_gp_address(secbase, sym[i].st_value); 653 654 sym[i].st_value += secbase; 655 break; ··· 660 } 661 662 #ifdef DEBUG_ELFLOADER 663 + static void dump_elfsymbols(Elf_Shdr *sechdrs, unsigned int symindex, 664 const char *strtab, struct module *mod) 665 { 666 Elf_Sym *sym = (void *)sechdrs[symindex].sh_addr; 667 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); 668 669 + pr_debug("dump_elfsymbols: n %d\n", n); 670 for (i = 1; i < n; i++) { 671 + pr_debug(" i %d name <%s> 0x%x\n", i, strtab + sym[i].st_name, 672 + sym[i].st_value); 673 } 674 } 675 #endif 676 677 + static int find_vpe_symbols(struct vpe *v, Elf_Shdr *sechdrs, 678 unsigned int symindex, const char *strtab, 679 struct module *mod) 680 { ··· 803 unsigned int i, n = sechdrs[symindex].sh_size / sizeof(Elf_Sym); 804 805 for (i = 1; i < n; i++) { 806 + if (strcmp(strtab + sym[i].st_name, "__start") == 0) 807 v->__start = sym[i].st_value; 808 809 + if (strcmp(strtab + sym[i].st_name, "vpe_shared") == 0) 810 v->shared_ptr = (void *)sym[i].st_value; 811 } 812 813 + if ((v->__start == 0) || (v->shared_ptr == NULL)) 814 return -1; 815 816 return 0; ··· 823 * contents of the program (p)buffer performing relocatations/etc, free's it 824 * when finished. 825 */ 826 + static int vpe_elfload(struct vpe *v) 827 { 828 Elf_Ehdr *hdr; 829 Elf_Shdr *sechdrs; 830 long err = 0; 831 char *secstrings, *strtab = NULL; 832 unsigned int len, i, symindex = 0, strindex = 0, relocate = 0; 833 + struct module mod; /* so we can re-use the relocations code */ 834 835 memset(&mod, 0, sizeof(struct module)); 836 strcpy(mod.name, "VPE loader"); ··· 844 || (hdr->e_type != ET_REL && hdr->e_type != ET_EXEC) 845 || !elf_check_arch(hdr) 846 || hdr->e_shentsize != sizeof(*sechdrs)) { 847 + pr_warn("VPE loader: program wrong arch or weird elf version\n"); 848 849 return -ENOEXEC; 850 } ··· 854 relocate = 1; 855 856 if (len < hdr->e_shoff + hdr->e_shnum * sizeof(Elf_Shdr)) { 857 + pr_err("VPE loader: program length %u truncated\n", len); 858 859 return -ENOEXEC; 860 } ··· 870 871 if (relocate) { 872 for (i = 1; i < hdr->e_shnum; i++) { 873 + if ((sechdrs[i].sh_type != SHT_NOBITS) && 874 + (len < sechdrs[i].sh_offset + sechdrs[i].sh_size)) { 875 + pr_err("VPE program length %u truncated\n", 876 len); 877 return -ENOEXEC; 878 } 879 880 /* Mark all sections sh_addr with their address in the 881 temporary image. */ 882 + sechdrs[i].sh_addr = (size_t) hdr + 883 + sechdrs[i].sh_offset; 884 885 /* Internal symbols and strings. */ 886 if (sechdrs[i].sh_type == SHT_SYMTAB) { 887 symindex = i; 888 strindex = sechdrs[i].sh_link; 889 + strtab = (char *)hdr + 890 + sechdrs[strindex].sh_offset; 891 } 892 } 893 layout_sections(&mod, hdr, sechdrs, secstrings); ··· 912 /* Update sh_addr to point to copy in image. */ 913 sechdrs[i].sh_addr = (unsigned long)dest; 914 915 + pr_debug(" section sh_name %s sh_addr 0x%x\n", 916 + secstrings + sechdrs[i].sh_name, 917 + sechdrs[i].sh_addr); 918 } 919 920 /* Fix up syms, so that st_value is a pointer to location. */ ··· 934 continue; 935 936 if (sechdrs[i].sh_type == SHT_REL) 937 + err = apply_relocations(sechdrs, strtab, 938 + symindex, i, &mod); 939 else if (sechdrs[i].sh_type == SHT_RELA) 940 + err = apply_relocate_add(sechdrs, strtab, 941 + symindex, i, &mod); 942 if (err < 0) 943 return err; 944 945 } 946 } else { 947 + struct elf_phdr *phdr = (struct elf_phdr *) 948 + ((char *)hdr + hdr->e_phoff); 949 950 for (i = 0; i < hdr->e_phnum; i++) { 951 if (phdr->p_type == PT_LOAD) { ··· 962 if (sechdrs[i].sh_type == SHT_SYMTAB) { 963 symindex = i; 964 strindex = sechdrs[i].sh_link; 965 + strtab = (char *)hdr + 966 + sechdrs[strindex].sh_offset; 967 968 + /* 969 + * mark symtab's address for when we try 970 + * to find the magic symbols 971 + */ 972 + sechdrs[i].sh_addr = (size_t) hdr + 973 + sechdrs[i].sh_offset; 974 } 975 } 976 } ··· 977 978 if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { 979 if (v->__start == 0) { 980 + pr_warn("VPE loader: program does not contain a __start symbol\n"); 981 return -ENOEXEC; 982 } 983 984 if (v->shared_ptr == NULL) 985 + pr_warn("VPE loader: program does not contain vpe_shared symbol.\n" 986 + " Unable to use AMVP (AP/SP) facilities.\n"); 987 } 988 989 + pr_info(" elf loaded\n"); 990 return 0; 991 } 992 993 static int getcwd(char *buff, int size) ··· 1043 static int vpe_open(struct inode *inode, struct file *filp) 1044 { 1045 enum vpe_state state; 1046 + struct vpe_notifications *notifier; 1047 struct vpe *v; 1048 int ret; 1049 1050 + if (VPE_MODULE_MINOR != iminor(inode)) { 1051 /* assume only 1 device at the moment. */ 1052 + pr_warn("VPE loader: only vpe1 is supported\n"); 1053 1054 return -ENODEV; 1055 } 1056 1057 + v = get_vpe(aprp_cpu_index()); 1058 + if (v == NULL) { 1059 + pr_warn("VPE loader: unable to get vpe\n"); 1060 1061 return -ENODEV; 1062 } 1063 1064 state = xchg(&v->state, VPE_STATE_INUSE); 1065 if (state != VPE_STATE_UNUSED) { 1066 + pr_debug("VPE loader: tc in use dumping regs\n"); 1067 1068 + list_for_each_entry(notifier, &v->notify, list) 1069 + notifier->stop(aprp_cpu_index()); 1070 1071 release_progmem(v->load_addr); 1072 + cleanup_tc(get_tc(aprp_cpu_index())); 1073 } 1074 1075 /* this of-course trashes what was there before... */ 1076 v->pbuffer = vmalloc(P_SIZE); 1077 if (!v->pbuffer) { 1078 + pr_warn("VPE loader: unable to allocate memory\n"); 1079 return -ENOMEM; 1080 } 1081 v->plen = P_SIZE; ··· 1085 v->cwd[0] = 0; 1086 ret = getcwd(v->cwd, VPE_PATH_MAX); 1087 if (ret < 0) 1088 + pr_warn("VPE loader: open, getcwd returned %d\n", ret); 1089 1090 v->shared_ptr = NULL; 1091 v->__start = 0; ··· 1099 Elf_Ehdr *hdr; 1100 int ret = 0; 1101 1102 + v = get_vpe(aprp_cpu_index()); 1103 if (v == NULL) 1104 return -ENODEV; 1105 1106 hdr = (Elf_Ehdr *) v->pbuffer; 1107 if (memcmp(hdr->e_ident, ELFMAG, SELFMAG) == 0) { 1108 + if ((vpe_elfload(v) >= 0) && vpe_run) { 1109 vpe_run(v); 1110 } else { 1111 + pr_warn("VPE loader: ELF load failed.\n"); 1112 ret = -ENOEXEC; 1113 } 1114 } else { 1115 + pr_warn("VPE loader: only elf files are supported\n"); 1116 ret = -ENOEXEC; 1117 } 1118 ··· 1130 return ret; 1131 } 1132 1133 + static ssize_t vpe_write(struct file *file, const char __user *buffer, 1134 + size_t count, loff_t *ppos) 1135 { 1136 size_t ret = count; 1137 struct vpe *v; 1138 1139 + if (iminor(file_inode(file)) != VPE_MODULE_MINOR) 1140 return -ENODEV; 1141 1142 + v = get_vpe(aprp_cpu_index()); 1143 + 1144 if (v == NULL) 1145 return -ENODEV; 1146 1147 if ((count + v->len) > v->plen) { 1148 + pr_warn("VPE loader: elf size too big. Perhaps strip uneeded symbols\n"); 1149 return -ENOMEM; 1150 } 1151 ··· 1157 return ret; 1158 } 1159 1160 + const struct file_operations vpe_fops = { 1161 .owner = THIS_MODULE, 1162 .open = vpe_open, 1163 .release = vpe_release, ··· 1165 .llseek = noop_llseek, 1166 }; 1167 1168 void *vpe_get_shared(int index) 1169 { 1170 + struct vpe *v = get_vpe(index); 1171 1172 + if (v == NULL) 1173 return NULL; 1174 1175 return v->shared_ptr; 1176 } 1177 EXPORT_SYMBOL(vpe_get_shared); 1178 1179 int vpe_notify(int index, struct vpe_notifications *notify) 1180 { 1181 + struct vpe *v = get_vpe(index); 1182 1183 + if (v == NULL) 1184 return -1; 1185 1186 list_add(&notify->list, &v->notify); 1187 return 0; 1188 } 1189 EXPORT_SYMBOL(vpe_notify); 1190 1191 char *vpe_getcwd(int index) 1192 { 1193 + struct vpe *v = get_vpe(index); 1194 1195 + if (v == NULL) 1196 return NULL; 1197 1198 return v->cwd; 1199 } 1200 EXPORT_SYMBOL(vpe_getcwd); 1201 1202 module_init(vpe_module_init); 1203 module_exit(vpe_module_exit);
-1
arch/mips/kvm/kvm_mips.c
··· 1001 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1002 HRTIMER_MODE_REL); 1003 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1004 - kvm_mips_init_shadow_tlb(vcpu); 1005 return 0; 1006 } 1007
··· 1001 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC, 1002 HRTIMER_MODE_REL); 1003 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup; 1004 return 0; 1005 } 1006
+1 -134
arch/mips/kvm/kvm_tlb.c
··· 10 * Authors: Sanjay Lal <sanjayl@kymasys.com> 11 */ 12 13 - #include <linux/init.h> 14 #include <linux/sched.h> 15 #include <linux/smp.h> 16 #include <linux/mm.h> ··· 24 #include <asm/mmu_context.h> 25 #include <asm/pgtable.h> 26 #include <asm/cacheflush.h> 27 28 #undef CONFIG_MIPS_MT 29 #include <asm/r4kcache.h> ··· 34 #define KVM_GUEST_SP_TLB 1 35 36 #define PRIx64 "llx" 37 - 38 - /* Use VZ EntryHi.EHINV to invalidate TLB entries */ 39 - #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) 40 41 atomic_t kvm_mips_instance; 42 EXPORT_SYMBOL(kvm_mips_instance); ··· 128 129 for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { 130 tlb = vcpu->arch.guest_tlb[i]; 131 - printk("TLB%c%3d Hi 0x%08lx ", 132 - (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*', 133 - i, tlb.tlb_hi); 134 - printk("Lo0=0x%09" PRIx64 " %c%c attr %lx ", 135 - (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo0), 136 - (tlb.tlb_lo0 & MIPS3_PG_D) ? 'D' : ' ', 137 - (tlb.tlb_lo0 & MIPS3_PG_G) ? 'G' : ' ', 138 - (tlb.tlb_lo0 >> 3) & 7); 139 - printk("Lo1=0x%09" PRIx64 " %c%c attr %lx sz=%lx\n", 140 - (uint64_t) mips3_tlbpfn_to_paddr(tlb.tlb_lo1), 141 - (tlb.tlb_lo1 & MIPS3_PG_D) ? 'D' : ' ', 142 - (tlb.tlb_lo1 & MIPS3_PG_G) ? 'G' : ' ', 143 - (tlb.tlb_lo1 >> 3) & 7, tlb.tlb_mask); 144 - } 145 - } 146 - 147 - void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu) 148 - { 149 - int i; 150 - volatile struct kvm_mips_tlb tlb; 151 - 152 - printk("Shadow TLBs:\n"); 153 - for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { 154 - tlb = vcpu->arch.shadow_tlb[smp_processor_id()][i]; 155 printk("TLB%c%3d Hi 0x%08lx ", 156 (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*', 157 i, tlb.tlb_hi); ··· 630 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 631 } 632 633 - void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu) 634 - { 635 - unsigned long flags; 636 - unsigned long old_entryhi; 637 - unsigned long old_pagemask; 638 - int entry = 0; 639 - int cpu = smp_processor_id(); 640 - 641 - local_irq_save(flags); 642 - 643 - old_entryhi = read_c0_entryhi(); 644 - old_pagemask = read_c0_pagemask(); 645 - 646 - for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { 647 - write_c0_index(entry); 648 - mtc0_tlbw_hazard(); 649 - tlb_read(); 650 - tlbw_use_hazard(); 651 - 652 - vcpu->arch.shadow_tlb[cpu][entry].tlb_hi = read_c0_entryhi(); 653 - vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = read_c0_entrylo0(); 654 - vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = read_c0_entrylo1(); 655 - vcpu->arch.shadow_tlb[cpu][entry].tlb_mask = read_c0_pagemask(); 656 - } 657 - 658 - write_c0_entryhi(old_entryhi); 659 - write_c0_pagemask(old_pagemask); 660 - mtc0_tlbw_hazard(); 661 - 662 - local_irq_restore(flags); 663 - 664 - } 665 - 666 - void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu) 667 - { 668 - unsigned long flags; 669 - unsigned long old_ctx; 670 - int entry; 671 - int cpu = smp_processor_id(); 672 - 673 - local_irq_save(flags); 674 - 675 - old_ctx = read_c0_entryhi(); 676 - 677 - for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { 678 - write_c0_entryhi(vcpu->arch.shadow_tlb[cpu][entry].tlb_hi); 679 - mtc0_tlbw_hazard(); 680 - write_c0_entrylo0(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0); 681 - write_c0_entrylo1(vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1); 682 - 683 - write_c0_index(entry); 684 - mtc0_tlbw_hazard(); 685 - 686 - tlb_write_indexed(); 687 - tlbw_use_hazard(); 688 - } 689 - 690 - tlbw_use_hazard(); 691 - write_c0_entryhi(old_ctx); 692 - mtc0_tlbw_hazard(); 693 - local_irq_restore(flags); 694 - } 695 - 696 - 697 void kvm_local_flush_tlb_all(void) 698 { 699 unsigned long flags; ··· 656 mtc0_tlbw_hazard(); 657 658 local_irq_restore(flags); 659 - } 660 - 661 - void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu) 662 - { 663 - int cpu, entry; 664 - 665 - for_each_possible_cpu(cpu) { 666 - for (entry = 0; entry < current_cpu_data.tlbsize; entry++) { 667 - vcpu->arch.shadow_tlb[cpu][entry].tlb_hi = 668 - UNIQUE_ENTRYHI(entry); 669 - vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0 = 0x0; 670 - vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1 = 0x0; 671 - vcpu->arch.shadow_tlb[cpu][entry].tlb_mask = 672 - read_c0_pagemask(); 673 - #ifdef DEBUG 674 - kvm_debug 675 - ("shadow_tlb[%d][%d]: tlb_hi: %#lx, lo0: %#lx, lo1: %#lx\n", 676 - cpu, entry, 677 - vcpu->arch.shadow_tlb[cpu][entry].tlb_hi, 678 - vcpu->arch.shadow_tlb[cpu][entry].tlb_lo0, 679 - vcpu->arch.shadow_tlb[cpu][entry].tlb_lo1); 680 - #endif 681 - } 682 - } 683 } 684 685 /* Restore ASID once we are scheduled back after preemption */ ··· 694 kvm_info("[%d->%d]KVM VCPU[%d] switch\n", 695 vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id); 696 } 697 - 698 - /* Only reload shadow host TLB if new ASIDs haven't been allocated */ 699 - #if 0 700 - if ((atomic_read(&kvm_mips_instance) > 1) && !newasid) { 701 - kvm_mips_flush_host_tlb(0); 702 - kvm_shadow_tlb_load(vcpu); 703 - } 704 - #endif 705 706 if (!newasid) { 707 /* If we preempted while the guest was executing, then reload the pre-empted ASID */ ··· 739 740 vcpu->arch.preempt_entryhi = read_c0_entryhi(); 741 vcpu->arch.last_sched_cpu = cpu; 742 - 743 - #if 0 744 - if ((atomic_read(&kvm_mips_instance) > 1)) { 745 - kvm_shadow_tlb_put(vcpu); 746 - } 747 - #endif 748 749 if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & 750 ASID_VERSION_MASK)) { ··· 801 } 802 803 EXPORT_SYMBOL(kvm_local_flush_tlb_all); 804 - EXPORT_SYMBOL(kvm_shadow_tlb_put); 805 EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault); 806 EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault); 807 - EXPORT_SYMBOL(kvm_mips_init_shadow_tlb); 808 EXPORT_SYMBOL(kvm_mips_dump_host_tlbs); 809 EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault); 810 EXPORT_SYMBOL(kvm_mips_host_tlb_lookup); ··· 810 EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup); 811 EXPORT_SYMBOL(kvm_mips_host_tlb_inv); 812 EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa); 813 - EXPORT_SYMBOL(kvm_shadow_tlb_load); 814 - EXPORT_SYMBOL(kvm_mips_dump_shadow_tlbs); 815 EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs); 816 EXPORT_SYMBOL(kvm_get_inst); 817 EXPORT_SYMBOL(kvm_arch_vcpu_load);
··· 10 * Authors: Sanjay Lal <sanjayl@kymasys.com> 11 */ 12 13 #include <linux/sched.h> 14 #include <linux/smp.h> 15 #include <linux/mm.h> ··· 25 #include <asm/mmu_context.h> 26 #include <asm/pgtable.h> 27 #include <asm/cacheflush.h> 28 + #include <asm/tlb.h> 29 30 #undef CONFIG_MIPS_MT 31 #include <asm/r4kcache.h> ··· 34 #define KVM_GUEST_SP_TLB 1 35 36 #define PRIx64 "llx" 37 38 atomic_t kvm_mips_instance; 39 EXPORT_SYMBOL(kvm_mips_instance); ··· 131 132 for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) { 133 tlb = vcpu->arch.guest_tlb[i]; 134 printk("TLB%c%3d Hi 0x%08lx ", 135 (tlb.tlb_lo0 | tlb.tlb_lo1) & MIPS3_PG_V ? ' ' : '*', 136 i, tlb.tlb_hi); ··· 657 cpu_context(cpu, mm) = asid_cache(cpu) = asid; 658 } 659 660 void kvm_local_flush_tlb_all(void) 661 { 662 unsigned long flags; ··· 747 mtc0_tlbw_hazard(); 748 749 local_irq_restore(flags); 750 } 751 752 /* Restore ASID once we are scheduled back after preemption */ ··· 809 kvm_info("[%d->%d]KVM VCPU[%d] switch\n", 810 vcpu->arch.last_sched_cpu, cpu, vcpu->vcpu_id); 811 } 812 813 if (!newasid) { 814 /* If we preempted while the guest was executing, then reload the pre-empted ASID */ ··· 862 863 vcpu->arch.preempt_entryhi = read_c0_entryhi(); 864 vcpu->arch.last_sched_cpu = cpu; 865 866 if (((cpu_context(cpu, current->mm) ^ asid_cache(cpu)) & 867 ASID_VERSION_MASK)) { ··· 930 } 931 932 EXPORT_SYMBOL(kvm_local_flush_tlb_all); 933 EXPORT_SYMBOL(kvm_mips_handle_mapped_seg_tlb_fault); 934 EXPORT_SYMBOL(kvm_mips_handle_commpage_tlb_fault); 935 EXPORT_SYMBOL(kvm_mips_dump_host_tlbs); 936 EXPORT_SYMBOL(kvm_mips_handle_kseg0_tlb_fault); 937 EXPORT_SYMBOL(kvm_mips_host_tlb_lookup); ··· 941 EXPORT_SYMBOL(kvm_mips_guest_tlb_lookup); 942 EXPORT_SYMBOL(kvm_mips_host_tlb_inv); 943 EXPORT_SYMBOL(kvm_mips_translate_guest_kseg0_to_hpa); 944 EXPORT_SYMBOL(kvm_mips_dump_guest_tlbs); 945 EXPORT_SYMBOL(kvm_get_inst); 946 EXPORT_SYMBOL(kvm_arch_vcpu_load);
-1
arch/mips/lantiq/xway/clk.c
··· 8 9 #include <linux/io.h> 10 #include <linux/export.h> 11 - #include <linux/init.h> 12 #include <linux/clk.h> 13 14 #include <asm/time.h>
··· 8 9 #include <linux/io.h> 10 #include <linux/export.h> 11 #include <linux/clk.h> 12 13 #include <asm/time.h>
-4
arch/mips/lantiq/xway/dma.c
··· 220 int i; 221 222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 223 - if (!res) 224 - panic("Failed to get dma resource"); 225 - 226 - /* remap dma register range */ 227 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); 228 if (IS_ERR(ltq_dma_membase)) 229 panic("Failed to remap dma resource");
··· 220 int i; 221 222 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 223 ltq_dma_membase = devm_ioremap_resource(&pdev->dev, res); 224 if (IS_ERR(ltq_dma_membase)) 225 panic("Failed to remap dma resource");
-1
arch/mips/lasat/at93c.c
··· 8 #include <linux/delay.h> 9 #include <asm/lasat/lasat.h> 10 #include <linux/module.h> 11 - #include <linux/init.h> 12 13 #include "at93c.h" 14
··· 8 #include <linux/delay.h> 9 #include <asm/lasat/lasat.h> 10 #include <linux/module.h> 11 12 #include "at93c.h" 13
-1
arch/mips/lasat/picvue.c
··· 9 #include <asm/bootinfo.h> 10 #include <asm/lasat/lasat.h> 11 #include <linux/module.h> 12 - #include <linux/init.h> 13 #include <linux/errno.h> 14 #include <linux/string.h> 15
··· 9 #include <asm/bootinfo.h> 10 #include <asm/lasat/lasat.h> 11 #include <linux/module.h> 12 #include <linux/errno.h> 13 #include <linux/string.h> 14
-1
arch/mips/lib/uncached.c
··· 8 * Author: Maciej W. Rozycki <macro@mips.com> 9 */ 10 11 - #include <linux/init.h> 12 13 #include <asm/addrspace.h> 14 #include <asm/bug.h>
··· 8 * Author: Maciej W. Rozycki <macro@mips.com> 9 */ 10 11 12 #include <asm/addrspace.h> 13 #include <asm/bug.h>
-1
arch/mips/loongson/lemote-2f/clock.c
··· 10 #include <linux/cpufreq.h> 11 #include <linux/errno.h> 12 #include <linux/export.h> 13 - #include <linux/init.h> 14 #include <linux/list.h> 15 #include <linux/mutex.h> 16 #include <linux/spinlock.h>
··· 10 #include <linux/cpufreq.h> 11 #include <linux/errno.h> 12 #include <linux/export.h> 13 #include <linux/list.h> 14 #include <linux/mutex.h> 15 #include <linux/spinlock.h>
+36 -6
arch/mips/math-emu/cp1emu.c
··· 417 case mm_mtc1_op: 418 case mm_cfc1_op: 419 case mm_ctc1_op: 420 if (insn.mm_fp1_format.op == mm_mfc1_op) 421 op = mfc_op; 422 else if (insn.mm_fp1_format.op == mm_mtc1_op) 423 op = mtc_op; 424 else if (insn.mm_fp1_format.op == mm_cfc1_op) 425 op = cfc_op; 426 - else 427 op = ctc_op; 428 mips32_insn.fp1_format.opcode = cop1_op; 429 mips32_insn.fp1_format.op = op; 430 mips32_insn.fp1_format.rt = ··· 859 * In the Linux kernel, we support selection of FPR format on the 860 * basis of the Status.FR bit. If an FPU is not present, the FR bit 861 * is hardwired to zero, which would imply a 32-bit FPU even for 862 - * 64-bit CPUs so we rather look at TIF_32BIT_REGS. 863 * FPU emu is slow and bulky and optimizing this function offers fairly 864 * sizeable benefits so we try to be clever and make this function return 865 * a constant whenever possible, that is on 64-bit kernels without O32 866 - * compatibility enabled and on 32-bit kernels. 867 */ 868 static inline int cop1_64bit(struct pt_regs *xcp) 869 { 870 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) 871 return 1; 872 - #elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32) 873 - return !test_thread_flag(TIF_32BIT_REGS); 874 - #else 875 return 0; 876 #endif 877 } 878 ··· 883 cop1_64bit(xcp) || !(x & 1) ? \ 884 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 885 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 886 887 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) 888 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) ··· 1064 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1065 break; 1066 #endif 1067 1068 case mfc_op: 1069 /* copregister rd -> gpr[rt] */ ··· 1292 #endif 1293 1294 default: 1295 return SIGILL; 1296 } 1297
··· 417 case mm_mtc1_op: 418 case mm_cfc1_op: 419 case mm_ctc1_op: 420 + case mm_mfhc1_op: 421 + case mm_mthc1_op: 422 if (insn.mm_fp1_format.op == mm_mfc1_op) 423 op = mfc_op; 424 else if (insn.mm_fp1_format.op == mm_mtc1_op) 425 op = mtc_op; 426 else if (insn.mm_fp1_format.op == mm_cfc1_op) 427 op = cfc_op; 428 + else if (insn.mm_fp1_format.op == mm_ctc1_op) 429 op = ctc_op; 430 + else if (insn.mm_fp1_format.op == mm_mfhc1_op) 431 + op = mfhc_op; 432 + else 433 + op = mthc_op; 434 mips32_insn.fp1_format.opcode = cop1_op; 435 mips32_insn.fp1_format.op = op; 436 mips32_insn.fp1_format.rt = ··· 853 * In the Linux kernel, we support selection of FPR format on the 854 * basis of the Status.FR bit. If an FPU is not present, the FR bit 855 * is hardwired to zero, which would imply a 32-bit FPU even for 856 + * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS. 857 * FPU emu is slow and bulky and optimizing this function offers fairly 858 * sizeable benefits so we try to be clever and make this function return 859 * a constant whenever possible, that is on 64-bit kernels without O32 860 + * compatibility enabled and on 32-bit without 64-bit FPU support. 861 */ 862 static inline int cop1_64bit(struct pt_regs *xcp) 863 { 864 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32) 865 return 1; 866 + #elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT) 867 return 0; 868 + #else 869 + return !test_thread_flag(TIF_32BIT_FPREGS); 870 #endif 871 } 872 ··· 877 cop1_64bit(xcp) || !(x & 1) ? \ 878 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 879 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 880 + 881 + #define SIFROMHREG(si, x) ((si) = (int)(ctx->fpr[x] >> 32)) 882 + #define SITOHREG(si, x) (ctx->fpr[x] = \ 883 + ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32) 884 885 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) 886 #define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) ··· 1054 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1055 break; 1056 #endif 1057 + 1058 + case mfhc_op: 1059 + if (!cpu_has_mips_r2) 1060 + goto sigill; 1061 + 1062 + /* copregister rd -> gpr[rt] */ 1063 + if (MIPSInst_RT(ir) != 0) { 1064 + SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], 1065 + MIPSInst_RD(ir)); 1066 + } 1067 + break; 1068 + 1069 + case mthc_op: 1070 + if (!cpu_has_mips_r2) 1071 + goto sigill; 1072 + 1073 + /* copregister rd <- gpr[rt] */ 1074 + SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 1075 + break; 1076 1077 case mfc_op: 1078 /* copregister rd -> gpr[rt] */ ··· 1263 #endif 1264 1265 default: 1266 + sigill: 1267 return SIGILL; 1268 } 1269
+4 -2
arch/mips/math-emu/kernel_linkage.c
··· 89 { 90 int i; 91 int err = 0; 92 93 - for (i = 0; i < 32; i+=2) { 94 err |= 95 __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 96 } ··· 104 { 105 int i; 106 int err = 0; 107 108 - for (i = 0; i < 32; i+=2) { 109 err |= 110 __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 111 }
··· 89 { 90 int i; 91 int err = 0; 92 + int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1; 93 94 + for (i = 0; i < 32; i += inc) { 95 err |= 96 __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 97 } ··· 103 { 104 int i; 105 int err = 0; 106 + int inc = test_thread_flag(TIF_32BIT_FPREGS) ? 2 : 1; 107 108 + for (i = 0; i < 32; i += inc) { 109 err |= 110 __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 111 }
-1
arch/mips/mm/c-octeon.c
··· 6 * Copyright (C) 2005-2007 Cavium Networks 7 */ 8 #include <linux/export.h> 9 - #include <linux/init.h> 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <linux/smp.h>
··· 6 * Copyright (C) 2005-2007 Cavium Networks 7 */ 8 #include <linux/export.h> 9 #include <linux/kernel.h> 10 #include <linux/sched.h> 11 #include <linux/smp.h>
-1
arch/mips/mm/c-r3k.c
··· 9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov 10 * Copyright (C) 2001, 2004, 2007 Maciej W. Rozycki 11 */ 12 - #include <linux/init.h> 13 #include <linux/kernel.h> 14 #include <linux/sched.h> 15 #include <linux/smp.h>
··· 9 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov 10 * Copyright (C) 2001, 2004, 2007 Maciej W. Rozycki 11 */ 12 #include <linux/kernel.h> 13 #include <linux/sched.h> 14 #include <linux/smp.h>
+18 -8
arch/mips/mm/c-r4k.c
··· 1020 */ 1021 config1 = read_c0_config1(); 1022 1023 - if ((lsize = ((config1 >> 19) & 7))) 1024 - c->icache.linesz = 2 << lsize; 1025 - else 1026 - c->icache.linesz = lsize; 1027 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1028 c->icache.ways = 1 + ((config1 >> 16) & 7); 1029 ··· 1044 */ 1045 c->dcache.flags = 0; 1046 1047 - if ((lsize = ((config1 >> 10) & 7))) 1048 - c->dcache.linesz = 2 << lsize; 1049 - else 1050 - c->dcache.linesz= lsize; 1051 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1052 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1053 ··· 1113 case CPU_34K: 1114 case CPU_74K: 1115 case CPU_1004K: 1116 if (current_cpu_type() == CPU_74K) 1117 alias_74k_erratum(c); 1118 if ((read_c0_config7() & (1 << 16))) {
··· 1020 */ 1021 config1 = read_c0_config1(); 1022 1023 + lsize = (config1 >> 19) & 7; 1024 + 1025 + /* IL == 7 is reserved */ 1026 + if (lsize == 7) 1027 + panic("Invalid icache line size"); 1028 + 1029 + c->icache.linesz = lsize ? 2 << lsize : 0; 1030 + 1031 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); 1032 c->icache.ways = 1 + ((config1 >> 16) & 7); 1033 ··· 1040 */ 1041 c->dcache.flags = 0; 1042 1043 + lsize = (config1 >> 10) & 7; 1044 + 1045 + /* DL == 7 is reserved */ 1046 + if (lsize == 7) 1047 + panic("Invalid dcache line size"); 1048 + 1049 + c->dcache.linesz = lsize ? 2 << lsize : 0; 1050 + 1051 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); 1052 c->dcache.ways = 1 + ((config1 >> 7) & 7); 1053 ··· 1105 case CPU_34K: 1106 case CPU_74K: 1107 case CPU_1004K: 1108 + case CPU_INTERAPTIV: 1109 + case CPU_PROAPTIV: 1110 if (current_cpu_type() == CPU_74K) 1111 alias_74k_erratum(c); 1112 if ((read_c0_config7() & (1 << 16))) {
-1
arch/mips/mm/cache.c
··· 8 */ 9 #include <linux/fs.h> 10 #include <linux/fcntl.h> 11 - #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/linkage.h> 14 #include <linux/module.h>
··· 8 */ 9 #include <linux/fs.h> 10 #include <linux/fcntl.h> 11 #include <linux/kernel.h> 12 #include <linux/linkage.h> 13 #include <linux/module.h>
-1
arch/mips/mm/cex-sb1.S
··· 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 - #include <linux/init.h> 19 20 #include <asm/asm.h> 21 #include <asm/regdef.h>
··· 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 17 */ 18 19 #include <asm/asm.h> 20 #include <asm/regdef.h>
+2
arch/mips/mm/dma-default.c
··· 23 24 #include <dma-coherence.h> 25 26 int coherentio = 0; /* User defined DMA coherency from command line. */ 27 EXPORT_SYMBOL_GPL(coherentio); 28 int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ ··· 43 return 0; 44 } 45 early_param("nocoherentio", setnocoherentio); 46 47 static inline struct page *dma_addr_to_page(struct device *dev, 48 dma_addr_t dma_addr)
··· 23 24 #include <dma-coherence.h> 25 26 + #ifdef CONFIG_DMA_MAYBE_COHERENT 27 int coherentio = 0; /* User defined DMA coherency from command line. */ 28 EXPORT_SYMBOL_GPL(coherentio); 29 int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ ··· 42 return 0; 43 } 44 early_param("nocoherentio", setnocoherentio); 45 + #endif 46 47 static inline struct page *dma_addr_to_page(struct device *dev, 48 dma_addr_t dma_addr)
-1
arch/mips/mm/hugetlbpage.c
··· 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 */ 13 14 - #include <linux/init.h> 15 #include <linux/fs.h> 16 #include <linux/mm.h> 17 #include <linux/hugetlb.h>
··· 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 */ 13 14 #include <linux/fs.h> 15 #include <linux/mm.h> 16 #include <linux/hugetlb.h>
-2
arch/mips/mm/init.c
··· 171 return (void*) vaddr; 172 } 173 174 - #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) 175 - 176 void kunmap_coherent(void) 177 { 178 #ifndef CONFIG_MIPS_MT_SMTC
··· 171 return (void*) vaddr; 172 } 173 174 void kunmap_coherent(void) 175 { 176 #ifndef CONFIG_MIPS_MT_SMTC
-1
arch/mips/mm/page.c
··· 8 * Copyright (C) 2008 Thiemo Seufer 9 * Copyright (C) 2012 MIPS Technologies, Inc. 10 */ 11 - #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <linux/sched.h> 14 #include <linux/smp.h>
··· 8 * Copyright (C) 2008 Thiemo Seufer 9 * Copyright (C) 2012 MIPS Technologies, Inc. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/sched.h> 13 #include <linux/smp.h>
+2
arch/mips/mm/sc-mips.c
··· 76 case CPU_34K: 77 case CPU_74K: 78 case CPU_1004K: 79 case CPU_BMIPS5000: 80 if (config2 & (1 << 12)) 81 return 0;
··· 76 case CPU_34K: 77 case CPU_74K: 78 case CPU_1004K: 79 + case CPU_INTERAPTIV: 80 + case CPU_PROAPTIV: 81 case CPU_BMIPS5000: 82 if (config2 & (1 << 12)) 83 return 0;
-1
arch/mips/mm/sc-rm7k.c
··· 6 7 #undef DEBUG 8 9 - #include <linux/init.h> 10 #include <linux/kernel.h> 11 #include <linux/mm.h> 12 #include <linux/bitops.h>
··· 6 7 #undef DEBUG 8 9 #include <linux/kernel.h> 10 #include <linux/mm.h> 11 #include <linux/bitops.h>
-1
arch/mips/mm/tlb-r3k.c
··· 10 * Copyright (C) 2002 Ralf Baechle 11 * Copyright (C) 2002 Maciej W. Rozycki 12 */ 13 - #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <linux/sched.h> 16 #include <linux/smp.h>
··· 10 * Copyright (C) 2002 Ralf Baechle 11 * Copyright (C) 2002 Maciej W. Rozycki 12 */ 13 #include <linux/kernel.h> 14 #include <linux/sched.h> 15 #include <linux/smp.h>
+32 -16
arch/mips/mm/tlb-r4k.c
··· 20 #include <asm/bootinfo.h> 21 #include <asm/mmu_context.h> 22 #include <asm/pgtable.h> 23 #include <asm/tlbmisc.h> 24 25 extern void build_tlb_refill_handler(void); 26 - 27 - /* 28 - * Make sure all entries differ. If they're not different 29 - * MIPS32 will take revenge ... 30 - */ 31 - #define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) 32 33 /* Atomicity and interruptability */ 34 #ifdef CONFIG_MIPS_MT_SMTC ··· 72 { 73 unsigned long flags; 74 unsigned long old_ctx; 75 - int entry; 76 77 ENTER_CRITICAL(flags); 78 /* Save old context and create impossible VPN2 value */ ··· 83 entry = read_c0_wired(); 84 85 /* Blast 'em all away. */ 86 - while (entry < current_cpu_data.tlbsize) { 87 - /* Make sure all entries differ. */ 88 - write_c0_entryhi(UNIQUE_ENTRYHI(entry)); 89 - write_c0_index(entry); 90 - mtc0_tlbw_hazard(); 91 - tlb_write_indexed(); 92 - entry++; 93 } 94 tlbw_use_hazard(); 95 write_c0_entryhi(old_ctx); ··· 145 start = round_down(start, PAGE_SIZE << 1); 146 end = round_up(end, PAGE_SIZE << 1); 147 size = (end - start) >> (PAGE_SHIFT + 1); 148 - if (size <= current_cpu_data.tlbsize/2) { 149 int oldpid = read_c0_entryhi(); 150 int newpid = cpu_asid(cpu, mm); 151 ··· 186 ENTER_CRITICAL(flags); 187 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 188 size = (size + 1) >> 1; 189 - if (size <= current_cpu_data.tlbsize / 2) { 190 int pid = read_c0_entryhi(); 191 192 start &= (PAGE_MASK << 1);
··· 20 #include <asm/bootinfo.h> 21 #include <asm/mmu_context.h> 22 #include <asm/pgtable.h> 23 + #include <asm/tlb.h> 24 #include <asm/tlbmisc.h> 25 26 extern void build_tlb_refill_handler(void); 27 28 /* Atomicity and interruptability */ 29 #ifdef CONFIG_MIPS_MT_SMTC ··· 77 { 78 unsigned long flags; 79 unsigned long old_ctx; 80 + int entry, ftlbhighset; 81 82 ENTER_CRITICAL(flags); 83 /* Save old context and create impossible VPN2 value */ ··· 88 entry = read_c0_wired(); 89 90 /* Blast 'em all away. */ 91 + if (cpu_has_tlbinv) { 92 + if (current_cpu_data.tlbsizevtlb) { 93 + write_c0_index(0); 94 + mtc0_tlbw_hazard(); 95 + tlbinvf(); /* invalidate VTLB */ 96 + } 97 + ftlbhighset = current_cpu_data.tlbsizevtlb + 98 + current_cpu_data.tlbsizeftlbsets; 99 + for (entry = current_cpu_data.tlbsizevtlb; 100 + entry < ftlbhighset; 101 + entry++) { 102 + write_c0_index(entry); 103 + mtc0_tlbw_hazard(); 104 + tlbinvf(); /* invalidate one FTLB set */ 105 + } 106 + } else { 107 + while (entry < current_cpu_data.tlbsize) { 108 + /* Make sure all entries differ. */ 109 + write_c0_entryhi(UNIQUE_ENTRYHI(entry)); 110 + write_c0_index(entry); 111 + mtc0_tlbw_hazard(); 112 + tlb_write_indexed(); 113 + entry++; 114 + } 115 } 116 tlbw_use_hazard(); 117 write_c0_entryhi(old_ctx); ··· 133 start = round_down(start, PAGE_SIZE << 1); 134 end = round_up(end, PAGE_SIZE << 1); 135 size = (end - start) >> (PAGE_SHIFT + 1); 136 + if (size <= (current_cpu_data.tlbsizeftlbsets ? 137 + current_cpu_data.tlbsize / 8 : 138 + current_cpu_data.tlbsize / 2)) { 139 int oldpid = read_c0_entryhi(); 140 int newpid = cpu_asid(cpu, mm); 141 ··· 172 ENTER_CRITICAL(flags); 173 size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; 174 size = (size + 1) >> 1; 175 + if (size <= (current_cpu_data.tlbsizeftlbsets ? 176 + current_cpu_data.tlbsize / 8 : 177 + current_cpu_data.tlbsize / 2)) { 178 int pid = read_c0_entryhi(); 179 180 start &= (PAGE_MASK << 1);
-1
arch/mips/mm/tlb-r8k.c
··· 8 * Carsten Langgaard, carstenl@mips.com 9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 10 */ 11 - #include <linux/init.h> 12 #include <linux/sched.h> 13 #include <linux/smp.h> 14 #include <linux/mm.h>
··· 8 * Carsten Langgaard, carstenl@mips.com 9 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 10 */ 11 #include <linux/sched.h> 12 #include <linux/smp.h> 13 #include <linux/mm.h>
+1 -1
arch/mips/mm/tlbex.c
··· 26 #include <linux/types.h> 27 #include <linux/smp.h> 28 #include <linux/string.h> 29 - #include <linux/init.h> 30 #include <linux/cache.h> 31 32 #include <asm/cacheflush.h> ··· 509 switch (current_cpu_type()) { 510 case CPU_M14KC: 511 case CPU_74K: 512 break; 513 514 default:
··· 26 #include <linux/types.h> 27 #include <linux/smp.h> 28 #include <linux/string.h> 29 #include <linux/cache.h> 30 31 #include <asm/cacheflush.h> ··· 510 switch (current_cpu_type()) { 511 case CPU_M14KC: 512 case CPU_74K: 513 + case CPU_PROAPTIV: 514 break; 515 516 default:
-1
arch/mips/mm/uasm-micromips.c
··· 15 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 - #include <linux/init.h> 19 20 #include <asm/inst.h> 21 #include <asm/elf.h>
··· 15 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 19 #include <asm/inst.h> 20 #include <asm/elf.h>
-1
arch/mips/mm/uasm-mips.c
··· 15 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 - #include <linux/init.h> 19 20 #include <asm/inst.h> 21 #include <asm/elf.h>
··· 15 16 #include <linux/kernel.h> 17 #include <linux/types.h> 18 19 #include <asm/inst.h> 20 #include <asm/elf.h>
-2
arch/mips/mti-malta/Makefile
··· 9 malta-int.o malta-memory.o malta-platform.o \ 10 malta-reset.o malta-setup.o malta-time.o 11 12 - obj-$(CONFIG_EARLY_PRINTK) += malta-console.o 13 - 14 # FIXME FIXME FIXME 15 obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o
··· 9 malta-int.o malta-memory.o malta-platform.o \ 10 malta-reset.o malta-setup.o malta-time.o 11 12 # FIXME FIXME FIXME 13 obj-$(CONFIG_MIPS_MT_SMTC) += malta-smtc.o
+28 -21
arch/mips/mti-malta/malta-amon.c
··· 1 /* 2 - * Copyright (C) 2007 MIPS Technologies, Inc. 3 - * All rights reserved. 4 - 5 - * This program is free software; you can distribute it and/or modify it 6 - * under the terms of the GNU General Public License (Version 2) as 7 - * published by the Free Software Foundation. 8 * 9 - * This program is distributed in the hope it will be useful, but WITHOUT 10 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 - * for more details. 13 * 14 - * You should have received a copy of the GNU General Public License along 15 - * with this program; if not, write to the Free Software Foundation, Inc., 16 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 - * 18 - * Arbitrary Monitor interface 19 */ 20 - 21 #include <linux/kernel.h> 22 - #include <linux/init.h> 23 #include <linux/smp.h> 24 25 #include <asm/addrspace.h> 26 - #include <asm/mips-boards/launch.h> 27 #include <asm/mipsmtregs.h> 28 29 int amon_cpu_avail(int cpu) 30 { ··· 38 return 1; 39 } 40 41 - void amon_cpu_start(int cpu, 42 unsigned long pc, unsigned long sp, 43 unsigned long gp, unsigned long a0) 44 { ··· 46 (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); 47 48 if (!amon_cpu_avail(cpu)) 49 - return; 50 if (cpu == smp_processor_id()) { 51 pr_debug("launch: I am cpu%d!\n", cpu); 52 - return; 53 } 54 launch += cpu; 55 ··· 68 ; 69 smp_rmb(); /* Target will be updating flags soon */ 70 pr_debug("launch: cpu%d gone!\n", cpu); 71 }
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 * 6 + * Copyright (C) 2007 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 * 9 + * Arbitrary Monitor Interface 10 */ 11 #include <linux/kernel.h> 12 #include <linux/smp.h> 13 14 #include <asm/addrspace.h> 15 #include <asm/mipsmtregs.h> 16 + #include <asm/mips-boards/launch.h> 17 + #include <asm/vpe.h> 18 19 int amon_cpu_avail(int cpu) 20 { ··· 48 return 1; 49 } 50 51 + int amon_cpu_start(int cpu, 52 unsigned long pc, unsigned long sp, 53 unsigned long gp, unsigned long a0) 54 { ··· 56 (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); 57 58 if (!amon_cpu_avail(cpu)) 59 + return -1; 60 if (cpu == smp_processor_id()) { 61 pr_debug("launch: I am cpu%d!\n", cpu); 62 + return -1; 63 } 64 launch += cpu; 65 ··· 78 ; 79 smp_rmb(); /* Target will be updating flags soon */ 80 pr_debug("launch: cpu%d gone!\n", cpu); 81 + 82 + return 0; 83 } 84 + 85 + #ifdef CONFIG_MIPS_VPE_LOADER 86 + int vpe_run(struct vpe *v) 87 + { 88 + struct vpe_notifications *n; 89 + 90 + if (amon_cpu_start(aprp_cpu_index(), v->__start, 0, 0, 0) < 0) 91 + return -1; 92 + 93 + list_for_each_entry(n, &v->notify, list) 94 + n->start(VPE_MODULE_MINOR); 95 + 96 + return 0; 97 + } 98 + #endif
-47
arch/mips/mti-malta/malta-console.c
··· 1 - /* 2 - * Carsten Langgaard, carstenl@mips.com 3 - * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 4 - * 5 - * This program is free software; you can distribute it and/or modify it 6 - * under the terms of the GNU General Public License (Version 2) as 7 - * published by the Free Software Foundation. 8 - * 9 - * This program is distributed in the hope it will be useful, but WITHOUT 10 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 - * for more details. 13 - * 14 - * You should have received a copy of the GNU General Public License along 15 - * with this program; if not, write to the Free Software Foundation, Inc., 16 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 17 - * 18 - * Putting things on the screen/serial line using YAMONs facilities. 19 - */ 20 - #include <linux/console.h> 21 - #include <linux/init.h> 22 - #include <linux/serial_reg.h> 23 - #include <asm/io.h> 24 - 25 - 26 - #define PORT(offset) (0x3f8 + (offset)) 27 - 28 - 29 - static inline unsigned int serial_in(int offset) 30 - { 31 - return inb(PORT(offset)); 32 - } 33 - 34 - static inline void serial_out(int offset, int value) 35 - { 36 - outb(value, PORT(offset)); 37 - } 38 - 39 - int prom_putchar(char c) 40 - { 41 - while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) 42 - ; 43 - 44 - serial_out(UART_TX, c); 45 - 46 - return 1; 47 - }
···
+33 -25
arch/mips/mti-malta/malta-init.c
··· 14 #include <linux/init.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 18 #include <asm/cacheflush.h> 19 #include <asm/smp-ops.h> ··· 45 char parity = '\0', bits = '\0', flow = '\0'; 46 char *s; 47 48 - if ((strstr(fw_getcmdline(), "console=")) == NULL) { 49 - s = fw_getenv("modetty0"); 50 - if (s) { 51 - while (*s >= '0' && *s <= '9') 52 - baud = baud*10 + *s++ - '0'; 53 - if (*s == ',') 54 - s++; 55 - if (*s) 56 - parity = *s++; 57 - if (*s == ',') 58 - s++; 59 - if (*s) 60 - bits = *s++; 61 - if (*s == ',') 62 - s++; 63 - if (*s == 'h') 64 - flow = 'r'; 65 - } 66 - if (baud == 0) 67 - baud = 38400; 68 - if (parity != 'n' && parity != 'o' && parity != 'e') 69 - parity = 'n'; 70 - if (bits != '7' && bits != '8') 71 - bits = '8'; 72 - if (flow == '\0') 73 flow = 'r'; 74 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 75 parity, bits, flow); 76 strcat(fw_getcmdline(), console_string);
··· 14 #include <linux/init.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 + #include <linux/serial_8250.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/smp-ops.h> ··· 44 char parity = '\0', bits = '\0', flow = '\0'; 45 char *s; 46 47 + s = fw_getenv("modetty0"); 48 + if (s) { 49 + while (*s >= '0' && *s <= '9') 50 + baud = baud*10 + *s++ - '0'; 51 + if (*s == ',') 52 + s++; 53 + if (*s) 54 + parity = *s++; 55 + if (*s == ',') 56 + s++; 57 + if (*s) 58 + bits = *s++; 59 + if (*s == ',') 60 + s++; 61 + if (*s == 'h') 62 flow = 'r'; 63 + } 64 + if (baud == 0) 65 + baud = 38400; 66 + if (parity != 'n' && parity != 'o' && parity != 'e') 67 + parity = 'n'; 68 + if (bits != '7' && bits != '8') 69 + bits = '8'; 70 + if (flow == '\0') 71 + flow = 'r'; 72 + 73 + if ((strstr(fw_getcmdline(), "earlycon=")) == NULL) { 74 + sprintf(console_string, "uart8250,io,0x3f8,%d%c%c", baud, 75 + parity, bits); 76 + setup_early_serial8250_console(console_string); 77 + } 78 + 79 + if ((strstr(fw_getcmdline(), "console=")) == NULL) { 80 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, 81 parity, bits, flow); 82 strcat(fw_getcmdline(), console_string);
+68 -59
arch/mips/mti-malta/malta-int.c
··· 1 /* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. 4 * Copyright (C) 2001 Ralf Baechle 5 - * 6 - * This program is free software; you can distribute it and/or modify it 7 - * under the terms of the GNU General Public License (Version 2) as 8 - * published by the Free Software Foundation. 9 - * 10 - * This program is distributed in the hope it will be useful, but WITHOUT 11 - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 - * for more details. 14 - * 15 - * You should have received a copy of the GNU General Public License along 16 - * with this program; if not, write to the Free Software Foundation, Inc., 17 - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 18 * 19 * Routines for generic manipulation of the interrupts found on the MIPS 20 - * Malta board. 21 - * The interrupt controller is located in the South Bridge a PIIX4 device 22 - * with two internal 82C95 interrupt controllers. 23 */ 24 #include <linux/init.h> 25 #include <linux/irq.h> ··· 35 #include <asm/gic.h> 36 #include <asm/gcmpregs.h> 37 #include <asm/setup.h> 38 39 int gcmp_present = -1; 40 static unsigned long _msc01_biu_base; ··· 82 BONITO_PCIMAP_CFG = 0; 83 break; 84 default: 85 - printk(KERN_WARNING "Unknown system controller.\n"); 86 return -1; 87 } 88 return irq; ··· 118 } 119 120 do_IRQ(MALTA_INT_BASE + irq); 121 } 122 123 static void malta_ipi_irqdispatch(void) ··· 146 unsigned int intrcause, datalo, datahi; 147 struct pt_regs *regs = get_irq_regs(); 148 149 - printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n"); 150 - printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n" 151 - "Cause : %08lx\nbadVaddr : %08lx\n", 152 - regs->cp0_epc, regs->cp0_status, 153 - regs->cp0_cause, regs->cp0_badvaddr); 154 155 /* Read all the registers and then print them as there is a 156 problem with interspersed printk's upsetting the Bonito controller. ··· 168 intrcause = GT_READ(GT_INTRCAUSE_OFS); 169 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 170 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 171 - printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause); 172 - printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n", 173 datahi, datalo); 174 break; 175 case MIPS_REVISION_SCON_BONITO: ··· 181 intedge = BONITO_INTEDGE; 182 intsteer = BONITO_INTSTEER; 183 pcicmd = BONITO_PCICMD; 184 - printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr); 185 - printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten); 186 - printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol); 187 - printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge); 188 - printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer); 189 - printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd); 190 - printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr); 191 - printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat); 192 break; 193 } 194 ··· 310 311 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 312 { 313 scheduler_ipi(); 314 315 return IRQ_HANDLED; ··· 367 .flags = IRQF_NO_THREAD, 368 }; 369 370 - static msc_irqmap_t __initdata msc_irqmap[] = { 371 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, 372 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, 373 }; 374 - static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap); 375 376 - static msc_irqmap_t __initdata msc_eicirqmap[] = { 377 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, 378 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, 379 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, ··· 386 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} 387 }; 388 389 - static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); 390 391 /* 392 * This GIC specific tabular array defines the association between External ··· 433 if (gcmp_present >= 0) 434 return gcmp_present; 435 436 - _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); 437 - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); 438 - gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; 439 440 if (gcmp_present) 441 pr_debug("GCMP present\n"); ··· 448 /* Return the number of IOCU's present */ 449 int __init gcmp_niocu(void) 450 { 451 - return gcmp_present ? 452 - (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : 453 - 0; 454 } 455 456 /* Set GCMP region attributes */ ··· 598 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); 599 } 600 /* Argh.. this really needs sorting out.. */ 601 - printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status()); 602 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); 603 - printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status()); 604 write_c0_status(0x1100dc00); 605 - printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); 606 for (i = 0; i < nr_cpu_ids; i++) { 607 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 608 GIC_RESCHED_INT(i), &irq_resched); ··· 623 cpu_ipi_call_irq = MSC01E_INT_SW1; 624 } else { 625 if (cpu_has_vint) { 626 - set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); 627 - set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); 628 } 629 - cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; 630 - cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; 631 } 632 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 633 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); ··· 641 642 void malta_be_init(void) 643 { 644 - if (gcmp_present) { 645 - /* Could change CM error mask register */ 646 - } 647 } 648 649 ··· 721 if (cause < 16) { 722 unsigned long cca_bits = (cm_error >> 15) & 7; 723 unsigned long tr_bits = (cm_error >> 12) & 7; 724 - unsigned long mcmd_bits = (cm_error >> 7) & 0x1f; 725 unsigned long stag_bits = (cm_error >> 3) & 15; 726 unsigned long sport_bits = (cm_error >> 0) & 7; 727 728 snprintf(buf, sizeof(buf), 729 "CCA=%lu TR=%s MCmd=%s STag=%lu " 730 "SPort=%lu\n", 731 - cca_bits, tr[tr_bits], mcmd[mcmd_bits], 732 stag_bits, sport_bits); 733 } else { 734 /* glob state & sresp together */ ··· 737 unsigned long c1_bits = (cm_error >> 12) & 7; 738 unsigned long c0_bits = (cm_error >> 9) & 7; 739 unsigned long sc_bit = (cm_error >> 8) & 1; 740 - unsigned long mcmd_bits = (cm_error >> 3) & 0x1f; 741 unsigned long sport_bits = (cm_error >> 0) & 7; 742 snprintf(buf, sizeof(buf), 743 "C3=%s C2=%s C1=%s C0=%s SC=%s " ··· 745 core[c3_bits], core[c2_bits], 746 core[c1_bits], core[c0_bits], 747 sc_bit ? "True" : "False", 748 - mcmd[mcmd_bits], sport_bits); 749 } 750 751 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> 752 GCMP_GCB_GMEO_ERROR_2ND_SHF; 753 754 - printk("CM_ERROR=%08lx %s <%s>\n", cm_error, 755 causes[cause], buf); 756 - printk("CM_ADDR =%08lx\n", cm_addr); 757 - printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); 758 759 /* reprime cause register */ 760 GCMPGCB(GCMEC) = 0;
··· 1 /* 2 + * This file is subject to the terms and conditions of the GNU General Public 3 + * License. See the file "COPYING" in the main directory of this archive 4 + * for more details. 5 + * 6 * Carsten Langgaard, carstenl@mips.com 7 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. 8 * Copyright (C) 2001 Ralf Baechle 9 + * Copyright (C) 2013 Imagination Technologies Ltd. 10 * 11 * Routines for generic manipulation of the interrupts found on the MIPS 12 + * Malta board. The interrupt controller is located in the South Bridge 13 + * a PIIX4 device with two internal 82C95 interrupt controllers. 14 */ 15 #include <linux/init.h> 16 #include <linux/irq.h> ··· 44 #include <asm/gic.h> 45 #include <asm/gcmpregs.h> 46 #include <asm/setup.h> 47 + #include <asm/rtlx.h> 48 49 int gcmp_present = -1; 50 static unsigned long _msc01_biu_base; ··· 90 BONITO_PCIMAP_CFG = 0; 91 break; 92 default: 93 + pr_emerg("Unknown system controller.\n"); 94 return -1; 95 } 96 return irq; ··· 126 } 127 128 do_IRQ(MALTA_INT_BASE + irq); 129 + 130 + #ifdef MIPS_VPE_APSP_API 131 + if (aprp_hook) 132 + aprp_hook(); 133 + #endif 134 } 135 136 static void malta_ipi_irqdispatch(void) ··· 149 unsigned int intrcause, datalo, datahi; 150 struct pt_regs *regs = get_irq_regs(); 151 152 + pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n"); 153 + pr_emerg("epc : %08lx\nStatus: %08lx\n" 154 + "Cause : %08lx\nbadVaddr : %08lx\n", 155 + regs->cp0_epc, regs->cp0_status, 156 + regs->cp0_cause, regs->cp0_badvaddr); 157 158 /* Read all the registers and then print them as there is a 159 problem with interspersed printk's upsetting the Bonito controller. ··· 171 intrcause = GT_READ(GT_INTRCAUSE_OFS); 172 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS); 173 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS); 174 + pr_emerg("GT_INTRCAUSE = %08x\n", intrcause); 175 + pr_emerg("GT_CPUERR_ADDR = %02x%08x\n", 176 datahi, datalo); 177 break; 178 case MIPS_REVISION_SCON_BONITO: ··· 184 intedge = BONITO_INTEDGE; 185 intsteer = BONITO_INTSTEER; 186 pcicmd = BONITO_PCICMD; 187 + pr_emerg("BONITO_INTISR = %08x\n", intisr); 188 + pr_emerg("BONITO_INTEN = %08x\n", inten); 189 + pr_emerg("BONITO_INTPOL = %08x\n", intpol); 190 + pr_emerg("BONITO_INTEDGE = %08x\n", intedge); 191 + pr_emerg("BONITO_INTSTEER = %08x\n", intsteer); 192 + pr_emerg("BONITO_PCICMD = %08x\n", pcicmd); 193 + pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr); 194 + pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat); 195 break; 196 } 197 ··· 313 314 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) 315 { 316 + #ifdef MIPS_VPE_APSP_API 317 + if (aprp_hook) 318 + aprp_hook(); 319 + #endif 320 + 321 scheduler_ipi(); 322 323 return IRQ_HANDLED; ··· 365 .flags = IRQF_NO_THREAD, 366 }; 367 368 + static msc_irqmap_t msc_irqmap[] __initdata = { 369 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0}, 370 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0}, 371 }; 372 + static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap); 373 374 + static msc_irqmap_t msc_eicirqmap[] __initdata = { 375 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0}, 376 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0}, 377 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0}, ··· 384 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0} 385 }; 386 387 + static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap); 388 389 /* 390 * This GIC specific tabular array defines the association between External ··· 431 if (gcmp_present >= 0) 432 return gcmp_present; 433 434 + _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, 435 + GCMP_ADDRSPACE_SZ); 436 + _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, 437 + MSC01_BIU_ADDRSPACE_SZ); 438 + gcmp_present = ((GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == 439 + GCMP_BASE_ADDR); 440 441 if (gcmp_present) 442 pr_debug("GCMP present\n"); ··· 443 /* Return the number of IOCU's present */ 444 int __init gcmp_niocu(void) 445 { 446 + return gcmp_present ? ((GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> 447 + GCMP_GCB_GC_NUMIOCU_SHF) : 0; 448 } 449 450 /* Set GCMP region attributes */ ··· 594 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch); 595 } 596 /* Argh.. this really needs sorting out.. */ 597 + pr_info("CPU%d: status register was %08x\n", 598 + smp_processor_id(), read_c0_status()); 599 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4); 600 + pr_info("CPU%d: status register now %08x\n", 601 + smp_processor_id(), read_c0_status()); 602 write_c0_status(0x1100dc00); 603 + pr_info("CPU%d: status register frc %08x\n", 604 + smp_processor_id(), read_c0_status()); 605 for (i = 0; i < nr_cpu_ids; i++) { 606 arch_init_ipiirq(MIPS_GIC_IRQ_BASE + 607 GIC_RESCHED_INT(i), &irq_resched); ··· 616 cpu_ipi_call_irq = MSC01E_INT_SW1; 617 } else { 618 if (cpu_has_vint) { 619 + set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, 620 + ipi_resched_dispatch); 621 + set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, 622 + ipi_call_dispatch); 623 } 624 + cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + 625 + MIPS_CPU_IPI_RESCHED_IRQ; 626 + cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + 627 + MIPS_CPU_IPI_CALL_IRQ; 628 } 629 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); 630 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); ··· 630 631 void malta_be_init(void) 632 { 633 + /* Could change CM error mask register. */ 634 } 635 636 ··· 712 if (cause < 16) { 713 unsigned long cca_bits = (cm_error >> 15) & 7; 714 unsigned long tr_bits = (cm_error >> 12) & 7; 715 + unsigned long cmd_bits = (cm_error >> 7) & 0x1f; 716 unsigned long stag_bits = (cm_error >> 3) & 15; 717 unsigned long sport_bits = (cm_error >> 0) & 7; 718 719 snprintf(buf, sizeof(buf), 720 "CCA=%lu TR=%s MCmd=%s STag=%lu " 721 "SPort=%lu\n", 722 + cca_bits, tr[tr_bits], mcmd[cmd_bits], 723 stag_bits, sport_bits); 724 } else { 725 /* glob state & sresp together */ ··· 728 unsigned long c1_bits = (cm_error >> 12) & 7; 729 unsigned long c0_bits = (cm_error >> 9) & 7; 730 unsigned long sc_bit = (cm_error >> 8) & 1; 731 + unsigned long cmd_bits = (cm_error >> 3) & 0x1f; 732 unsigned long sport_bits = (cm_error >> 0) & 7; 733 snprintf(buf, sizeof(buf), 734 "C3=%s C2=%s C1=%s C0=%s SC=%s " ··· 736 core[c3_bits], core[c2_bits], 737 core[c1_bits], core[c0_bits], 738 sc_bit ? "True" : "False", 739 + mcmd[cmd_bits], sport_bits); 740 } 741 742 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >> 743 GCMP_GCB_GMEO_ERROR_2ND_SHF; 744 745 + pr_err("CM_ERROR=%08lx %s <%s>\n", cm_error, 746 causes[cause], buf); 747 + pr_err("CM_ADDR =%08lx\n", cm_addr); 748 + pr_err("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]); 749 750 /* reprime cause register */ 751 GCMPGCB(GCMEC) = 0;
+2
arch/mips/mti-malta/malta-platform.c
··· 47 static struct plat_serial8250_port uart8250_data[] = { 48 SMC_PORT(0x3F8, 4), 49 SMC_PORT(0x2F8, 3), 50 { 51 .mapbase = 0x1f000900, /* The CBUS UART */ 52 .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, ··· 56 .flags = CBUS_UART_FLAGS, 57 .regshift = 3, 58 }, 59 { }, 60 }; 61
··· 47 static struct plat_serial8250_port uart8250_data[] = { 48 SMC_PORT(0x3F8, 4), 49 SMC_PORT(0x2F8, 3), 50 + #ifndef CONFIG_MIPS_CMP 51 { 52 .mapbase = 0x1f000900, /* The CBUS UART */ 53 .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2, ··· 55 .flags = CBUS_UART_FLAGS, 56 .regshift = 3, 57 }, 58 + #endif 59 { }, 60 }; 61
+13 -3
arch/mips/mti-malta/malta-time.c
··· 42 #include <asm/mips-boards/generic.h> 43 #include <asm/mips-boards/maltaint.h> 44 45 - unsigned long cpu_khz; 46 - 47 static int mips_cpu_timer_irq; 48 static int mips_cpu_perf_irq; 49 extern int cp0_perfcount_irq; ··· 166 return mips_cpu_timer_irq; 167 } 168 169 void __init plat_time_init(void) 170 { 171 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 172 unsigned int freq; 173 174 estimate_frequencies(); 175 176 freq = mips_hpt_frequency; ··· 193 freq = freqround(freq, 5000); 194 printk("CPU frequency %d.%02d MHz\n", freq/1000000, 195 (freq%1000000)*100/1000000); 196 - cpu_khz = freq / 1000; 197 198 mips_scroll_message(); 199
··· 42 #include <asm/mips-boards/generic.h> 43 #include <asm/mips-boards/maltaint.h> 44 45 static int mips_cpu_timer_irq; 46 static int mips_cpu_perf_irq; 47 extern int cp0_perfcount_irq; ··· 168 return mips_cpu_timer_irq; 169 } 170 171 + static void __init init_rtc(void) 172 + { 173 + /* stop the clock whilst setting it up */ 174 + CMOS_WRITE(RTC_SET | RTC_24H, RTC_CONTROL); 175 + 176 + /* 32KHz time base */ 177 + CMOS_WRITE(RTC_REF_CLCK_32KHZ, RTC_FREQ_SELECT); 178 + 179 + /* start the clock */ 180 + CMOS_WRITE(RTC_24H, RTC_CONTROL); 181 + } 182 + 183 void __init plat_time_init(void) 184 { 185 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK); 186 unsigned int freq; 187 188 + init_rtc(); 189 estimate_frequencies(); 190 191 freq = mips_hpt_frequency; ··· 182 freq = freqround(freq, 5000); 183 printk("CPU frequency %d.%02d MHz\n", freq/1000000, 184 (freq%1000000)*100/1000000); 185 186 mips_scroll_message(); 187
+2
arch/mips/mti-sead3/Makefile
··· 21 obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o 22 obj-$(CONFIG_OF) += sead3.dtb.o 23 24 $(obj)/%.dtb: $(obj)/%.dts 25 $(call if_changed,dtc)
··· 21 obj-$(CONFIG_USB_EHCI_HCD) += sead3-ehci.o 22 obj-$(CONFIG_OF) += sead3.dtb.o 23 24 + CFLAGS_sead3-setup.o = -I$(src)/../../../scripts/dtc/libfdt 25 + 26 $(obj)/%.dtb: $(obj)/%.dts 27 $(call if_changed,dtc)
-1
arch/mips/mti-sead3/sead3-pic32-bus.c
··· 8 #include <linux/delay.h> 9 #include <linux/kernel.h> 10 #include <linux/spinlock.h> 11 - #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/errno.h> 14
··· 8 #include <linux/delay.h> 9 #include <linux/kernel.h> 10 #include <linux/spinlock.h> 11 #include <linux/io.h> 12 #include <linux/errno.h> 13
+76 -10
arch/mips/mti-sead3/sead3-setup.c
··· 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 */ 8 #include <linux/init.h> 9 #include <linux/of_platform.h> 10 #include <linux/of_fdt.h> 11 - #include <linux/bootmem.h> 12 13 #include <asm/prom.h> 14 15 #include <asm/mips-boards/generic.h> 16 ··· 21 return "MIPS SEAD3"; 22 } 23 24 void __init plat_mem_setup(void) 25 { 26 /* 27 * Load the builtin devicetree. This causes the chosen node to be 28 * parsed resulting in our memory appearing ··· 97 98 void __init device_tree_init(void) 99 { 100 - unsigned long base, size; 101 - 102 if (!initial_boot_params) 103 return; 104 105 - base = virt_to_phys((void *)initial_boot_params); 106 - size = be32_to_cpu(initial_boot_params->totalsize); 107 - 108 - /* Before we do anything, lets reserve the dt blob */ 109 - reserve_bootmem(base, size, BOOTMEM_DEFAULT); 110 - 111 - unflatten_device_tree(); 112 }
··· 4 * for more details. 5 * 6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. 7 + * Copyright (C) 2013 Imagination Technologies Ltd. 8 */ 9 #include <linux/init.h> 10 + #include <linux/libfdt.h> 11 #include <linux/of_platform.h> 12 #include <linux/of_fdt.h> 13 14 #include <asm/prom.h> 15 + #include <asm/fw/fw.h> 16 17 #include <asm/mips-boards/generic.h> 18 ··· 19 return "MIPS SEAD3"; 20 } 21 22 + static uint32_t get_memsize_from_cmdline(void) 23 + { 24 + int memsize = 0; 25 + char *p = arcs_cmdline; 26 + char *s = "memsize="; 27 + 28 + p = strstr(p, s); 29 + if (p) { 30 + p += strlen(s); 31 + memsize = memparse(p, NULL); 32 + } 33 + 34 + return memsize; 35 + } 36 + 37 + static uint32_t get_memsize_from_env(void) 38 + { 39 + int memsize = 0; 40 + char *p; 41 + 42 + p = fw_getenv("memsize"); 43 + if (p) 44 + memsize = memparse(p, NULL); 45 + 46 + return memsize; 47 + } 48 + 49 + static uint32_t get_memsize(void) 50 + { 51 + uint32_t memsize; 52 + 53 + memsize = get_memsize_from_cmdline(); 54 + if (memsize) 55 + return memsize; 56 + 57 + return get_memsize_from_env(); 58 + } 59 + 60 + static void __init parse_memsize_param(void) 61 + { 62 + int offset; 63 + const uint64_t *prop_value; 64 + int prop_len; 65 + uint32_t memsize = get_memsize(); 66 + 67 + if (!memsize) 68 + return; 69 + 70 + offset = fdt_path_offset(&__dtb_start, "/memory"); 71 + if (offset > 0) { 72 + uint64_t new_value; 73 + /* 74 + * reg contains 2 32-bits BE values, offset and size. We just 75 + * want to replace the size value without affecting the offset 76 + */ 77 + prop_value = fdt_getprop(&__dtb_start, offset, "reg", &prop_len); 78 + new_value = be64_to_cpu(*prop_value); 79 + new_value = (new_value & ~0xffffffffllu) | memsize; 80 + fdt_setprop_inplace_u64(&__dtb_start, offset, "reg", new_value); 81 + } 82 + } 83 + 84 void __init plat_mem_setup(void) 85 { 86 + /* allow command line/bootloader env to override memory size in DT */ 87 + parse_memsize_param(); 88 + 89 /* 90 * Load the builtin devicetree. This causes the chosen node to be 91 * parsed resulting in our memory appearing ··· 30 31 void __init device_tree_init(void) 32 { 33 if (!initial_boot_params) 34 return; 35 36 + unflatten_and_copy_device_tree(); 37 } 38 + 39 + static int __init customize_machine(void) 40 + { 41 + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 42 + return 0; 43 + } 44 + arch_initcall(customize_machine);
-4
arch/mips/mti-sead3/sead3-time.c
··· 13 #include <asm/irq.h> 14 #include <asm/mips-boards/generic.h> 15 16 - unsigned long cpu_khz; 17 - 18 static int mips_cpu_timer_irq; 19 static int mips_cpu_perf_irq; 20 ··· 106 107 pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000), 108 (est_freq % 1000000) * 100 / 1000000); 109 - 110 - cpu_khz = est_freq / 1000; 111 112 mips_scroll_message(); 113
··· 13 #include <asm/irq.h> 14 #include <asm/mips-boards/generic.h> 15 16 static int mips_cpu_timer_irq; 17 static int mips_cpu_perf_irq; 18 ··· 108 109 pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000), 110 (est_freq % 1000000) * 100 / 1000000); 111 112 mips_scroll_message(); 113
-4
arch/mips/mti-sead3/sead3.dts
··· 15 }; 16 }; 17 18 - chosen { 19 - bootargs = "console=ttyS1,38400 rootdelay=10 root=/dev/sda3"; 20 - }; 21 - 22 memory { 23 device_type = "memory"; 24 reg = <0x0 0x08000000>;
··· 15 }; 16 }; 17 18 memory { 19 device_type = "memory"; 20 reg = <0x0 0x08000000>;
+9
arch/mips/netlogic/Kconfig
··· 28 pointer to the kernel. The corresponding DTS file is at 29 arch/mips/netlogic/dts/xlp_fvp.dts 30 31 config NLM_MULTINODE 32 bool "Support for multi-chip boards" 33 depends on NLM_XLP_BOARD
··· 28 pointer to the kernel. The corresponding DTS file is at 29 arch/mips/netlogic/dts/xlp_fvp.dts 30 31 + config DT_XLP_GVP 32 + bool "Built-in device tree for XLP GVP boards" 33 + default y 34 + help 35 + Add an FDT blob for XLP GVP board into the kernel. 36 + This DTB will be used if the firmware does not pass in a DTB 37 + pointer to the kernel. The corresponding DTS file is at 38 + arch/mips/netlogic/dts/xlp_gvp.dts 39 + 40 config NLM_MULTINODE 41 bool "Support for multi-chip boards" 42 depends on NLM_XLP_BOARD
+2
arch/mips/netlogic/common/earlycons.c
··· 37 38 #include <asm/mipsregs.h> 39 #include <asm/netlogic/haldefs.h> 40 41 #if defined(CONFIG_CPU_XLP) 42 #include <asm/netlogic/xlp-hal/iomap.h> 43 #include <asm/netlogic/xlp-hal/uart.h> 44 #elif defined(CONFIG_CPU_XLR) 45 #include <asm/netlogic/xlr/iomap.h>
··· 37 38 #include <asm/mipsregs.h> 39 #include <asm/netlogic/haldefs.h> 40 + #include <asm/netlogic/common.h> 41 42 #if defined(CONFIG_CPU_XLP) 43 #include <asm/netlogic/xlp-hal/iomap.h> 44 + #include <asm/netlogic/xlp-hal/xlp.h> 45 #include <asm/netlogic/xlp-hal/uart.h> 46 #elif defined(CONFIG_CPU_XLR) 47 #include <asm/netlogic/xlr/iomap.h>
+55 -17
arch/mips/netlogic/common/irq.c
··· 180 #endif 181 } 182 183 void nlm_setup_pic_irq(int node, int picirq, int irq, int irt) 184 { 185 struct nlm_pic_irq *pic_data; ··· 208 209 static void nlm_init_node_irqs(int node) 210 { 211 - int i, irt; 212 - uint64_t irqmask; 213 struct nlm_soc_info *nodep; 214 215 pr_info("Init IRQ for node %d\n", node); 216 nodep = nlm_get_node(node); 217 - irqmask = PERCPU_IRQ_MASK; 218 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) { 219 irt = nlm_irq_to_irt(i); 220 - if (irt == -1) 221 continue; 222 - nlm_setup_pic_irq(node, i, i, irt); 223 - /* set interrupts to first cpu in node */ 224 nlm_pic_init_irt(nodep->picbase, irt, i, 225 - node * NLM_CPUS_PER_NODE, 0); 226 - irqmask |= (1ull << i); 227 } 228 - nodep->irqmask = irqmask; 229 } 230 231 void nlm_smp_irq_init(int hwcpuid) 232 { 233 int node, cpu; 234 235 - node = hwcpuid / NLM_CPUS_PER_NODE; 236 - cpu = hwcpuid % NLM_CPUS_PER_NODE; 237 238 if (cpu == 0 && node != 0) 239 nlm_init_node_irqs(node); ··· 257 return; 258 } 259 260 /* top level irq handling */ 261 do_IRQ(nlm_irq_to_xirq(node, i)); 262 } 263 264 #ifdef CONFIG_OF 265 - static struct irq_domain *xlp_pic_domain; 266 - 267 static const struct irq_domain_ops xlp_pic_irq_domain_ops = { 268 .xlate = irq_domain_xlate_onetwocell, 269 }; ··· 282 struct device_node *parent) 283 { 284 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1; 285 struct resource res; 286 - int socid, ret; 287 288 /* we need a hack to get the PIC's SoC chip id */ 289 ret = of_address_to_resource(node, 0, &res); ··· 292 pr_err("PIC %s: reg property not found!\n", node->name); 293 return -EINVAL; 294 } 295 - socid = (res.start >> 18) & 0x3; 296 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs, 297 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, 298 &xlp_pic_irq_domain_ops, NULL); ··· 327 pr_err("PIC %s: Creating legacy domain failed!\n", node->name); 328 return -EINVAL; 329 } 330 - pr_info("Node %d: IRQ domain created for PIC@%pa\n", socid, 331 - &res.start); 332 return 0; 333 } 334
··· 180 #endif 181 } 182 183 + 184 void nlm_setup_pic_irq(int node, int picirq, int irq, int irt) 185 { 186 struct nlm_pic_irq *pic_data; ··· 207 208 static void nlm_init_node_irqs(int node) 209 { 210 struct nlm_soc_info *nodep; 211 + int i, irt; 212 213 pr_info("Init IRQ for node %d\n", node); 214 nodep = nlm_get_node(node); 215 + nodep->irqmask = PERCPU_IRQ_MASK; 216 for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) { 217 irt = nlm_irq_to_irt(i); 218 + if (irt == -1) /* unused irq */ 219 continue; 220 + nodep->irqmask |= 1ull << i; 221 + if (irt == -2) /* not a direct PIC irq */ 222 + continue; 223 + 224 nlm_pic_init_irt(nodep->picbase, irt, i, 225 + node * nlm_threads_per_node(), 0); 226 + nlm_setup_pic_irq(node, i, i, irt); 227 } 228 } 229 230 void nlm_smp_irq_init(int hwcpuid) 231 { 232 int node, cpu; 233 234 + node = nlm_cpuid_to_node(hwcpuid); 235 + cpu = hwcpuid % nlm_threads_per_node(); 236 237 if (cpu == 0 && node != 0) 238 nlm_init_node_irqs(node); ··· 256 return; 257 } 258 259 + #if defined(CONFIG_PCI_MSI) && defined(CONFIG_CPU_XLP) 260 + /* PCI interrupts need a second level dispatch for MSI bits */ 261 + if (i >= PIC_PCIE_LINK_MSI_IRQ(0) && i <= PIC_PCIE_LINK_MSI_IRQ(3)) { 262 + nlm_dispatch_msi(node, i); 263 + return; 264 + } 265 + if (i >= PIC_PCIE_MSIX_IRQ(0) && i <= PIC_PCIE_MSIX_IRQ(3)) { 266 + nlm_dispatch_msix(node, i); 267 + return; 268 + } 269 + 270 + #endif 271 /* top level irq handling */ 272 do_IRQ(nlm_irq_to_xirq(node, i)); 273 } 274 275 #ifdef CONFIG_OF 276 static const struct irq_domain_ops xlp_pic_irq_domain_ops = { 277 .xlate = irq_domain_xlate_onetwocell, 278 }; ··· 271 struct device_node *parent) 272 { 273 const int n_picirqs = PIC_IRT_LAST_IRQ - PIC_IRQ_BASE + 1; 274 + struct irq_domain *xlp_pic_domain; 275 struct resource res; 276 + int socid, ret, bus; 277 278 /* we need a hack to get the PIC's SoC chip id */ 279 ret = of_address_to_resource(node, 0, &res); ··· 280 pr_err("PIC %s: reg property not found!\n", node->name); 281 return -EINVAL; 282 } 283 + 284 + if (cpu_is_xlp9xx()) { 285 + bus = (res.start >> 20) & 0xf; 286 + for (socid = 0; socid < NLM_NR_NODES; socid++) { 287 + if (!nlm_node_present(socid)) 288 + continue; 289 + if (nlm_get_node(socid)->socbus == bus) 290 + break; 291 + } 292 + if (socid == NLM_NR_NODES) { 293 + pr_err("PIC %s: Node mapping for bus %d not found!\n", 294 + node->name, bus); 295 + return -EINVAL; 296 + } 297 + } else { 298 + socid = (res.start >> 18) & 0x3; 299 + if (!nlm_node_present(socid)) { 300 + pr_err("PIC %s: node %d does not exist!\n", 301 + node->name, socid); 302 + return -EINVAL; 303 + } 304 + } 305 + 306 + if (!nlm_node_present(socid)) { 307 + pr_err("PIC %s: node %d does not exist!\n", node->name, socid); 308 + return -EINVAL; 309 + } 310 + 311 xlp_pic_domain = irq_domain_add_legacy(node, n_picirqs, 312 nlm_irq_to_xirq(socid, PIC_IRQ_BASE), PIC_IRQ_BASE, 313 &xlp_pic_irq_domain_ops, NULL); ··· 288 pr_err("PIC %s: Creating legacy domain failed!\n", node->name); 289 return -EINVAL; 290 } 291 + pr_info("Node %d: IRQ domain created for PIC@%pR\n", socid, &res); 292 return 0; 293 } 294
+46 -17
arch/mips/netlogic/common/reset.S
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 - #include <linux/init.h> 36 37 #include <asm/asm.h> 38 #include <asm/asm-offsets.h> 39 #include <asm/regdef.h> 40 #include <asm/mipsregs.h> 41 #include <asm/stackframe.h> ··· 50 #include <asm/netlogic/xlp-hal/cpucontrol.h> 51 52 #define CP0_EBASE $15 53 - #define SYS_CPU_COHERENT_BASE(node) CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 54 - XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \ 55 SYS_CPU_NONCOHERENT_MODE * 4 56 57 /* Enable XLP features and workarounds in the LSU */ ··· 74 .endm 75 76 /* 77 - * Low level flush for L1D cache on XLP, the normal cache ops does 78 - * not do the complete and correct cache flush. 79 */ 80 .macro xlp_flush_l1_dcache 81 li t0, LSU_DEBUG_DATA0 82 li t1, LSU_DEBUG_ADDR 83 li t2, 0 /* index */ 84 li t3, 0x1000 /* loop count */ 85 - 1: 86 sll v0, t2, 5 87 mtcr zero, t0 88 ori v1, v0, 0x3 /* way0 | write_enable | write_active */ 89 mtcr v1, t1 90 - 2: 91 mfcr v1, t1 92 andi v1, 0x1 /* wait for write_active == 0 */ 93 - bnez v1, 2b 94 nop 95 mtcr zero, t0 96 ori v1, v0, 0x7 /* way1 | write_enable | write_active */ 97 mtcr v1, t1 98 - 3: 99 mfcr v1, t1 100 andi v1, 0x1 /* wait for write_active == 0 */ 101 - bnez v1, 3b 102 nop 103 addi t2, 1 104 - bne t3, t2, 1b 105 nop 106 .endm 107 108 /* ··· 158 nop 159 160 1: /* Entry point on core wakeup */ 161 mfc0 t0, CP0_EBASE, 1 162 mfc0 t1, CP0_EBASE, 1 163 srl t1, 5 ··· 176 li t1, 0x1 177 sll t0, t1, t0 178 nor t0, t0, zero /* t0 <- ~(1 << core) */ 179 - li t2, SYS_CPU_COHERENT_BASE(0) 180 add t2, t2, t3 /* t2 <- SYS offset for node */ 181 lw t1, 0(t2) 182 and t1, t1, t0 ··· 186 lw t1, 0(t2) 187 sync 188 189 /* Configure LSU on Non-0 Cores. */ 190 xlp_config_lsu 191 /* FALL THROUGH */ 192 193 /* 194 - * Wake up sibling threads from the initial thread in 195 - * a core. 196 */ 197 EXPORT(nlm_boot_siblings) 198 /* core L1D flush before enable threads */ ··· 208 /* 209 * The new hardware thread starts at the next instruction 210 * For all the cases other than core 0 thread 0, we will 211 - * jump to the secondary wait function. 212 - */ 213 mfc0 v0, CP0_EBASE, 1 214 andi v0, 0x3ff /* v0 <- node/core */ 215 ··· 225 #endif 226 mtc0 t1, CP0_STATUS 227 228 - /* mark CPU ready, careful here, previous mtcr trashed registers */ 229 li t3, CKSEG1ADDR(RESET_DATA_PHYS) 230 ADDIU t1, t3, BOOT_CPU_READY 231 sll v1, v0, 2
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 36 #include <asm/asm.h> 37 #include <asm/asm-offsets.h> 38 + #include <asm/cacheops.h> 39 #include <asm/regdef.h> 40 #include <asm/mipsregs.h> 41 #include <asm/stackframe.h> ··· 50 #include <asm/netlogic/xlp-hal/cpucontrol.h> 51 52 #define CP0_EBASE $15 53 + #define SYS_CPU_COHERENT_BASE CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \ 54 + XLP_IO_SYS_OFFSET(0) + XLP_IO_PCI_HDRSZ + \ 55 SYS_CPU_NONCOHERENT_MODE * 4 56 57 /* Enable XLP features and workarounds in the LSU */ ··· 74 .endm 75 76 /* 77 + * L1D cache has to be flushed before enabling threads in XLP. 78 + * On XLP8xx/XLP3xx, we do a low level flush using processor control 79 + * registers. On XLPII CPUs, usual cache instructions work. 80 */ 81 .macro xlp_flush_l1_dcache 82 + mfc0 t0, CP0_EBASE, 0 83 + andi t0, t0, 0xff00 84 + slt t1, t0, 0x1200 85 + beqz t1, 15f 86 + nop 87 + 88 + /* XLP8xx low level cache flush */ 89 li t0, LSU_DEBUG_DATA0 90 li t1, LSU_DEBUG_ADDR 91 li t2, 0 /* index */ 92 li t3, 0x1000 /* loop count */ 93 + 11: 94 sll v0, t2, 5 95 mtcr zero, t0 96 ori v1, v0, 0x3 /* way0 | write_enable | write_active */ 97 mtcr v1, t1 98 + 12: 99 mfcr v1, t1 100 andi v1, 0x1 /* wait for write_active == 0 */ 101 + bnez v1, 12b 102 nop 103 mtcr zero, t0 104 ori v1, v0, 0x7 /* way1 | write_enable | write_active */ 105 mtcr v1, t1 106 + 13: 107 mfcr v1, t1 108 andi v1, 0x1 /* wait for write_active == 0 */ 109 + bnez v1, 13b 110 nop 111 addi t2, 1 112 + bne t3, t2, 11b 113 nop 114 + b 17f 115 + nop 116 + 117 + /* XLPII CPUs, Invalidate all 64k of L1 D-cache */ 118 + 15: 119 + li t0, 0x80000000 120 + li t1, 0x80010000 121 + 16: cache Index_Writeback_Inv_D, 0(t0) 122 + addiu t0, t0, 32 123 + bne t0, t1, 16b 124 + nop 125 + 17: 126 .endm 127 128 /* ··· 138 nop 139 140 1: /* Entry point on core wakeup */ 141 + mfc0 t0, CP0_EBASE, 0 /* processor ID */ 142 + andi t0, 0xff00 143 + li t1, 0x1500 /* XLP 9xx */ 144 + beq t0, t1, 2f /* does not need to set coherent */ 145 + nop 146 + 147 + /* set bit in SYS coherent register for the core */ 148 mfc0 t0, CP0_EBASE, 1 149 mfc0 t1, CP0_EBASE, 1 150 srl t1, 5 ··· 149 li t1, 0x1 150 sll t0, t1, t0 151 nor t0, t0, zero /* t0 <- ~(1 << core) */ 152 + li t2, SYS_CPU_COHERENT_BASE 153 add t2, t2, t3 /* t2 <- SYS offset for node */ 154 lw t1, 0(t2) 155 and t1, t1, t0 ··· 159 lw t1, 0(t2) 160 sync 161 162 + 2: 163 /* Configure LSU on Non-0 Cores. */ 164 xlp_config_lsu 165 /* FALL THROUGH */ 166 167 /* 168 + * Wake up sibling threads from the initial thread in a core. 169 */ 170 EXPORT(nlm_boot_siblings) 171 /* core L1D flush before enable threads */ ··· 181 /* 182 * The new hardware thread starts at the next instruction 183 * For all the cases other than core 0 thread 0, we will 184 + * jump to the secondary wait function. 185 + 186 + * NOTE: All GPR contents are lost after the mtcr above! 187 + */ 188 mfc0 v0, CP0_EBASE, 1 189 andi v0, 0x3ff /* v0 <- node/core */ 190 ··· 196 #endif 197 mtc0 t1, CP0_STATUS 198 199 + /* mark CPU ready */ 200 li t3, CKSEG1ADDR(RESET_DATA_PHYS) 201 ADDIU t1, t3, BOOT_CPU_READY 202 sll v1, v0, 2
+5 -3
arch/mips/netlogic/common/smp.c
··· 63 uint64_t picbase; 64 65 cpu = cpu_logical_map(logical_cpu); 66 - node = cpu / NLM_CPUS_PER_NODE; 67 picbase = nlm_get_node(node)->picbase; 68 69 if (action & SMP_CALL_FUNCTION) ··· 152 int cpu, node; 153 154 cpu = cpu_logical_map(logical_cpu); 155 - node = cpu / NLM_CPUS_PER_NODE; 156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle); 157 nlm_next_gp = (unsigned long)task_thread_info(idle); 158 ··· 164 void __init nlm_smp_setup(void) 165 { 166 unsigned int boot_cpu; 167 - int num_cpus, i, ncore; 168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 169 char buf[64]; 170 ··· 187 __cpu_number_map[i] = num_cpus; 188 __cpu_logical_map[num_cpus] = i; 189 set_cpu_possible(num_cpus, true); 190 ++num_cpus; 191 } 192 }
··· 63 uint64_t picbase; 64 65 cpu = cpu_logical_map(logical_cpu); 66 + node = nlm_cpuid_to_node(cpu); 67 picbase = nlm_get_node(node)->picbase; 68 69 if (action & SMP_CALL_FUNCTION) ··· 152 int cpu, node; 153 154 cpu = cpu_logical_map(logical_cpu); 155 + node = nlm_cpuid_to_node(logical_cpu); 156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle); 157 nlm_next_gp = (unsigned long)task_thread_info(idle); 158 ··· 164 void __init nlm_smp_setup(void) 165 { 166 unsigned int boot_cpu; 167 + int num_cpus, i, ncore, node; 168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 169 char buf[64]; 170 ··· 187 __cpu_number_map[i] = num_cpus; 188 __cpu_logical_map[num_cpus] = i; 189 set_cpu_possible(num_cpus, true); 190 + node = nlm_cpuid_to_node(i); 191 + cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask); 192 ++num_cpus; 193 } 194 }
+2 -2
arch/mips/netlogic/common/smpboot.S
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 - #include <linux/init.h> 36 37 #include <asm/asm.h> 38 #include <asm/asm-offsets.h> ··· 97 * In case of RMIboot bootloader which is used on XLR boards, the CPUs 98 * be already woken up and waiting in bootloader code. 99 * This will get them out of the bootloader code and into linux. Needed 100 - * because the bootloader area will be taken and initialized by linux. 101 */ 102 NESTED(nlm_rmiboot_preboot, 16, sp) 103 mfc0 t0, $15, 1 /* read ebase */ ··· 132 or t1, t2, v1 /* put in new value */ 133 mtcr t1, t0 /* update core control */ 134 135 1: wait 136 b 1b 137 nop
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 36 #include <asm/asm.h> 37 #include <asm/asm-offsets.h> ··· 98 * In case of RMIboot bootloader which is used on XLR boards, the CPUs 99 * be already woken up and waiting in bootloader code. 100 * This will get them out of the bootloader code and into linux. Needed 101 + * because the bootloader area will be taken and initialized by linux. 102 */ 103 NESTED(nlm_rmiboot_preboot, 16, sp) 104 mfc0 t0, $15, 1 /* read ebase */ ··· 133 or t1, t2, v1 /* put in new value */ 134 mtcr t1, t0 /* update core control */ 135 136 + /* wait for NMI to hit */ 137 1: wait 138 b 1b 139 nop
+1
arch/mips/netlogic/dts/Makefile
··· 1 obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o 2 obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o 3 obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o
··· 1 obj-$(CONFIG_DT_XLP_EVP) := xlp_evp.dtb.o 2 obj-$(CONFIG_DT_XLP_SVP) += xlp_svp.dtb.o 3 obj-$(CONFIG_DT_XLP_FVP) += xlp_fvp.dtb.o 4 + obj-$(CONFIG_DT_XLP_GVP) += xlp_gvp.dtb.o
+76
arch/mips/netlogic/dts/xlp_gvp.dts
···
··· 1 + /* 2 + * XLP9XX Device Tree Source for GVP boards 3 + */ 4 + 5 + /dts-v1/; 6 + / { 7 + model = "netlogic,XLP-GVP"; 8 + compatible = "netlogic,xlp"; 9 + #address-cells = <2>; 10 + #size-cells = <2>; 11 + 12 + soc { 13 + #address-cells = <2>; 14 + #size-cells = <1>; 15 + compatible = "simple-bus"; 16 + ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG 17 + 1 0 0 0x16000000 0x02000000>; // GBU chipselects 18 + 19 + serial0: serial@30000 { 20 + device_type = "serial"; 21 + compatible = "ns16550"; 22 + reg = <0 0x112100 0xa00>; 23 + reg-shift = <2>; 24 + reg-io-width = <4>; 25 + clock-frequency = <125000000>; 26 + interrupt-parent = <&pic>; 27 + interrupts = <17>; 28 + }; 29 + pic: pic@4000 { 30 + interrupt-controller; 31 + #address-cells = <0>; 32 + #interrupt-cells = <1>; 33 + reg = <0 0x110000 0x200>; 34 + }; 35 + 36 + nor_flash@1,0 { 37 + compatible = "cfi-flash"; 38 + #address-cells = <1>; 39 + #size-cells = <1>; 40 + bank-width = <2>; 41 + reg = <1 0 0x1000000>; 42 + 43 + partition@0 { 44 + label = "x-loader"; 45 + reg = <0x0 0x100000>; /* 1M */ 46 + read-only; 47 + }; 48 + 49 + partition@100000 { 50 + label = "u-boot"; 51 + reg = <0x100000 0x100000>; /* 1M */ 52 + }; 53 + 54 + partition@200000 { 55 + label = "kernel"; 56 + reg = <0x200000 0x500000>; /* 5M */ 57 + }; 58 + 59 + partition@700000 { 60 + label = "rootfs"; 61 + reg = <0x700000 0x800000>; /* 8M */ 62 + }; 63 + 64 + partition@f00000 { 65 + label = "env"; 66 + reg = <0xf00000 0x100000>; /* 1M */ 67 + read-only; 68 + }; 69 + }; 70 + 71 + }; 72 + 73 + chosen { 74 + bootargs = "console=ttyS0,115200 rdinit=/sbin/init"; 75 + }; 76 + };
+6 -1
arch/mips/netlogic/xlp/dt.c
··· 42 #include <asm/prom.h> 43 44 extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], 45 - __dtb_xlp_fvp_begin[], __dtb_start[]; 46 static void *xlp_fdt_blob; 47 48 void __init *xlp_dt_init(void *fdtp) 49 { 50 if (!fdtp) { 51 switch (current_cpu_data.processor_id & 0xff00) { 52 #ifdef CONFIG_DT_XLP_FVP 53 case PRID_IMP_NETLOGIC_XLP2XX: 54 fdtp = __dtb_xlp_fvp_begin;
··· 42 #include <asm/prom.h> 43 44 extern u32 __dtb_xlp_evp_begin[], __dtb_xlp_svp_begin[], 45 + __dtb_xlp_fvp_begin[], __dtb_xlp_gvp_begin[], __dtb_start[]; 46 static void *xlp_fdt_blob; 47 48 void __init *xlp_dt_init(void *fdtp) 49 { 50 if (!fdtp) { 51 switch (current_cpu_data.processor_id & 0xff00) { 52 + #ifdef CONFIG_DT_XLP_GVP 53 + case PRID_IMP_NETLOGIC_XLP9XX: 54 + fdtp = __dtb_xlp_gvp_begin; 55 + break; 56 + #endif 57 #ifdef CONFIG_DT_XLP_FVP 58 case PRID_IMP_NETLOGIC_XLP2XX: 59 fdtp = __dtb_xlp_fvp_begin;
+61 -10
arch/mips/netlogic/xlp/nlm_hal.c
··· 57 nodep->sysbase = nlm_get_sys_regbase(node); 58 nodep->picbase = nlm_get_pic_regbase(node); 59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); 60 spin_lock_init(&nodep->piclock); 61 } 62 ··· 68 { 69 uint64_t pcibase; 70 int devoff, irt; 71 72 devoff = 0; 73 switch (irq) { ··· 159 case PIC_I2C_3_IRQ: 160 irt = irt + 3; break; 161 } 162 - } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) { 163 /* HW bug, PCI IRT entries are bad on early silicon, fix */ 164 - irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ); 165 } else { 166 irt = -1; 167 } ··· 183 uint64_t num, sysbase; 184 185 sysbase = nlm_get_node(node)->sysbase; 186 - rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); 187 if (cpu_is_xlpii()) { 188 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26)); 189 denom = 3; ··· 300 301 unsigned int nlm_get_pic_frequency(int node) 302 { 303 if (cpu_is_xlpii()) 304 return nlm_2xx_get_pic_frequency(node); 305 else ··· 323 { 324 uint64_t bridgebase, base, lim; 325 uint32_t val; 326 int i, node, rv; 327 328 /* Look only at mapping on Node 0, we don't handle crazy configs */ 329 bridgebase = nlm_get_bridge_regbase(0); 330 rv = 0; 331 for (i = 0; i < 8; i++) { 332 - val = nlm_read_bridge_reg(bridgebase, 333 - BRIDGE_DRAM_NODE_TRANSLN(i)); 334 - node = (val >> 1) & 0x3; 335 - if (n >= 0 && n != node) 336 - continue; 337 - val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i)); 338 val = (val >> 12) & 0xfffff; 339 base = (uint64_t) val << 20; 340 - val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i)); 341 val = (val >> 12) & 0xfffff; 342 if (val == 0) /* BAR not used */ 343 continue;
··· 57 nodep->sysbase = nlm_get_sys_regbase(node); 58 nodep->picbase = nlm_get_pic_regbase(node); 59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1)); 60 + if (cpu_is_xlp9xx()) 61 + nodep->socbus = xlp9xx_get_socbus(node); 62 + else 63 + nodep->socbus = 0; 64 spin_lock_init(&nodep->piclock); 65 } 66 ··· 64 { 65 uint64_t pcibase; 66 int devoff, irt; 67 + 68 + /* bypass for 9xx */ 69 + if (cpu_is_xlp9xx()) { 70 + switch (irq) { 71 + case PIC_9XX_XHCI_0_IRQ: 72 + return 114; 73 + case PIC_9XX_XHCI_1_IRQ: 74 + return 115; 75 + case PIC_UART_0_IRQ: 76 + return 133; 77 + case PIC_UART_1_IRQ: 78 + return 134; 79 + case PIC_PCIE_LINK_LEGACY_IRQ(0): 80 + case PIC_PCIE_LINK_LEGACY_IRQ(1): 81 + case PIC_PCIE_LINK_LEGACY_IRQ(2): 82 + case PIC_PCIE_LINK_LEGACY_IRQ(3): 83 + return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE; 84 + } 85 + return -1; 86 + } 87 88 devoff = 0; 89 switch (irq) { ··· 135 case PIC_I2C_3_IRQ: 136 irt = irt + 3; break; 137 } 138 + } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) && 139 + irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) { 140 /* HW bug, PCI IRT entries are bad on early silicon, fix */ 141 + irt = PIC_IRT_PCIE_LINK_INDEX(irq - 142 + PIC_PCIE_LINK_LEGACY_IRQ_BASE); 143 + } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && 144 + irq <= PIC_PCIE_LINK_MSI_IRQ(3)) { 145 + irt = -2; 146 + } else if (irq >= PIC_PCIE_MSIX_IRQ(0) && 147 + irq <= PIC_PCIE_MSIX_IRQ(3)) { 148 + irt = -2; 149 } else { 150 irt = -1; 151 } ··· 151 uint64_t num, sysbase; 152 153 sysbase = nlm_get_node(node)->sysbase; 154 + if (cpu_is_xlp9xx()) 155 + rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG); 156 + else 157 + rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG); 158 if (cpu_is_xlpii()) { 159 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26)); 160 denom = 3; ··· 265 266 unsigned int nlm_get_pic_frequency(int node) 267 { 268 + /* TODO Has to calculate freq as like 2xx */ 269 + if (cpu_is_xlp9xx()) 270 + return 250000000; 271 + 272 if (cpu_is_xlpii()) 273 return nlm_2xx_get_pic_frequency(node); 274 else ··· 284 { 285 uint64_t bridgebase, base, lim; 286 uint32_t val; 287 + unsigned int barreg, limreg, xlatreg; 288 int i, node, rv; 289 290 /* Look only at mapping on Node 0, we don't handle crazy configs */ 291 bridgebase = nlm_get_bridge_regbase(0); 292 rv = 0; 293 for (i = 0; i < 8; i++) { 294 + if (cpu_is_xlp9xx()) { 295 + barreg = BRIDGE_9XX_DRAM_BAR(i); 296 + limreg = BRIDGE_9XX_DRAM_LIMIT(i); 297 + xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i); 298 + } else { 299 + barreg = BRIDGE_DRAM_BAR(i); 300 + limreg = BRIDGE_DRAM_LIMIT(i); 301 + xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i); 302 + } 303 + if (n >= 0) { 304 + /* node specified, get node mapping of BAR */ 305 + val = nlm_read_bridge_reg(bridgebase, xlatreg); 306 + node = (val >> 1) & 0x3; 307 + if (n != node) 308 + continue; 309 + } 310 + val = nlm_read_bridge_reg(bridgebase, barreg); 311 val = (val >> 12) & 0xfffff; 312 base = (uint64_t) val << 20; 313 + val = nlm_read_bridge_reg(bridgebase, limreg); 314 val = (val >> 12) & 0xfffff; 315 if (val == 0) /* BAR not used */ 316 continue;
+18 -7
arch/mips/netlogic/xlp/setup.c
··· 51 struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 52 cpumask_t nlm_cpumask = CPU_MASK_CPU0; 53 unsigned int nlm_threads_per_core; 54 55 static void nlm_linux_exit(void) 56 { 57 uint64_t sysbase = nlm_get_node(0)->sysbase; 58 59 - nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); 60 for ( ; ; ) 61 cpu_wait(); 62 } ··· 96 97 void __init plat_mem_setup(void) 98 { 99 _machine_restart = (void (*)(char *))nlm_linux_exit; 100 _machine_halt = nlm_linux_exit; 101 pm_power_off = nlm_linux_exit; ··· 122 const char *get_system_type(void) 123 { 124 switch (read_c0_prid() & 0xff00) { 125 case PRID_IMP_NETLOGIC_XLP2XX: 126 return "Broadcom XLPII Series"; 127 default: ··· 162 void *reset_vec; 163 164 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 165 nlm_init_boot_cpu(); 166 xlp_mmu_init(); 167 nlm_node_init(0); ··· 179 180 #ifdef CONFIG_SMP 181 cpumask_setall(&nlm_cpumask); 182 - nlm_wakeup_secondary_cpus(); 183 - 184 - /* update TLB size after waking up threads */ 185 - current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 186 - 187 - register_smp_ops(&nlm_smp_ops); 188 #endif 189 }
··· 51 struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 52 cpumask_t nlm_cpumask = CPU_MASK_CPU0; 53 unsigned int nlm_threads_per_core; 54 + unsigned int xlp_cores_per_node; 55 56 static void nlm_linux_exit(void) 57 { 58 uint64_t sysbase = nlm_get_node(0)->sysbase; 59 60 + if (cpu_is_xlp9xx()) 61 + nlm_write_sys_reg(sysbase, SYS_9XX_CHIP_RESET, 1); 62 + else 63 + nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1); 64 for ( ; ; ) 65 cpu_wait(); 66 } ··· 92 93 void __init plat_mem_setup(void) 94 { 95 + #ifdef CONFIG_SMP 96 + nlm_wakeup_secondary_cpus(); 97 + 98 + /* update TLB size after waking up threads */ 99 + current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; 100 + 101 + register_smp_ops(&nlm_smp_ops); 102 + #endif 103 _machine_restart = (void (*)(char *))nlm_linux_exit; 104 _machine_halt = nlm_linux_exit; 105 pm_power_off = nlm_linux_exit; ··· 110 const char *get_system_type(void) 111 { 112 switch (read_c0_prid() & 0xff00) { 113 + case PRID_IMP_NETLOGIC_XLP9XX: 114 case PRID_IMP_NETLOGIC_XLP2XX: 115 return "Broadcom XLPII Series"; 116 default: ··· 149 void *reset_vec; 150 151 nlm_io_base = CKSEG1ADDR(XLP_DEFAULT_IO_BASE); 152 + if (cpu_is_xlp9xx()) 153 + xlp_cores_per_node = 32; 154 + else 155 + xlp_cores_per_node = 8; 156 nlm_init_boot_cpu(); 157 xlp_mmu_init(); 158 nlm_node_init(0); ··· 162 163 #ifdef CONFIG_SMP 164 cpumask_setall(&nlm_cpumask); 165 #endif 166 }
+75 -13
arch/mips/netlogic/xlp/usb-init-xlp2.c
··· 37 #include <linux/delay.h> 38 #include <linux/init.h> 39 #include <linux/pci.h> 40 #include <linux/platform_device.h> 41 #include <linux/irq.h> 42 ··· 84 #define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) 85 #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) 86 87 - #define nlm_xlpii_get_usb_pcibase(node, inst) \ 88 - nlm_pcicfg_base(XLP2XX_IO_USB_OFFSET(node, inst)) 89 #define nlm_xlpii_get_usb_regbase(node, inst) \ 90 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 91 92 - static void xlpii_usb_ack(struct irq_data *data) 93 { 94 u64 port_addr; 95 ··· 107 break; 108 default: 109 pr_err("No matching USB irq!\n"); 110 return; 111 } 112 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); ··· 204 205 static int __init nlm_platform_xlpii_usb_init(void) 206 { 207 if (!cpu_is_xlpii()) 208 return 0; 209 210 - pr_info("Initializing 2XX USB Interface\n"); 211 - nlm_xlpii_usb_hw_reset(0, 1); 212 - nlm_xlpii_usb_hw_reset(0, 2); 213 - nlm_xlpii_usb_hw_reset(0, 3); 214 - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlpii_usb_ack); 215 - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlpii_usb_ack); 216 - nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlpii_usb_ack); 217 218 return 0; 219 } 220 ··· 238 239 static u64 xlp_usb_dmamask = ~(u32)0; 240 241 - /* Fixup IRQ for USB devices on XLP the SoC PCIe bus */ 242 - static void nlm_usb_fixup_final(struct pci_dev *dev) 243 { 244 dev->dev.dma_mask = &xlp_usb_dmamask; 245 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); ··· 274 } 275 } 276 277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, 278 - nlm_usb_fixup_final);
··· 37 #include <linux/delay.h> 38 #include <linux/init.h> 39 #include <linux/pci.h> 40 + #include <linux/pci_ids.h> 41 #include <linux/platform_device.h> 42 #include <linux/irq.h> 43 ··· 83 #define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) 84 #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) 85 86 + #define nlm_xlpii_get_usb_pcibase(node, inst) \ 87 + nlm_pcicfg_base(cpu_is_xlp9xx() ? \ 88 + XLP9XX_IO_USB_OFFSET(node, inst) : \ 89 + XLP2XX_IO_USB_OFFSET(node, inst)) 90 #define nlm_xlpii_get_usb_regbase(node, inst) \ 91 (nlm_xlpii_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) 92 93 + static void xlp2xx_usb_ack(struct irq_data *data) 94 { 95 u64 port_addr; 96 ··· 104 break; 105 default: 106 pr_err("No matching USB irq!\n"); 107 + return; 108 + } 109 + nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); 110 + } 111 + 112 + static void xlp9xx_usb_ack(struct irq_data *data) 113 + { 114 + u64 port_addr; 115 + int node, irq; 116 + 117 + /* Find the node and irq on the node */ 118 + irq = data->irq % NLM_IRQS_PER_NODE; 119 + node = data->irq / NLM_IRQS_PER_NODE; 120 + 121 + switch (irq) { 122 + case PIC_9XX_XHCI_0_IRQ: 123 + port_addr = nlm_xlpii_get_usb_regbase(node, 1); 124 + break; 125 + case PIC_9XX_XHCI_1_IRQ: 126 + port_addr = nlm_xlpii_get_usb_regbase(node, 2); 127 + break; 128 + default: 129 + pr_err("No matching USB irq %d node %d!\n", irq, node); 130 return; 131 } 132 nlm_write_usb_reg(port_addr, XLPII_USB3_INT_REG, 0xffffffff); ··· 178 179 static int __init nlm_platform_xlpii_usb_init(void) 180 { 181 + int node; 182 + 183 if (!cpu_is_xlpii()) 184 return 0; 185 186 + if (!cpu_is_xlp9xx()) { 187 + /* XLP 2XX single node */ 188 + pr_info("Initializing 2XX USB Interface\n"); 189 + nlm_xlpii_usb_hw_reset(0, 1); 190 + nlm_xlpii_usb_hw_reset(0, 2); 191 + nlm_xlpii_usb_hw_reset(0, 3); 192 + nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_0_IRQ, xlp2xx_usb_ack); 193 + nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_1_IRQ, xlp2xx_usb_ack); 194 + nlm_set_pic_extra_ack(0, PIC_2XX_XHCI_2_IRQ, xlp2xx_usb_ack); 195 + return 0; 196 + } 197 198 + /* XLP 9XX, multi-node */ 199 + pr_info("Initializing 9XX USB Interface\n"); 200 + for (node = 0; node < NLM_NR_NODES; node++) { 201 + if (!nlm_node_present(node)) 202 + continue; 203 + nlm_xlpii_usb_hw_reset(node, 1); 204 + nlm_xlpii_usb_hw_reset(node, 2); 205 + nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_0_IRQ, xlp9xx_usb_ack); 206 + nlm_set_pic_extra_ack(node, PIC_9XX_XHCI_1_IRQ, xlp9xx_usb_ack); 207 + } 208 return 0; 209 } 210 ··· 196 197 static u64 xlp_usb_dmamask = ~(u32)0; 198 199 + /* Fixup the IRQ for USB devices which is exist on XLP9XX SOC PCIE bus */ 200 + static void nlm_xlp9xx_usb_fixup_final(struct pci_dev *dev) 201 + { 202 + int node; 203 + 204 + node = xlp_socdev_to_node(dev); 205 + dev->dev.dma_mask = &xlp_usb_dmamask; 206 + dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); 207 + switch (dev->devfn) { 208 + case 0x21: 209 + dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_0_IRQ); 210 + break; 211 + case 0x22: 212 + dev->irq = nlm_irq_to_xirq(node, PIC_9XX_XHCI_1_IRQ); 213 + break; 214 + } 215 + } 216 + 217 + /* Fixup the IRQ for USB devices which is exist on XLP2XX SOC PCIE bus */ 218 + static void nlm_xlp2xx_usb_fixup_final(struct pci_dev *dev) 219 { 220 dev->dev.dma_mask = &xlp_usb_dmamask; 221 dev->dev.coherent_dma_mask = DMA_BIT_MASK(32); ··· 214 } 215 } 216 217 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_XLP9XX_XHCI, 218 + nlm_xlp9xx_usb_fixup_final); 219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_XHCI, 220 + nlm_xlp2xx_usb_fixup_final);
+75 -27
arch/mips/netlogic/xlp/wakeup.c
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 - #include <linux/init.h> 36 #include <linux/kernel.h> 37 #include <linux/threads.h> 38 ··· 46 #include <asm/netlogic/mips-extns.h> 47 48 #include <asm/netlogic/xlp-hal/iomap.h> 49 - #include <asm/netlogic/xlp-hal/pic.h> 50 #include <asm/netlogic/xlp-hal/xlp.h> 51 #include <asm/netlogic/xlp-hal/sys.h> 52 53 static int xlp_wakeup_core(uint64_t sysbase, int node, int core) 54 { 55 uint32_t coremask, value; 56 - int count; 57 58 coremask = (1 << core); 59 ··· 64 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); 65 } 66 67 - /* Remove CPU Reset */ 68 - value = nlm_read_sys_reg(sysbase, SYS_CPU_RESET); 69 - value &= ~coremask; 70 - nlm_write_sys_reg(sysbase, SYS_CPU_RESET, value); 71 72 - /* Poll for CPU to mark itself coherent */ 73 count = 100000; 74 do { 75 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); ··· 95 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 96 int i, count, notready; 97 98 - count = 0x20000000; 99 do { 100 notready = nlm_threads_per_core; 101 for (i = 0; i < nlm_threads_per_core; i++) ··· 109 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) 110 { 111 struct nlm_soc_info *nodep; 112 - uint64_t syspcibase; 113 - uint32_t syscoremask; 114 int core, n, cpu; 115 116 for (n = 0; n < NLM_NR_NODES; n++) { 117 - syspcibase = nlm_get_sys_pcibase(n); 118 - if (nlm_read_reg(syspcibase, 0) == 0xffffffff) 119 - break; 120 - 121 - /* read cores in reset from SYS */ 122 - if (n != 0) 123 nlm_node_init(n); 124 - nodep = nlm_get_node(n); 125 - syscoremask = nlm_read_sys_reg(nodep->sysbase, SYS_CPU_RESET); 126 - /* The boot cpu */ 127 - if (n == 0) { 128 - syscoremask |= 1; 129 - nodep->coremask = 1; 130 } 131 132 - for (core = 0; core < NLM_CORES_PER_NODE; core++) { 133 /* we will be on node 0 core 0 */ 134 if (n == 0 && core == 0) 135 continue; ··· 174 continue; 175 176 /* see if at least the first hw thread is enabled */ 177 - cpu = (n * NLM_CORES_PER_NODE + core) 178 * NLM_THREADS_PER_CORE; 179 if (!cpumask_test_cpu(cpu, wakeup_mask)) 180 continue; ··· 187 nodep->coremask |= 1u << core; 188 189 /* spin until the hw threads sets their ready */ 190 - wait_for_cpus(cpu, 0); 191 } 192 } 193 } ··· 200 * first wakeup core 0 threads 201 */ 202 xlp_boot_core0_siblings(); 203 - wait_for_cpus(0, 0); 204 205 /* now get other cores out of reset */ 206 xlp_enable_secondary_cores(&nlm_cpumask);
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/threads.h> 37 ··· 47 #include <asm/netlogic/mips-extns.h> 48 49 #include <asm/netlogic/xlp-hal/iomap.h> 50 #include <asm/netlogic/xlp-hal/xlp.h> 51 + #include <asm/netlogic/xlp-hal/pic.h> 52 #include <asm/netlogic/xlp-hal/sys.h> 53 54 static int xlp_wakeup_core(uint64_t sysbase, int node, int core) 55 { 56 uint32_t coremask, value; 57 + int count, resetreg; 58 59 coremask = (1 << core); 60 ··· 65 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value); 66 } 67 68 + /* On 9XX, mark coherent first */ 69 + if (cpu_is_xlp9xx()) { 70 + value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE); 71 + value &= ~coremask; 72 + nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value); 73 + } 74 75 + /* Remove CPU Reset */ 76 + resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET; 77 + value = nlm_read_sys_reg(sysbase, resetreg); 78 + value &= ~coremask; 79 + nlm_write_sys_reg(sysbase, resetreg, value); 80 + 81 + /* We are done on 9XX */ 82 + if (cpu_is_xlp9xx()) 83 + return 1; 84 + 85 + /* Poll for CPU to mark itself coherent on other type of XLP */ 86 count = 100000; 87 do { 88 value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE); ··· 84 volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY); 85 int i, count, notready; 86 87 + count = 0x800000; 88 do { 89 notready = nlm_threads_per_core; 90 for (i = 0; i < nlm_threads_per_core; i++) ··· 98 static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask) 99 { 100 struct nlm_soc_info *nodep; 101 + uint64_t syspcibase, fusebase; 102 + uint32_t syscoremask, mask, fusemask; 103 int core, n, cpu; 104 105 for (n = 0; n < NLM_NR_NODES; n++) { 106 + if (n != 0) { 107 + /* check if node exists and is online */ 108 + if (cpu_is_xlp9xx()) { 109 + int b = xlp9xx_get_socbus(n); 110 + pr_info("Node %d SoC PCI bus %d.\n", n, b); 111 + if (b == 0) 112 + break; 113 + } else { 114 + syspcibase = nlm_get_sys_pcibase(n); 115 + if (nlm_read_reg(syspcibase, 0) == 0xffffffff) 116 + break; 117 + } 118 nlm_node_init(n); 119 } 120 121 + /* read cores in reset from SYS */ 122 + nodep = nlm_get_node(n); 123 + 124 + if (cpu_is_xlp9xx()) { 125 + fusebase = nlm_get_fuse_regbase(n); 126 + fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6); 127 + mask = 0xfffff; 128 + } else { 129 + fusemask = nlm_read_sys_reg(nodep->sysbase, 130 + SYS_EFUSE_DEVICE_CFG_STATUS0); 131 + switch (read_c0_prid() & 0xff00) { 132 + case PRID_IMP_NETLOGIC_XLP3XX: 133 + mask = 0xf; 134 + break; 135 + case PRID_IMP_NETLOGIC_XLP2XX: 136 + mask = 0x3; 137 + break; 138 + case PRID_IMP_NETLOGIC_XLP8XX: 139 + default: 140 + mask = 0xff; 141 + break; 142 + } 143 + } 144 + 145 + /* 146 + * Fused out cores are set in the fusemask, and the remaining 147 + * cores are renumbered to range 0 .. nactive-1 148 + */ 149 + syscoremask = (1 << hweight32(~fusemask & mask)) - 1; 150 + 151 + /* The boot cpu */ 152 + if (n == 0) 153 + nodep->coremask = 1; 154 + 155 + pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask); 156 + for (core = 0; core < nlm_cores_per_node(); core++) { 157 /* we will be on node 0 core 0 */ 158 if (n == 0 && core == 0) 159 continue; ··· 128 continue; 129 130 /* see if at least the first hw thread is enabled */ 131 + cpu = (n * nlm_cores_per_node() + core) 132 * NLM_THREADS_PER_CORE; 133 if (!cpumask_test_cpu(cpu, wakeup_mask)) 134 continue; ··· 141 nodep->coremask |= 1u << core; 142 143 /* spin until the hw threads sets their ready */ 144 + if (!wait_for_cpus(cpu, 0)) 145 + pr_err("Node %d : timeout core %d\n", n, core); 146 } 147 } 148 } ··· 153 * first wakeup core 0 threads 154 */ 155 xlp_boot_core0_siblings(); 156 + if (!wait_for_cpus(0, 0)) 157 + pr_err("Node 0 : timeout core 0\n"); 158 159 /* now get other cores out of reset */ 160 xlp_enable_secondary_cores(&nlm_cpumask);
+2 -2
arch/mips/netlogic/xlr/platform.c
··· 23 #include <asm/netlogic/xlr/pic.h> 24 #include <asm/netlogic/xlr/xlr.h> 25 26 - unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 27 { 28 uint64_t uartbase; 29 unsigned int value; ··· 41 return value; 42 } 43 44 - void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 45 { 46 uint64_t uartbase; 47
··· 23 #include <asm/netlogic/xlr/pic.h> 24 #include <asm/netlogic/xlr/xlr.h> 25 26 + static unsigned int nlm_xlr_uart_in(struct uart_port *p, int offset) 27 { 28 uint64_t uartbase; 29 unsigned int value; ··· 41 return value; 42 } 43 44 + static void nlm_xlr_uart_out(struct uart_port *p, int offset, int value) 45 { 46 uint64_t uartbase; 47
-20
arch/mips/netlogic/xlr/setup.c
··· 60 struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 61 cpumask_t nlm_cpumask = CPU_MASK_CPU0; 62 63 - static void __init nlm_early_serial_setup(void) 64 - { 65 - struct uart_port s; 66 - unsigned long uart_base; 67 - 68 - uart_base = (unsigned long)nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET); 69 - memset(&s, 0, sizeof(s)); 70 - s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; 71 - s.iotype = UPIO_MEM32; 72 - s.regshift = 2; 73 - s.irq = PIC_UART_0_IRQ; 74 - s.uartclk = PIC_CLK_HZ; 75 - s.serial_in = nlm_xlr_uart_in; 76 - s.serial_out = nlm_xlr_uart_out; 77 - s.mapbase = uart_base; 78 - s.membase = (unsigned char __iomem *)uart_base; 79 - early_serial_setup(&s); 80 - } 81 - 82 static void nlm_linux_exit(void) 83 { 84 uint64_t gpiobase; ··· 195 memcpy(reset_vec, (void *)nlm_reset_entry, 196 (nlm_reset_entry_end - nlm_reset_entry)); 197 198 - nlm_early_serial_setup(); 199 build_arcs_cmdline(argv); 200 prom_add_memory(); 201
··· 60 struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; 61 cpumask_t nlm_cpumask = CPU_MASK_CPU0; 62 63 static void nlm_linux_exit(void) 64 { 65 uint64_t gpiobase; ··· 214 memcpy(reset_vec, (void *)nlm_reset_entry, 215 (nlm_reset_entry_end - nlm_reset_entry)); 216 217 build_arcs_cmdline(argv); 218 prom_add_memory(); 219
+1 -2
arch/mips/netlogic/xlr/wakeup.c
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 - #include <linux/init.h> 36 #include <linux/delay.h> 37 #include <linux/threads.h> 38 ··· 69 70 /* Fill up the coremask early */ 71 nodep->coremask = 1; 72 - for (i = 1; i < NLM_CORES_PER_NODE; i++) { 73 for (j = 1000000; j > 0; j--) { 74 if (cpu_ready[i * NLM_THREADS_PER_CORE]) 75 break;
··· 32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/delay.h> 36 #include <linux/threads.h> 37 ··· 70 71 /* Fill up the coremask early */ 72 nodep->coremask = 1; 73 + for (i = 1; i < nlm_cores_per_node(); i++) { 74 for (j = 1000000; j > 0; j--) { 75 if (cpu_ready[i * NLM_THREADS_PER_CORE]) 76 break;
+2
arch/mips/oprofile/common.c
··· 86 case CPU_34K: 87 case CPU_1004K: 88 case CPU_74K: 89 case CPU_LOONGSON1: 90 case CPU_SB1: 91 case CPU_SB1A:
··· 86 case CPU_34K: 87 case CPU_1004K: 88 case CPU_74K: 89 + case CPU_INTERAPTIV: 90 + case CPU_PROAPTIV: 91 case CPU_LOONGSON1: 92 case CPU_SB1: 93 case CPU_SB1A:
+8
arch/mips/oprofile/op_model_mipsxx.c
··· 376 op_model_mipsxx_ops.cpu_type = "mips/74K"; 377 break; 378 379 case CPU_5KC: 380 op_model_mipsxx_ops.cpu_type = "mips/5K"; 381 break;
··· 376 op_model_mipsxx_ops.cpu_type = "mips/74K"; 377 break; 378 379 + case CPU_INTERAPTIV: 380 + op_model_mipsxx_ops.cpu_type = "mips/interAptiv"; 381 + break; 382 + 383 + case CPU_PROAPTIV: 384 + op_model_mipsxx_ops.cpu_type = "mips/proAptiv"; 385 + break; 386 + 387 case CPU_5KC: 388 op_model_mipsxx_ops.cpu_type = "mips/5K"; 389 break;
+1
arch/mips/pci/Makefile
··· 60 61 ifdef CONFIG_PCI_MSI 62 obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o 63 endif
··· 60 61 ifdef CONFIG_PCI_MSI 62 obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o 63 + obj-$(CONFIG_CPU_XLP) += msi-xlp.o 64 endif
+11
arch/mips/pci/fixup-malta.c
··· 54 static void malta_piix_func0_fixup(struct pci_dev *pdev) 55 { 56 unsigned char reg_val; 57 /* PIIX PIRQC[A:D] irq mappings */ 58 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { 59 0, 0, 0, 3, ··· 84 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | 85 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK); 86 } 87 } 88 89 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
··· 54 static void malta_piix_func0_fixup(struct pci_dev *pdev) 55 { 56 unsigned char reg_val; 57 + u32 reg_val32; 58 /* PIIX PIRQC[A:D] irq mappings */ 59 static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = { 60 0, 0, 0, 3, ··· 83 pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val | 84 PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK); 85 } 86 + 87 + /* Mux SERIRQ to its pin */ 88 + pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32); 89 + pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG, 90 + reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ); 91 + 92 + /* Enable SERIRQ */ 93 + pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val); 94 + reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT; 95 + pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val); 96 } 97 98 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
-1
arch/mips/pci/fixup-rc32434.c
··· 27 #include <linux/types.h> 28 #include <linux/pci.h> 29 #include <linux/kernel.h> 30 - #include <linux/init.h> 31 32 #include <asm/mach-rc32434/rc32434.h> 33 #include <asm/mach-rc32434/irq.h>
··· 27 #include <linux/types.h> 28 #include <linux/pci.h> 29 #include <linux/kernel.h> 30 31 #include <asm/mach-rc32434/rc32434.h> 32 #include <asm/mach-rc32434/irq.h>
-1
arch/mips/pci/fixup-sb1250.c
··· 8 * 2 of the License, or (at your option) any later version. 9 */ 10 11 - #include <linux/init.h> 12 #include <linux/pci.h> 13 14 /*
··· 8 * 2 of the License, or (at your option) any later version. 9 */ 10 11 #include <linux/pci.h> 12 13 /*
+494
arch/mips/pci/msi-xlp.c
···
··· 1 + /* 2 + * Copyright (c) 2003-2012 Broadcom Corporation 3 + * All Rights Reserved 4 + * 5 + * This software is available to you under a choice of one of two 6 + * licenses. You may choose to be licensed under the terms of the GNU 7 + * General Public License (GPL) Version 2, available from the file 8 + * COPYING in the main directory of this source tree, or the Broadcom 9 + * license below: 10 + * 11 + * Redistribution and use in source and binary forms, with or without 12 + * modification, are permitted provided that the following conditions 13 + * are met: 14 + * 15 + * 1. Redistributions of source code must retain the above copyright 16 + * notice, this list of conditions and the following disclaimer. 17 + * 2. Redistributions in binary form must reproduce the above copyright 18 + * notice, this list of conditions and the following disclaimer in 19 + * the documentation and/or other materials provided with the 20 + * distribution. 21 + * 22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 + */ 34 + 35 + #include <linux/types.h> 36 + #include <linux/pci.h> 37 + #include <linux/kernel.h> 38 + #include <linux/init.h> 39 + #include <linux/msi.h> 40 + #include <linux/mm.h> 41 + #include <linux/irq.h> 42 + #include <linux/irqdesc.h> 43 + #include <linux/console.h> 44 + 45 + #include <asm/io.h> 46 + 47 + #include <asm/netlogic/interrupt.h> 48 + #include <asm/netlogic/haldefs.h> 49 + #include <asm/netlogic/common.h> 50 + #include <asm/netlogic/mips-extns.h> 51 + 52 + #include <asm/netlogic/xlp-hal/iomap.h> 53 + #include <asm/netlogic/xlp-hal/xlp.h> 54 + #include <asm/netlogic/xlp-hal/pic.h> 55 + #include <asm/netlogic/xlp-hal/pcibus.h> 56 + #include <asm/netlogic/xlp-hal/bridge.h> 57 + 58 + #define XLP_MSIVEC_PER_LINK 32 59 + #define XLP_MSIXVEC_TOTAL 32 60 + #define XLP_MSIXVEC_PER_LINK 8 61 + 62 + /* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */ 63 + static inline int nlm_link_msiirq(int link, int msivec) 64 + { 65 + return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec; 66 + } 67 + 68 + static inline int nlm_irq_msivec(int irq) 69 + { 70 + return irq % XLP_MSIVEC_PER_LINK; 71 + } 72 + 73 + static inline int nlm_irq_msilink(int irq) 74 + { 75 + return (irq % (XLP_MSIVEC_PER_LINK * PCIE_NLINKS)) / 76 + XLP_MSIVEC_PER_LINK; 77 + } 78 + 79 + /* 80 + * Only 32 MSI-X vectors are possible because there are only 32 PIC 81 + * interrupts for MSI. We split them statically and use 8 MSI-X vectors 82 + * per link - this keeps the allocation and lookup simple. 83 + */ 84 + static inline int nlm_link_msixirq(int link, int bit) 85 + { 86 + return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit; 87 + } 88 + 89 + static inline int nlm_irq_msixvec(int irq) 90 + { 91 + return irq % XLP_MSIXVEC_TOTAL; /* works when given xirq */ 92 + } 93 + 94 + static inline int nlm_irq_msixlink(int irq) 95 + { 96 + return nlm_irq_msixvec(irq) / XLP_MSIXVEC_PER_LINK; 97 + } 98 + 99 + /* 100 + * Per link MSI and MSI-X information, set as IRQ handler data for 101 + * MSI and MSI-X interrupts. 102 + */ 103 + struct xlp_msi_data { 104 + struct nlm_soc_info *node; 105 + uint64_t lnkbase; 106 + uint32_t msi_enabled_mask; 107 + uint32_t msi_alloc_mask; 108 + uint32_t msix_alloc_mask; 109 + spinlock_t msi_lock; 110 + }; 111 + 112 + /* 113 + * MSI Chip definitions 114 + * 115 + * On XLP, there is a PIC interrupt associated with each PCIe link on the 116 + * chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa 117 + * per link and 128 overall. 118 + * 119 + * When a device connected to the link raises a MSI interrupt, we get a 120 + * link interrupt and we then have to look at PCIE_MSI_STATUS register at 121 + * the bridge to map it to the IRQ 122 + */ 123 + static void xlp_msi_enable(struct irq_data *d) 124 + { 125 + struct xlp_msi_data *md = irq_data_get_irq_handler_data(d); 126 + unsigned long flags; 127 + int vec; 128 + 129 + vec = nlm_irq_msivec(d->irq); 130 + spin_lock_irqsave(&md->msi_lock, flags); 131 + md->msi_enabled_mask |= 1u << vec; 132 + nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); 133 + spin_unlock_irqrestore(&md->msi_lock, flags); 134 + } 135 + 136 + static void xlp_msi_disable(struct irq_data *d) 137 + { 138 + struct xlp_msi_data *md = irq_data_get_irq_handler_data(d); 139 + unsigned long flags; 140 + int vec; 141 + 142 + vec = nlm_irq_msivec(d->irq); 143 + spin_lock_irqsave(&md->msi_lock, flags); 144 + md->msi_enabled_mask &= ~(1u << vec); 145 + nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); 146 + spin_unlock_irqrestore(&md->msi_lock, flags); 147 + } 148 + 149 + static void xlp_msi_mask_ack(struct irq_data *d) 150 + { 151 + struct xlp_msi_data *md = irq_data_get_irq_handler_data(d); 152 + int link, vec; 153 + 154 + link = nlm_irq_msilink(d->irq); 155 + vec = nlm_irq_msivec(d->irq); 156 + xlp_msi_disable(d); 157 + 158 + /* Ack MSI on bridge */ 159 + nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec); 160 + 161 + /* Ack at eirr and PIC */ 162 + ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link)); 163 + nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link)); 164 + } 165 + 166 + static struct irq_chip xlp_msi_chip = { 167 + .name = "XLP-MSI", 168 + .irq_enable = xlp_msi_enable, 169 + .irq_disable = xlp_msi_disable, 170 + .irq_mask_ack = xlp_msi_mask_ack, 171 + .irq_unmask = xlp_msi_enable, 172 + }; 173 + 174 + /* 175 + * The MSI-X interrupt handling is different from MSI, there are 32 176 + * MSI-X interrupts generated by the PIC and each of these correspond 177 + * to a MSI-X vector (0-31) that can be assigned. 178 + * 179 + * We divide the MSI-X vectors to 8 per link and do a per-link 180 + * allocation 181 + * 182 + * Enable and disable done using standard MSI functions. 183 + */ 184 + static void xlp_msix_mask_ack(struct irq_data *d) 185 + { 186 + struct xlp_msi_data *md = irq_data_get_irq_handler_data(d); 187 + int link, msixvec; 188 + 189 + msixvec = nlm_irq_msixvec(d->irq); 190 + link = nlm_irq_msixlink(d->irq); 191 + mask_msi_irq(d); 192 + 193 + /* Ack MSI on bridge */ 194 + nlm_write_reg(md->lnkbase, PCIE_MSIX_STATUS, 1u << msixvec); 195 + 196 + /* Ack at eirr and PIC */ 197 + ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link)); 198 + nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_MSIX_INDEX(msixvec)); 199 + } 200 + 201 + static struct irq_chip xlp_msix_chip = { 202 + .name = "XLP-MSIX", 203 + .irq_enable = unmask_msi_irq, 204 + .irq_disable = mask_msi_irq, 205 + .irq_mask_ack = xlp_msix_mask_ack, 206 + .irq_unmask = unmask_msi_irq, 207 + }; 208 + 209 + void destroy_irq(unsigned int irq) 210 + { 211 + /* nothing to do yet */ 212 + } 213 + 214 + void arch_teardown_msi_irq(unsigned int irq) 215 + { 216 + destroy_irq(irq); 217 + } 218 + 219 + /* 220 + * Setup a PCIe link for MSI. By default, the links are in 221 + * legacy interrupt mode. We will switch them to MSI mode 222 + * at the first MSI request. 223 + */ 224 + static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr) 225 + { 226 + u32 val; 227 + 228 + val = nlm_read_reg(lnkbase, PCIE_INT_EN0); 229 + if ((val & 0x200) == 0) { 230 + val |= 0x200; /* MSI Interrupt enable */ 231 + nlm_write_reg(lnkbase, PCIE_INT_EN0, val); 232 + } 233 + 234 + val = nlm_read_reg(lnkbase, 0x1); /* CMD */ 235 + if ((val & 0x0400) == 0) { 236 + val |= 0x0400; 237 + nlm_write_reg(lnkbase, 0x1, val); 238 + } 239 + 240 + /* Update IRQ in the PCI irq reg */ 241 + val = nlm_read_pci_reg(lnkbase, 0xf); 242 + val &= ~0x1fu; 243 + val |= (1 << 8) | lirq; 244 + nlm_write_pci_reg(lnkbase, 0xf, val); 245 + 246 + /* MSI addr */ 247 + nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32); 248 + nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff); 249 + 250 + /* MSI cap for bridge */ 251 + val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP); 252 + if ((val & (1 << 16)) == 0) { 253 + val |= 0xb << 16; /* mmc32, msi enable */ 254 + nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val); 255 + } 256 + } 257 + 258 + /* 259 + * Allocate a MSI vector on a link 260 + */ 261 + static int xlp_setup_msi(uint64_t lnkbase, int node, int link, 262 + struct msi_desc *desc) 263 + { 264 + struct xlp_msi_data *md; 265 + struct msi_msg msg; 266 + unsigned long flags; 267 + int msivec, irt, lirq, xirq, ret; 268 + uint64_t msiaddr; 269 + 270 + /* Get MSI data for the link */ 271 + lirq = PIC_PCIE_LINK_MSI_IRQ(link); 272 + xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); 273 + md = irq_get_handler_data(xirq); 274 + msiaddr = MSI_LINK_ADDR(node, link); 275 + 276 + spin_lock_irqsave(&md->msi_lock, flags); 277 + if (md->msi_alloc_mask == 0) { 278 + /* switch the link IRQ to MSI range */ 279 + xlp_config_link_msi(lnkbase, lirq, msiaddr); 280 + irt = PIC_IRT_PCIE_LINK_INDEX(link); 281 + nlm_setup_pic_irq(node, lirq, lirq, irt); 282 + nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq, 283 + node * nlm_threads_per_node(), 1 /*en */); 284 + } 285 + 286 + /* allocate a MSI vec, and tell the bridge about it */ 287 + msivec = fls(md->msi_alloc_mask); 288 + if (msivec == XLP_MSIVEC_PER_LINK) { 289 + spin_unlock_irqrestore(&md->msi_lock, flags); 290 + return -ENOMEM; 291 + } 292 + md->msi_alloc_mask |= (1u << msivec); 293 + spin_unlock_irqrestore(&md->msi_lock, flags); 294 + 295 + msg.address_hi = msiaddr >> 32; 296 + msg.address_lo = msiaddr & 0xffffffff; 297 + msg.data = 0xc00 | msivec; 298 + 299 + xirq = xirq + msivec; /* msi mapped to global irq space */ 300 + ret = irq_set_msi_desc(xirq, desc); 301 + if (ret < 0) { 302 + destroy_irq(xirq); 303 + return ret; 304 + } 305 + 306 + write_msi_msg(xirq, &msg); 307 + return 0; 308 + } 309 + 310 + /* 311 + * Switch a link to MSI-X mode 312 + */ 313 + static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr) 314 + { 315 + u32 val; 316 + 317 + val = nlm_read_reg(lnkbase, 0x2C); 318 + if ((val & 0x80000000U) == 0) { 319 + val |= 0x80000000U; 320 + nlm_write_reg(lnkbase, 0x2C, val); 321 + } 322 + val = nlm_read_reg(lnkbase, PCIE_INT_EN0); 323 + if ((val & 0x200) == 0) { 324 + val |= 0x200; /* MSI Interrupt enable */ 325 + nlm_write_reg(lnkbase, PCIE_INT_EN0, val); 326 + } 327 + 328 + val = nlm_read_reg(lnkbase, 0x1); /* CMD */ 329 + if ((val & 0x0400) == 0) { 330 + val |= 0x0400; 331 + nlm_write_reg(lnkbase, 0x1, val); 332 + } 333 + 334 + /* Update IRQ in the PCI irq reg */ 335 + val = nlm_read_pci_reg(lnkbase, 0xf); 336 + val &= ~0x1fu; 337 + val |= (1 << 8) | lirq; 338 + nlm_write_pci_reg(lnkbase, 0xf, val); 339 + 340 + /* MSI-X addresses */ 341 + nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, msixaddr >> 8); 342 + nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT, 343 + (msixaddr + MSI_ADDR_SZ) >> 8); 344 + } 345 + 346 + /* 347 + * Allocate a MSI-X vector 348 + */ 349 + static int xlp_setup_msix(uint64_t lnkbase, int node, int link, 350 + struct msi_desc *desc) 351 + { 352 + struct xlp_msi_data *md; 353 + struct msi_msg msg; 354 + unsigned long flags; 355 + int t, msixvec, lirq, xirq, ret; 356 + uint64_t msixaddr; 357 + 358 + /* Get MSI data for the link */ 359 + lirq = PIC_PCIE_MSIX_IRQ(link); 360 + xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0)); 361 + md = irq_get_handler_data(xirq); 362 + msixaddr = MSIX_LINK_ADDR(node, link); 363 + 364 + spin_lock_irqsave(&md->msi_lock, flags); 365 + /* switch the PCIe link to MSI-X mode at the first alloc */ 366 + if (md->msix_alloc_mask == 0) 367 + xlp_config_link_msix(lnkbase, lirq, msixaddr); 368 + 369 + /* allocate a MSI-X vec, and tell the bridge about it */ 370 + t = fls(md->msix_alloc_mask); 371 + if (t == XLP_MSIXVEC_PER_LINK) { 372 + spin_unlock_irqrestore(&md->msi_lock, flags); 373 + return -ENOMEM; 374 + } 375 + md->msix_alloc_mask |= (1u << t); 376 + spin_unlock_irqrestore(&md->msi_lock, flags); 377 + 378 + xirq += t; 379 + msixvec = nlm_irq_msixvec(xirq); 380 + msg.address_hi = msixaddr >> 32; 381 + msg.address_lo = msixaddr & 0xffffffff; 382 + msg.data = 0xc00 | msixvec; 383 + 384 + ret = irq_set_msi_desc(xirq, desc); 385 + if (ret < 0) { 386 + destroy_irq(xirq); 387 + return ret; 388 + } 389 + 390 + write_msi_msg(xirq, &msg); 391 + return 0; 392 + } 393 + 394 + int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) 395 + { 396 + struct pci_dev *lnkdev; 397 + uint64_t lnkbase; 398 + int node, link, slot; 399 + 400 + lnkdev = xlp_get_pcie_link(dev); 401 + if (lnkdev == NULL) { 402 + dev_err(&dev->dev, "Could not find bridge\n"); 403 + return 1; 404 + } 405 + slot = PCI_SLOT(lnkdev->devfn); 406 + link = PCI_FUNC(lnkdev->devfn); 407 + node = slot / 8; 408 + lnkbase = nlm_get_pcie_base(node, link); 409 + 410 + if (desc->msi_attrib.is_msix) 411 + return xlp_setup_msix(lnkbase, node, link, desc); 412 + else 413 + return xlp_setup_msi(lnkbase, node, link, desc); 414 + } 415 + 416 + void __init xlp_init_node_msi_irqs(int node, int link) 417 + { 418 + struct nlm_soc_info *nodep; 419 + struct xlp_msi_data *md; 420 + int irq, i, irt, msixvec; 421 + 422 + pr_info("[%d %d] Init node PCI IRT\n", node, link); 423 + nodep = nlm_get_node(node); 424 + 425 + /* Alloc an MSI block for the link */ 426 + md = kzalloc(sizeof(*md), GFP_KERNEL); 427 + spin_lock_init(&md->msi_lock); 428 + md->msi_enabled_mask = 0; 429 + md->msi_alloc_mask = 0; 430 + md->msix_alloc_mask = 0; 431 + md->node = nodep; 432 + md->lnkbase = nlm_get_pcie_base(node, link); 433 + 434 + /* extended space for MSI interrupts */ 435 + irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); 436 + for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) { 437 + irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq); 438 + irq_set_handler_data(i, md); 439 + } 440 + 441 + for (i = 0; i < XLP_MSIXVEC_PER_LINK; i++) { 442 + /* Initialize MSI-X irts to generate one interrupt per link */ 443 + msixvec = link * XLP_MSIXVEC_PER_LINK + i; 444 + irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec); 445 + nlm_pic_init_irt(nodep->picbase, irt, PIC_PCIE_MSIX_IRQ(link), 446 + node * nlm_threads_per_node(), 1 /* enable */); 447 + 448 + /* Initialize MSI-X extended irq space for the link */ 449 + irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i)); 450 + irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq); 451 + irq_set_handler_data(irq, md); 452 + } 453 + 454 + } 455 + 456 + void nlm_dispatch_msi(int node, int lirq) 457 + { 458 + struct xlp_msi_data *md; 459 + int link, i, irqbase; 460 + u32 status; 461 + 462 + link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE; 463 + irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); 464 + md = irq_get_handler_data(irqbase); 465 + status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) & 466 + md->msi_enabled_mask; 467 + while (status) { 468 + i = __ffs(status); 469 + do_IRQ(irqbase + i); 470 + status &= status - 1; 471 + } 472 + } 473 + 474 + void nlm_dispatch_msix(int node, int lirq) 475 + { 476 + struct xlp_msi_data *md; 477 + int link, i, irqbase; 478 + u32 status; 479 + 480 + link = lirq - PIC_PCIE_MSIX_IRQ_BASE; 481 + irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0)); 482 + md = irq_get_handler_data(irqbase); 483 + status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS); 484 + 485 + /* narrow it down to the MSI-x vectors for our link */ 486 + status = (status >> (link * XLP_MSIXVEC_PER_LINK)) & 487 + ((1 << XLP_MSIXVEC_PER_LINK) - 1); 488 + 489 + while (status) { 490 + i = __ffs(status); 491 + do_IRQ(irqbase + i); 492 + status &= status - 1; 493 + } 494 + }
-1
arch/mips/pci/ops-bcm63xx.c
··· 9 #include <linux/types.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 - #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/io.h> 15
··· 9 #include <linux/types.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/delay.h> 13 #include <linux/io.h> 14
-1
arch/mips/pci/ops-bonito64.c
··· 22 #include <linux/types.h> 23 #include <linux/pci.h> 24 #include <linux/kernel.h> 25 - #include <linux/init.h> 26 27 #include <asm/mips-boards/bonito64.h> 28
··· 22 #include <linux/types.h> 23 #include <linux/pci.h> 24 #include <linux/kernel.h> 25 26 #include <asm/mips-boards/bonito64.h> 27
-1
arch/mips/pci/ops-lantiq.c
··· 9 #include <linux/types.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 - #include <linux/init.h> 13 #include <linux/delay.h> 14 #include <linux/mm.h> 15 #include <asm/addrspace.h>
··· 9 #include <linux/types.h> 10 #include <linux/pci.h> 11 #include <linux/kernel.h> 12 #include <linux/delay.h> 13 #include <linux/mm.h> 14 #include <asm/addrspace.h>
-1
arch/mips/pci/ops-loongson2.c
··· 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/kernel.h> 17 - #include <linux/init.h> 18 #include <linux/export.h> 19 20 #include <loongson.h>
··· 14 #include <linux/types.h> 15 #include <linux/pci.h> 16 #include <linux/kernel.h> 17 #include <linux/export.h> 18 19 #include <loongson.h>
-1
arch/mips/pci/ops-mace.c
··· 6 * Copyright (C) 2000, 2001 Keith M Wesolowski 7 */ 8 #include <linux/kernel.h> 9 - #include <linux/init.h> 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <asm/pci.h>
··· 6 * Copyright (C) 2000, 2001 Keith M Wesolowski 7 */ 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/types.h> 11 #include <asm/pci.h>
-1
arch/mips/pci/ops-msc.c
··· 24 #include <linux/types.h> 25 #include <linux/pci.h> 26 #include <linux/kernel.h> 27 - #include <linux/init.h> 28 29 #include <asm/mips-boards/msc01_pci.h> 30
··· 24 #include <linux/types.h> 25 #include <linux/pci.h> 26 #include <linux/kernel.h> 27 28 #include <asm/mips-boards/msc01_pci.h> 29
-1
arch/mips/pci/ops-nile4.c
··· 1 #include <linux/kernel.h> 2 - #include <linux/init.h> 3 #include <linux/pci.h> 4 #include <asm/bootinfo.h> 5
··· 1 #include <linux/kernel.h> 2 #include <linux/pci.h> 3 #include <asm/bootinfo.h> 4
-1
arch/mips/pci/ops-rc32434.c
··· 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 #include <linux/delay.h> 29 - #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/pci.h> 32 #include <linux/types.h>
··· 26 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 */ 28 #include <linux/delay.h> 29 #include <linux/io.h> 30 #include <linux/pci.h> 31 #include <linux/types.h>
-1
arch/mips/pci/pci-ip27.c
··· 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 - #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/export.h> 13 #include <linux/pci.h>
··· 7 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org) 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 */ 10 #include <linux/kernel.h> 11 #include <linux/export.h> 12 #include <linux/pci.h>
+3 -3
arch/mips/pci/pci-malta.c
··· 241 return; 242 } 243 244 - /* Change start address to avoid conflicts with ACPI and SMB devices */ 245 - if (controller->io_resource->start < 0x00002000UL) 246 - controller->io_resource->start = 0x00002000UL; 247 248 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 249 ioport_resource.end = controller->io_resource->end;
··· 241 return; 242 } 243 244 + /* PIIX4 ACPI starts at 0x1000 */ 245 + if (controller->io_resource->start < 0x00001000UL) 246 + controller->io_resource->start = 0x00001000UL; 247 248 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 249 ioport_resource.end = controller->io_resource->end;
-3
arch/mips/pci/pci-rt3883.c
··· 436 return -ENOMEM; 437 438 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 439 - if (!res) 440 - return -EINVAL; 441 - 442 rpc->base = devm_ioremap_resource(dev, res); 443 if (IS_ERR(rpc->base)) 444 return PTR_ERR(rpc->base);
··· 436 return -ENOMEM; 437 438 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 439 rpc->base = devm_ioremap_resource(dev, res); 440 if (IS_ERR(rpc->base)) 441 return PTR_ERR(rpc->base);
+76 -28
arch/mips/pci/pci-xlp.c
··· 47 #include <asm/netlogic/interrupt.h> 48 #include <asm/netlogic/haldefs.h> 49 #include <asm/netlogic/common.h> 50 51 #include <asm/netlogic/xlp-hal/iomap.h> 52 - #include <asm/netlogic/xlp-hal/pic.h> 53 #include <asm/netlogic/xlp-hal/xlp.h> 54 #include <asm/netlogic/xlp-hal/pcibus.h> 55 #include <asm/netlogic/xlp-hal/bridge.h> 56 ··· 67 u32 *cfgaddr; 68 69 where &= ~3; 70 - if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) 71 return 0xffffffff; 72 - 73 cfgaddr = (u32 *)(pci_config_base + 74 pci_cfg_addr(bus->number, devfn, where)); 75 data = *cfgaddr; ··· 176 .io_offset = 0x00000000UL, 177 }; 178 179 - static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) 180 { 181 struct pci_bus *bus, *p; 182 183 - /* Find the bridge on bus 0 */ 184 bus = dev->bus; 185 - for (p = bus->parent; p && p->number != 0; p = p->parent) 186 - bus = p; 187 188 - return p ? bus->self : NULL; 189 } 190 191 - static inline int nlm_pci_link_to_irq(int link) 192 { 193 - return PIC_PCIE_LINK_0_IRQ + link; 194 } 195 196 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 197 { 198 struct pci_dev *lnkdev; 199 - int lnkslot, lnkfunc; 200 201 /* 202 * For XLP PCIe, there is an IRQ per Link, find out which ··· 217 lnkdev = xlp_get_pcie_link(dev); 218 if (lnkdev == NULL) 219 return 0; 220 lnkfunc = PCI_FUNC(lnkdev->devfn); 221 - lnkslot = PCI_SLOT(lnkdev->devfn); 222 - return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); 223 } 224 225 /* Do platform specific device initialization at pci_enable_device() time */ ··· 248 * Enable byte swap in hardware. Program each link's PCIe SWAP regions 249 * from the link's address ranges. 250 */ 251 - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); 252 - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); 253 254 - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_LIMIT0 + link); 255 - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); 256 257 - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); 258 - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); 259 260 - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); 261 - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); 262 } 263 #else 264 /* Swap configuration not needed in little-endian mode */ ··· 288 289 static int __init pcibios_init(void) 290 { 291 - struct nlm_soc_info *nodep; 292 uint64_t pciebase; 293 int link, n; 294 u32 reg; ··· 301 ioport_resource.end = ~0; 302 303 for (n = 0; n < NLM_NR_NODES; n++) { 304 - nodep = nlm_get_node(n); 305 - if (!nodep->coremask) 306 - continue; /* node does not exist */ 307 308 - for (link = 0; link < 4; link++) { 309 pciebase = nlm_get_pcie_base(n, link); 310 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) 311 continue; 312 xlp_config_pci_bswap(n, link); 313 314 /* put in intpin and irq - u-boot does not */ 315 reg = nlm_read_pci_reg(pciebase, 0xf); 316 - reg &= ~0x1fu; 317 - reg |= (1 << 8) | nlm_pci_link_to_irq(link); 318 nlm_write_pci_reg(pciebase, 0xf, reg); 319 pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); 320 }
··· 47 #include <asm/netlogic/interrupt.h> 48 #include <asm/netlogic/haldefs.h> 49 #include <asm/netlogic/common.h> 50 + #include <asm/netlogic/mips-extns.h> 51 52 #include <asm/netlogic/xlp-hal/iomap.h> 53 #include <asm/netlogic/xlp-hal/xlp.h> 54 + #include <asm/netlogic/xlp-hal/pic.h> 55 #include <asm/netlogic/xlp-hal/pcibus.h> 56 #include <asm/netlogic/xlp-hal/bridge.h> 57 ··· 66 u32 *cfgaddr; 67 68 where &= ~3; 69 + if (cpu_is_xlp9xx()) { 70 + /* be very careful on SoC buses */ 71 + if (bus->number == 0) { 72 + /* Scan only existing nodes - uboot bug? */ 73 + if (PCI_SLOT(devfn) != 0 || 74 + !nlm_node_present(PCI_FUNC(devfn))) 75 + return 0xffffffff; 76 + } else if (bus->parent->number == 0) { /* SoC bus */ 77 + if (PCI_SLOT(devfn) == 0) /* b.0.0 hangs */ 78 + return 0xffffffff; 79 + if (devfn == 44) /* b.5.4 hangs */ 80 + return 0xffffffff; 81 + } 82 + } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) { 83 return 0xffffffff; 84 + } 85 cfgaddr = (u32 *)(pci_config_base + 86 pci_cfg_addr(bus->number, devfn, where)); 87 data = *cfgaddr; ··· 162 .io_offset = 0x00000000UL, 163 }; 164 165 + struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) 166 { 167 struct pci_bus *bus, *p; 168 169 bus = dev->bus; 170 171 + if (cpu_is_xlp9xx()) { 172 + /* find bus with grand parent number == 0 */ 173 + for (p = bus->parent; p && p->parent && p->parent->number != 0; 174 + p = p->parent) 175 + bus = p; 176 + return (p && p->parent) ? bus->self : NULL; 177 + } else { 178 + /* Find the bridge on bus 0 */ 179 + for (p = bus->parent; p && p->number != 0; p = p->parent) 180 + bus = p; 181 + 182 + return p ? bus->self : NULL; 183 + } 184 } 185 186 + int xlp_socdev_to_node(const struct pci_dev *lnkdev) 187 { 188 + if (cpu_is_xlp9xx()) 189 + return PCI_FUNC(lnkdev->bus->self->devfn); 190 + else 191 + return PCI_SLOT(lnkdev->devfn) / 8; 192 } 193 194 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 195 { 196 struct pci_dev *lnkdev; 197 + int lnkfunc, node; 198 199 /* 200 * For XLP PCIe, there is an IRQ per Link, find out which ··· 191 lnkdev = xlp_get_pcie_link(dev); 192 if (lnkdev == NULL) 193 return 0; 194 + 195 lnkfunc = PCI_FUNC(lnkdev->devfn); 196 + node = xlp_socdev_to_node(lnkdev); 197 + 198 + return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc)); 199 } 200 201 /* Do platform specific device initialization at pci_enable_device() time */ ··· 220 * Enable byte swap in hardware. Program each link's PCIe SWAP regions 221 * from the link's address ranges. 222 */ 223 + if (cpu_is_xlp9xx()) { 224 + reg = nlm_read_bridge_reg(nbubase, 225 + BRIDGE_9XX_PCIEMEM_BASE0 + link); 226 + nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg); 227 228 + reg = nlm_read_bridge_reg(nbubase, 229 + BRIDGE_9XX_PCIEMEM_LIMIT0 + link); 230 + nlm_write_pci_reg(lnkbase, 231 + PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff); 232 233 + reg = nlm_read_bridge_reg(nbubase, 234 + BRIDGE_9XX_PCIEIO_BASE0 + link); 235 + nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg); 236 237 + reg = nlm_read_bridge_reg(nbubase, 238 + BRIDGE_9XX_PCIEIO_LIMIT0 + link); 239 + nlm_write_pci_reg(lnkbase, 240 + PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff); 241 + } else { 242 + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); 243 + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); 244 + 245 + reg = nlm_read_bridge_reg(nbubase, 246 + BRIDGE_PCIEMEM_LIMIT0 + link); 247 + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); 248 + 249 + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); 250 + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); 251 + 252 + reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); 253 + nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); 254 + } 255 } 256 #else 257 /* Swap configuration not needed in little-endian mode */ ··· 239 240 static int __init pcibios_init(void) 241 { 242 uint64_t pciebase; 243 int link, n; 244 u32 reg; ··· 253 ioport_resource.end = ~0; 254 255 for (n = 0; n < NLM_NR_NODES; n++) { 256 + if (!nlm_node_present(n)) 257 + continue; 258 259 + for (link = 0; link < PCIE_NLINKS; link++) { 260 pciebase = nlm_get_pcie_base(n, link); 261 if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) 262 continue; 263 xlp_config_pci_bswap(n, link); 264 + xlp_init_node_msi_irqs(n, link); 265 266 /* put in intpin and irq - u-boot does not */ 267 reg = nlm_read_pci_reg(pciebase, 0xf); 268 + reg &= ~0x1ffu; 269 + reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link); 270 nlm_write_pci_reg(pciebase, 0xf, reg); 271 pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); 272 }
+1
arch/mips/pmcs-msp71xx/Kconfig
··· 6 bool "PMC-Sierra MSP4200 Eval Board" 7 select IRQ_MSP_SLP 8 select HW_HAS_PCI 9 10 config PMC_MSP4200_GW 11 bool "PMC-Sierra MSP4200 VoIP Gateway"
··· 6 bool "PMC-Sierra MSP4200 Eval Board" 7 select IRQ_MSP_SLP 8 select HW_HAS_PCI 9 + select MIPS_L1_CACHE_SHIFT_4 10 11 config PMC_MSP4200_GW 12 bool "PMC-Sierra MSP4200 VoIP Gateway"
+1
arch/mips/ralink/Kconfig
··· 15 16 config SOC_RT288X 17 bool "RT288x" 18 19 config SOC_RT305X 20 bool "RT305x"
··· 15 16 config SOC_RT288X 17 bool "RT288x" 18 + select MIPS_L1_CACHE_SHIFT_4 19 20 config SOC_RT305X 21 bool "RT305x"
-1
arch/mips/sgi-ip27/ip27-console.c
··· 5 * 6 * Copyright (C) 2001, 2002 Ralf Baechle 7 */ 8 - #include <linux/init.h> 9 10 #include <asm/page.h> 11 #include <asm/sn/addrs.h>
··· 5 * 6 * Copyright (C) 2001, 2002 Ralf Baechle 7 */ 8 9 #include <asm/page.h> 10 #include <asm/sn/addrs.h>
-1
arch/mips/sgi-ip27/ip27-irq-pci.c
··· 8 9 #undef DEBUG 10 11 - #include <linux/init.h> 12 #include <linux/irq.h> 13 #include <linux/errno.h> 14 #include <linux/signal.h>
··· 8 9 #undef DEBUG 10 11 #include <linux/irq.h> 12 #include <linux/errno.h> 13 #include <linux/signal.h>
-1
arch/mips/sgi-ip27/ip27-klconfig.c
··· 2 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 3 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 4 */ 5 - #include <linux/init.h> 6 #include <linux/kernel.h> 7 #include <linux/sched.h> 8 #include <linux/interrupt.h>
··· 2 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org) 3 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/sched.h> 7 #include <linux/interrupt.h>
-1
arch/mips/sgi-ip27/ip27-xtalk.c
··· 7 * Generic XTALK initialization code 8 */ 9 10 - #include <linux/init.h> 11 #include <linux/kernel.h> 12 #include <linux/smp.h> 13 #include <asm/sn/types.h>
··· 7 * Generic XTALK initialization code 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/smp.h> 12 #include <asm/sn/types.h>
+1
drivers/bcma/Kconfig
··· 75 config BCMA_DRIVER_GPIO 76 bool "BCMA GPIO driver" 77 depends on BCMA && GPIOLIB 78 help 79 Driver to provide access to the GPIO pins of the bcma bus. 80
··· 75 config BCMA_DRIVER_GPIO 76 bool "BCMA GPIO driver" 77 depends on BCMA && GPIOLIB 78 + select IRQ_DOMAIN if BCMA_HOST_SOC 79 help 80 Driver to provide access to the GPIO pins of the bcma bus. 81
+135 -2
drivers/bcma/driver_gpio.c
··· 9 */ 10 11 #include <linux/gpio.h> 12 #include <linux/export.h> 13 #include <linux/bcma/bcma.h> 14 ··· 76 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); 77 } 78 79 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 80 { 81 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); 82 83 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) 84 - return bcma_core_irq(cc->core); 85 else 86 return -EINVAL; 87 } 88 89 int bcma_gpio_init(struct bcma_drv_cc *cc) 90 { 91 struct gpio_chip *chip = &cc->gpio; 92 93 chip->label = "bcma_gpio"; 94 chip->owner = THIS_MODULE; ··· 215 chip->set = bcma_gpio_set_value; 216 chip->direction_input = bcma_gpio_direction_input; 217 chip->direction_output = bcma_gpio_direction_output; 218 chip->to_irq = bcma_gpio_to_irq; 219 chip->ngpio = 16; 220 /* There is just one SoC in one device and its GPIO addresses should be 221 * deterministic to address them more easily. The other buses could get ··· 227 else 228 chip->base = -1; 229 230 - return gpiochip_add(chip); 231 } 232 233 int bcma_gpio_unregister(struct bcma_drv_cc *cc) 234 { 235 return gpiochip_remove(&cc->gpio); 236 }
··· 9 */ 10 11 #include <linux/gpio.h> 12 + #include <linux/irq.h> 13 + #include <linux/interrupt.h> 14 + #include <linux/irqdomain.h> 15 #include <linux/export.h> 16 #include <linux/bcma/bcma.h> 17 ··· 73 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0); 74 } 75 76 + #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) 77 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 78 { 79 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip); 80 81 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC) 82 + return irq_find_mapping(cc->irq_domain, gpio); 83 else 84 return -EINVAL; 85 } 86 87 + static void bcma_gpio_irq_unmask(struct irq_data *d) 88 + { 89 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d); 90 + int gpio = irqd_to_hwirq(d); 91 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio)); 92 + 93 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val); 94 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio)); 95 + } 96 + 97 + static void bcma_gpio_irq_mask(struct irq_data *d) 98 + { 99 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d); 100 + int gpio = irqd_to_hwirq(d); 101 + 102 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0); 103 + } 104 + 105 + static struct irq_chip bcma_gpio_irq_chip = { 106 + .name = "BCMA-GPIO", 107 + .irq_mask = bcma_gpio_irq_mask, 108 + .irq_unmask = bcma_gpio_irq_unmask, 109 + }; 110 + 111 + static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id) 112 + { 113 + struct bcma_drv_cc *cc = dev_id; 114 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN); 115 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ); 116 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL); 117 + unsigned long irqs = (val ^ pol) & mask; 118 + int gpio; 119 + 120 + if (!irqs) 121 + return IRQ_NONE; 122 + 123 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio) 124 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio)); 125 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs); 126 + 127 + return IRQ_HANDLED; 128 + } 129 + 130 + static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc) 131 + { 132 + struct gpio_chip *chip = &cc->gpio; 133 + int gpio, hwirq, err; 134 + 135 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC) 136 + return 0; 137 + 138 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio, 139 + &irq_domain_simple_ops, cc); 140 + if (!cc->irq_domain) { 141 + err = -ENODEV; 142 + goto err_irq_domain; 143 + } 144 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 145 + int irq = irq_create_mapping(cc->irq_domain, gpio); 146 + 147 + irq_set_chip_data(irq, cc); 148 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip, 149 + handle_simple_irq); 150 + } 151 + 152 + hwirq = bcma_core_irq(cc->core); 153 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio", 154 + cc); 155 + if (err) 156 + goto err_req_irq; 157 + 158 + bcma_chipco_gpio_intmask(cc, ~0, 0); 159 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO); 160 + 161 + return 0; 162 + 163 + err_req_irq: 164 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 165 + int irq = irq_find_mapping(cc->irq_domain, gpio); 166 + 167 + irq_dispose_mapping(irq); 168 + } 169 + irq_domain_remove(cc->irq_domain); 170 + err_irq_domain: 171 + return err; 172 + } 173 + 174 + static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc) 175 + { 176 + struct gpio_chip *chip = &cc->gpio; 177 + int gpio; 178 + 179 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC) 180 + return; 181 + 182 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO); 183 + free_irq(bcma_core_irq(cc->core), cc); 184 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 185 + int irq = irq_find_mapping(cc->irq_domain, gpio); 186 + 187 + irq_dispose_mapping(irq); 188 + } 189 + irq_domain_remove(cc->irq_domain); 190 + } 191 + #else 192 + static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc) 193 + { 194 + return 0; 195 + } 196 + 197 + static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc) 198 + { 199 + } 200 + #endif 201 + 202 int bcma_gpio_init(struct bcma_drv_cc *cc) 203 { 204 struct gpio_chip *chip = &cc->gpio; 205 + int err; 206 207 chip->label = "bcma_gpio"; 208 chip->owner = THIS_MODULE; ··· 95 chip->set = bcma_gpio_set_value; 96 chip->direction_input = bcma_gpio_direction_input; 97 chip->direction_output = bcma_gpio_direction_output; 98 + #if IS_BUILTIN(CONFIG_BCMA_HOST_SOC) 99 chip->to_irq = bcma_gpio_to_irq; 100 + #endif 101 chip->ngpio = 16; 102 /* There is just one SoC in one device and its GPIO addresses should be 103 * deterministic to address them more easily. The other buses could get ··· 105 else 106 chip->base = -1; 107 108 + err = bcma_gpio_irq_domain_init(cc); 109 + if (err) 110 + return err; 111 + 112 + err = gpiochip_add(chip); 113 + if (err) { 114 + bcma_gpio_irq_domain_exit(cc); 115 + return err; 116 + } 117 + 118 + return 0; 119 } 120 121 int bcma_gpio_unregister(struct bcma_drv_cc *cc) 122 { 123 + bcma_gpio_irq_domain_exit(cc); 124 return gpiochip_remove(&cc->gpio); 125 }
+1
drivers/ssb/Kconfig
··· 168 config SSB_DRIVER_GPIO 169 bool "SSB GPIO driver" 170 depends on SSB && GPIOLIB 171 help 172 Driver to provide access to the GPIO pins on the bus. 173
··· 168 config SSB_DRIVER_GPIO 169 bool "SSB GPIO driver" 170 depends on SSB && GPIOLIB 171 + select IRQ_DOMAIN if SSB_EMBEDDED 172 help 173 Driver to provide access to the GPIO pins on the bus. 174
+290 -16
drivers/ssb/driver_gpio.c
··· 9 */ 10 11 #include <linux/gpio.h> 12 #include <linux/export.h> 13 #include <linux/ssb/ssb.h> 14 15 #include "ssb_private.h" 16 17 static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip) 18 { 19 return container_of(chip, struct ssb_bus, gpio); 20 } 21 22 static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio) 23 { ··· 98 ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); 99 } 100 101 - static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio) 102 { 103 - struct ssb_bus *bus = ssb_gpio_get_bus(chip); 104 105 - if (bus->bustype == SSB_BUSTYPE_SSB) 106 - return ssb_mips_irq(bus->chipco.dev) + 2; 107 - else 108 - return -EINVAL; 109 } 110 111 static int ssb_gpio_chipco_init(struct ssb_bus *bus) 112 { 113 struct gpio_chip *chip = &bus->gpio; 114 115 chip->label = "ssb_chipco_gpio"; 116 chip->owner = THIS_MODULE; ··· 230 chip->set = ssb_gpio_chipco_set_value; 231 chip->direction_input = ssb_gpio_chipco_direction_input; 232 chip->direction_output = ssb_gpio_chipco_direction_output; 233 - chip->to_irq = ssb_gpio_chipco_to_irq; 234 chip->ngpio = 16; 235 /* There is just one SoC in one device and its GPIO addresses should be 236 * deterministic to address them more easily. The other buses could get ··· 242 else 243 chip->base = -1; 244 245 - return gpiochip_add(chip); 246 } 247 248 #ifdef CONFIG_SSB_DRIVER_EXTIF 249 ··· 295 return 0; 296 } 297 298 - static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio) 299 { 300 - struct ssb_bus *bus = ssb_gpio_get_bus(chip); 301 302 - if (bus->bustype == SSB_BUSTYPE_SSB) 303 - return ssb_mips_irq(bus->extif.dev) + 2; 304 - else 305 - return -EINVAL; 306 } 307 308 static int ssb_gpio_extif_init(struct ssb_bus *bus) 309 { 310 struct gpio_chip *chip = &bus->gpio; 311 312 chip->label = "ssb_extif_gpio"; 313 chip->owner = THIS_MODULE; ··· 423 chip->set = ssb_gpio_extif_set_value; 424 chip->direction_input = ssb_gpio_extif_direction_input; 425 chip->direction_output = ssb_gpio_extif_direction_output; 426 - chip->to_irq = ssb_gpio_extif_to_irq; 427 chip->ngpio = 5; 428 /* There is just one SoC in one device and its GPIO addresses should be 429 * deterministic to address them more easily. The other buses could get ··· 435 else 436 chip->base = -1; 437 438 - return gpiochip_add(chip); 439 } 440 441 #else ··· 454 return -ENOTSUPP; 455 } 456 #endif 457 458 int ssb_gpio_init(struct ssb_bus *bus) 459 {
··· 9 */ 10 11 #include <linux/gpio.h> 12 + #include <linux/irq.h> 13 + #include <linux/interrupt.h> 14 + #include <linux/irqdomain.h> 15 #include <linux/export.h> 16 #include <linux/ssb/ssb.h> 17 18 #include "ssb_private.h" 19 20 + 21 + /************************************************** 22 + * Shared 23 + **************************************************/ 24 + 25 static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip) 26 { 27 return container_of(chip, struct ssb_bus, gpio); 28 } 29 + 30 + #if IS_ENABLED(CONFIG_SSB_EMBEDDED) 31 + static int ssb_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) 32 + { 33 + struct ssb_bus *bus = ssb_gpio_get_bus(chip); 34 + 35 + if (bus->bustype == SSB_BUSTYPE_SSB) 36 + return irq_find_mapping(bus->irq_domain, gpio); 37 + else 38 + return -EINVAL; 39 + } 40 + #endif 41 + 42 + /************************************************** 43 + * ChipCommon 44 + **************************************************/ 45 46 static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio) 47 { ··· 74 ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0); 75 } 76 77 + #if IS_ENABLED(CONFIG_SSB_EMBEDDED) 78 + static void ssb_gpio_irq_chipco_mask(struct irq_data *d) 79 { 80 + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); 81 + int gpio = irqd_to_hwirq(d); 82 83 + ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), 0); 84 } 85 + 86 + static void ssb_gpio_irq_chipco_unmask(struct irq_data *d) 87 + { 88 + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); 89 + int gpio = irqd_to_hwirq(d); 90 + u32 val = ssb_chipco_gpio_in(&bus->chipco, BIT(gpio)); 91 + 92 + ssb_chipco_gpio_polarity(&bus->chipco, BIT(gpio), val); 93 + ssb_chipco_gpio_intmask(&bus->chipco, BIT(gpio), BIT(gpio)); 94 + } 95 + 96 + static struct irq_chip ssb_gpio_irq_chipco_chip = { 97 + .name = "SSB-GPIO-CC", 98 + .irq_mask = ssb_gpio_irq_chipco_mask, 99 + .irq_unmask = ssb_gpio_irq_chipco_unmask, 100 + }; 101 + 102 + static irqreturn_t ssb_gpio_irq_chipco_handler(int irq, void *dev_id) 103 + { 104 + struct ssb_bus *bus = dev_id; 105 + struct ssb_chipcommon *chipco = &bus->chipco; 106 + u32 val = chipco_read32(chipco, SSB_CHIPCO_GPIOIN); 107 + u32 mask = chipco_read32(chipco, SSB_CHIPCO_GPIOIRQ); 108 + u32 pol = chipco_read32(chipco, SSB_CHIPCO_GPIOPOL); 109 + unsigned long irqs = (val ^ pol) & mask; 110 + int gpio; 111 + 112 + if (!irqs) 113 + return IRQ_NONE; 114 + 115 + for_each_set_bit(gpio, &irqs, bus->gpio.ngpio) 116 + generic_handle_irq(ssb_gpio_to_irq(&bus->gpio, gpio)); 117 + ssb_chipco_gpio_polarity(chipco, irqs, val & irqs); 118 + 119 + return IRQ_HANDLED; 120 + } 121 + 122 + static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus) 123 + { 124 + struct ssb_chipcommon *chipco = &bus->chipco; 125 + struct gpio_chip *chip = &bus->gpio; 126 + int gpio, hwirq, err; 127 + 128 + if (bus->bustype != SSB_BUSTYPE_SSB) 129 + return 0; 130 + 131 + bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio, 132 + &irq_domain_simple_ops, chipco); 133 + if (!bus->irq_domain) { 134 + err = -ENODEV; 135 + goto err_irq_domain; 136 + } 137 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 138 + int irq = irq_create_mapping(bus->irq_domain, gpio); 139 + 140 + irq_set_chip_data(irq, bus); 141 + irq_set_chip_and_handler(irq, &ssb_gpio_irq_chipco_chip, 142 + handle_simple_irq); 143 + } 144 + 145 + hwirq = ssb_mips_irq(bus->chipco.dev) + 2; 146 + err = request_irq(hwirq, ssb_gpio_irq_chipco_handler, IRQF_SHARED, 147 + "gpio", bus); 148 + if (err) 149 + goto err_req_irq; 150 + 151 + ssb_chipco_gpio_intmask(&bus->chipco, ~0, 0); 152 + chipco_set32(chipco, SSB_CHIPCO_IRQMASK, SSB_CHIPCO_IRQ_GPIO); 153 + 154 + return 0; 155 + 156 + err_req_irq: 157 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 158 + int irq = irq_find_mapping(bus->irq_domain, gpio); 159 + 160 + irq_dispose_mapping(irq); 161 + } 162 + irq_domain_remove(bus->irq_domain); 163 + err_irq_domain: 164 + return err; 165 + } 166 + 167 + static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus) 168 + { 169 + struct ssb_chipcommon *chipco = &bus->chipco; 170 + struct gpio_chip *chip = &bus->gpio; 171 + int gpio; 172 + 173 + if (bus->bustype != SSB_BUSTYPE_SSB) 174 + return; 175 + 176 + chipco_mask32(chipco, SSB_CHIPCO_IRQMASK, ~SSB_CHIPCO_IRQ_GPIO); 177 + free_irq(ssb_mips_irq(bus->chipco.dev) + 2, chipco); 178 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 179 + int irq = irq_find_mapping(bus->irq_domain, gpio); 180 + 181 + irq_dispose_mapping(irq); 182 + } 183 + irq_domain_remove(bus->irq_domain); 184 + } 185 + #else 186 + static int ssb_gpio_irq_chipco_domain_init(struct ssb_bus *bus) 187 + { 188 + return 0; 189 + } 190 + 191 + static void ssb_gpio_irq_chipco_domain_exit(struct ssb_bus *bus) 192 + { 193 + } 194 + #endif 195 196 static int ssb_gpio_chipco_init(struct ssb_bus *bus) 197 { 198 struct gpio_chip *chip = &bus->gpio; 199 + int err; 200 201 chip->label = "ssb_chipco_gpio"; 202 chip->owner = THIS_MODULE; ··· 96 chip->set = ssb_gpio_chipco_set_value; 97 chip->direction_input = ssb_gpio_chipco_direction_input; 98 chip->direction_output = ssb_gpio_chipco_direction_output; 99 + #if IS_ENABLED(CONFIG_SSB_EMBEDDED) 100 + chip->to_irq = ssb_gpio_to_irq; 101 + #endif 102 chip->ngpio = 16; 103 /* There is just one SoC in one device and its GPIO addresses should be 104 * deterministic to address them more easily. The other buses could get ··· 106 else 107 chip->base = -1; 108 109 + err = ssb_gpio_irq_chipco_domain_init(bus); 110 + if (err) 111 + return err; 112 + 113 + err = gpiochip_add(chip); 114 + if (err) { 115 + ssb_gpio_irq_chipco_domain_exit(bus); 116 + return err; 117 + } 118 + 119 + return 0; 120 } 121 + 122 + /************************************************** 123 + * EXTIF 124 + **************************************************/ 125 126 #ifdef CONFIG_SSB_DRIVER_EXTIF 127 ··· 145 return 0; 146 } 147 148 + #if IS_ENABLED(CONFIG_SSB_EMBEDDED) 149 + static void ssb_gpio_irq_extif_mask(struct irq_data *d) 150 { 151 + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); 152 + int gpio = irqd_to_hwirq(d); 153 154 + ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), 0); 155 } 156 + 157 + static void ssb_gpio_irq_extif_unmask(struct irq_data *d) 158 + { 159 + struct ssb_bus *bus = irq_data_get_irq_chip_data(d); 160 + int gpio = irqd_to_hwirq(d); 161 + u32 val = ssb_extif_gpio_in(&bus->extif, BIT(gpio)); 162 + 163 + ssb_extif_gpio_polarity(&bus->extif, BIT(gpio), val); 164 + ssb_extif_gpio_intmask(&bus->extif, BIT(gpio), BIT(gpio)); 165 + } 166 + 167 + static struct irq_chip ssb_gpio_irq_extif_chip = { 168 + .name = "SSB-GPIO-EXTIF", 169 + .irq_mask = ssb_gpio_irq_extif_mask, 170 + .irq_unmask = ssb_gpio_irq_extif_unmask, 171 + }; 172 + 173 + static irqreturn_t ssb_gpio_irq_extif_handler(int irq, void *dev_id) 174 + { 175 + struct ssb_bus *bus = dev_id; 176 + struct ssb_extif *extif = &bus->extif; 177 + u32 val = ssb_read32(extif->dev, SSB_EXTIF_GPIO_IN); 178 + u32 mask = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTMASK); 179 + u32 pol = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTPOL); 180 + unsigned long irqs = (val ^ pol) & mask; 181 + int gpio; 182 + 183 + if (!irqs) 184 + return IRQ_NONE; 185 + 186 + for_each_set_bit(gpio, &irqs, bus->gpio.ngpio) 187 + generic_handle_irq(ssb_gpio_to_irq(&bus->gpio, gpio)); 188 + ssb_extif_gpio_polarity(extif, irqs, val & irqs); 189 + 190 + return IRQ_HANDLED; 191 + } 192 + 193 + static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus) 194 + { 195 + struct ssb_extif *extif = &bus->extif; 196 + struct gpio_chip *chip = &bus->gpio; 197 + int gpio, hwirq, err; 198 + 199 + if (bus->bustype != SSB_BUSTYPE_SSB) 200 + return 0; 201 + 202 + bus->irq_domain = irq_domain_add_linear(NULL, chip->ngpio, 203 + &irq_domain_simple_ops, extif); 204 + if (!bus->irq_domain) { 205 + err = -ENODEV; 206 + goto err_irq_domain; 207 + } 208 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 209 + int irq = irq_create_mapping(bus->irq_domain, gpio); 210 + 211 + irq_set_chip_data(irq, bus); 212 + irq_set_chip_and_handler(irq, &ssb_gpio_irq_extif_chip, 213 + handle_simple_irq); 214 + } 215 + 216 + hwirq = ssb_mips_irq(bus->extif.dev) + 2; 217 + err = request_irq(hwirq, ssb_gpio_irq_extif_handler, IRQF_SHARED, 218 + "gpio", bus); 219 + if (err) 220 + goto err_req_irq; 221 + 222 + ssb_extif_gpio_intmask(&bus->extif, ~0, 0); 223 + 224 + return 0; 225 + 226 + err_req_irq: 227 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 228 + int irq = irq_find_mapping(bus->irq_domain, gpio); 229 + 230 + irq_dispose_mapping(irq); 231 + } 232 + irq_domain_remove(bus->irq_domain); 233 + err_irq_domain: 234 + return err; 235 + } 236 + 237 + static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus) 238 + { 239 + struct ssb_extif *extif = &bus->extif; 240 + struct gpio_chip *chip = &bus->gpio; 241 + int gpio; 242 + 243 + if (bus->bustype != SSB_BUSTYPE_SSB) 244 + return; 245 + 246 + free_irq(ssb_mips_irq(bus->extif.dev) + 2, extif); 247 + for (gpio = 0; gpio < chip->ngpio; gpio++) { 248 + int irq = irq_find_mapping(bus->irq_domain, gpio); 249 + 250 + irq_dispose_mapping(irq); 251 + } 252 + irq_domain_remove(bus->irq_domain); 253 + } 254 + #else 255 + static int ssb_gpio_irq_extif_domain_init(struct ssb_bus *bus) 256 + { 257 + return 0; 258 + } 259 + 260 + static void ssb_gpio_irq_extif_domain_exit(struct ssb_bus *bus) 261 + { 262 + } 263 + #endif 264 265 static int ssb_gpio_extif_init(struct ssb_bus *bus) 266 { 267 struct gpio_chip *chip = &bus->gpio; 268 + int err; 269 270 chip->label = "ssb_extif_gpio"; 271 chip->owner = THIS_MODULE; ··· 165 chip->set = ssb_gpio_extif_set_value; 166 chip->direction_input = ssb_gpio_extif_direction_input; 167 chip->direction_output = ssb_gpio_extif_direction_output; 168 + #if IS_ENABLED(CONFIG_SSB_EMBEDDED) 169 + chip->to_irq = ssb_gpio_to_irq; 170 + #endif 171 chip->ngpio = 5; 172 /* There is just one SoC in one device and its GPIO addresses should be 173 * deterministic to address them more easily. The other buses could get ··· 175 else 176 chip->base = -1; 177 178 + err = ssb_gpio_irq_extif_domain_init(bus); 179 + if (err) 180 + return err; 181 + 182 + err = gpiochip_add(chip); 183 + if (err) { 184 + ssb_gpio_irq_extif_domain_exit(bus); 185 + return err; 186 + } 187 + 188 + return 0; 189 } 190 191 #else ··· 184 return -ENOTSUPP; 185 } 186 #endif 187 + 188 + /************************************************** 189 + * Init 190 + **************************************************/ 191 192 int ssb_gpio_init(struct ssb_bus *bus) 193 {
+7 -5
drivers/ssb/main.c
··· 593 ssb_pcicore_init(&bus->pcicore); 594 if (bus->bustype == SSB_BUSTYPE_SSB) 595 ssb_watchdog_register(bus); 596 ssb_bus_may_powerdown(bus); 597 598 err = ssb_devices_register(bus); ··· 837 ssb_chipcommon_init(&bus->chipco); 838 ssb_extif_init(&bus->extif); 839 ssb_mipscore_init(&bus->mipscore); 840 - err = ssb_gpio_init(bus); 841 - if (err == -ENOTSUPP) 842 - ssb_dbg("GPIO driver not activated\n"); 843 - else if (err) 844 - ssb_dbg("Error registering GPIO driver: %i\n", err); 845 err = ssb_fetch_invariants(bus, get_invariants); 846 if (err) { 847 ssb_bus_may_powerdown(bus);
··· 593 ssb_pcicore_init(&bus->pcicore); 594 if (bus->bustype == SSB_BUSTYPE_SSB) 595 ssb_watchdog_register(bus); 596 + 597 + err = ssb_gpio_init(bus); 598 + if (err == -ENOTSUPP) 599 + ssb_dbg("GPIO driver not activated\n"); 600 + else if (err) 601 + ssb_dbg("Error registering GPIO driver: %i\n", err); 602 + 603 ssb_bus_may_powerdown(bus); 604 605 err = ssb_devices_register(bus); ··· 830 ssb_chipcommon_init(&bus->chipco); 831 ssb_extif_init(&bus->extif); 832 ssb_mipscore_init(&bus->mipscore); 833 err = ssb_fetch_invariants(bus, get_invariants); 834 if (err) { 835 ssb_bus_may_powerdown(bus);
+3 -6
drivers/tty/serial/bcm63xx_uart.c
··· 29 #include <linux/sysrq.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 - 33 - #include <bcm63xx_irq.h> 34 - #include <bcm63xx_regs.h> 35 - #include <bcm63xx_io.h> 36 37 #define BCM63XX_NR_UARTS 2 38 ··· 78 static inline unsigned int bcm_uart_readl(struct uart_port *port, 79 unsigned int offset) 80 { 81 - return bcm_readl(port->membase + offset); 82 } 83 84 static inline void bcm_uart_writel(struct uart_port *port, 85 unsigned int value, unsigned int offset) 86 { 87 - bcm_writel(value, port->membase + offset); 88 } 89 90 /*
··· 29 #include <linux/sysrq.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 + #include <linux/serial_bcm63xx.h> 33 34 #define BCM63XX_NR_UARTS 2 35 ··· 81 static inline unsigned int bcm_uart_readl(struct uart_port *port, 82 unsigned int offset) 83 { 84 + return __raw_readl(port->membase + offset); 85 } 86 87 static inline void bcm_uart_writel(struct uart_port *port, 88 unsigned int value, unsigned int offset) 89 { 90 + __raw_writel(value, port->membase + offset); 91 } 92 93 /*
+1
include/linux/bcma/bcma_driver_chipcommon.h
··· 640 spinlock_t gpio_lock; 641 #ifdef CONFIG_BCMA_DRIVER_GPIO 642 struct gpio_chip gpio; 643 #endif 644 }; 645
··· 640 spinlock_t gpio_lock; 641 #ifdef CONFIG_BCMA_DRIVER_GPIO 642 struct gpio_chip gpio; 643 + struct irq_domain *irq_domain; 644 #endif 645 }; 646
+119
include/linux/serial_bcm63xx.h
···
··· 1 + #ifndef _LINUX_SERIAL_BCM63XX_H 2 + #define _LINUX_SERIAL_BCM63XX_H 3 + 4 + /* UART Control Register */ 5 + #define UART_CTL_REG 0x0 6 + #define UART_CTL_RXTMOUTCNT_SHIFT 0 7 + #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) 8 + #define UART_CTL_RSTTXDN_SHIFT 5 9 + #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) 10 + #define UART_CTL_RSTRXFIFO_SHIFT 6 11 + #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) 12 + #define UART_CTL_RSTTXFIFO_SHIFT 7 13 + #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) 14 + #define UART_CTL_STOPBITS_SHIFT 8 15 + #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) 16 + #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) 17 + #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) 18 + #define UART_CTL_BITSPERSYM_SHIFT 12 19 + #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) 20 + #define UART_CTL_XMITBRK_SHIFT 14 21 + #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) 22 + #define UART_CTL_RSVD_SHIFT 15 23 + #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) 24 + #define UART_CTL_RXPAREVEN_SHIFT 16 25 + #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) 26 + #define UART_CTL_RXPAREN_SHIFT 17 27 + #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) 28 + #define UART_CTL_TXPAREVEN_SHIFT 18 29 + #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) 30 + #define UART_CTL_TXPAREN_SHIFT 18 31 + #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) 32 + #define UART_CTL_LOOPBACK_SHIFT 20 33 + #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) 34 + #define UART_CTL_RXEN_SHIFT 21 35 + #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) 36 + #define UART_CTL_TXEN_SHIFT 22 37 + #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) 38 + #define UART_CTL_BRGEN_SHIFT 23 39 + #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) 40 + 41 + /* UART Baudword register */ 42 + #define UART_BAUD_REG 0x4 43 + 44 + /* UART Misc Control register */ 45 + #define UART_MCTL_REG 0x8 46 + #define UART_MCTL_DTR_SHIFT 0 47 + #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) 48 + #define UART_MCTL_RTS_SHIFT 1 49 + #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) 50 + #define UART_MCTL_RXFIFOTHRESH_SHIFT 8 51 + #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) 52 + #define UART_MCTL_TXFIFOTHRESH_SHIFT 12 53 + #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) 54 + #define UART_MCTL_RXFIFOFILL_SHIFT 16 55 + #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) 56 + #define UART_MCTL_TXFIFOFILL_SHIFT 24 57 + #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) 58 + 59 + /* UART External Input Configuration register */ 60 + #define UART_EXTINP_REG 0xc 61 + #define UART_EXTINP_RI_SHIFT 0 62 + #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) 63 + #define UART_EXTINP_CTS_SHIFT 1 64 + #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) 65 + #define UART_EXTINP_DCD_SHIFT 2 66 + #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) 67 + #define UART_EXTINP_DSR_SHIFT 3 68 + #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) 69 + #define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) 70 + #define UART_EXTINP_IRMASK(x) (1 << (x + 8)) 71 + #define UART_EXTINP_IR_RI 0 72 + #define UART_EXTINP_IR_CTS 1 73 + #define UART_EXTINP_IR_DCD 2 74 + #define UART_EXTINP_IR_DSR 3 75 + #define UART_EXTINP_RI_NOSENSE_SHIFT 16 76 + #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) 77 + #define UART_EXTINP_CTS_NOSENSE_SHIFT 17 78 + #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) 79 + #define UART_EXTINP_DCD_NOSENSE_SHIFT 18 80 + #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) 81 + #define UART_EXTINP_DSR_NOSENSE_SHIFT 19 82 + #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) 83 + 84 + /* UART Interrupt register */ 85 + #define UART_IR_REG 0x10 86 + #define UART_IR_MASK(x) (1 << (x + 16)) 87 + #define UART_IR_STAT(x) (1 << (x)) 88 + #define UART_IR_EXTIP 0 89 + #define UART_IR_TXUNDER 1 90 + #define UART_IR_TXOVER 2 91 + #define UART_IR_TXTRESH 3 92 + #define UART_IR_TXRDLATCH 4 93 + #define UART_IR_TXEMPTY 5 94 + #define UART_IR_RXUNDER 6 95 + #define UART_IR_RXOVER 7 96 + #define UART_IR_RXTIMEOUT 8 97 + #define UART_IR_RXFULL 9 98 + #define UART_IR_RXTHRESH 10 99 + #define UART_IR_RXNOTEMPTY 11 100 + #define UART_IR_RXFRAMEERR 12 101 + #define UART_IR_RXPARERR 13 102 + #define UART_IR_RXBRK 14 103 + #define UART_IR_TXDONE 15 104 + 105 + /* UART Fifo register */ 106 + #define UART_FIFO_REG 0x14 107 + #define UART_FIFO_VALID_SHIFT 0 108 + #define UART_FIFO_VALID_MASK 0xff 109 + #define UART_FIFO_FRAMEERR_SHIFT 8 110 + #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) 111 + #define UART_FIFO_PARERR_SHIFT 9 112 + #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) 113 + #define UART_FIFO_BRKDET_SHIFT 10 114 + #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) 115 + #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ 116 + UART_FIFO_PARERR_MASK | \ 117 + UART_FIFO_BRKDET_MASK) 118 + 119 + #endif /* _LINUX_SERIAL_BCM63XX_H */
+1
include/linux/ssb/ssb.h
··· 486 #endif /* EMBEDDED */ 487 #ifdef CONFIG_SSB_DRIVER_GPIO 488 struct gpio_chip gpio; 489 #endif /* DRIVER_GPIO */ 490 491 /* Internal-only stuff follows. Do not touch. */
··· 486 #endif /* EMBEDDED */ 487 #ifdef CONFIG_SSB_DRIVER_GPIO 488 struct gpio_chip gpio; 489 + struct irq_domain *irq_domain; 490 #endif /* DRIVER_GPIO */ 491 492 /* Internal-only stuff follows. Do not touch. */