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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/include:cleanup vega10 gc header files.
Cleanup asic_reg/vega10/GC folder.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Feifei Xu
and committed by
Alex Deucher
cde5c34f
18297a21
+14
-14
+2
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
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#include "soc15d.h"
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#include "vega10/soc15ip.h"
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-
#include "vega10/GC/gc_9_0_offset.h"
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-
#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "vega10/vega10_enum.h"
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#include "hdp/hdp_4_0_offset.h"
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+3
-3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
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-3
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
···
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#include "gfxhub_v1_0.h"
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#include "vega10/soc15ip.h"
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#include "vega10/GC/gc_9_0_offset.h"
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#include "vega10/GC/gc_9_0_sh_mask.h"
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-
#include "vega10/GC/gc_9_0_default.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_default.h"
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#include "vega10/vega10_enum.h"
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#include "soc15_common.h"
+1
-1
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+1
-1
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
···
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#include "vega10/soc15ip.h"
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#include "hdp/hdp_4_0_offset.h"
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#include "hdp/hdp_4_0_sh_mask.h"
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-
#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "dce/dce_12_0_offset.h"
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#include "dce/dce_12_0_sh_mask.h"
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#include "vega10/vega10_enum.h"
+2
-2
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
+2
-2
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
···
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#include "vega10/soc15ip.h"
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#include "vega10/NBIO/nbio_6_1_offset.h"
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#include "vega10/NBIO/nbio_6_1_sh_mask.h"
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-
#include "vega10/GC/gc_9_0_offset.h"
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-
#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "soc15.h"
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#include "vega10_ih.h"
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#include "soc15_common.h"
+1
-1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+1
-1
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+2
-2
drivers/gpu/drm/amd/amdgpu/soc15.c
+2
-2
drivers/gpu/drm/amd/amdgpu/soc15.c
···
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#include "vega10/soc15ip.h"
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#include "uvd/uvd_7_0_offset.h"
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#include "vega10/GC/gc_9_0_offset.h"
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#include "vega10/GC/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "sdma0/sdma0_4_0_offset.h"
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#include "sdma1/sdma1_4_0_offset.h"
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#include "hdp/hdp_4_0_offset.h"
drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h
drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h
+3
-3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
+3
-3
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
···
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#include "asic_reg/mp/mp_9_0_offset.h"
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#include "asic_reg/mp/mp_9_0_sh_mask.h"
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#include "asic_reg/vega10/GC/gc_9_0_default.h"
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#include "asic_reg/vega10/GC/gc_9_0_offset.h"
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-
#include "asic_reg/vega10/GC/gc_9_0_sh_mask.h"
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#include "asic_reg/gc/gc_9_0_default.h"
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#include "asic_reg/gc/gc_9_0_offset.h"
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#include "asic_reg/gc/gc_9_0_sh_mask.h"
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#include "asic_reg/vega10/NBIO/nbio_6_1_default.h"
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#include "asic_reg/vega10/NBIO/nbio_6_1_offset.h"