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kernel
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linux
ASoC: Allow configuration of WM8904 GPIO pin functions
Provide platform data allowing the configuration of the GPIO pins
on the WM8904 to be selected, allowing alternate functions to be
enabled.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
+84
-66
+72
-2
include/sound/wm8904.h
+72
-2
include/sound/wm8904.h
···
15
15
#ifndef __MFD_WM8994_PDATA_H__
16
16
#define __MFD_WM8994_PDATA_H__
17
17
18
-
#define WM8904_DRC_REGS 4
19
-
#define WM8904_EQ_REGS 25
18
+
/* Used to enable configuration of a GPIO to all zeros */
19
+
#define WM8904_GPIO_NO_CONFIG 0x8000
20
+
21
+
/*
22
+
* R121 (0x79) - GPIO Control 1
23
+
*/
24
+
#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
25
+
#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
26
+
#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
27
+
#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
28
+
#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
29
+
#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
30
+
#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
31
+
#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
32
+
#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
33
+
#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
34
+
#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
35
+
36
+
/*
37
+
* R122 (0x7A) - GPIO Control 2
38
+
*/
39
+
#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
40
+
#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
41
+
#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
42
+
#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
43
+
#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
44
+
#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
45
+
#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
46
+
#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
47
+
#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
48
+
#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
49
+
#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
50
+
51
+
/*
52
+
* R123 (0x7B) - GPIO Control 3
53
+
*/
54
+
#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
55
+
#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
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+
#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
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+
#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
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+
#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
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+
#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
60
+
#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
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+
#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
62
+
#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
63
+
#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
64
+
#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
65
+
66
+
/*
67
+
* R124 (0x7C) - GPIO Control 4
68
+
*/
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+
#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
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+
#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
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+
#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
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+
#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
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+
#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
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+
#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
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+
#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
76
+
#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
77
+
#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
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+
#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
79
+
#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
80
+
#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
81
+
#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
82
+
#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
83
+
#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
84
+
85
+
#define WM8904_GPIO_REGS 4
86
+
#define WM8904_DRC_REGS 4
87
+
#define WM8904_EQ_REGS 25
20
88
21
89
/**
22
90
* DRC configurations are specified with a label and a set of register
···
120
52
121
53
int num_retune_mobile_cfgs;
122
54
struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
55
+
56
+
u32 gpio_cfg[WM8904_GPIO_REGS];
123
57
};
124
58
125
59
#endif
+12
sound/soc/codecs/wm8904.c
+12
sound/soc/codecs/wm8904.c
···
2425
2425
static int wm8904_register(struct wm8904_priv *wm8904,
2426
2426
enum snd_soc_control_type control)
2427
2427
{
2428
+
struct wm8904_pdata *pdata = wm8904->pdata;
2428
2429
int ret;
2429
2430
struct snd_soc_codec *codec = &wm8904->codec;
2430
2431
int i;
···
2530
2529
wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU |
2531
2530
WM8904_LINEOUTRZC;
2532
2531
wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE;
2532
+
2533
+
/* Apply configuration from the platform data. */
2534
+
if (wm8904->pdata) {
2535
+
for (i = 0; i < WM8904_GPIO_REGS; i++) {
2536
+
if (!pdata->gpio_cfg[i])
2537
+
continue;
2538
+
2539
+
wm8904->reg_cache[WM8904_GPIO_CONTROL_1 + i]
2540
+
= pdata->gpio_cfg[i] & 0xffff;
2541
+
}
2542
+
}
2533
2543
2534
2544
/* Set Class W by default - this will be managed by the Class
2535
2545
* G widget at runtime where bypass paths are available.
-64
sound/soc/codecs/wm8904.h
-64
sound/soc/codecs/wm8904.h
···
1200
1200
#define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */
1201
1201
1202
1202
/*
1203
-
* R121 (0x79) - GPIO Control 1
1204
-
*/
1205
-
#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
1206
-
#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
1207
-
#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
1208
-
#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
1209
-
#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
1210
-
#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
1211
-
#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
1212
-
#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
1213
-
#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
1214
-
#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
1215
-
#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
1216
-
1217
-
/*
1218
-
* R122 (0x7A) - GPIO Control 2
1219
-
*/
1220
-
#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
1221
-
#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
1222
-
#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
1223
-
#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
1224
-
#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
1225
-
#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
1226
-
#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
1227
-
#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
1228
-
#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
1229
-
#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
1230
-
#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
1231
-
1232
-
/*
1233
-
* R123 (0x7B) - GPIO Control 3
1234
-
*/
1235
-
#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
1236
-
#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
1237
-
#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
1238
-
#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
1239
-
#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
1240
-
#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
1241
-
#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
1242
-
#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
1243
-
#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
1244
-
#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
1245
-
#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
1246
-
1247
-
/*
1248
-
* R124 (0x7C) - GPIO Control 4
1249
-
*/
1250
-
#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
1251
-
#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
1252
-
#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
1253
-
#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
1254
-
#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
1255
-
#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
1256
-
#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
1257
-
#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
1258
-
#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
1259
-
#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
1260
-
#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
1261
-
#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
1262
-
#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
1263
-
#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
1264
-
#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
1265
-
1266
-
/*
1267
1203
* R126 (0x7E) - Digital Pulls
1268
1204
*/
1269
1205
#define WM8904_MCLK_PU 0x0080 /* MCLK_PU */