tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
x86/cpufeature: Carve out X86_FEATURE_*
Move them to a separate header and have the following
dependency:
x86/cpufeatures.h <- x86/processor.h <- x86/cpufeature.h
This makes it easier to use the header in asm code and not
include the whole cpufeature.h and add guards for asm.
Suggested-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1453842730-28463-5-git-send-email-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
authored by
Borislav Petkov
and committed by
Ingo Molnar
cd4d09ec
78726ee5
+336
-328
+1
-1
Documentation/kernel-parameters.txt
+1
-1
Documentation/kernel-parameters.txt
···
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clearcpuid=BITNUM [X86]
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Disable CPUID feature X for the kernel. See
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arch/x86/include/asm/cpufeature.h for the valid bit
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+
arch/x86/include/asm/cpufeatures.h for the valid bit
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numbers. Note the Linux specific bits are not necessarily
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stable over kernel options, but the vendor specific
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ones should be.
+1
-1
arch/x86/boot/cpuflags.h
+1
-1
arch/x86/boot/cpuflags.h
+1
-1
arch/x86/boot/mkcpustr.c
+1
-1
arch/x86/boot/mkcpustr.c
+1
-1
arch/x86/crypto/crc32-pclmul_glue.c
+1
-1
arch/x86/crypto/crc32-pclmul_glue.c
+1
-1
arch/x86/crypto/crc32c-intel_glue.c
+1
-1
arch/x86/crypto/crc32c-intel_glue.c
+1
-1
arch/x86/crypto/crct10dif-pclmul_glue.c
+1
-1
arch/x86/crypto/crct10dif-pclmul_glue.c
+1
arch/x86/entry/common.c
+1
arch/x86/entry/common.c
+1
-1
arch/x86/entry/entry_32.S
+1
-1
arch/x86/entry/entry_32.S
-1
arch/x86/entry/vdso/vdso32-setup.c
-1
arch/x86/entry/vdso/vdso32-setup.c
+1
-1
arch/x86/entry/vdso/vdso32/system_call.S
+1
-1
arch/x86/entry/vdso/vdso32/system_call.S
+1
arch/x86/entry/vdso/vma.c
+1
arch/x86/entry/vdso/vma.c
-6
arch/x86/include/asm/alternative.h
-6
arch/x86/include/asm/alternative.h
···
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".popsection"
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/*
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* This must be included *after* the definition of ALTERNATIVE due to
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* <asm/arch_hweight.h>
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*/
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#include <asm/cpufeature.h>
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/*
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* Alternative instructions for different CPU types or capabilities.
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*
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* This allows to use optimized instructions even on generic binary
-1
arch/x86/include/asm/apic.h
-1
arch/x86/include/asm/apic.h
+2
arch/x86/include/asm/arch_hweight.h
+2
arch/x86/include/asm/arch_hweight.h
+1
arch/x86/include/asm/cmpxchg.h
+1
arch/x86/include/asm/cmpxchg.h
+1
-283
arch/x86/include/asm/cpufeature.h
+1
-283
arch/x86/include/asm/cpufeature.h
···
1
-
/*
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* Defines x86 CPU feature bits
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-
*/
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#ifndef _ASM_X86_CPUFEATURE_H
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#define _ASM_X86_CPUFEATURE_H
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#ifndef _ASM_X86_REQUIRED_FEATURES_H
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#include <asm/required-features.h>
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#endif
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#ifndef _ASM_X86_DISABLED_FEATURES_H
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#include <asm/disabled-features.h>
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#endif
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#define NCAPINTS 16 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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/*
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* Note: If the comment begins with a quoted string, that string is used
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* in /proc/cpuinfo instead of the macro name. If the string is "",
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* this feature bit is not displayed in /proc/cpuinfo at all.
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*/
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/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
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#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
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#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
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#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
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#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
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#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
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#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
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#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
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#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
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#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
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#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
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#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
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#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
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#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
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#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
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/* (plus FCMOVcc, FCOMI with FPU) */
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#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
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#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
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#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
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#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
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#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
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#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
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#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
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#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
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#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
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#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
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#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
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#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
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#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
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#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
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/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/* Don't duplicate feature flags which are redundant with Intel! */
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#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
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#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
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#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
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#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
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#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
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#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
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#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
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#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
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/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
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#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
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#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
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#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
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/* Other features, Linux-defined mapping, word 3 */
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/* This range is used for feature bits which conflict or are synthesized */
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#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
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#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
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/* cpu types for specific tunings: */
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#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
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#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
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#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
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#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
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#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
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#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
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/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
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#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
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#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
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/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
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#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
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#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
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/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
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#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
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#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
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#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
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#define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
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#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
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#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
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#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
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#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
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#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
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#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
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#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
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#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
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#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
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#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
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#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
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#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
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#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
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#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
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#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
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#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
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#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
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#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
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#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
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#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
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#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
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#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
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#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
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#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
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#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
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#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
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#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
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#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
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#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
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#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
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#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
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#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
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#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
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#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
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#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
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#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
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#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
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#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
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-
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/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
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#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
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#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
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#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
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#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
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#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
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#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
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#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
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#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
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#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
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#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
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#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
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#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
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#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
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#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
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#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
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#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
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#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
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#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
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#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
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#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
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#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
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#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
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#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
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#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
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#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
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-
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/*
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* Auxiliary flags: Linux defined - For features scattered in various
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* CPUID levels like 0x6, 0xA etc, word 7.
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-
*
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* Reuse free bits when adding new feature flags!
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-
*/
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-
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#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
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#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
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-
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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-
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
196
-
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/* Virtualization flags: Linux defined, word 8 */
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-
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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-
#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
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-
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
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#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
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#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
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-
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#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
205
-
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
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-
207
-
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
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-
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
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#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
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#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
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#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
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#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
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#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
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-
#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
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#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
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#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
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#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
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#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
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#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
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#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
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#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
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#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
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#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
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-
#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
226
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#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
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-
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
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#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
229
-
#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
230
-
#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
231
-
#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
232
-
233
-
/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
234
-
#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
235
-
#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
236
-
#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
237
-
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
238
-
239
-
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
240
-
#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
241
-
242
-
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
243
-
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
244
-
245
-
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
246
-
#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
247
-
248
-
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
249
-
#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
250
-
#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
251
-
#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
252
-
#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
253
-
#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
254
-
#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
255
-
#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
256
-
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
257
-
#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
258
-
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
259
-
260
-
/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
261
-
#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
262
-
#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
263
-
#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
264
-
#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
265
-
#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
266
-
#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
267
-
#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
268
-
#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
269
-
#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
270
-
#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
271
-
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
272
-
273
-
/*
274
-
* BUG word(s)
275
-
*/
276
-
#define X86_BUG(x) (NCAPINTS*32 + (x))
277
-
278
-
#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
279
-
#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
280
-
#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
281
-
#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
282
-
#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
283
-
#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
284
-
#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
285
-
#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
286
-
#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
4
+
#include <asm/processor.h>
287
5
288
6
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
289
7
+288
arch/x86/include/asm/cpufeatures.h
+288
arch/x86/include/asm/cpufeatures.h
···
1
+
#ifndef _ASM_X86_CPUFEATURES_H
2
+
#define _ASM_X86_CPUFEATURES_H
3
+
4
+
#ifndef _ASM_X86_REQUIRED_FEATURES_H
5
+
#include <asm/required-features.h>
6
+
#endif
7
+
8
+
#ifndef _ASM_X86_DISABLED_FEATURES_H
9
+
#include <asm/disabled-features.h>
10
+
#endif
11
+
12
+
/*
13
+
* Defines x86 CPU feature bits
14
+
*/
15
+
#define NCAPINTS 16 /* N 32-bit words worth of info */
16
+
#define NBUGINTS 1 /* N 32-bit bug flags */
17
+
18
+
/*
19
+
* Note: If the comment begins with a quoted string, that string is used
20
+
* in /proc/cpuinfo instead of the macro name. If the string is "",
21
+
* this feature bit is not displayed in /proc/cpuinfo at all.
22
+
*/
23
+
24
+
/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
25
+
#define X86_FEATURE_FPU ( 0*32+ 0) /* Onboard FPU */
26
+
#define X86_FEATURE_VME ( 0*32+ 1) /* Virtual Mode Extensions */
27
+
#define X86_FEATURE_DE ( 0*32+ 2) /* Debugging Extensions */
28
+
#define X86_FEATURE_PSE ( 0*32+ 3) /* Page Size Extensions */
29
+
#define X86_FEATURE_TSC ( 0*32+ 4) /* Time Stamp Counter */
30
+
#define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
31
+
#define X86_FEATURE_PAE ( 0*32+ 6) /* Physical Address Extensions */
32
+
#define X86_FEATURE_MCE ( 0*32+ 7) /* Machine Check Exception */
33
+
#define X86_FEATURE_CX8 ( 0*32+ 8) /* CMPXCHG8 instruction */
34
+
#define X86_FEATURE_APIC ( 0*32+ 9) /* Onboard APIC */
35
+
#define X86_FEATURE_SEP ( 0*32+11) /* SYSENTER/SYSEXIT */
36
+
#define X86_FEATURE_MTRR ( 0*32+12) /* Memory Type Range Registers */
37
+
#define X86_FEATURE_PGE ( 0*32+13) /* Page Global Enable */
38
+
#define X86_FEATURE_MCA ( 0*32+14) /* Machine Check Architecture */
39
+
#define X86_FEATURE_CMOV ( 0*32+15) /* CMOV instructions */
40
+
/* (plus FCMOVcc, FCOMI with FPU) */
41
+
#define X86_FEATURE_PAT ( 0*32+16) /* Page Attribute Table */
42
+
#define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
43
+
#define X86_FEATURE_PN ( 0*32+18) /* Processor serial number */
44
+
#define X86_FEATURE_CLFLUSH ( 0*32+19) /* CLFLUSH instruction */
45
+
#define X86_FEATURE_DS ( 0*32+21) /* "dts" Debug Store */
46
+
#define X86_FEATURE_ACPI ( 0*32+22) /* ACPI via MSR */
47
+
#define X86_FEATURE_MMX ( 0*32+23) /* Multimedia Extensions */
48
+
#define X86_FEATURE_FXSR ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
49
+
#define X86_FEATURE_XMM ( 0*32+25) /* "sse" */
50
+
#define X86_FEATURE_XMM2 ( 0*32+26) /* "sse2" */
51
+
#define X86_FEATURE_SELFSNOOP ( 0*32+27) /* "ss" CPU self snoop */
52
+
#define X86_FEATURE_HT ( 0*32+28) /* Hyper-Threading */
53
+
#define X86_FEATURE_ACC ( 0*32+29) /* "tm" Automatic clock control */
54
+
#define X86_FEATURE_IA64 ( 0*32+30) /* IA-64 processor */
55
+
#define X86_FEATURE_PBE ( 0*32+31) /* Pending Break Enable */
56
+
57
+
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
58
+
/* Don't duplicate feature flags which are redundant with Intel! */
59
+
#define X86_FEATURE_SYSCALL ( 1*32+11) /* SYSCALL/SYSRET */
60
+
#define X86_FEATURE_MP ( 1*32+19) /* MP Capable. */
61
+
#define X86_FEATURE_NX ( 1*32+20) /* Execute Disable */
62
+
#define X86_FEATURE_MMXEXT ( 1*32+22) /* AMD MMX extensions */
63
+
#define X86_FEATURE_FXSR_OPT ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
64
+
#define X86_FEATURE_GBPAGES ( 1*32+26) /* "pdpe1gb" GB pages */
65
+
#define X86_FEATURE_RDTSCP ( 1*32+27) /* RDTSCP */
66
+
#define X86_FEATURE_LM ( 1*32+29) /* Long Mode (x86-64) */
67
+
#define X86_FEATURE_3DNOWEXT ( 1*32+30) /* AMD 3DNow! extensions */
68
+
#define X86_FEATURE_3DNOW ( 1*32+31) /* 3DNow! */
69
+
70
+
/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
71
+
#define X86_FEATURE_RECOVERY ( 2*32+ 0) /* CPU in recovery mode */
72
+
#define X86_FEATURE_LONGRUN ( 2*32+ 1) /* Longrun power control */
73
+
#define X86_FEATURE_LRTI ( 2*32+ 3) /* LongRun table interface */
74
+
75
+
/* Other features, Linux-defined mapping, word 3 */
76
+
/* This range is used for feature bits which conflict or are synthesized */
77
+
#define X86_FEATURE_CXMMX ( 3*32+ 0) /* Cyrix MMX extensions */
78
+
#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
79
+
#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
80
+
#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
81
+
/* cpu types for specific tunings: */
82
+
#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
83
+
#define X86_FEATURE_K7 ( 3*32+ 5) /* "" Athlon */
84
+
#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
85
+
#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
86
+
#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
87
+
#define X86_FEATURE_UP ( 3*32+ 9) /* smp kernel running on up */
88
+
/* free, was #define X86_FEATURE_FXSAVE_LEAK ( 3*32+10) * "" FXSAVE leaks FOP/FIP/FOP */
89
+
#define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* Intel Architectural PerfMon */
90
+
#define X86_FEATURE_PEBS ( 3*32+12) /* Precise-Event Based Sampling */
91
+
#define X86_FEATURE_BTS ( 3*32+13) /* Branch Trace Store */
92
+
#define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in ia32 userspace */
93
+
#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in ia32 userspace */
94
+
#define X86_FEATURE_REP_GOOD ( 3*32+16) /* rep microcode works well */
95
+
#define X86_FEATURE_MFENCE_RDTSC ( 3*32+17) /* "" Mfence synchronizes RDTSC */
96
+
#define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" Lfence synchronizes RDTSC */
97
+
/* free, was #define X86_FEATURE_11AP ( 3*32+19) * "" Bad local APIC aka 11AP */
98
+
#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
99
+
#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
100
+
#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
101
+
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
102
+
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
103
+
/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
104
+
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
105
+
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
106
+
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
107
+
#define X86_FEATURE_EAGER_FPU ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
108
+
#define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in S3 state */
109
+
110
+
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
111
+
#define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
112
+
#define X86_FEATURE_PCLMULQDQ ( 4*32+ 1) /* PCLMULQDQ instruction */
113
+
#define X86_FEATURE_DTES64 ( 4*32+ 2) /* 64-bit Debug Store */
114
+
#define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" Monitor/Mwait support */
115
+
#define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
116
+
#define X86_FEATURE_VMX ( 4*32+ 5) /* Hardware virtualization */
117
+
#define X86_FEATURE_SMX ( 4*32+ 6) /* Safer mode */
118
+
#define X86_FEATURE_EST ( 4*32+ 7) /* Enhanced SpeedStep */
119
+
#define X86_FEATURE_TM2 ( 4*32+ 8) /* Thermal Monitor 2 */
120
+
#define X86_FEATURE_SSSE3 ( 4*32+ 9) /* Supplemental SSE-3 */
121
+
#define X86_FEATURE_CID ( 4*32+10) /* Context ID */
122
+
#define X86_FEATURE_SDBG ( 4*32+11) /* Silicon Debug */
123
+
#define X86_FEATURE_FMA ( 4*32+12) /* Fused multiply-add */
124
+
#define X86_FEATURE_CX16 ( 4*32+13) /* CMPXCHG16B */
125
+
#define X86_FEATURE_XTPR ( 4*32+14) /* Send Task Priority Messages */
126
+
#define X86_FEATURE_PDCM ( 4*32+15) /* Performance Capabilities */
127
+
#define X86_FEATURE_PCID ( 4*32+17) /* Process Context Identifiers */
128
+
#define X86_FEATURE_DCA ( 4*32+18) /* Direct Cache Access */
129
+
#define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
130
+
#define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
131
+
#define X86_FEATURE_X2APIC ( 4*32+21) /* x2APIC */
132
+
#define X86_FEATURE_MOVBE ( 4*32+22) /* MOVBE instruction */
133
+
#define X86_FEATURE_POPCNT ( 4*32+23) /* POPCNT instruction */
134
+
#define X86_FEATURE_TSC_DEADLINE_TIMER ( 4*32+24) /* Tsc deadline timer */
135
+
#define X86_FEATURE_AES ( 4*32+25) /* AES instructions */
136
+
#define X86_FEATURE_XSAVE ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
137
+
#define X86_FEATURE_OSXSAVE ( 4*32+27) /* "" XSAVE enabled in the OS */
138
+
#define X86_FEATURE_AVX ( 4*32+28) /* Advanced Vector Extensions */
139
+
#define X86_FEATURE_F16C ( 4*32+29) /* 16-bit fp conversions */
140
+
#define X86_FEATURE_RDRAND ( 4*32+30) /* The RDRAND instruction */
141
+
#define X86_FEATURE_HYPERVISOR ( 4*32+31) /* Running on a hypervisor */
142
+
143
+
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
144
+
#define X86_FEATURE_XSTORE ( 5*32+ 2) /* "rng" RNG present (xstore) */
145
+
#define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
146
+
#define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
147
+
#define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
148
+
#define X86_FEATURE_ACE2 ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
149
+
#define X86_FEATURE_ACE2_EN ( 5*32+ 9) /* ACE v2 enabled */
150
+
#define X86_FEATURE_PHE ( 5*32+10) /* PadLock Hash Engine */
151
+
#define X86_FEATURE_PHE_EN ( 5*32+11) /* PHE enabled */
152
+
#define X86_FEATURE_PMM ( 5*32+12) /* PadLock Montgomery Multiplier */
153
+
#define X86_FEATURE_PMM_EN ( 5*32+13) /* PMM enabled */
154
+
155
+
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
156
+
#define X86_FEATURE_LAHF_LM ( 6*32+ 0) /* LAHF/SAHF in long mode */
157
+
#define X86_FEATURE_CMP_LEGACY ( 6*32+ 1) /* If yes HyperThreading not valid */
158
+
#define X86_FEATURE_SVM ( 6*32+ 2) /* Secure virtual machine */
159
+
#define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* Extended APIC space */
160
+
#define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* CR8 in 32-bit mode */
161
+
#define X86_FEATURE_ABM ( 6*32+ 5) /* Advanced bit manipulation */
162
+
#define X86_FEATURE_SSE4A ( 6*32+ 6) /* SSE-4A */
163
+
#define X86_FEATURE_MISALIGNSSE ( 6*32+ 7) /* Misaligned SSE mode */
164
+
#define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* 3DNow prefetch instructions */
165
+
#define X86_FEATURE_OSVW ( 6*32+ 9) /* OS Visible Workaround */
166
+
#define X86_FEATURE_IBS ( 6*32+10) /* Instruction Based Sampling */
167
+
#define X86_FEATURE_XOP ( 6*32+11) /* extended AVX instructions */
168
+
#define X86_FEATURE_SKINIT ( 6*32+12) /* SKINIT/STGI instructions */
169
+
#define X86_FEATURE_WDT ( 6*32+13) /* Watchdog timer */
170
+
#define X86_FEATURE_LWP ( 6*32+15) /* Light Weight Profiling */
171
+
#define X86_FEATURE_FMA4 ( 6*32+16) /* 4 operands MAC instructions */
172
+
#define X86_FEATURE_TCE ( 6*32+17) /* translation cache extension */
173
+
#define X86_FEATURE_NODEID_MSR ( 6*32+19) /* NodeId MSR */
174
+
#define X86_FEATURE_TBM ( 6*32+21) /* trailing bit manipulations */
175
+
#define X86_FEATURE_TOPOEXT ( 6*32+22) /* topology extensions CPUID leafs */
176
+
#define X86_FEATURE_PERFCTR_CORE ( 6*32+23) /* core performance counter extensions */
177
+
#define X86_FEATURE_PERFCTR_NB ( 6*32+24) /* NB performance counter extensions */
178
+
#define X86_FEATURE_BPEXT (6*32+26) /* data breakpoint extension */
179
+
#define X86_FEATURE_PERFCTR_L2 ( 6*32+28) /* L2 performance counter extensions */
180
+
#define X86_FEATURE_MWAITX ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
181
+
182
+
/*
183
+
* Auxiliary flags: Linux defined - For features scattered in various
184
+
* CPUID levels like 0x6, 0xA etc, word 7.
185
+
*
186
+
* Reuse free bits when adding new feature flags!
187
+
*/
188
+
189
+
#define X86_FEATURE_CPB ( 7*32+ 2) /* AMD Core Performance Boost */
190
+
#define X86_FEATURE_EPB ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
191
+
192
+
#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
193
+
#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
194
+
195
+
#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
196
+
197
+
/* Virtualization flags: Linux defined, word 8 */
198
+
#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
199
+
#define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
200
+
#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2) /* Intel FlexPriority */
201
+
#define X86_FEATURE_EPT ( 8*32+ 3) /* Intel Extended Page Table */
202
+
#define X86_FEATURE_VPID ( 8*32+ 4) /* Intel Virtual Processor ID */
203
+
204
+
#define X86_FEATURE_VMMCALL ( 8*32+15) /* Prefer vmmcall to vmcall */
205
+
#define X86_FEATURE_XENPV ( 8*32+16) /* "" Xen paravirtual guest */
206
+
207
+
208
+
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
209
+
#define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
210
+
#define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3b */
211
+
#define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */
212
+
#define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */
213
+
#define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */
214
+
#define X86_FEATURE_SMEP ( 9*32+ 7) /* Supervisor Mode Execution Protection */
215
+
#define X86_FEATURE_BMI2 ( 9*32+ 8) /* 2nd group bit manipulation extensions */
216
+
#define X86_FEATURE_ERMS ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB */
217
+
#define X86_FEATURE_INVPCID ( 9*32+10) /* Invalidate Processor Context ID */
218
+
#define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional Memory */
219
+
#define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
220
+
#define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection Extension */
221
+
#define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
222
+
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
223
+
#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
224
+
#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
225
+
#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
226
+
#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
227
+
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
228
+
#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
229
+
#define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
230
+
#define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */
231
+
#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
232
+
233
+
/* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */
234
+
#define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */
235
+
#define X86_FEATURE_XSAVEC (10*32+ 1) /* XSAVEC */
236
+
#define X86_FEATURE_XGETBV1 (10*32+ 2) /* XGETBV with ECX = 1 */
237
+
#define X86_FEATURE_XSAVES (10*32+ 3) /* XSAVES/XRSTORS */
238
+
239
+
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:0 (edx), word 11 */
240
+
#define X86_FEATURE_CQM_LLC (11*32+ 1) /* LLC QoS if 1 */
241
+
242
+
/* Intel-defined CPU QoS Sub-leaf, CPUID level 0x0000000F:1 (edx), word 12 */
243
+
#define X86_FEATURE_CQM_OCCUP_LLC (12*32+ 0) /* LLC occupancy monitoring if 1 */
244
+
245
+
/* AMD-defined CPU features, CPUID level 0x80000008 (ebx), word 13 */
246
+
#define X86_FEATURE_CLZERO (13*32+0) /* CLZERO instruction */
247
+
248
+
/* Thermal and Power Management Leaf, CPUID level 0x00000006 (eax), word 14 */
249
+
#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
250
+
#define X86_FEATURE_IDA (14*32+ 1) /* Intel Dynamic Acceleration */
251
+
#define X86_FEATURE_ARAT (14*32+ 2) /* Always Running APIC Timer */
252
+
#define X86_FEATURE_PLN (14*32+ 4) /* Intel Power Limit Notification */
253
+
#define X86_FEATURE_PTS (14*32+ 6) /* Intel Package Thermal Status */
254
+
#define X86_FEATURE_HWP (14*32+ 7) /* Intel Hardware P-states */
255
+
#define X86_FEATURE_HWP_NOTIFY (14*32+ 8) /* HWP Notification */
256
+
#define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */
257
+
#define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */
258
+
#define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */
259
+
260
+
/* AMD SVM Feature Identification, CPUID level 0x8000000a (edx), word 15 */
261
+
#define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */
262
+
#define X86_FEATURE_LBRV (15*32+ 1) /* LBR Virtualization support */
263
+
#define X86_FEATURE_SVML (15*32+ 2) /* "svm_lock" SVM locking MSR */
264
+
#define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
265
+
#define X86_FEATURE_TSCRATEMSR (15*32+ 4) /* "tsc_scale" TSC scaling support */
266
+
#define X86_FEATURE_VMCBCLEAN (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
267
+
#define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* flush-by-ASID support */
268
+
#define X86_FEATURE_DECODEASSISTS (15*32+ 7) /* Decode Assists support */
269
+
#define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
270
+
#define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
271
+
#define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt Controller */
272
+
273
+
/*
274
+
* BUG word(s)
275
+
*/
276
+
#define X86_BUG(x) (NCAPINTS*32 + (x))
277
+
278
+
#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
279
+
#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
280
+
#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
281
+
#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
282
+
#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
283
+
#define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */
284
+
#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
285
+
#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
286
+
#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
287
+
288
+
#endif /* _ASM_X86_CPUFEATURES_H */
+1
arch/x86/include/asm/fpu/internal.h
+1
arch/x86/include/asm/fpu/internal.h
+1
-1
arch/x86/include/asm/irq_work.h
+1
-1
arch/x86/include/asm/irq_work.h
+2
arch/x86/include/asm/mwait.h
+2
arch/x86/include/asm/mwait.h
+1
-2
arch/x86/include/asm/processor.h
+1
-2
arch/x86/include/asm/processor.h
···
13
13
#include <asm/types.h>
14
14
#include <uapi/asm/sigcontext.h>
15
15
#include <asm/current.h>
16
-
#include <asm/cpufeature.h>
16
+
#include <asm/cpufeatures.h>
17
17
#include <asm/page.h>
18
18
#include <asm/pgtable_types.h>
19
19
#include <asm/percpu.h>
···
24
24
#include <asm/fpu/types.h>
25
25
26
26
#include <linux/personality.h>
27
-
#include <linux/cpumask.h>
28
27
#include <linux/cache.h>
29
28
#include <linux/threads.h>
30
29
#include <linux/math64.h>
+1
-1
arch/x86/include/asm/smap.h
+1
-1
arch/x86/include/asm/smap.h
-1
arch/x86/include/asm/smp.h
-1
arch/x86/include/asm/smp.h
+1
-1
arch/x86/include/asm/thread_info.h
+1
-1
arch/x86/include/asm/thread_info.h
+1
arch/x86/include/asm/tlbflush.h
+1
arch/x86/include/asm/tlbflush.h
+1
-1
arch/x86/include/asm/uaccess_64.h
+1
-1
arch/x86/include/asm/uaccess_64.h
+1
-1
arch/x86/kernel/cpu/Makefile
+1
-1
arch/x86/kernel/cpu/Makefile
···
64
64
quiet_cmd_mkcapflags = MKCAP $@
65
65
cmd_mkcapflags = $(CONFIG_SHELL) $(srctree)/$(src)/mkcapflags.sh $< $@
66
66
67
-
cpufeature = $(src)/../../include/asm/cpufeature.h
67
+
cpufeature = $(src)/../../include/asm/cpufeatures.h
68
68
69
69
targets += capflags.c
70
70
$(obj)/capflags.c: $(cpufeature) $(src)/mkcapflags.sh FORCE
+1
-1
arch/x86/kernel/cpu/centaur.c
+1
-1
arch/x86/kernel/cpu/centaur.c
+1
arch/x86/kernel/cpu/cyrix.c
+1
arch/x86/kernel/cpu/cyrix.c
+1
-1
arch/x86/kernel/cpu/intel.c
+1
-1
arch/x86/kernel/cpu/intel.c
+1
-1
arch/x86/kernel/cpu/intel_cacheinfo.c
+1
-1
arch/x86/kernel/cpu/intel_cacheinfo.c
+1
-1
arch/x86/kernel/cpu/match.c
+1
-1
arch/x86/kernel/cpu/match.c
+3
-3
arch/x86/kernel/cpu/mkcapflags.sh
+3
-3
arch/x86/kernel/cpu/mkcapflags.sh
···
1
1
#!/bin/sh
2
2
#
3
-
# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeature.h
3
+
# Generate the x86_cap/bug_flags[] arrays from include/asm/cpufeatures.h
4
4
#
5
5
6
6
IN=$1
···
49
49
trap 'rm "$OUT"' EXIT
50
50
51
51
(
52
-
echo "#ifndef _ASM_X86_CPUFEATURE_H"
53
-
echo "#include <asm/cpufeature.h>"
52
+
echo "#ifndef _ASM_X86_CPUFEATURES_H"
53
+
echo "#include <asm/cpufeatures.h>"
54
54
echo "#endif"
55
55
echo ""
56
56
+1
-1
arch/x86/kernel/cpu/mtrr/main.c
+1
-1
arch/x86/kernel/cpu/mtrr/main.c
+1
-1
arch/x86/kernel/cpu/transmeta.c
+1
-1
arch/x86/kernel/cpu/transmeta.c
+1
arch/x86/kernel/e820.c
+1
arch/x86/kernel/e820.c
+1
-1
arch/x86/kernel/head_32.S
+1
-1
arch/x86/kernel/head_32.S
+1
arch/x86/kernel/hpet.c
+1
arch/x86/kernel/hpet.c
+1
-1
arch/x86/kernel/msr.c
+1
-1
arch/x86/kernel/msr.c
+1
-1
arch/x86/kernel/verify_cpu.S
+1
-1
arch/x86/kernel/verify_cpu.S
+1
-1
arch/x86/lib/clear_page_64.S
+1
-1
arch/x86/lib/clear_page_64.S
+1
-1
arch/x86/lib/copy_page_64.S
+1
-1
arch/x86/lib/copy_page_64.S
+1
-1
arch/x86/lib/copy_user_64.S
+1
-1
arch/x86/lib/copy_user_64.S
+1
-1
arch/x86/lib/memcpy_64.S
+1
-1
arch/x86/lib/memcpy_64.S
+1
-1
arch/x86/lib/memmove_64.S
+1
-1
arch/x86/lib/memmove_64.S
+1
-1
arch/x86/lib/memset_64.S
+1
-1
arch/x86/lib/memset_64.S
+1
arch/x86/mm/setup_nx.c
+1
arch/x86/mm/setup_nx.c
-1
arch/x86/oprofile/op_model_amd.c
-1
arch/x86/oprofile/op_model_amd.c
+1
-1
arch/x86/um/asm/barrier.h
+1
-1
arch/x86/um/asm/barrier.h