tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom: qmp-combo: reuse register layouts for some more registers

Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN
registers. This will allow us to unify qmp_v[456]_configure_dp_phy()
functions in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230621153317.1025914-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul cd1f3343 186ad90a

+24 -12
+22 -12
drivers/phy/qualcomm/phy-qcom-qmp-combo.c
··· 116 116 QPHY_TX_TX_POL_INV, 117 117 QPHY_TX_TX_DRV_LVL, 118 118 QPHY_TX_TX_EMP_POST1_LVL, 119 + QPHY_TX_HIGHZ_DRVR_EN, 120 + QPHY_TX_TRANSCEIVER_BIAS_EN, 119 121 120 122 /* Keep last to ensure regs_layout arrays are properly initialized */ 121 123 QPHY_LAYOUT_SIZE ··· 140 138 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 141 139 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 142 140 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 141 + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 142 + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 143 143 }; 144 144 145 145 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 163 159 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 164 160 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 165 161 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 162 + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 163 + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 166 164 }; 167 165 168 166 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 186 180 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 187 181 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 188 182 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 183 + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 184 + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 189 185 }; 190 186 191 187 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { ··· 209 201 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 210 202 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 211 203 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 204 + [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 205 + [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 212 206 }; 213 207 214 208 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { ··· 2356 2346 drvr1_en = 0x10; 2357 2347 } 2358 2348 2359 - writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2360 - writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2361 - writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2362 - writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2349 + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2350 + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2351 + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2352 + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2363 2353 2364 2354 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2365 2355 udelay(2000); ··· 2416 2406 drvr1_en = 0x10; 2417 2407 } 2418 2408 2419 - writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 2420 - writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 2421 - writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN); 2422 - writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN); 2409 + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2410 + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2411 + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2412 + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2423 2413 2424 2414 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2425 2415 udelay(2000); ··· 2474 2464 drvr1_en = 0x10; 2475 2465 } 2476 2466 2477 - writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2478 - writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2479 - writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN); 2480 - writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN); 2467 + writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2468 + writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2469 + writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2470 + writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2481 2471 2482 2472 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2483 2473 udelay(2000);
+2
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
··· 17 17 #define QSERDES_V6_TX_RES_CODE_LANE_RX 0x38 18 18 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX 0x3c 19 19 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX 0x40 20 + #define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN 0x54 21 + #define QSERDES_V6_TX_HIGHZ_DRVR_EN 0x58 20 22 #define QSERDES_V6_TX_TX_POL_INV 0x5c 21 23 #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 22 24 #define QSERDES_V6_TX_BIST_PATTERN7 0x7c