Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: stm32: stm32-core: convert from round_rate() to determine_rate()

The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>

+18 -10
+18 -10
drivers/clk/stm32/clk-stm32-core.c
··· 351 351 return ret; 352 352 } 353 353 354 - static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate, 355 - unsigned long *prate) 354 + static int clk_stm32_divider_determine_rate(struct clk_hw *hw, 355 + struct clk_rate_request *req) 356 356 { 357 357 struct clk_stm32_div *div = to_clk_stm32_divider(hw); 358 358 const struct stm32_div_cfg *divider; 359 359 360 360 if (div->div_id == NO_STM32_DIV) 361 - return rate; 361 + return 0; 362 362 363 363 divider = &div->clock_data->dividers[div->div_id]; 364 364 ··· 369 369 val = readl(div->base + divider->offset) >> divider->shift; 370 370 val &= clk_div_mask(divider->width); 371 371 372 - return divider_ro_round_rate(hw, rate, prate, divider->table, 373 - divider->width, divider->flags, 374 - val); 372 + req->rate = divider_ro_round_rate(hw, req->rate, 373 + &req->best_parent_rate, 374 + divider->table, 375 + divider->width, 376 + divider->flags, val); 377 + 378 + return 0; 375 379 } 376 380 377 - return divider_round_rate_parent(hw, clk_hw_get_parent(hw), 378 - rate, prate, divider->table, 379 - divider->width, divider->flags); 381 + req->rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw), 382 + req->rate, 383 + &req->best_parent_rate, 384 + divider->table, 385 + divider->width, divider->flags); 386 + 387 + return 0; 380 388 } 381 389 382 390 static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw, ··· 400 392 401 393 const struct clk_ops clk_stm32_divider_ops = { 402 394 .recalc_rate = clk_stm32_divider_recalc_rate, 403 - .round_rate = clk_stm32_divider_round_rate, 395 + .determine_rate = clk_stm32_divider_determine_rate, 404 396 .set_rate = clk_stm32_divider_set_rate, 405 397 }; 406 398