Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

mfd/extcon: max77693: Rename defines to allow inclusion with max77843

Add MAX77693 prefix to some of the defines used in max77693 extcon
driver so the max77693-private.h can be included simultaneously with
max77843-private.h.

Additionally use BIT() macro in header.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Mark Brown
cceb433a bc1aadc1

+86 -82
+38 -34
drivers/extcon/extcon-max77693.c
··· 43 43 { 44 44 /* STATUS2 - [3]ChgDetRun */ 45 45 .addr = MAX77693_MUIC_REG_STATUS2, 46 - .data = STATUS2_CHGDETRUN_MASK, 46 + .data = MAX77693_STATUS2_CHGDETRUN_MASK, 47 47 }, { 48 48 /* INTMASK1 - Unmask [3]ADC1KM,[0]ADCM */ 49 49 .addr = MAX77693_MUIC_REG_INTMASK1, ··· 236 236 */ 237 237 ret = regmap_write(info->max77693->regmap_muic, 238 238 MAX77693_MUIC_REG_CTRL3, 239 - time << CONTROL3_ADCDBSET_SHIFT); 239 + time << MAX77693_CONTROL3_ADCDBSET_SHIFT); 240 240 if (ret) { 241 241 dev_err(info->dev, "failed to set ADC debounce time\n"); 242 242 return ret; ··· 269 269 if (attached) 270 270 ctrl1 = val; 271 271 else 272 - ctrl1 = CONTROL1_SW_OPEN; 272 + ctrl1 = MAX77693_CONTROL1_SW_OPEN; 273 273 274 274 ret = regmap_update_bits(info->max77693->regmap_muic, 275 275 MAX77693_MUIC_REG_CTRL1, COMP_SW_MASK, ctrl1); ··· 279 279 } 280 280 281 281 if (attached) 282 - ctrl2 |= CONTROL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ 282 + ctrl2 |= MAX77693_CONTROL2_CPEN_MASK; /* LowPwr=0, CPEn=1 */ 283 283 else 284 - ctrl2 |= CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ 284 + ctrl2 |= MAX77693_CONTROL2_LOWPWR_MASK; /* LowPwr=1, CPEn=0 */ 285 285 286 286 ret = regmap_update_bits(info->max77693->regmap_muic, 287 287 MAX77693_MUIC_REG_CTRL2, 288 - CONTROL2_LOWPWR_MASK | CONTROL2_CPEN_MASK, ctrl2); 288 + MAX77693_CONTROL2_LOWPWR_MASK | MAX77693_CONTROL2_CPEN_MASK, 289 + ctrl2); 289 290 if (ret < 0) { 290 291 dev_err(info->dev, "failed to update MUIC register\n"); 291 292 return ret; ··· 328 327 * Read ADC value to check cable type and decide cable state 329 328 * according to cable type 330 329 */ 331 - adc = info->status[0] & STATUS1_ADC_MASK; 332 - adc >>= STATUS1_ADC_SHIFT; 330 + adc = info->status[0] & MAX77693_STATUS1_ADC_MASK; 331 + adc >>= MAX77693_STATUS1_ADC_SHIFT; 333 332 334 333 /* 335 334 * Check current cable state/cable type and store cable type ··· 352 351 * Read ADC value to check cable type and decide cable state 353 352 * according to cable type 354 353 */ 355 - adc = info->status[0] & STATUS1_ADC_MASK; 356 - adc >>= STATUS1_ADC_SHIFT; 354 + adc = info->status[0] & MAX77693_STATUS1_ADC_MASK; 355 + adc >>= MAX77693_STATUS1_ADC_SHIFT; 357 356 358 357 /* 359 358 * Check current cable state/cable type and store cable type ··· 368 367 } else { 369 368 *attached = true; 370 369 371 - adclow = info->status[0] & STATUS1_ADCLOW_MASK; 372 - adclow >>= STATUS1_ADCLOW_SHIFT; 373 - adc1k = info->status[0] & STATUS1_ADC1K_MASK; 374 - adc1k >>= STATUS1_ADC1K_SHIFT; 370 + adclow = info->status[0] & MAX77693_STATUS1_ADCLOW_MASK; 371 + adclow >>= MAX77693_STATUS1_ADCLOW_SHIFT; 372 + adc1k = info->status[0] & MAX77693_STATUS1_ADC1K_MASK; 373 + adc1k >>= MAX77693_STATUS1_ADC1K_SHIFT; 375 374 376 - vbvolt = info->status[1] & STATUS2_VBVOLT_MASK; 377 - vbvolt >>= STATUS2_VBVOLT_SHIFT; 375 + vbvolt = info->status[1] & MAX77693_STATUS2_VBVOLT_MASK; 376 + vbvolt >>= MAX77693_STATUS2_VBVOLT_SHIFT; 378 377 379 378 /** 380 379 * [0x1|VBVolt|ADCLow|ADC1K] ··· 399 398 * Read charger type to check cable type and decide cable state 400 399 * according to type of charger cable. 401 400 */ 402 - chg_type = info->status[1] & STATUS2_CHGTYP_MASK; 403 - chg_type >>= STATUS2_CHGTYP_SHIFT; 401 + chg_type = info->status[1] & MAX77693_STATUS2_CHGTYP_MASK; 402 + chg_type >>= MAX77693_STATUS2_CHGTYP_SHIFT; 404 403 405 404 if (chg_type == MAX77693_CHARGER_TYPE_NONE) { 406 405 *attached = false; ··· 424 423 * Read ADC value to check cable type and decide cable state 425 424 * according to cable type 426 425 */ 427 - adc = info->status[0] & STATUS1_ADC_MASK; 428 - adc >>= STATUS1_ADC_SHIFT; 429 - chg_type = info->status[1] & STATUS2_CHGTYP_MASK; 430 - chg_type >>= STATUS2_CHGTYP_SHIFT; 426 + adc = info->status[0] & MAX77693_STATUS1_ADC_MASK; 427 + adc >>= MAX77693_STATUS1_ADC_SHIFT; 428 + chg_type = info->status[1] & MAX77693_STATUS2_CHGTYP_MASK; 429 + chg_type >>= MAX77693_STATUS2_CHGTYP_SHIFT; 431 430 432 431 if (adc == MAX77693_MUIC_ADC_OPEN 433 432 && chg_type == MAX77693_CHARGER_TYPE_NONE) ··· 439 438 * Read vbvolt field, if vbvolt is 1, 440 439 * this cable is used for charging. 441 440 */ 442 - vbvolt = info->status[1] & STATUS2_VBVOLT_MASK; 443 - vbvolt >>= STATUS2_VBVOLT_SHIFT; 441 + vbvolt = info->status[1] & MAX77693_STATUS2_VBVOLT_MASK; 442 + vbvolt >>= MAX77693_STATUS2_VBVOLT_SHIFT; 444 443 445 444 cable_type = vbvolt; 446 445 break; ··· 522 521 } 523 522 524 523 /* Dock-Car/Desk/Audio, PATH:AUDIO */ 525 - ret = max77693_muic_set_path(info, CONTROL1_SW_AUDIO, attached); 524 + ret = max77693_muic_set_path(info, MAX77693_CONTROL1_SW_AUDIO, 525 + attached); 526 526 if (ret < 0) 527 527 return ret; 528 528 extcon_set_cable_state_(info->edev, dock_id, attached); ··· 588 586 case MAX77693_MUIC_GND_USB_HOST: 589 587 case MAX77693_MUIC_GND_USB_HOST_VB: 590 588 /* USB_HOST, PATH: AP_USB */ 591 - ret = max77693_muic_set_path(info, CONTROL1_SW_USB, attached); 589 + ret = max77693_muic_set_path(info, MAX77693_CONTROL1_SW_USB, 590 + attached); 592 591 if (ret < 0) 593 592 return ret; 594 593 extcon_set_cable_state_(info->edev, EXTCON_USB_HOST, attached); 595 594 break; 596 595 case MAX77693_MUIC_GND_AV_CABLE_LOAD: 597 596 /* Audio Video Cable with load, PATH:AUDIO */ 598 - ret = max77693_muic_set_path(info, CONTROL1_SW_AUDIO, attached); 597 + ret = max77693_muic_set_path(info, MAX77693_CONTROL1_SW_AUDIO, 598 + attached); 599 599 if (ret < 0) 600 600 return ret; 601 601 extcon_set_cable_state_(info->edev, EXTCON_USB, attached); ··· 620 616 int cable_type, bool attached) 621 617 { 622 618 int ret = 0; 623 - u8 path = CONTROL1_SW_OPEN; 619 + u8 path = MAX77693_CONTROL1_SW_OPEN; 624 620 625 621 dev_info(info->dev, 626 622 "external connector is %s (adc:0x%02x)\n", ··· 630 626 case MAX77693_MUIC_ADC_FACTORY_MODE_USB_OFF: /* ADC_JIG_USB_OFF */ 631 627 case MAX77693_MUIC_ADC_FACTORY_MODE_USB_ON: /* ADC_JIG_USB_ON */ 632 628 /* PATH:AP_USB */ 633 - path = CONTROL1_SW_USB; 629 + path = MAX77693_CONTROL1_SW_USB; 634 630 break; 635 631 case MAX77693_MUIC_ADC_FACTORY_MODE_UART_OFF: /* ADC_JIG_UART_OFF */ 636 632 case MAX77693_MUIC_ADC_FACTORY_MODE_UART_ON: /* ADC_JIG_UART_ON */ 637 633 /* PATH:AP_UART */ 638 - path = CONTROL1_SW_UART; 634 + path = MAX77693_CONTROL1_SW_UART; 639 635 break; 640 636 default: 641 637 dev_err(info->dev, "failed to detect %s jig cable\n", ··· 1185 1181 if (muic_pdata->path_uart) 1186 1182 info->path_uart = muic_pdata->path_uart; 1187 1183 else 1188 - info->path_uart = CONTROL1_SW_UART; 1184 + info->path_uart = MAX77693_CONTROL1_SW_UART; 1189 1185 1190 1186 if (muic_pdata->path_usb) 1191 1187 info->path_usb = muic_pdata->path_usb; 1192 1188 else 1193 - info->path_usb = CONTROL1_SW_USB; 1189 + info->path_usb = MAX77693_CONTROL1_SW_USB; 1194 1190 1195 1191 /* 1196 1192 * Default delay time for detecting cable state ··· 1202 1198 else 1203 1199 delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 1204 1200 } else { 1205 - info->path_usb = CONTROL1_SW_USB; 1206 - info->path_uart = CONTROL1_SW_UART; 1201 + info->path_usb = MAX77693_CONTROL1_SW_USB; 1202 + info->path_uart = MAX77693_CONTROL1_SW_UART; 1207 1203 delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); 1208 1204 } 1209 1205
+48 -48
include/linux/mfd/max77693-private.h
··· 310 310 #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT) 311 311 312 312 /* MAX77693 MUIC - STATUS1~3 Register */ 313 - #define STATUS1_ADC_SHIFT (0) 314 - #define STATUS1_ADCLOW_SHIFT (5) 315 - #define STATUS1_ADCERR_SHIFT (6) 316 - #define STATUS1_ADC1K_SHIFT (7) 317 - #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) 318 - #define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT) 319 - #define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT) 320 - #define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT) 313 + #define MAX77693_STATUS1_ADC_SHIFT 0 314 + #define MAX77693_STATUS1_ADCLOW_SHIFT 5 315 + #define MAX77693_STATUS1_ADCERR_SHIFT 6 316 + #define MAX77693_STATUS1_ADC1K_SHIFT 7 317 + #define MAX77693_STATUS1_ADC_MASK (0x1f << MAX77693_STATUS1_ADC_SHIFT) 318 + #define MAX77693_STATUS1_ADCLOW_MASK BIT(MAX77693_STATUS1_ADCLOW_SHIFT) 319 + #define MAX77693_STATUS1_ADCERR_MASK BIT(MAX77693_STATUS1_ADCERR_SHIFT) 320 + #define MAX77693_STATUS1_ADC1K_MASK BIT(MAX77693_STATUS1_ADC1K_SHIFT) 321 321 322 - #define STATUS2_CHGTYP_SHIFT (0) 323 - #define STATUS2_CHGDETRUN_SHIFT (3) 324 - #define STATUS2_DCDTMR_SHIFT (4) 325 - #define STATUS2_DXOVP_SHIFT (5) 326 - #define STATUS2_VBVOLT_SHIFT (6) 327 - #define STATUS2_VIDRM_SHIFT (7) 328 - #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) 329 - #define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT) 330 - #define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT) 331 - #define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT) 332 - #define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT) 333 - #define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT) 322 + #define MAX77693_STATUS2_CHGTYP_SHIFT 0 323 + #define MAX77693_STATUS2_CHGDETRUN_SHIFT 3 324 + #define MAX77693_STATUS2_DCDTMR_SHIFT 4 325 + #define MAX77693_STATUS2_DXOVP_SHIFT 5 326 + #define MAX77693_STATUS2_VBVOLT_SHIFT 6 327 + #define MAX77693_STATUS2_VIDRM_SHIFT 7 328 + #define MAX77693_STATUS2_CHGTYP_MASK (0x7 << MAX77693_STATUS2_CHGTYP_SHIFT) 329 + #define MAX77693_STATUS2_CHGDETRUN_MASK BIT(MAX77693_STATUS2_CHGDETRUN_SHIFT) 330 + #define MAX77693_STATUS2_DCDTMR_MASK BIT(MAX77693_STATUS2_DCDTMR_SHIFT) 331 + #define MAX77693_STATUS2_DXOVP_MASK BIT(MAX77693_STATUS2_DXOVP_SHIFT) 332 + #define MAX77693_STATUS2_VBVOLT_MASK BIT(MAX77693_STATUS2_VBVOLT_SHIFT) 333 + #define MAX77693_STATUS2_VIDRM_MASK BIT(MAX77693_STATUS2_VIDRM_SHIFT) 334 334 335 - #define STATUS3_OVP_SHIFT (2) 336 - #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT) 335 + #define MAX77693_STATUS3_OVP_SHIFT 2 336 + #define MAX77693_STATUS3_OVP_MASK BIT(MAX77693_STATUS3_OVP_SHIFT) 337 337 338 338 /* MAX77693 CDETCTRL1~2 register */ 339 339 #define CDETCTRL1_CHGDETEN_SHIFT (0) ··· 362 362 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT) 363 363 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT) 364 364 #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK) 365 - #define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \ 365 + #define MAX77693_CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \ 366 366 | (1 << COMN1SW_SHIFT)) 367 - #define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ 367 + #define MAX77693_CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \ 368 368 | (2 << COMN1SW_SHIFT)) 369 - #define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \ 369 + #define MAX77693_CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \ 370 370 | (3 << COMN1SW_SHIFT)) 371 - #define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ 371 + #define MAX77693_CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \ 372 372 | (0 << COMN1SW_SHIFT)) 373 373 374 - #define CONTROL2_LOWPWR_SHIFT (0) 375 - #define CONTROL2_ADCEN_SHIFT (1) 376 - #define CONTROL2_CPEN_SHIFT (2) 377 - #define CONTROL2_SFOUTASRT_SHIFT (3) 378 - #define CONTROL2_SFOUTORD_SHIFT (4) 379 - #define CONTROL2_ACCDET_SHIFT (5) 380 - #define CONTROL2_USBCPINT_SHIFT (6) 381 - #define CONTROL2_RCPS_SHIFT (7) 382 - #define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT) 383 - #define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT) 384 - #define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT) 385 - #define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT) 386 - #define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT) 387 - #define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT) 388 - #define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT) 389 - #define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT) 374 + #define MAX77693_CONTROL2_LOWPWR_SHIFT 0 375 + #define MAX77693_CONTROL2_ADCEN_SHIFT 1 376 + #define MAX77693_CONTROL2_CPEN_SHIFT 2 377 + #define MAX77693_CONTROL2_SFOUTASRT_SHIFT 3 378 + #define MAX77693_CONTROL2_SFOUTORD_SHIFT 4 379 + #define MAX77693_CONTROL2_ACCDET_SHIFT 5 380 + #define MAX77693_CONTROL2_USBCPINT_SHIFT 6 381 + #define MAX77693_CONTROL2_RCPS_SHIFT 7 382 + #define MAX77693_CONTROL2_LOWPWR_MASK BIT(MAX77693_CONTROL2_LOWPWR_SHIFT) 383 + #define MAX77693_CONTROL2_ADCEN_MASK BIT(MAX77693_CONTROL2_ADCEN_SHIFT) 384 + #define MAX77693_CONTROL2_CPEN_MASK BIT(MAX77693_CONTROL2_CPEN_SHIFT) 385 + #define MAX77693_CONTROL2_SFOUTASRT_MASK BIT(MAX77693_CONTROL2_SFOUTASRT_SHIFT) 386 + #define MAX77693_CONTROL2_SFOUTORD_MASK BIT(MAX77693_CONTROL2_SFOUTORD_SHIFT) 387 + #define MAX77693_CONTROL2_ACCDET_MASK BIT(MAX77693_CONTROL2_ACCDET_SHIFT) 388 + #define MAX77693_CONTROL2_USBCPINT_MASK BIT(MAX77693_CONTROL2_USBCPINT_SHIFT) 389 + #define MAX77693_CONTROL2_RCPS_MASK BIT(MAX77693_CONTROL2_RCPS_SHIFT) 390 390 391 - #define CONTROL3_JIGSET_SHIFT (0) 392 - #define CONTROL3_BTLDSET_SHIFT (2) 393 - #define CONTROL3_ADCDBSET_SHIFT (4) 394 - #define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT) 395 - #define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT) 396 - #define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT) 391 + #define MAX77693_CONTROL3_JIGSET_SHIFT 0 392 + #define MAX77693_CONTROL3_BTLDSET_SHIFT 2 393 + #define MAX77693_CONTROL3_ADCDBSET_SHIFT 4 394 + #define MAX77693_CONTROL3_JIGSET_MASK (0x3 << MAX77693_CONTROL3_JIGSET_SHIFT) 395 + #define MAX77693_CONTROL3_BTLDSET_MASK (0x3 << MAX77693_CONTROL3_BTLDSET_SHIFT) 396 + #define MAX77693_CONTROL3_ADCDBSET_MASK (0x3 << MAX77693_CONTROL3_ADCDBSET_SHIFT) 397 397 398 398 /* Slave addr = 0x90: Haptic */ 399 399 enum max77693_haptic_reg {