tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
+408
-45
+289
-9
drivers/gpu/drm/msm/adreno/a2xx.xml.h
+289
-9
drivers/gpu/drm/msm/adreno/a2xx.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
···
239
239
enum sq_tex_filter {
240
240
SQ_TEX_FILTER_POINT = 0,
241
241
SQ_TEX_FILTER_BILINEAR = 1,
242
-
SQ_TEX_FILTER_BICUBIC = 2,
242
+
SQ_TEX_FILTER_BASEMAP = 2,
243
+
SQ_TEX_FILTER_USE_FETCH_CONST = 3,
244
+
};
245
+
246
+
enum sq_tex_aniso_filter {
247
+
SQ_TEX_ANISO_FILTER_DISABLED = 0,
248
+
SQ_TEX_ANISO_FILTER_MAX_1_1 = 1,
249
+
SQ_TEX_ANISO_FILTER_MAX_2_1 = 2,
250
+
SQ_TEX_ANISO_FILTER_MAX_4_1 = 3,
251
+
SQ_TEX_ANISO_FILTER_MAX_8_1 = 4,
252
+
SQ_TEX_ANISO_FILTER_MAX_16_1 = 5,
253
+
SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7,
254
+
};
255
+
256
+
enum sq_tex_dimension {
257
+
SQ_TEX_DIMENSION_1D = 0,
258
+
SQ_TEX_DIMENSION_2D = 1,
259
+
SQ_TEX_DIMENSION_3D = 2,
260
+
SQ_TEX_DIMENSION_CUBE = 3,
261
+
};
262
+
263
+
enum sq_tex_border_color {
264
+
SQ_TEX_BORDER_COLOR_BLACK = 0,
265
+
SQ_TEX_BORDER_COLOR_WHITE = 1,
266
+
SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2,
267
+
SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3,
268
+
};
269
+
270
+
enum sq_tex_sign {
271
+
SQ_TEX_SIGN_UNISIGNED = 0,
272
+
SQ_TEX_SIGN_SIGNED = 1,
273
+
SQ_TEX_SIGN_UNISIGNED_BIASED = 2,
274
+
SQ_TEX_SIGN_GAMMA = 3,
275
+
};
276
+
277
+
enum sq_tex_endian {
278
+
SQ_TEX_ENDIAN_NONE = 0,
279
+
SQ_TEX_ENDIAN_8IN16 = 1,
280
+
SQ_TEX_ENDIAN_8IN32 = 2,
281
+
SQ_TEX_ENDIAN_16IN32 = 3,
282
+
};
283
+
284
+
enum sq_tex_clamp_policy {
285
+
SQ_TEX_CLAMP_POLICY_D3D = 0,
286
+
SQ_TEX_CLAMP_POLICY_OGL = 1,
287
+
};
288
+
289
+
enum sq_tex_num_format {
290
+
SQ_TEX_NUM_FORMAT_FRAC = 0,
291
+
SQ_TEX_NUM_FORMAT_INT = 1,
292
+
};
293
+
294
+
enum sq_tex_type {
295
+
SQ_TEX_TYPE_0 = 0,
296
+
SQ_TEX_TYPE_1 = 1,
297
+
SQ_TEX_TYPE_2 = 2,
298
+
SQ_TEX_TYPE_3 = 3,
243
299
};
244
300
245
301
#define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001
···
379
323
}
380
324
381
325
#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
326
+
#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff
327
+
#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0
328
+
static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
329
+
{
330
+
return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK;
331
+
}
332
+
#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000
333
+
#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12
334
+
static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
335
+
{
336
+
return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK;
337
+
}
382
338
383
339
#define REG_A2XX_MH_MMU_PT_BASE 0x00000042
384
340
···
399
331
#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
400
332
401
333
#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
334
+
#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001
335
+
#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002
402
336
403
337
#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
404
338
···
459
389
#define REG_A2XX_RBBM_READ_ERROR 0x000003b3
460
390
461
391
#define REG_A2XX_RBBM_INT_CNTL 0x000003b4
392
+
#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001
393
+
#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002
394
+
#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000
462
395
463
396
#define REG_A2XX_RBBM_INT_STATUS 0x000003b5
464
397
465
398
#define REG_A2XX_RBBM_INT_ACK 0x000003b6
466
399
467
400
#define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7
401
+
#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020
402
+
#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000
403
+
#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000
404
+
#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000
468
405
469
406
#define REG_A2XX_RBBM_PERIPHID1 0x000003f9
470
407
···
543
466
#define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000
544
467
#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000
545
468
#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000
469
+
470
+
#define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42
471
+
#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001
472
+
#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002
473
+
#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004
474
+
475
+
#define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43
476
+
477
+
#define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44
478
+
479
+
#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54
480
+
481
+
#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55
546
482
547
483
#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
548
484
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
···
738
648
#define REG_A2XX_RB_DEBUG_DATA 0x00000f27
739
649
740
650
#define REG_A2XX_RB_SURFACE_INFO 0x00002000
651
+
#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff
652
+
#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0
653
+
static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
654
+
{
655
+
return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK;
656
+
}
657
+
#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000
658
+
#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14
659
+
static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
660
+
{
661
+
return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK;
662
+
}
741
663
742
664
#define REG_A2XX_RB_COLOR_INFO 0x00002001
743
665
#define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f
···
781
679
#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
782
680
static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
783
681
{
784
-
return ((val >> 10) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
682
+
return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
785
683
}
786
684
787
685
#define REG_A2XX_RB_DEPTH_INFO 0x00002002
···
795
693
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
796
694
static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
797
695
{
798
-
return ((val >> 10) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
696
+
return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
799
697
}
800
698
801
699
#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
···
1859
1757
#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
1860
1758
1861
1759
#define REG_A2XX_SQ_TEX_0 0x00000000
1760
+
#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
1761
+
#define A2XX_SQ_TEX_0_TYPE__SHIFT 0
1762
+
static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val)
1763
+
{
1764
+
return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK;
1765
+
}
1766
+
#define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c
1767
+
#define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2
1768
+
static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val)
1769
+
{
1770
+
return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK;
1771
+
}
1772
+
#define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030
1773
+
#define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4
1774
+
static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val)
1775
+
{
1776
+
return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK;
1777
+
}
1778
+
#define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0
1779
+
#define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6
1780
+
static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val)
1781
+
{
1782
+
return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK;
1783
+
}
1784
+
#define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300
1785
+
#define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8
1786
+
static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val)
1787
+
{
1788
+
return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK;
1789
+
}
1862
1790
#define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00
1863
1791
#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10
1864
1792
static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
···
1907
1775
{
1908
1776
return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
1909
1777
}
1910
-
#define A2XX_SQ_TEX_0_PITCH__MASK 0xffc00000
1778
+
#define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000
1911
1779
#define A2XX_SQ_TEX_0_PITCH__SHIFT 22
1912
1780
static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
1913
1781
{
1914
1782
return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
1915
1783
}
1784
+
#define A2XX_SQ_TEX_0_TILED 0x00000002
1916
1785
1917
1786
#define REG_A2XX_SQ_TEX_1 0x00000001
1787
+
#define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f
1788
+
#define A2XX_SQ_TEX_1_FORMAT__SHIFT 0
1789
+
static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val)
1790
+
{
1791
+
return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK;
1792
+
}
1793
+
#define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0
1794
+
#define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6
1795
+
static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val)
1796
+
{
1797
+
return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK;
1798
+
}
1799
+
#define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300
1800
+
#define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8
1801
+
static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val)
1802
+
{
1803
+
return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK;
1804
+
}
1805
+
#define A2XX_SQ_TEX_1_STACKED 0x00000400
1806
+
#define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800
1807
+
#define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11
1808
+
static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val)
1809
+
{
1810
+
return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK;
1811
+
}
1812
+
#define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000
1813
+
#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12
1814
+
static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
1815
+
{
1816
+
return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
1817
+
}
1918
1818
1919
1819
#define REG_A2XX_SQ_TEX_2 0x00000002
1920
1820
#define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff
···
1961
1797
{
1962
1798
return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
1963
1799
}
1800
+
#define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000
1801
+
#define A2XX_SQ_TEX_2_DEPTH__SHIFT 26
1802
+
static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val)
1803
+
{
1804
+
return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK;
1805
+
}
1964
1806
1965
1807
#define REG_A2XX_SQ_TEX_3 0x00000003
1808
+
#define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001
1809
+
#define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0
1810
+
static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val)
1811
+
{
1812
+
return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK;
1813
+
}
1966
1814
#define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e
1967
1815
#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1
1968
1816
static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
···
1999
1823
{
2000
1824
return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
2001
1825
}
1826
+
#define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000
1827
+
#define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13
1828
+
static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val)
1829
+
{
1830
+
return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
1831
+
}
2002
1832
#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000
2003
1833
#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19
2004
1834
static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
···
2016
1834
static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
2017
1835
{
2018
1836
return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
1837
+
}
1838
+
#define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000
1839
+
#define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23
1840
+
static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val)
1841
+
{
1842
+
return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK;
1843
+
}
1844
+
#define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000
1845
+
#define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25
1846
+
static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val)
1847
+
{
1848
+
return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK;
1849
+
}
1850
+
#define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000
1851
+
#define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31
1852
+
static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val)
1853
+
{
1854
+
return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK;
1855
+
}
1856
+
1857
+
#define REG_A2XX_SQ_TEX_4 0x00000004
1858
+
#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001
1859
+
#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0
1860
+
static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val)
1861
+
{
1862
+
return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK;
1863
+
}
1864
+
#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002
1865
+
#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1
1866
+
static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val)
1867
+
{
1868
+
return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK;
1869
+
}
1870
+
#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c
1871
+
#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2
1872
+
static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val)
1873
+
{
1874
+
return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK;
1875
+
}
1876
+
#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0
1877
+
#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6
1878
+
static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val)
1879
+
{
1880
+
return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK;
1881
+
}
1882
+
#define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400
1883
+
#define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800
1884
+
#define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000
1885
+
#define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12
1886
+
static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val)
1887
+
{
1888
+
return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK;
1889
+
}
1890
+
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000
1891
+
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22
1892
+
static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val)
1893
+
{
1894
+
return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK;
1895
+
}
1896
+
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000
1897
+
#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27
1898
+
static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val)
1899
+
{
1900
+
return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK;
1901
+
}
1902
+
1903
+
#define REG_A2XX_SQ_TEX_5 0x00000005
1904
+
#define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003
1905
+
#define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0
1906
+
static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val)
1907
+
{
1908
+
return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK;
1909
+
}
1910
+
#define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004
1911
+
#define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018
1912
+
#define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3
1913
+
static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val)
1914
+
{
1915
+
return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK;
1916
+
}
1917
+
#define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0
1918
+
#define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5
1919
+
static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val)
1920
+
{
1921
+
return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK;
1922
+
}
1923
+
#define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600
1924
+
#define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9
1925
+
static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val)
1926
+
{
1927
+
return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK;
1928
+
}
1929
+
#define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800
1930
+
#define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000
1931
+
#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12
1932
+
static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
1933
+
{
1934
+
return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
2019
1935
}
2020
1936
2021
1937
+5
-5
drivers/gpu/drm/msm/adreno/a3xx.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a3xx.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
+5
-5
drivers/gpu/drm/msm/adreno/a4xx.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a4xx.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
+5
-5
drivers/gpu/drm/msm/adreno/a5xx.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a5xx.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
+72
-6
drivers/gpu/drm/msm/adreno/a6xx.xml.h
+72
-6
drivers/gpu/drm/msm/adreno/a6xx.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
···
501
501
PERF_VFDP_VS_STAGE_WAVES = 22,
502
502
};
503
503
504
-
enum a6xx_hslq_perfcounter_select {
504
+
enum a6xx_hlsq_perfcounter_select {
505
505
PERF_HLSQ_BUSY_CYCLES = 0,
506
506
PERF_HLSQ_STALL_CYCLES_UCHE = 1,
507
507
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
···
2959
2959
#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2960
2960
#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2961
2961
#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2962
+
#define A6XX_GRAS_LRZ_CNTL_UNK3 0x00000008
2963
+
#define A6XX_GRAS_LRZ_CNTL_UNK4 0x00000010
2962
2964
2963
2965
#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
2964
2966
···
2999
2997
#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
3000
2998
3001
2999
#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
3000
+
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
3001
+
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
3002
+
static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_color_fmt val)
3003
+
{
3004
+
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3005
+
}
3006
+
#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
3002
3007
3003
3008
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
3004
3009
#define A6XX_GRAS_2D_SRC_TL_X_X__MASK 0x00ffff00
···
3458
3449
return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3459
3450
}
3460
3451
#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3452
+
#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3461
3453
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3462
3454
#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3463
3455
static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
···
3652
3642
#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
3653
3643
#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3654
3644
3645
+
#define REG_A6XX_RB_LRZ_CNTL 0x00008898
3646
+
#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
3647
+
3655
3648
#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
3656
3649
3657
3650
#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
···
3687
3674
return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
3688
3675
}
3689
3676
3677
+
#define REG_A6XX_RB_MSAA_CNTL 0x000088d5
3678
+
#define A6XX_RB_MSAA_CNTL_SAMPLES__MASK 0x00000018
3679
+
#define A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT 3
3680
+
static inline uint32_t A6XX_RB_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3681
+
{
3682
+
return ((val) << A6XX_RB_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_MSAA_CNTL_SAMPLES__MASK;
3683
+
}
3684
+
3690
3685
#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
3691
3686
3692
3687
#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
···
3705
3684
return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
3706
3685
}
3707
3686
#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
3687
+
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
3688
+
#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
3689
+
static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
3690
+
{
3691
+
return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
3692
+
}
3708
3693
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
3709
3694
#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
3710
3695
static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_color_fmt val)
···
3807
3780
{
3808
3781
return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
3809
3782
}
3783
+
#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
3784
+
3785
+
#define REG_A6XX_RB_UNKNOWN_8C01 0x00008c01
3810
3786
3811
3787
#define REG_A6XX_RB_2D_DST_INFO 0x00008c17
3812
3788
#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
···
4495
4465
#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
4496
4466
#define A6XX_SP_BLEND_CNTL_ENABLED 0x00000001
4497
4467
#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
4468
+
#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4498
4469
4499
4470
#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
4500
4471
#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
···
4674
4643
4675
4644
#define REG_A6XX_SP_UNKNOWN_AB20 0x0000ab20
4676
4645
4646
+
#define REG_A6XX_SP_UNKNOWN_ACC0 0x0000acc0
4647
+
4677
4648
#define REG_A6XX_SP_UNKNOWN_AE00 0x0000ae00
4678
4649
4679
4650
#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
···
4733
4700
return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
4734
4701
}
4735
4702
#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
4703
+
#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
4704
+
4705
+
#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
4706
+
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
4707
+
#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
4708
+
static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
4709
+
{
4710
+
return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
4711
+
}
4712
+
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
4713
+
#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
4714
+
static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
4715
+
{
4716
+
return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
4717
+
}
4736
4718
4737
4719
#define REG_A6XX_SP_PS_2D_SRC_LO 0x0000b4c2
4738
4720
4739
4721
#define REG_A6XX_SP_PS_2D_SRC_HI 0x0000b4c3
4722
+
4723
+
#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
4724
+
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x01fffe00
4725
+
#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
4726
+
static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
4727
+
{
4728
+
return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
4729
+
}
4740
4730
4741
4731
#define REG_A6XX_SP_PS_2D_SRC_FLAGS_LO 0x0000b4ca
4742
4732
···
5088
5032
static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5089
5033
{
5090
5034
return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
5035
+
}
5036
+
#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
5037
+
#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
5038
+
static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5039
+
{
5040
+
return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
5091
5041
}
5092
5042
#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
5093
5043
#define A6XX_TEX_CONST_0_FMT__SHIFT 22
···
5426
5364
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
5427
5365
5428
5366
#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
5367
+
5368
+
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
5369
+
5370
+
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
5429
5371
5430
5372
5431
5373
#endif /* A6XX_XML */
+5
-5
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+5
-5
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
+14
-5
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+14
-5
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
···
339
339
#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
340
340
341
341
#define REG_AXXX_CP_INT_CNTL 0x000001f2
342
+
#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000
343
+
#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000
344
+
#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000
345
+
#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000
346
+
#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000
347
+
#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000
348
+
#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000
349
+
#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000
350
+
#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000
342
351
343
352
#define REG_AXXX_CP_INT_STATUS 0x000001f3
344
353
+13
-5
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+13
-5
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
···
10
10
The rules-ng-ng source files this header was generated from are:
11
11
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12
12
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13
-
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15
-
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42585 bytes, from 2018-10-04 19:06:37)
13
+
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
14
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
15
+
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
16
16
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17
17
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18
-
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-10-04 19:06:37)
19
-
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139581 bytes, from 2018-10-04 19:06:42)
18
+
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
19
+
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
20
20
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21
21
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
22
···
106
106
DI_SRC_SEL_IMMEDIATE = 1,
107
107
DI_SRC_SEL_AUTO_INDEX = 2,
108
108
DI_SRC_SEL_RESERVED = 3,
109
+
};
110
+
111
+
enum pc_di_face_cull_sel {
112
+
DI_FACE_CULL_NONE = 0,
113
+
DI_FACE_CULL_FETCH = 1,
114
+
DI_FACE_BACKFACE_CULL = 2,
115
+
DI_FACE_FRONTFACE_CULL = 3,
109
116
};
110
117
111
118
enum pc_di_index_size {
···
363
356
RM6_GMEM = 4,
364
357
RM6_BLIT2D = 5,
365
358
RM6_RESOLVE = 6,
359
+
RM6_BLIT2DSCALE = 12,
366
360
};
367
361
368
362
enum pseudo_reg {