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MIPS: Remove unused R5432_CP0_INTERRUPT_WAR

R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and
so the workaround is never used. Remove the dead code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org

Paul Burton ccd51b9f 8e96b084

-28
-1
arch/mips/include/asm/mach-cavium-octeon/war.h
··· 12 12 #define R4600_V1_INDEX_ICACHEOP_WAR 0 13 13 #define R4600_V1_HIT_CACHEOP_WAR 0 14 14 #define R4600_V2_HIT_CACHEOP_WAR 0 15 - #define R5432_CP0_INTERRUPT_WAR 0 16 15 #define BCM1250_M3_WAR 0 17 16 #define SIBYTE_1956_WAR 0 18 17 #define MIPS4K_ICACHE_REFILL_WAR 0
-1
arch/mips/include/asm/mach-generic/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 0
-1
arch/mips/include/asm/mach-ip22/war.h
··· 15 15 #define R4600_V1_INDEX_ICACHEOP_WAR 1 16 16 #define R4600_V1_HIT_CACHEOP_WAR 1 17 17 #define R4600_V2_HIT_CACHEOP_WAR 1 18 - #define R5432_CP0_INTERRUPT_WAR 0 19 18 #define BCM1250_M3_WAR 0 20 19 #define SIBYTE_1956_WAR 0 21 20 #define MIPS4K_ICACHE_REFILL_WAR 0
-1
arch/mips/include/asm/mach-ip27/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 0
-1
arch/mips/include/asm/mach-ip28/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 0
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arch/mips/include/asm/mach-ip32/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 0
-1
arch/mips/include/asm/mach-malta/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 1
-1
arch/mips/include/asm/mach-pmcs-msp71xx/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 0
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arch/mips/include/asm/mach-rc32434/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 1
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arch/mips/include/asm/mach-rm/war.h
··· 15 15 #define R4600_V1_INDEX_ICACHEOP_WAR 0 16 16 #define R4600_V1_HIT_CACHEOP_WAR 0 17 17 #define R4600_V2_HIT_CACHEOP_WAR 1 18 - #define R5432_CP0_INTERRUPT_WAR 0 19 18 #define BCM1250_M3_WAR 0 20 19 #define SIBYTE_1956_WAR 0 21 20 #define MIPS4K_ICACHE_REFILL_WAR 0
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arch/mips/include/asm/mach-sibyte/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 16 15 #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS) 17 16
-1
arch/mips/include/asm/mach-tx49xx/war.h
··· 11 11 #define R4600_V1_INDEX_ICACHEOP_WAR 0 12 12 #define R4600_V1_HIT_CACHEOP_WAR 0 13 13 #define R4600_V2_HIT_CACHEOP_WAR 0 14 - #define R5432_CP0_INTERRUPT_WAR 0 15 14 #define BCM1250_M3_WAR 0 16 15 #define SIBYTE_1956_WAR 0 17 16 #define MIPS4K_ICACHE_REFILL_WAR 0
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arch/mips/include/asm/war.h
··· 129 129 #endif 130 130 131 131 /* 132 - * When an interrupt happens on a CP0 register read instruction, CPU may 133 - * lock up or read corrupted values of CP0 registers after it enters 134 - * the exception handler. 135 - * 136 - * This workaround makes sure that we read a "safe" CP0 register as the 137 - * first thing in the exception handler, which breaks one of the 138 - * pre-conditions for this problem. 139 - */ 140 - #ifndef R5432_CP0_INTERRUPT_WAR 141 - #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform 142 - #endif 143 - 144 - /* 145 132 * Workaround for the Sibyte M3 errata the text of which can be found at 146 133 * 147 134 * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
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arch/mips/kernel/genex.S
··· 32 32 NESTED(except_vec3_generic, 0, sp) 33 33 .set push 34 34 .set noat 35 - #if R5432_CP0_INTERRUPT_WAR 36 - mfc0 k0, CP0_INDEX 37 - #endif 38 35 mfc0 k1, CP0_CAUSE 39 36 andi k1, k1, 0x7c 40 37 #ifdef CONFIG_64BIT